Method for forming semiconductor structure, semiconductor structure and electronic device
By selective lateral etching and the formation of a sidewall protective material layer, the sidewall defect problem of RRAM devices was solved, improving the performance consistency and reliability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2026-05-21
- Publication Date
- 2026-06-19
Smart Images
Figure CN122248967A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory fabrication technology, specifically to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Technology
[0002] Resistive random access memory (RRAM), as an emerging non-volatile memory based on the resistance switching effect, is considered one of the important candidates for next-generation memory technology due to its advantages such as simple structure, high storage density, fast operation speed, and good compatibility with CMOS processes. Its core structure is usually a metal-insulator-metal (MIM) sandwich configuration. By applying a specific electrical signal between the upper and lower electrodes, the resistance of the intermediate resistive switching layer (usually a dielectric material such as metal oxide) can be reversibly switched between a high-resistivity state (HRS) and a low-resistivity state (LRS), thereby realizing data storage.
[0003] In the fabrication of RRAM arrays, patterning etching of the deposited MIM stack is typically required to define individual device cells. Dry etching (such as reactive ion etching) is the mainstream technique for this step, but its high-energy plasma, while etching the material vertically, continuously bombards the sidewalls of the formed pattern with physical and chemical agents. See also Figure 1 This bombardment leads to defects in the resistive switching layer (RSL) sidewall region, such as lattice damage, the formation of numerous dangling bonds, and the introduction of charge traps. These defects significantly alter the chemical state and local electrical properties of the sidewall surface, for example, becoming additional ion migration channels or carrier recombination centers. In high-density integration, these sidewall-originating defects have become a key factor affecting the performance of RRAM devices, leading to: Device performance inconsistency: The randomness of sidewall defects causes significant fluctuations in the initial resistance, operating voltage, and cycle endurance of different device cells. Decreased reliability: Leakage paths and charge traps on the sidewalls accelerate the degradation of the resistive switching layer, affecting data retention characteristics and endurance. Increased leakage current: In unselected device cells, defect-induced sidewall leakage paths are exacerbated.
[0004] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0005] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device.
[0006] This application provides a method for forming a semiconductor structure, including the following steps: A stacked structure is provided, the stacked structure including a lower electrode layer, a resistive switching material layer located on the lower electrode layer, and an upper electrode layer located on the resistive switching material layer; The stacked structure is patterned to form a MIM stacked pillar, the MIM stacked pillar including a lower electrode formed by the lower electrode layer, a resistive switching layer formed by the resistive switching material layer, and an upper electrode structure formed by the upper electrode layer, the MIM stacked pillar having sidewalls; Selective lateral etching is performed on the MIM stack pillars, such that at least a portion of the sidewalls of the resistive switching layer are laterally retracted relative to the sidewalls of the upper electrode structure and / or the sidewalls of the lower electrode. A layer of deposited sidewall protective material is applied to cover the exposed surfaces of the top, sidewalls, and bottom of the MIM stacked column. The sidewall protective material layer is anisotropically etched to remove the sidewall protective material layer located on the top and bottom fields of the MIM stacked column, while retaining the sidewall protective material layer located on the sidewall of the MIM stacked column, forming a sidewall protective layer with flat vertical sidewalls.
[0007] In some embodiments, the upper electrode layer includes a cover material layer and an upper electrode material layer located on the cover material layer, wherein the cover material layer is located above the resistive switching material layer.
[0008] In some embodiments, in the step of selectively etching the MIM stack pillars laterally, the etching process used has a higher etching rate for the resistive switching layer material than for the upper electrode structure material and the lower electrode material.
[0009] In some embodiments, the etching process has a selectivity ratio of etching rate for the resistive switching layer material to etching rate for the upper electrode structure material and / or the lower electrode material greater than 10:1.
[0010] In some embodiments, the selective lateral etching employs wet chemical etching, atomic layer etching, or chemical-based dry etching processes.
[0011] In some embodiments, the resistive switching material layer is made of a metal oxide.
[0012] In some embodiments, the metal oxide includes at least one of HfO2 and Ta2O5.
[0013] In some embodiments, the material of the sidewall protective material layer includes a high dielectric constant dielectric material.
[0014] In some embodiments, the high dielectric constant dielectric material includes Al2O3, HfO2, ZrO2, SiO2, and SiN. X At least one of them.
[0015] In some embodiments, the sidewall protective material layer is deposited using an atomic layer deposition process.
[0016] In some embodiments, the anisotropic etching of the sidewall protective material layer is performed using a reactive ion etching process.
[0017] In some embodiments, the selective lateral etching causes at least a portion of the sidewalls of the resistive switching layer to retract laterally by an amount of 5 nm to 15 nm.
[0018] This application also provides a semiconductor structure, including: The MIM stacked column includes a lower electrode, a resistive switching layer, and an upper electrode structure stacked sequentially; wherein at least a portion of the sidewalls of the resistive switching layer are laterally recessed relative to the sidewalls of the upper electrode structure and / or the sidewalls of the lower electrode. The sidewall protective layer is filled in the groove formed by the retraction of the resistive switching layer sidewall and is in direct contact with the sidewall of the upper electrode structure and / or the sidewall of the lower electrode, so that the outer sidewall of the MIM stacked column has a flat vertical profile.
[0019] In some embodiments, the upper electrode structure includes a cover layer and an upper electrode, wherein the cover layer is disposed between the resistive switching layer and the upper electrode.
[0020] In some embodiments, the resistive switching layer is made of a metal oxide.
[0021] In some embodiments, the metal oxide includes at least one of HfO2 and Ta2O5.
[0022] In some embodiments, the material of the sidewall protective layer includes a high dielectric constant dielectric material.
[0023] In some embodiments, the high dielectric constant dielectric material includes Al2O3, HfO2, ZrO2, SiO2, and SiN. X At least one of them.
[0024] In some embodiments, the lateral retraction of at least a portion of the sidewalls of the resistive switching layer is 5 nm to 15 nm.
[0025] This application also provides an electronic device, including the semiconductor structure described in any of the above embodiments.
[0026] The semiconductor structure formation method, semiconductor structure, and electronic device proposed in this application provide a stacked structure, which includes a lower electrode layer, a resistive switching material layer located on the lower electrode layer, and an upper electrode layer located on the resistive switching material layer; the stacked structure is patterned to form a MIM stacked pillar, which includes a lower electrode formed by the lower electrode layer, a resistive switching layer formed by the resistive switching material layer, and an upper electrode structure formed by the upper electrode layer, and the MIM stacked pillar has sidewalls; the MIM stacked pillar is then subjected to... Selective lateral etching causes at least a portion of the sidewalls of the resistive switching layer to recede laterally relative to the sidewalls of the upper electrode structure and / or the lower electrode. A sidewall protection material layer is deposited, covering the exposed surfaces of the top, sidewalls, and bottom field regions of the MIM stack pillar. Anisotropic etching is then performed on the sidewall protection material layer to remove the sidewall protection material layers located on the top and bottom field regions of the MIM stack pillar, while retaining the sidewall protection material layers located on the sidewalls of the MIM stack pillar, forming a sidewall protection layer with flat, vertical sidewalls. Thus, by using selective resistive switching layer push-back etching and self-aligned sidewall formation to flatten the device sidewalls, the device structure is optimized, thereby improving sidewall defects and enhancing device performance consistency and reliability. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the sidewall defects in an RRAM device structure etched by resistive variable layer pushback.
[0028] Figure 2 This is a schematic flowchart of a method for forming a semiconductor structure provided in this application.
[0029] Figures 3 to 6 This is a schematic diagram of the semiconductor structure formed by each key process step in a semiconductor structure formation method provided in this application embodiment. Detailed Implementation
[0030] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.
[0031] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.
[0032] To better understand this application, the research background of this application will be explained in detail below.
[0033] To address the sidewall defect problem, the industry has proposed a variety of solutions aimed at physically "isolating" or reducing the electrically active areas on the sidewalls. The core idea behind these solutions is to design the process so that the size of the upper and lower electrodes is smaller than the size of the resistive switching layer, thereby placing the main contact interface between the electrode and the resistive switching layer in an area less susceptible to etching damage, and excluding the defective sidewall areas from the effective conductive channels.
[0034] For example, a representative approach employs a step-by-step etching process combined with a spacer technique, resulting in a top electrode material with a smaller lateral dimension than the underlying resistive switching layer. This method utilizes the sidewalls as part of a hard mask, exposing the edges of the resistive switching layer after etching, while the top electrode does not completely cover these edges, thus achieving electrical isolation of the sidewall region.
[0035] Another representative approach involves using a wet etching process with high selectivity for electrode materials to traversely etch back the bottom electrode material beneath the resistive switching layer. This results in the top surface dimension of the bottom electrode being smaller than the size of the resistive switching layer covering it, thus achieving the goal of keeping the effective conductive interface away from the sidewalls formed by etching.
[0036] The aforementioned prior art, by reducing the size of the electrode material and changing the relative size relationship between the electrode and the resistive switching layer, alleviates the direct impact of sidewall defects to some extent.
[0037] This application proposes a novel approach: by selectively wet etching or chemically etching with low etch damage, the sidewall-damaged resistive switching layer material can be directly removed, and further sidewall protection measures can be implemented to improve device reliability.
[0038] Figure 2 This is a schematic flowchart illustrating a method for forming a semiconductor structure provided in this application. Figure 2 As shown, this application provides a method for forming a semiconductor structure, comprising the following steps: S1. A stacked structure is provided, the stacked structure including a lower electrode layer, a resistive switching material layer located on the lower electrode layer, and an upper electrode layer located on the resistive switching material layer; In step S1, the stacked structure is typically formed by a deposition process during the fabrication of the RRAM array. In some embodiments, the upper electrode layer may include a cover material layer and an upper electrode material layer located on the cover material layer, wherein the cover material layer is located above the resistive switching material layer.
[0039] S2. Pattern the stacked structure to form a MIM stacked pillar 1. The MIM stacked pillar 1 includes a lower electrode 11 formed by the lower electrode layer, a resistive switching layer 12 formed by the resistive switching material layer, and an upper electrode structure 13 formed by the upper electrode layer. The MIM stacked pillar 1 has sidewalls. In step S2, see Figure 3 To define independent RRAM device cells, the stacked structure needs to be patterned and etched, for example, by dry etching (such as reactive ion etching, RIE) to form independent MIM stack pillars 1. In this step, the sidewall region of the resistive switching layer 12 in the MIM stack pillar 1 will generate defects such as lattice damage, formation of a large number of dangling bonds, and introduction of charge traps.
[0040] S3. Selectively etch the MIM stack pillar 1 laterally, so that at least a portion of the sidewalls of the resistive switching layer 12 are laterally retracted relative to the sidewalls of the upper electrode structure 13 and / or the sidewalls of the lower electrode 11. Step S3 is the selective resistive switching layer pushback etching step, see [link to relevant documentation]. Figure 4 After forming the initial MIM stacked columnar structure, a highly selective etching process is used for the upper electrode (TE) 132 / capping layer (CPL) 131 material and the lower electrode (BE) 11 material to selectively and laterally remove a layer of material damaged by dry etching on the sidewall surface of the resistive switching layer 12.
[0041] The etching process can employ wet chemical etching, atomic layer etching, or chemical-based dry etching (with less physical attack). Compared to conventional dry etching, which is mainly based on physical bombardment, these methods can significantly reduce secondary damage to the remaining material.
[0042] The etching process can achieve a high etching rate for the resistive switching layer 12 material (generally including high-oxygen-content metal oxides such as HfO2, Ta2O5, etc.), while the etching rate for the electrode materials (such as the upper electrode 132 / TE, the capping layer 131 / CPL, and the lower electrode 11 / BE, typically pure metals such as W and TiN, or low-oxygen-content conductive oxides such as ITO) is extremely low. Optionally, the selectivity ratio of the etching rate of the resistive switching layer 12 material to the etching rate of the upper electrode structure 13 material and / or the lower electrode 11 material is greater than 10:1.
[0043] This step directly removes the resistive switching layer in the boundary region of the damaged device, which is rich in dangling bonds, lattice damage, and charge traps, fundamentally mitigating or even eliminating the impact of the original sidewall defects on ion migration and carrier transport.
[0044] In some embodiments, the selective lateral etching causes at least a portion of the sidewalls of the resistive switching layer to retract laterally by an amount of 5 nm to 15 nm.
[0045] S4. Deposit sidewall protective material layer 2 to cover the top, sidewalls and exposed surface of the bottom field area 3 of the MIM stacked column 1; In step S4, see Figure 5 Atomic layer deposition (ALD) can be used to conformally deposit a high dielectric constant (high K) dielectric layer on the entire device structure (including the top, sidewalls, and bottom). The deposited dielectric material is preferably a high K oxide or nitride, such as Al2O3, HfO2, ZrO2, SiO2, or SiN. X (at least one of them).
[0046] S5. Anisotropic etching is performed on the sidewall protective material layer 2 to remove the sidewall protective material layer located on the top and bottom field areas 3 of the MIM stacked column 1, while retaining the sidewall protective material layer 2 located on the sidewall of the MIM stacked column 1, forming a sidewall protective layer 21 with flat vertical sidewalls.
[0047] In step S5, see Figure 6 The sidewall protective material layer 2 on the top plane and bottom field region 3 of the device can be removed by a single anisotropic dry etching process (such as RIE, reactive ion etching), leaving only the portion on the vertical sidewalls of the device. The resulting device structure can be restored to the flat state before the resistive switching layer 12 was etched and adjusted.
[0048] The semiconductor structure formation method provided in this application embodiment involves providing a stacked structure, the stacked structure including a lower electrode layer, a resistive switching material layer located on the lower electrode layer, and an upper electrode layer located on the resistive switching material layer; patterning the stacked structure to form a MIM stacked pillar 1, the MIM stacked pillar 1 including a lower electrode 11 formed by the lower electrode layer, a resistive switching layer 12 formed by the resistive switching material layer, and an upper electrode structure 13 formed by the upper electrode layer, the MIM stacked pillar 1 having sidewalls; and selectively lateral etching the MIM stacked pillar 1. At least a portion of the sidewalls of the resistive switching layer 12 are laterally retracted relative to the sidewalls of the upper electrode structure 13 and / or the sidewalls of the lower electrode 11; a sidewall protection material layer 2 is deposited, covering the top, sidewalls, and exposed surfaces of the bottom field region of the MIM stack pillar 1; the sidewall protection material layer 2 is anisotropically etched to remove the sidewall protection material layers located on the top and bottom field regions 3 of the MIM stack pillar 1, while retaining the sidewall protection material layer 2 located on the sidewalls of the MIM stack pillar 1, forming a sidewall protection layer 21 with flat vertical sidewalls. Thus, by selectively retracting the resistive switching layer through back-etching and self-aligned sidewall formation, the device sidewalls are flattened, optimizing the device structure and thereby improving sidewall defects, device performance consistency, and reliability.
[0049] Based on the same inventive concept, embodiments of this application also provide a semiconductor structure.
[0050] Figure 6 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application. For example... Figure 6 As shown in the embodiment of this application, a semiconductor structure includes: MIM stacked column 1 includes a lower electrode 11, a resistive switching layer 12 and an upper electrode structure 13 stacked sequentially; wherein, at least a portion of the sidewall of the resistive switching layer 12 is laterally recessed relative to the sidewall of the upper electrode structure 13 and / or the sidewall of the lower electrode 11. The sidewall protective layer 21 is filled in the groove formed by the retraction of the sidewall of the resistive switching layer 12, and is in direct contact with the sidewall of the upper electrode structure 13 and / or the sidewall of the lower electrode 11, so that the outer sidewall of the MIM stacked column 1 has a flat vertical profile.
[0051] The semiconductor structure provided in this application improves the reliability of the device by directly removing the damaged resistive switching layer 12 material and forming a sidewall protection layer 21 through a further sidewall protection scheme.
[0052] In some embodiments, the upper electrode structure 13 includes a cover layer 131 and an upper electrode 132, wherein the cover layer 131 is disposed between the resistive switching layer 12 and the upper electrode 132.
[0053] In some embodiments, the resistive switching layer 12 is made of a metal oxide.
[0054] In some embodiments, the metal oxide includes at least one of HfO2 and Ta2O5.
[0055] In some embodiments, the material of the sidewall protective layer 21 includes a high dielectric constant dielectric material.
[0056] In some embodiments, the high dielectric constant dielectric material includes Al2O3, HfO2, ZrO2, SiO2, and SiN. X At least one of them.
[0057] In some embodiments, the lateral retraction of at least a portion of the sidewalls of the resistive switching layer 12 is 5 nm to 15 nm.
[0058] Since the semiconductor structure provided in this embodiment can be formed based on any of the methods described in the foregoing embodiments, it has the same technical effects as the semiconductor structure formed in the above method embodiments, and will not be described again here.
[0059] Based on the same inventive concept, embodiments of this application also provide an electronic device, including the semiconductor structure described in any of the above embodiments.
[0060] Since the electronic device provided in this embodiment includes the semiconductor structure, it can achieve the same technical effects as the semiconductor structure provided in the above embodiments, and will not be described again here.
[0061] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0062] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A stacked structure is provided, the stacked structure including a lower electrode layer, a resistive switching material layer located on the lower electrode layer, and an upper electrode layer located on the resistive switching material layer; The stacked structure is patterned to form a MIM stacked pillar, the MIM stacked pillar including a lower electrode formed by the lower electrode layer, a resistive switching layer formed by the resistive switching material layer, and an upper electrode structure formed by the upper electrode layer, the MIM stacked pillar having sidewalls; Selective lateral etching is performed on the MIM stack pillars, such that at least a portion of the sidewalls of the resistive switching layer are laterally retracted relative to the sidewalls of the upper electrode structure and / or the sidewalls of the lower electrode. A layer of deposited sidewall protective material is applied to cover the exposed surfaces of the top, sidewalls, and bottom of the MIM stacked column. The sidewall protective material layer is anisotropically etched to remove the sidewall protective material layer located on the top and bottom fields of the MIM stacked column, while retaining the sidewall protective material layer located on the sidewall of the MIM stacked column, forming a sidewall protective layer with flat vertical sidewalls.
2. The forming method according to claim 1, characterized in that, The upper electrode layer includes a cover material layer and an upper electrode material layer located on the cover material layer, wherein the cover material layer is located above the resistive switching material layer.
3. The forming method according to claim 1 or 2, characterized in that, In the step of selectively etching the MIM stack pillars laterally, the etching process used has a higher etching rate for the resistive switching layer material than for the upper electrode structure material and the lower electrode material.
4. The forming method according to claim 3, characterized in that, The selectivity ratio of the etching rate of the etching process for the resistive switching layer material to the etching rate of the upper electrode structure material and / or the lower electrode material is greater than 10:
1.
5. The forming method according to claim 3, characterized in that, The selective lateral etching employs wet chemical etching, atomic layer etching, or chemical-based dry etching processes.
6. The forming method according to claim 1, characterized in that, The resistive switching material layer is made of metal oxides.
7. The forming method according to claim 6, characterized in that, The metal oxide includes at least one of HfO2 and Ta2O5.
8. The forming method according to claim 1, characterized in that, The material of the sidewall protective layer includes a high dielectric constant dielectric material.
9. The forming method according to claim 8, characterized in that, The high dielectric constant dielectric material includes Al2O3, HfO2, ZrO2, SiO2, and SiN. X At least one of them.
10. The forming method according to claim 1, characterized in that, The sidewall protective material layer was deposited using atomic layer deposition (ALD) technology.
11. The forming method according to claim 1, characterized in that, The anisotropic etching of the sidewall protective material layer is performed using reactive ion etching technology.
12. The forming method according to claim 1, characterized in that, The selective lateral etching causes at least a portion of the sidewalls of the resistive switching layer to laterally retract by an amount of 5 nm to 15 nm.
13. A semiconductor structure, characterized in that, include: The MIM stacked column includes a lower electrode, a resistive switching layer, and an upper electrode structure stacked sequentially; wherein at least a portion of the sidewalls of the resistive switching layer are laterally recessed relative to the sidewalls of the upper electrode structure and / or the sidewalls of the lower electrode. The sidewall protective layer is filled in the groove formed by the retraction of the resistive switching layer sidewall and is in direct contact with the sidewall of the upper electrode structure and / or the sidewall of the lower electrode, so that the outer sidewall of the MIM stacked column has a flat vertical profile.
14. The semiconductor structure according to claim 13, characterized in that, The upper electrode structure includes a cover layer and an upper electrode, wherein the cover layer is disposed between the resistive switching layer and the upper electrode.
15. The semiconductor structure according to claim 13, characterized in that, The resistive switching layer is made of metal oxide.
16. The semiconductor structure according to claim 15, characterized in that, The metal oxide includes at least one of HfO2 and Ta2O5.
17. The semiconductor structure according to claim 13, characterized in that, The material of the sidewall protective layer includes a high dielectric constant dielectric material.
18. The semiconductor structure according to claim 17, characterized in that, The high dielectric constant dielectric material includes Al2O3, HfO2, ZrO2, SiO2, and SiN. X At least one of them.
19. The semiconductor structure according to claim 13, characterized in that, The lateral retraction dimension of at least a portion of the sidewalls of the resistive switching layer is 5 nm to 15 nm.
20. An electronic device, characterized in that, The semiconductor structure included in any one of claims 13 to 19.