A semiconductor device and a manufacturing method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RONGXIN SEMICON (HUAIAN) CO LTD
- Filing Date
- 2026-05-20
- Publication Date
- 2026-06-19
Smart Images
Figure CN122248975A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method. Background Technology
[0002] In high-end semiconductor device packaging and interconnection, such as BCD (Bipolar-CMOS-DMOS) devices and CIS (CMOS Image Sensor) devices, thick passivation layers serve as critical insulation and protection structures. They must completely fill the trench structure to ensure the device's mechanical stability and long-term reliability. High-density plasma (HDP) technology, with its simultaneous deposition and sputtering characteristics, combines high deposition efficiency with excellent trench filling capabilities, making it a core technology for thick passivation layer trench filling.
[0003] However, existing HDP thick passivation layer trench filling processes generally face the technical bottleneck of high cracking risk, which seriously restricts device yield. In order to balance efficiency and filling effect, existing technologies mostly adopt multi-step HDP filling or a combination of high aspect ratio process (HARP) and HDP. However, the process parameters between each step are mostly adjusted in a step, or the film quality varies significantly between different processes, resulting in abrupt changes in film density and grain structure. Stress accumulation is prone to occur at the interface, and interface peeling and cracking are likely to occur during long-term use.
[0004] In summary, existing technologies suffer from drawbacks such as complex processes, high costs, and low efficiency, making it difficult to simultaneously meet the requirements of low cracking rate, high filling efficiency, and high reliability in thick passivation layer trenches. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To address the existing problems, one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: A substrate is provided, the surface of which is formed with passivation trenches; A first passivation layer is deposited in the passivation trench using a first high-density plasma process; A second passivation layer is deposited on the first passivation layer using a second high-density plasma process. The bombardment energy of the second high-density plasma process is higher than that of the first high-density plasma process, so as to bombard and flatten the first passivation layer. A third passivation layer is deposited on the second passivation layer using a third high-density plasma process, wherein the bombardment energy of the third high-density plasma process is lower than that of the second high-density plasma process. A fourth high-density plasma process is used to deposit a fourth passivation layer on the third passivation layer to fill the remaining space of the passivation trench. The deposition rate of the fourth high-density plasma process is higher than that of the third high-density plasma process.
[0007] In one embodiment, the second high-density plasma process includes multiple sub-steps, each sub-step having a progressively increasing bombardment energy and a progressively decreasing deposition rate.
[0008] In one embodiment, the second high-density plasma process includes a first sub-step and a second sub-step executed sequentially. The bias power of the first sub-step is 4000W to 6000W, and the deposition rate is 3000A / min to 5000A / min. The bias power of the second sub-step is 5000W to 7000W, and the deposition rate is 1500A / min to 3000A / min.
[0009] In one embodiment, the deposition rate of the third high-density plasma process is greater than or equal to the deposition rate of the second high-density plasma process, and the bias power of the fourth high-density plasma process is lower than the bias power of the third high-density plasma process.
[0010] In one embodiment, the bias power of the first high-density plasma process is 3000W to 5000W, and the deposition rate is 4000A / min to 6000A / min. The bias power of the third high-density plasma process is 3000W to 5000W, and the deposition rate is 3000A / min to 5000A / min. The deposition rate of the fourth high-density plasma process is 4000A / min to 6000A / min, and the bias power is 2500W to 4500W.
[0011] In one embodiment, the first passivation layer fills to 45% to 55% of the total depth of the passivation trench; The second passivation layer fills to 75% to 85% of the total depth of the passivation trench; The third passivation layer fills to 92% to 96% of the total depth of the passivation trench; The fourth passivation layer completely fills the passivation trench.
[0012] In one embodiment, prior to depositing the first passivation layer using the first high-density plasma process, the substrate surface is further pretreated, the pretreatment including surface activation and micromorphological modification of the substrate surface using plasma.
[0013] In one embodiment, the pretreatment uses a mixture of argon, oxygen and helium as the treatment gas, with a bias power of 1000W to 3000W and a treatment time of 3 to 10 seconds.
[0014] In one embodiment, the pretreatment, the first high-density plasma process, the second high-density plasma process, the third high-density plasma process, and the fourth high-density plasma process are performed in the same high-density plasma device.
[0015] Another aspect of the present invention provides a semiconductor device manufactured using the method described above.
[0016] The semiconductor device manufacturing method provided by the present invention employs a multi-stage HDP process: the first HDP process rapidly fills and controls stress; the second HDP process removes protrusions with higher bombardment energy to eliminate stress concentration points; the third HDP process uses lower bombardment energy for transition buffering to avoid interfacial stress caused by abrupt changes in film quality; and the fourth HDP process rapidly caps the layer with a higher deposition rate. Ultimately, this significantly improves the crack resistance of the passivation layer, and the entire process uses a single HDP device, which is simple, requires no equipment switching, and reduces the introduction of impurities. Attached Figure Description
[0017] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.
[0018] In the attached image: Figure 1A A schematic diagram showing the location of stress concentration in the passivation layer in related technologies is provided. Figure 1B It shows in Figure 1A A schematic diagram showing the passivation layer cracking at the stress concentration location; Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown; Figures 3A-3E A cross-sectional view of a semiconductor device during the implementation of a semiconductor device manufacturing method according to an embodiment of the present invention is shown; Figure 4 A schematic diagram of a semiconductor device obtained by a manufacturing method according to an embodiment of the present invention is shown. Detailed Implementation
[0019] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.
[0020] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0022] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0024] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0025] Existing HDP thick passivation layer trench filling processes generally face a high risk of cracking, severely restricting device yield. In-depth analysis reveals two core causes of the cracking problem: First, poor top cap flatness leads to significant stress concentration. Existing processes often employ a "high deposition-low bombardment" or "gradually reducing bombardment energy" filling strategy, which easily results in defects such as protrusions and edge steps at the top of the trench, forming stress concentration points. These stress concentration points are prone to cracking during subsequent high-temperature processes. Second, abrupt changes in film composition during multi-step filling result in weak interfacial stress. For example... Figure 1A As shown, a top metal line 101 is formed on the substrate 100, and passivation trenches are formed between adjacent top metal lines. When a passivation layer 102 is formed on the surface of the substrate 100 using the existing HDP process, a noticeable protrusion is formed on the top of the passivation layer 102. The areas between adjacent protrusions are stress concentration points, which are prone to cracking. The cracking state is as follows: Figure 1B As shown.
[0026] To address the above problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. For example... Figure 2 As shown, the manufacturing method mainly includes the following steps: In step S201, a substrate is provided, and passivation trenches are formed on the surface of the substrate; In step S202, a first passivation layer is deposited in the passivation trench using a first high-density plasma process; In step S203, a second passivation layer is deposited on the first passivation layer using a second high-density plasma process. The bombardment energy of the second high-density plasma process is higher than that of the first high-density plasma process, so as to bombard and flatten the first passivation layer. In step S204, a third passivation layer is deposited on the second passivation layer using a third high-density plasma process. The bombardment energy of the third high-density plasma process is lower than that of the second high-density plasma process. In step S205, a fourth passivation layer is deposited on the third passivation layer using a fourth high-density plasma process to fill the remaining space of the passivation trench. The deposition rate of the fourth high-density plasma process is higher than that of the third high-density plasma process.
[0027] The semiconductor device manufacturing method provided in the embodiments of the present invention adopts a multi-stage HDP process, which can significantly improve the crack resistance of the passivation layer. Moreover, the entire process uses a single HDP device, which is simple, does not require equipment switching, and reduces the introduction of impurities.
[0028] Below, for reference Figures 3A to 3E The method for fabricating the semiconductor device in this embodiment is described in detail.
[0029] First, such as Figure 3A As shown, a substrate 300 is provided, and passivation trenches are formed on the surface of the substrate 300.
[0030] The substrate 300 may include a semiconductor substrate, such as a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. In this embodiment, the semiconductor substrate is a silicon substrate. Semiconductor device structures, such as transistors, capacitors, and resistors, are formed on the semiconductor substrate. An interconnect structure is formed above the semiconductor device structure, and the interconnect structure includes multiple metal layers and inter-metal dielectric layers.
[0031] A top layer metal line 301, such as an aluminum line, copper line, or an ultra-thick metal line, is formed on the surface of the substrate 300, and passivation trenches are formed between adjacent metal lines. The aspect ratio of the passivation trenches can be determined according to the actual device requirements. The passivation trenches are used to fill subsequent thick passivation layers to protect the metal lines and provide electrical isolation.
[0032] Optionally, the surface of the substrate 300 can be cleaned before performing subsequent steps, for example, by cleaning with deionized water or standard cleaning solutions (SC1, SC2) to remove surface particulate contaminants and the natural oxide layer, thereby improving the adhesion of the subsequently deposited film.
[0033] Next, the surface of substrate 300 is pretreated. Specifically, plasma is used to activate and modify the micro-morphology of the surface of substrate 300.
[0034] Specifically, the pretreatment step is performed in an HDP device. First, the substrate 300 is placed in the reaction chamber of the HDP device, and the temperature of the reaction chamber and the wafer are set within a suitable temperature range; the vacuum level of the reaction chamber can be controlled within the range of 1 mTorr to 100 mTorr. Next, a processing gas is introduced, which is a mixture of argon (Ar), oxygen (O2), and helium (He), and the flow rate of each reaction gas can be set according to actual needs.
[0035] Next, the radio frequency source is activated to generate high-density plasma. The bias power can be set within a moderate range, for example, from 1000W to 3000W, with a processing time of 3 to 10 seconds. During this process, Ar ions gain kinetic energy under the acceleration of the electric field, physically bombarding the surface of the substrate 300, stripping surface contaminants and the native oxide layer through physical sputtering. Simultaneously, the active oxygen atoms generated by the O2 plasma react chemically with residual organic impurities to produce gaseous products (CO2, H2O), which are then removed by the vacuum system. He, as an inert gas, helps stabilize and homogenize the plasma, improving processing uniformity.
[0036] After plasma treatment, the atomic bonds on the surface of the substrate 300 are broken, resulting in surface activation and a significant increase in surface energy. This provides more nucleation sites for subsequent passivation layer deposition, thereby greatly enhancing the film-substrate adhesion. Furthermore, directional plasma bombardment exhibits a higher sputtering rate at protruding, sharp trench opening edges. By controlling the bombardment energy and time, sharp corners can be preferentially removed, forming a rounded structure. From a mechanical perspective, sharp corners act as stress amplifiers, easily becoming the starting point for crack initiation. Rounding them disperses stress, eliminating the critical cracking hazard at its source.
[0037] Next, the HDP process is performed to deposit a passivation layer in the passivation trenches. HDP, also known as HDP CVD (High-Density Plasma Chemical Vapor Deposition), is a chemical vapor deposition technique that simultaneously performs deposition and sputtering, using high-density plasma to achieve thin film deposition and in-situ sputtering etching. Exemplarily, the HDP process and the preceding pretreatment steps are performed within the same reaction chamber of an HDP apparatus.
[0038] In this embodiment of the invention, a four-step HDP process is used for deposition. By precisely controlling the process parameters, the cracking rate is significantly reduced, the device reliability is improved, the process is simple and efficient, the cost is controllable, and there is no need to switch equipment, which reduces the introduction of impurities and ensures high device safety.
[0039] Specifically, a first passivation layer 302 is first deposited on the surface of the substrate 300 using a first HDP process. The material of the first passivation layer 302 can be silicon oxide (SiO2), silicon nitride (SiN), or silicon phosphosilicate glass (PSG), etc., which can be selected according to the device requirements. In this embodiment, the first passivation layer 302 is silicon oxide.
[0040] During the first HDP process, the chamber of the HDP equipment is heated to a predetermined temperature and deposition gases are introduced. When the material of the first passivation layer is silicon oxide, silane (SiH4) is used as the silicon source gas, oxygen (O2) is used as the oxygen source gas, and helium (He) or argon (Ar) is used as the carrier gas. The flow rate and ratio of each reaction gas can be set according to actual needs. During the gas introduction process, the radio frequency source is turned on to generate high-density plasma; at the same time, the radio frequency bias generator is turned on to establish a bias electric field on the wafer surface to control the plasma bombardment energy on the wafer.
[0041] The first HDP process employs a combination of low bombardment energy and high deposition rate to achieve rapid coverage of the bottom and sidewalls of the passivation trenches while keeping the initial film stress accumulation at a low level. Specifically, the bias power is set to 3000W to 5000W, which is considered medium-level, resulting in lower plasma bombardment energy and a weaker sputtering effect; the deposition rate is set to 4000A / min to 6000A / min, which is considered high-speed deposition. Due to the weak sputtering effect, the deposition process mainly involves deposition reactions, and the plasma bombardment has a limited effect on film removal. Therefore, the formed first passivation layer 302 is relatively loose, and its inherent intrinsic compressive stress is controlled at a low level, avoiding excessive stress accumulation in the initial filling stage. At the same time, the high deposition rate ensures process efficiency and achieves rapid coverage of the bottom and sidewalls of the trenches.
[0042] It should be noted that the first passivation layer 302 is relatively loose compared to subsequent passivation layers, but it is still denser than the film produced by PECVD (plasma-enhanced chemical vapor deposition) process, ensuring the reliability of the passivation layer.
[0043] For example, the first passivation layer 302 fills to 45% to 55% of the total depth of the passivation trench. This depth range is chosen to achieve rapid coverage of the trench bottom and sidewalls while avoiding excessive stress buildup in the initial filling stage.
[0044] Next, as Figure 3C As shown, a second HDP process is used to deposit a second passivation layer 303 on the first passivation layer 302. The bombardment energy of the second HDP process is higher than that of the first HDP process. Furthermore, the deposition rate of the second HDP process is lower than that of the first HDP process.
[0045] For example, the material of the second passivation layer 303 is the same as that of the first passivation layer 302, which is silicon oxide. The deposition gas also uses silane (SiH4), oxygen (O2), and carrier gas (He or Ar), and the gas flow rate range may be the same as or different from that of the first HDP process, which can be set according to actual needs. For example, the second passivation layer fills 75% to 85% of the total depth of the passivation trench.
[0046] After the first HDP process, significant protrusions form at the top of the passivation trenches and the edges of the openings. These protrusions create stress concentration points after subsequent deposition and capping. When internal stress exists throughout the passivation layer, the force lines twist and converge at the roots of these sharp, irregular protrusions, resulting in actual stress at these points being much higher than the average stress of the film. During subsequent thermal cycling, cracks readily initiate and propagate from these stress concentration points.
[0047] To address this issue, the second HDP process employs higher bombardment energy. This increased energy effectively smooths out protrusions and rough areas formed on the top and sidewalls of the trench, as the sputtering removal rate of directional plasma on these protruding areas is significantly higher than on flat and recessed regions. By increasing the bombardment energy, sharp geometric defects at stress concentration points that may form after capping can be fundamentally eliminated.
[0048] Furthermore, to achieve gradual smoothing of the protruding structure and avoid film damage caused by abrupt changes in bombardment energy, a step-by-step approach to increasing bombardment energy can be adopted. This means the second HDP process comprises multiple sub-steps, with the bombardment energy increasing in a stepwise manner in each sub-step. Simultaneously, to further enhance the sputtering effect and improve smoothing, the deposition rate can be gradually reduced, allowing the sputtering effect to gradually dominate the competition between deposition and sputtering; that is, the deposition rate of each sub-step gradually decreases.
[0049] Specifically, the second HDP process may include a first sub-step and a second sub-step executed sequentially: In the first sub-step, a medium-to-high bias power and a medium-to-low deposition rate are used, with the bias power increased to 4000W to 6000W and the deposition rate reduced to 3000A / min to 5000A / min. Compared with the first HDP process, the bias power is significantly increased, the bombardment energy is enhanced, and the sputtering effect is strengthened; the deposition rate is correspondingly reduced. This sub-step fills the lower middle part of the passivation trench and performs preliminary bombardment to flatten the protrusions at the top of the trench and the edge of the opening.
[0050] In the second sub-step, a high bias voltage power supply and a low deposition rate are employed, with the bias voltage power further increased to 5000W to 7000W and the deposition rate further reduced to 1500A / min to 3000A / min. Compared to the first sub-step, the bombardment energy is further enhanced, and the sputtering effect dominates; the deposition rate is reduced to a minimum, making the sputtering removal rate much higher than the deposition rate, ensuring that the plasma has sufficient bombardment time to deeply remove the protrusions. This sub-step fills the upper part of the passivation trench, using the strongest bombardment energy to deeply smooth the protrusions.
[0051] By progressively increasing bombardment energy and simultaneously decreasing the deposition rate in a stepwise manner, this step achieves gradual smoothing of the protruding structure. The design intent of this combined strategy is that as the filling depth increases, the protrusions above the trench become more prominent, requiring a stronger sputtering effect to effectively smooth them; at the same time, gradual adjustment can avoid film damage caused by abrupt changes in process parameters, ensuring a smooth and controllable smoothing process.
[0052] For example, during the execution of the second HDP process, the directionality of plasma bombardment can be enhanced and redeposition on the trench sidewalls reduced by adjusting the Ar to O2 gas flow rate ratio. A higher Ar flow rate increases the physical sputtering effect and improves bombardment directionality; a higher O2 flow rate enhances the oxidation reaction and increases the deposition rate. By optimizing the gas flow rate ratio, deposition and sputtering effects can be balanced to achieve optimal trench profile control.
[0053] Next, as Figure 3D As shown, the third passivation layer 304 is deposited on the second passivation layer 303 using the third HDP process. The bombardment energy of the third HDP process is lower than that of the second HDP process, that is, a relatively low bias power is used to achieve a smooth transition of the film.
[0054] Exemplarily, the material of the third passivation layer 304 is the same as that of the second passivation layer 303, which is silicon oxide. The deposition gas also uses silane (SiH4), oxygen (O2), and a carrier gas (He or Ar), with gas flow rates that are the same as or different from those of the second HDP process. Exemplarily, the third passivation layer fills to 92% to 96% of the total depth of the passivation trench.
[0055] After the high-impact planarization and filling process of the second HDP process, the protrusions at the top and middle of the trench have been effectively smoothed, and the trench profile has been optimized. However, if the process is switched directly from the high-impact planarization stage to the final rapid filling stage, the abrupt change in process parameters will lead to abrupt changes in film quality, namely, abrupt changes in film density and grain structure. Stress accumulation is likely to occur at the interface, which may lead to interface peeling and cracking during long-term use.
[0056] To address the aforementioned issues, this embodiment of the invention provides a transition buffer third HDP process between the second HDP process and the subsequent fourth HDP process. This process employs a moderate bombardment energy, meaning its bombardment energy is lower than that of the second HDP process but higher than that of the fourth HDP process, in order to achieve a smooth transition of the membrane material.
[0057] Specifically, the bias power of the third HDP process can be set to a medium level of 3000W to 5000W, and the deposition rate can be set to 70% to 85% of that of the first HDP process, specifically a medium-low level of 3000A / min to 5000A / min.
[0058] By maintaining moderate bombardment energy and a medium-low deposition rate, this step achieves a smooth transition in film density between the high-bombardment leveling stage and the final filling stage. The second HDP process uses high bombardment energy and a low deposition rate, resulting in a film with higher density; the fourth HDP process uses a high deposition rate and a medium-low bombardment energy, resulting in a relatively loose film. If the process directly switches from high bombardment and low deposition to high deposition and medium-low bombardment, the film density will change abruptly, and stress concentration will easily occur at the interface. This step uses bombardment energy and deposition rate between the two, allowing the film density to change continuously and avoiding abrupt changes in interfacial stress.
[0059] Next, as Figure 3E As shown, a fourth passivation layer 305 is deposited on the third passivation layer 304 using a fourth HDP process to fill the remaining space in the passivation trench. The deposition rate of the fourth HDP process is higher than that of the third HDP process to achieve rapid trench capping. Furthermore, the bias power of the fourth HDP process is lower than that of the third HDP process.
[0060] For example, the material of the fourth passivation layer 305 is the same as that of the third passivation layer 304, which is silicon oxide in this embodiment. The deposition gas is also silane (SiH4), oxygen (O2) and carrier gas (He or Ar), and the gas flow rate range remains unchanged.
[0061] After the transition buffer filling of the third HDP process, the passivation trench has reached 92% to 96% of its total depth, leaving little space. The purpose of this step is to quickly fill the remaining space while ensuring a smooth top cap to avoid creating new stress concentration points.
[0062] To achieve the above objectives, the fourth HDP process employs a high deposition rate and medium-low bombardment energy strategy. The high deposition rate is used to improve process efficiency and quickly fill the remaining space; the medium-low bombardment energy is used to ensure a flat top cap and avoid excessive bombardment that could lead to top depressions or film damage.
[0063] Specifically, the bias power for the fourth HDP process is set to a low to medium level of 2500W to 4500W, and the deposition rate is set to a high level of 4000A / min to 6000A / min. The deposition rate in this step is comparable to that of the first HDP process, which is considered high-speed deposition. The bias power is set to a low to medium level and can be fine-tuned according to the actual flatness of the trench top: if the top is basically flat, the bias power can be appropriately reduced to increase the deposition rate; if there are still slight protrusions on the top, the bias power can be appropriately increased for final trimming.
[0064] By employing a combination of high deposition rate and medium-to-low bombardment energy, this step achieves rapid filling of the remaining space in the passivation trenches. After the transition buffer of the third HDP process, the film surface is basically smooth with little remaining space. At this point, high bombardment energy is not required for smoothing; maintaining a moderate bombardment energy is sufficient to ensure the quality of the deposited film. Simultaneously, restoring a high deposition rate can significantly improve process efficiency and shorten the production cycle.
[0065] After the fourth passivation layer 305 is filled, the passivation trench is completely filled. The first passivation layer 302, the second passivation layer 303, the third passivation layer 304, and the fourth passivation layer 305 together constitute a thick passivation layer structure, achieving complete coverage and protection of the metal wire. Testing showed that the internal stress value of this thick passivation layer is controlled within a low stress range, the filling density meets the requirements for high-quality applications, and the cracking rate remains at an extremely low level after high-temperature aging.
[0066] Table 1 below shows exemplary parameter ranges for the four-stage HDP process of this invention. In summary, the first HDP process uses medium bias power and high deposition rate for rapid filling to control stress; the second HDP process uses higher bias power and lower deposition rate to remove protrusions and eliminate stress concentration points; the third HDP process uses medium bias power and medium-low deposition rate for transition buffering to avoid interfacial stress caused by abrupt changes in film quality; and the fourth HDP process uses high deposition rate and medium-low bias power for rapid capping.
[0067] Table 1. Exemplary parameter ranges for the four-stage HDP process. Figure 4 A passivation layer obtained by a manufacturing method according to an embodiment of the present invention is shown. The passivation layer has a smooth surface and is free of cracks.
[0068] In summary, the semiconductor device manufacturing method of this invention employs a multi-stage HDP process, significantly improving the crack resistance of the passivation layer. Furthermore, it utilizes a single HDP device throughout the entire process, simplifying the process, eliminating the need for equipment switching, and reducing impurity introduction. This process also eliminates the need for high-temperature annealing, avoiding potential damage to the active region of the device caused by thermal annealing, resulting in high device safety. The process also exhibits strong compatibility and can be widely applied to devices requiring thick passivation layer protection, such as power semiconductors and high-voltage integrated circuits.
[0069] The present invention also provides a semiconductor device that can be prepared by the method described in the first embodiment above.
[0070] Below, for reference Figure 3E The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For specific explanations and descriptions, please refer to the descriptions in the foregoing embodiments.
[0071] Specifically, such as Figure 3E As shown, the semiconductor device in this embodiment of the invention includes: 300 for the substrate; A top metal line 301 is formed on the surface of the substrate 300, and a passivation trench is formed between adjacent top metal lines 301. A thick passivation layer structure is formed on the surface of the substrate 300. The thick passivation layer structure includes a first passivation layer 302, a second passivation layer 303, a third passivation layer 304 and a fourth passivation layer 305 stacked sequentially from bottom to top. The first passivation layer 302 is formed by deposition using the first HDP process, filling 45% to 55% of the total depth of the passivation trench; The second passivation layer 303 is deposited using a second HDP process, covering the first passivation layer 302 and filling to 75% to 85% of the total depth of the passivation trench; The third passivation layer 304 is deposited using the third HDP process, covering the second passivation layer 303 and filling to 92% to 96% of the total depth of the passivation trench; The fourth passivation layer 305 is deposited using the fourth HDP process, covering the third passivation layer 304 and completely filling the passivation trench.
[0072] The semiconductor device of this invention is manufactured using the above method, therefore the passivation layer has no obvious interface abrupt change, the film is continuous and dense, the weak area of interface stress is eliminated, and the initiation and propagation of cracks are suppressed.
[0073] In another embodiment of the present invention, an electronic device is also provided, including the aforementioned semiconductor device, which is prepared according to the aforementioned method.
[0074] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.
[0075] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the surface of which is formed with passivation trenches; A first passivation layer is deposited in the passivation trench using a first high-density plasma process; A second passivation layer is deposited on the first passivation layer using a second high-density plasma process, wherein the bombardment energy of the second high-density plasma process is higher than that of the first high-density plasma process. A third passivation layer is deposited on the second passivation layer using a third high-density plasma process, wherein the bombardment energy of the third high-density plasma process is lower than that of the second high-density plasma process. A fourth passivation layer is deposited on the third passivation layer using a fourth high-density plasma process, wherein the deposition rate of the fourth high-density plasma process is higher than that of the third high-density plasma process.
2. The method according to claim 1, characterized in that, The second high-density plasma process includes multiple sub-steps, with the bombardment energy of each sub-step increasing in a stepwise manner and the deposition rate decreasing in a stepwise manner.
3. The method according to claim 2, characterized in that, The second high-density plasma process includes a first sub-step and a second sub-step executed sequentially; The bias power of the first sub-step is 4000W to 6000W, and the deposition rate is 3000A / min to 5000A / min. The bias power of the second sub-step is 5000W to 7000W, and the deposition rate is 1500A / min to 3000A / min.
4. The method according to claim 1, characterized in that, The deposition rate of the third high-density plasma process is greater than or equal to the deposition rate of the second high-density plasma process, and the bias power of the fourth high-density plasma process is lower than the bias power of the third high-density plasma process.
5. The method according to claim 4, characterized in that, The bias power of the first high-density plasma process is 3000W to 5000W, and the deposition rate is 4000A / min to 6000A / min. The bias power of the third high-density plasma process is 3000W to 5000W, and the deposition rate is 3000A / min to 5000A / min. The bias power of the fourth high-density plasma process is 2500W to 4500W, and the deposition rate is 4000A / min to 6000A / min.
6. The method according to claim 1, characterized in that, The first passivation layer fills to 45% to 55% of the total depth of the passivation trench; The second passivation layer fills to 75% to 85% of the total depth of the passivation trench; The third passivation layer fills to 92% to 96% of the total depth of the passivation trench; The fourth passivation layer completely fills the passivation trench.
7. The method according to claim 1, characterized in that, Before depositing the first passivation layer using the first high-density plasma process, the substrate surface is further pretreated, the pretreatment including surface activation and micromorphological modification of the substrate surface using plasma.
8. The method according to claim 7, characterized in that, The pretreatment uses a mixture of argon, oxygen and helium as the treatment gas, with a bias power of 1000W to 3000W and a treatment time of 3 to 10 seconds.
9. The method according to claim 7, characterized in that, The pretreatment, the first high-density plasma process, the second high-density plasma process, the third high-density plasma process, and the fourth high-density plasma process are performed in the same high-density plasma equipment.
10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-9.