A method for manufacturing a semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing an initial structure including a substrate and a channel layer located on a first surface of the substrate; implanting ions into portions of the substrate located on both sides of the channel layer to form implantation regions; forming source / drain electrodes on the implantation regions, the source / drain electrodes covering the sidewalls of the channel layer; etching the implantation regions from the side opposite to the source / drain electrodes to form a first contact hole exposing the source / drain electrodes; wherein the etching rate of the implantation regions is greater than the etching rate of other portions of the substrate excluding the implantation regions; and forming a first contact plug in the substrate, the first contact plug being at least partially located within the first contact hole and electrically connected to the source / drain electrodes.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] As manufacturing processes advance, some semiconductor devices (such as logic chips) have begun to adopt back-side power supply network (BSPDN) technology. This technology optimizes current transmission and reduces voltage drop by separating the power layer and signal layer in the chip and placing the power network on the back of the wafer.

[0003] However, as semiconductor devices continue to develop towards miniaturization and high integration, the distance between the source / drain region and the gate of the transistor in the semiconductor device is reduced, and the thinned wafer is prone to bending, which can cause the contact between the back power supply and the source / drain region to deviate and short-circuit with the gate. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0005] An initial structure is provided, the initial structure including a substrate and a channel layer located on a first surface of the substrate;

[0006] Ions are implanted into portions of the substrate located on both sides of the channel layer to form implantation regions;

[0007] A source / drain electrode is formed on the injection region, and the source / drain electrode covers the sidewall of the channel layer;

[0008] The implantation region is etched from the side opposite to the source / drain to form a first contact hole exposing the source / drain; wherein the etching rate of the implantation region is greater than the etching rate of other parts of the substrate excluding the implantation region;

[0009] A first contact plug is formed within the substrate, the first contact plug being at least partially located within the first contact hole and electrically connected to the source / drain.

[0010] In some embodiments, the doping concentration of the ions gradually increases in a direction from the first surface toward the interior of the substrate and perpendicular to the plane of the substrate; during the etching of the implanted region, the etching rate of the implanted region gradually decreases with etching time.

[0011] In some embodiments, the substrate further includes a second surface opposite to the first surface; and before etching the implantation region, it further includes:

[0012] A thinning process is performed on the second surface of the substrate to reduce the substrate to a predetermined thickness.

[0013] In some embodiments, the implantation region is exposed after a thinning process is performed on the second surface of the substrate; etching the implantation region from the side opposite to the source / drain includes:

[0014] An etching process is performed on the implantation region from the second surface of the substrate after the thinning process is performed to form a first contact hole exposing the source / drain electrodes;

[0015] Forming a first contact plug within the substrate includes:

[0016] The first contact plug is formed within the first contact hole.

[0017] In some embodiments, the implanted region is not exposed after a thinning process is performed on the second surface of the substrate; and after the thinning process is performed on the second surface of the substrate but before etching the implanted region, the process further includes:

[0018] The substrate is etched from a second surface after the thinning process is performed on the substrate to form a second contact hole that exposes the injection region;

[0019] Etching the implantation region from the side opposite to the source / drain includes:

[0020] The injection region is etched from the second contact hole to form a first contact hole that exposes the source / drain electrodes;

[0021] Forming a first contact plug within the substrate includes:

[0022] The first contact plug is formed within the first contact hole and the second contact hole.

[0023] In some embodiments, an initial structure is provided, including:

[0024] A substrate is provided, and a multilayer structure is formed on a first surface of the substrate, the multilayer structure comprising sacrificial layers and channel layers alternately stacked in a direction perpendicular to the plane of the substrate;

[0025] The multilayer structure and the substrate are patterned to form a stacked structure extending along a first direction and a fin-like structure located below the stacked structure, respectively.

[0026] Forming an isolation structure between the fin-like structures;

[0027] A dummy gate structure is formed that extends along the second direction and intersects with the stacked structure; the first direction and the second direction intersect and are parallel to the plane of the substrate 10;

[0028] The stacked structure and the fin structure are etched to form a groove between adjacent dummy gate structures, the groove cutting through the stacked structure along a second direction and penetrating the stacked structure in a direction perpendicular to the substrate plane;

[0029] Implanting ions into portions of the substrate located on both sides of the channel layer includes:

[0030] Ions are injected into the substrate from the bottom of the groove.

[0031] In some embodiments, after forming source / drain electrodes on the injection region, the method further includes:

[0032] A gate structure is formed, which replaces the sacrificial layer and the dummy gate structure and is disposed around the channel layer.

[0033] In some embodiments, the method further includes:

[0034] A dielectric layer is formed, which covers the gate structure and the source / drain;

[0035] The dielectric layer is etched to form a third contact hole and a fourth contact hole, respectively, the third contact hole exposing the source / drain electrode and the fourth contact hole exposing the gate structure;

[0036] A second contact plug is formed in the third contact hole, and the second contact plug is electrically connected to the source / drain electrode; a third contact plug is formed in the fourth contact hole, and the third contact plug is electrically connected to the gate structure.

[0037] In some embodiments, the ion includes at least one of argon, boron, germanium, phosphorus, helium, nitrogen, and oxygen.

[0038] In some embodiments, during the step of etching the implanted region, the etching selectivity ratio of the implanted region to other portions of the substrate excluding the implanted region is greater than or equal to 5:1.

[0039] In this embodiment, ions are implanted into the substrate below the growth region of the source / drain to form an implantation region, and then the source / drain is formed above the implantation region, achieving self-alignment between the implantation region and the source / drain. When etching the implantation region to form the first contact hole, the presence of ions makes the etching rate of the implantation region greater than the etching rate of other parts of the substrate except for the implantation region. In this way, the self-alignment between the first contact hole and the source / drain is achieved, thereby achieving self-alignment between the first contact plug and the source / drain, avoiding the first contact plug from deviating, and reducing the risk of short circuit between the first contact plug and other structures in the semiconductor structure (such as the gate structure or channel layer).

[0040] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and the drawings. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0043] Figures 2 to 19b This is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; wherein, Figure 3a This is a top view schematic diagram of the semiconductor structure during the fabrication process; Figure 3b For along Figure 3a A schematic diagram of the cross-sectional structure taken by line AA' in the diagram; Figure 4a , Figure 5a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a , Figure 17a , Figure 18a , Figure 19a These are schematic diagrams of the three-dimensional structure of the semiconductor structure during the fabrication process. Figure 4b , Figure 5b , Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b , Figure 12b , Figure 13b , Figure 14b , Figure 15b , Figure 16b , Figure 17b , Figure 18b , Figure 19b respectively along Figure 4a , Figure 5a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a , Figure 17a , Figure 18a , Figure 19a A schematic diagram of the cross-sectional structure taken from line BB' in the diagram. Figure 9c for Figure 9b A magnified view of the details in the central region Q.

[0044] Figures 20 to 22 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0045] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] As manufacturing processes advance, some semiconductor devices (such as logic chips) have begun to adopt back-side power supply network (BSPDN) technology. This technology separates the power and signal layers in the chip and places the power network on the back of the wafer, thereby optimizing current transmission and reducing voltage drop. However, as semiconductor devices continue to evolve towards miniaturization and high integration, the distance between the source / drain regions and the gate of transistors in semiconductor devices is decreasing, and the thinned wafers are prone to bending. This can cause the contact between the back-side power supply and the source / drain regions to deviate, resulting in a short circuit with the gate.

[0052] In related technologies, back-side power supply technology typically involves pre-drilling trenches below the source / drain regions and then growing an amorphous material layer within the trenches using chemical vapor deposition (CVD) as a sacrificial layer to achieve self-alignment of the back-side metal connections. However, this approach is complex overall, and it is difficult to subsequently form source / drain regions on the amorphous material layer using epitaxial growth (EPI) technology. This results in the source / drain regions not growing from the bottom up, thereby increasing the resistance of the source / drain regions.

[0053] Based on this, the technical solution of the present disclosure embodiment is proposed as follows:

[0054] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the preparation method includes the following steps:

[0055] Step S101: Provide an initial structure, the initial structure including a substrate and a channel layer located on a first surface of the substrate;

[0056] Step S102: Implant ions into the portion of the substrate located on both sides of the channel layer to form an implantation region;

[0057] Step S103: Form source / drain electrodes on the injection region, with the source / drain electrodes covering the sidewalls of the channel layer;

[0058] Step S104: Etch the implantation region from the side away from the source / drain to form a first contact hole exposing the source / drain; wherein the etching rate of the implantation region is greater than the etching rate of other parts of the substrate excluding the implantation region.

[0059] Step S105: Form a first contact plug in the substrate. The first contact plug is at least partially located in the first contact hole and electrically connected to the source / drain.

[0060] In this embodiment, ions are implanted into the substrate below the growth region of the source / drain to form an implantation region, and then the source / drain is formed above the implantation region, achieving self-alignment between the implantation region and the source / drain. When etching the implantation region to form the first contact hole, the presence of ions makes the etching rate of the implantation region greater than the etching rate of other parts of the substrate except for the implantation region. In this way, the self-alignment between the first contact hole and the source / drain is achieved, thereby achieving self-alignment between the first contact plug and the source / drain, avoiding the first contact plug from deviating, and reducing the risk of short circuit between the first contact plug and other structures in the semiconductor structure (such as the gate structure or channel layer).

[0061] It should be understood that, although Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0062] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this disclosure. Figure 3a To more clearly illustrate the extension and arrangement directions of the stacked structure, [the following is omitted]. Figure 3b The virtual gate dielectric layer in the middle; Figure 17a and Figure 18a The first sublayer in the first dielectric layer is omitted.

[0063] First, execute step S101, as follows: Figures 2 to 5b As shown, an initial structure 100 is provided, which includes a substrate 10 and a channel layer 112 located on a first surface S1 of the substrate 10.

[0064] Here, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 10 is a silicon substrate.

[0065] In some embodiments, an initial structure 100 is provided, including:

[0066] A substrate 10 is provided, and a multilayer structure 11' is formed on a first surface S1 of the substrate 10. The multilayer structure 11' includes sacrificial layers 111 and channel layers 112 (e.g., ...) stacked alternately in a direction perpendicular to the plane of the substrate 10. Figure 2 );

[0067] The multilayer structure 11' and the substrate 10 are patterned to form a stacked structure 11 extending along a first direction and a fin-like structure 101 located below the stacked structure 11, respectively; and an isolation structure 12 is formed between the fin-like structures 101 (e.g., Figure 3a and 3b );

[0068] A dummy gate structure 13 is formed that extends along the second direction and intersects with the stacked structure 11. The dummy gate structure 13 covers a portion of the stacked structure 11 and a portion of the isolation structure 12 along the second direction (e.g., Figure 4a and Figure 4b );

[0069] The stacked structure 11 and the fin structure 101 are etched to form a groove S between adjacent dummy gate structures 13. The groove S cuts through the stacked structure 11 along the second direction and penetrates the stacked structure 11 in a direction perpendicular to the plane of the substrate 10 (e.g., Figure 5a and Figure 5b ).

[0070] In some embodiments, the substrate 10 further includes a second surface S2 opposite to the first surface S1; the first surface S1 of the substrate 10 may be designated as... Figure 2 To be continued Figure 14b The upper surface of the substrate 10 and the second surface S2 of the substrate 10 can be indexed. Figure 2 To be continued Figure 14b The lower surface of the middle substrate 10.

[0071] In some embodiments, the sacrificial layer 111 and the channel layer 112 may be materials with high etch selectivity to each other, such that in a subsequent process, the sacrificial layer 111 can be removed without significantly removing the channel layer 112. In some embodiments, one of the sacrificial layer 111 and the channel layer 112 may be made of one or more of silicon or silicon carbide, and the other may be made of one or a combination of silicon-germanium, germanium, etc., and the channel layer 112 may be p-type doped or n-type doped, for example, silicon or silicon carbide with n-type doping, or silicon-germanium or germanium with p-type doping.

[0072] like Figures 3a to 3b As shown, in some embodiments, there can be multiple fin structures 101 and multiple stacked structures 11. These multiple fin structures 101 and multiple stacked structures 11 can be arranged along a second direction, which intersects the first direction and is parallel to the plane of the substrate 10. Specifically, the first direction and the second direction can be oblique or perpendicular.

[0073] Figure 3b The fin structure 101 shown is formed by etching the substrate 10. However, it is not limited to this; the fin structure 101 can also be obtained by forming a material layer.

[0074] Figure 3b The stacked structure 11 shown is formed by etching a multilayer structure 11'. However, it is not limited to this and can also be formed by using a mask combined with one or more thin-film processes.

[0075] The isolation structure 12 extends along a first direction for electrically isolating adjacent fin structures 101. In some embodiments, the fin structures 101 protrude from the isolation structure 12 in a direction perpendicular to the plane of the substrate 10. However, this is not the only possibility. Figure 3b As shown, the upper surfaces of the isolation structure 12 and the fin structure 101 can be flush or substantially flush. The material of the isolation structure 12 can be one or a combination of oxides, nitrides, and oxynitrides, among others.

[0076] See you again Figure 3a and Figure 3b In some embodiments, before forming the dummy gate structure 13, the method further includes forming a dummy gate dielectric layer 14 covering the exposed surface of the stacked structure 11. Specifically, the dummy gate dielectric layer 14 covers the sidewalls and top surface of the stacked structure 11. However, it is not limited to this; if the fin structure 101 protrudes from the isolation structure 12 in a direction perpendicular to the plane of the substrate 10, the dummy gate dielectric layer 14 may also cover the portion of the sidewall of the fin structure 101 protruding from the isolation structure 12. The material of the dummy gate dielectric layer 14 includes, but is not limited to, one or more of silicon oxide, silicon nitride, etc.

[0077] like Figure 4a and Figure 4b As shown, in some embodiments, there are multiple dummy gate structures 13, and the multiple dummy gate structures 13 and multiple stacked structures 11 are arranged in a cross manner; the multiple dummy gate structures 13 are arranged along a first direction and cover part of the stacked structure 11 and part of the isolation structure 12 along a second direction.

[0078] See you again Figure 4a and Figure 4b In some embodiments, the method further includes forming a mask layer 15 covering the upper surface of the dummy gate structure 13. In practice, a material layer of the dummy gate structure 13 may first be formed, covering the surfaces of the dummy gate dielectric layer 14 and the isolation structure 12, and filling the gaps between adjacent stacked structures 11. Then, a material layer of the mask layer 15 is formed on the material layer of the dummy gate structure 13. Subsequently, the material layers of the dummy gate structure 13 and the mask layer 15 are etched using the same etching process to form the dummy gate structure 13 and the mask layer 15 extending along the second direction, respectively.

[0079] In some embodiments, the mask layer 15 may be a multilayer stacked structure composed of multiple masks of the same or different materials.

[0080] See also Figure 4a and Figure 4b In some embodiments, after forming the mask layer 15, the method further includes: forming a first spacer layer 161, the first spacer layer 161 covering the semiconductor structure after forming the mask layer 15, and a second spacer layer 162 covering the first spacer layer 161. Specifically, the first spacer layer 161 covers the surfaces of the dummy gate dielectric layer 14, the dummy gate structure 13, the mask layer 15, and the isolation structure 12.

[0081] In some embodiments, the materials of the first spacer layer 161 and the second spacer layer 162 may be different, and the second spacer layer 162 may be formed of a material having an etch rate different from that of the first spacer layer 161. The materials of the first spacer layer 161 and the second spacer layer 162 include, but are not limited to, one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0082] In actual operation, during the formation of the above-mentioned film layers, including the sacrificial layer 111, the channel layer 112, the isolation structure 12, the dummy gate structure 13, the dummy gate dielectric layer 14, the mask layer 15, the first spacer layer 161, and the second spacer layer 162, the materials involved can be grown using one or more thin film deposition processes. Specifically, the thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), and combinations thereof.

[0083] See you again Figure 5a and Figure 5b In some embodiments, forming a groove S includes etching a stacked structure 11 and a fin structure 101 located below the stacked structure 11 using a dummy gate structure 13, a mask layer 15, a first spacer layer 161, and a second spacer layer 162 as masks, to form a groove S that cuts through the stacked structure 11 along a second direction and penetrates the stacked structure 11 in a direction perpendicular to the plane of the substrate 10. The groove S exposes the sidewalls of the sacrificial layer 111 and the channel layer 112. In some embodiments, a portion of the groove S is located within the fin structure 101.

[0084] In practice, the groove S can be formed by etching the stacked structure 11 and the fin structure 101 using anisotropic etching processes (such as plasma etching processes).

[0085] In some embodiments, a plurality of grooves S are formed in each stacked structure 11 and fin structure 101, the plurality of grooves S are arranged along a first direction, and the dummy gate structure 13 is located between two adjacent grooves S in the first direction.

[0086] In actual operation, before etching the stacked structure 11, a portion of the second spacer layer 162, a portion of the first spacer layer 161, and a portion of the dummy gate dielectric layer 14 located between adjacent dummy gate structures 13 are removed to expose the stacked structure 11 located between adjacent dummy gate structures 13 so as to facilitate etching of the stacked structure 11.

[0087] like Figure 5a and Figure 5b As shown, in some embodiments, during the formation of the groove S, a portion of the mask layer 15 and the first spacer layer 161 and the second spacer layer 162 covering the portion of the mask layer 15 are consumed.

[0088] Next, proceed with step S102, as follows: Figures 8a to 8b As shown, ions are implanted into a portion of the substrate 10 located on both sides of the channel layer 112 to form an implantation region 102.

[0089] Specifically, ions are implanted into portions of the substrate 10 located on both sides of the channel layer 112, including: implanting ions into the substrate 10 from the bottom of the groove S to form an implantation region 102, which extends from the bottom of the groove S into the interior of the substrate 10. In practice, an ion implantation process can be used to implant ions into the substrate 10.

[0090] like Figure 8b As shown, in some embodiments, the lower surface of the injection region 102 may be higher than the lower surface of the isolation structure 12, and the thickness of the injection region 102 in the direction perpendicular to the plane of the substrate 10 is less than the thickness of the fin structure 101 in the direction perpendicular to the plane of the substrate 10. The injection region 102 is located within the fin structure 101. However, this is not a limitation; the lower surface of the injection region 102 may also be lower than or flush with the lower surface of the isolation structure 12. This disclosure does not impose any special limitations on this aspect.

[0091] In some embodiments, the ions implanted into the substrate 10 include one or a combination of argon, boron, germanium, phosphorus, helium, nitrogen, oxygen, etc. By implanting ions into the substrate 10 to form an implantation region 102, the etching selectivity ratio between the implantation region 102 and other portions of the substrate 10 excluding the implantation region 102 can be changed.

[0092] In some embodiments, the projection of the injection region 102 in a direction perpendicular to the plane of the substrate 10 does not overlap with the projection of the channel layer 112 in a direction perpendicular to the plane of the substrate 10, thereby avoiding the subsequent formation of the first contact hole T1 (see...). Figure 18a and Figure 18b ) deviates from the exposed channel layer 112, thereby avoiding the subsequent formation of the first contact plug V1 (see Figure 19a and Figure 19b A short circuit occurred between the channel layer 112 and the channel layer 112.

[0093] like Figure 6 As shown, in some embodiments, before forming the injection region 102, the method further includes etching the sidewalls of the sacrificial layer 111 exposed by the groove S to cause the sidewalls of the sacrificial layer 111 exposed by the groove S to be recessed inward relative to the sidewalls of the channel layer 112 exposed by the groove S.

[0094] Figure 6The sidewalls of the etched sacrificial layer 111 shown extend in a straight line in a direction perpendicular to the plane of the substrate 10, but are not limited thereto; these sidewalls may also be recessed inward or convex outward. In practice, isotropic etching processes (e.g., wet etching) can be used to etch the sidewalls of the sacrificial layer 111. Specifically, in embodiments where the material of the sacrificial layer 111 includes, for example, silicon or silicon carbide, and the material of the channel layer 112 includes silicon germanium, the sidewalls of the sacrificial layer 111 can be etched using an etchant such as hydrogen fluoride.

[0095] Next, as Figures 7a to 7b As shown, after etching the sidewalls of the sacrificial layer 111 exposed by the groove S, the method further includes forming an inner spacer layer 17, which covers the sidewalls of the sacrificial layer 111 exposed by the groove S. In practice, the inner spacer layer 17 can be deposited by one or more thin-film processes, and the material of the inner spacer layer 17 can be one or a combination of silicon nitride or silicon oxynitride, among others.

[0096] Figure 7b The outer wall of the inner spacer 17 shown is flush with the side wall of the channel layer 112, but it is not limited thereto. The outer wall of the inner spacer 17 may also protrude outward from the side wall of the channel layer 112 or be recessed inward relative to the side wall of the channel layer 112.

[0097] See you again Figure 7a and Figure 7b In some embodiments, the second spacer layer 162 may also be removed before or after the formation of the inner spacer layer 17.

[0098] Next, proceed to step S103, as follows: Figures 9a to 9c As shown, a source / drain 18 is formed on the injection region 102, and the source / drain 18 covers the sidewall of the channel layer 112.

[0099] Specifically, the source / drain 18 covers the sidewalls of the channel layer 112 exposed by the recess S. In some embodiments, the source / drain 18 is also covered by an inner spacer layer 17, which separates the source / drain 18 from the sacrificial layer 111.

[0100] In this embodiment, ions are implanted into the substrate 10 below the growth region of the source / drain 18 to form an implantation region 102, and then the source / drain 18 is formed above the implantation region 102, thereby achieving self-alignment between the implantation region 102 and the source / drain 18.

[0101] In practice, the source / drain 18 can be formed above the injection region 102 by an epitaxial growth process. The epitaxial process can include chemical vapor deposition (CVD) processes (e.g., low-pressure chemical vapor deposition (LPCVD), vapor phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial growth processes or combinations thereof.

[0102] In some embodiments, the material of the source / drain 18 includes semiconductor materials, such as one or more of silicon, silicon carbide, silicon germanium, germanium, germanium tin, etc., and the source / drain 18 may have N-type or P-type doping. When the source / drain 18 has N-type or P-type doping, the doping type of the source / drain 18 is opposite to the doping type of the channel layer 112, and the source / drain 18 may be doped using an in-situ doping process or an ion implantation process.

[0103] In some embodiments, the source / drain 18 may include multiple semiconductor material layers, which may be formed of the same or different semiconductor materials and may be doped to different dopant concentrations. For example... Figure 9c As shown, in some embodiments, the source / drain 18 may include a first semiconductor material layer 181, a second semiconductor material layer 182, and a third semiconductor material layer 183 stacked sequentially from bottom to top on the implantation region 102. The material of the first semiconductor material layer 181 may be silicon, and the materials of the second semiconductor material layer 182 and the third semiconductor material layer 183 may be silicon-germanium. The ratio of silicon to germanium in the second semiconductor material layer 182 may be less than the ratio of silicon to germanium in the third semiconductor material layer 183. For example, the ratio of silicon to germanium in the second semiconductor material layer 182 may be 1:1, and the ratio of silicon to germanium in the third semiconductor material layer 183 may be 7:3.

[0104] Next, as Figure 10a and Figure 10b As shown, after forming the source / drain 18, the method further includes:

[0105] A first dielectric layer 19 is formed, which extends along a second direction between adjacent dummy gate structures 13 and covers the source / drain 18.

[0106] A planarization process is performed to make the top surfaces of the first dielectric layer 19 and the dummy gate structure 13 flush or relatively flush.

[0107] In some embodiments, after performing the planarization process, a portion of the mask layer 15 may be retained, in which case the planarization process makes the top surfaces of the first dielectric layer 19 and the mask layer 15 flush.

[0108] In some embodiments, the first dielectric layer 19 may include a first sublayer 191 and a second sublayer 192, the second sublayer 192 filling the gaps between adjacent dummy gate structures 13, and the first sublayer 191 located between the second sublayer 192 and the first spacer layer 161, the source / drain 18 and the isolation structure 12.

[0109] The material of the first sublayer 191 includes, but is not limited to, one or a combination of silicon nitride, silicon oxide, and silicon oxynitride; the material of the second sublayer 192 includes, but is not limited to, one or a combination of phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, and undoped silicate glass.

[0110] Next, as Figures 11a to 13b As shown, after forming the first dielectric layer 19, the method further includes forming a gate structure 202, which replaces the sacrificial layer 111 and the dummy gate structure 13 and is disposed around the channel layer 112.

[0111] In some embodiments, before forming the gate structure 202, the method further includes forming a gate dielectric layer 201, wherein the gate dielectric layer 201 is located at least between the gate structure 202 and the channel layer 112.

[0112] Specifically, forming the gate dielectric layer 201 and the gate structure 202 includes: first, removing the dummy gate structure 13 (or the dummy gate structure 13 and the mask layer 15) to form an opening P1, and then removing the portion of the dummy gate dielectric layer 14 exposed by the opening P1 (e.g., ...) Figure 11a and Figure 11b Next, the sacrificial layer 112 is removed from the opening P1 to form a void P2 between the channel layers 112 (e.g., Figure 12a and Figure 12b Next, a gate dielectric layer 201 is conformally formed in the opening P1 and the gap P2, the gate dielectric layer 201 at least covering the surface of the channel layer 112; then, a gate structure 202 is filled in the opening P1 and the gap P2, the gate structure 202 extending along the second direction and disposed around the channel layer 112 (e.g. Figure 13a and Figure 13b ).

[0113] In practice, anisotropic dry etching can be used to remove the dummy gate structure 13 (or the dummy gate structure 13 and the mask layer 15) and part of the dummy gate dielectric layer 14, and an isotropic wet etching can be used to remove the sacrificial layer 112.

[0114] In some embodiments, the material of the gate dielectric layer 201 can be a high dielectric constant material, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0115] In some embodiments, the gate structure 202 may be a single-layer or multi-layer structure, and the material of the gate structure 202 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy, such as titanium nitride (TiN).

[0116] Next, as Figure 14a and Figure 14b As shown, the method further includes: forming a second dielectric layer 21, the second dielectric layer 21 covering the first dielectric layer 19, the gate dielectric layer 201 and the gate structure 202.

[0117] In some embodiments, the second dielectric layer 21 may have a single-layer or multi-layer structure, and the material of the second dielectric layer 21 includes, but is not limited to, one or a combination of silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, and undoped silicate glass.

[0118] The first dielectric layer 19 and the second dielectric layer 21 constitute the dielectric layer 22; see again Figure 14a and Figure 14b In some embodiments, after forming the dielectric layer 22, the method further includes: etching the dielectric layer 22 to form a third contact hole T3 and a fourth contact hole T4, respectively, wherein the third contact hole T3 exposes the source / drain 18 and the fourth contact hole T4 exposes the gate structure 202;

[0119] A second contact plug V2 is formed in the third contact hole T3, and the second contact plug V2 is electrically connected to the source / drain electrode 18; a third contact plug V3 is formed in the fourth contact hole T4, and the third contact plug V3 is electrically connected to the gate structure 202.

[0120] Specifically, the third contact hole T3 penetrates the second dielectric layer 21 and the first dielectric layer 19 in a direction perpendicular to the plane of the substrate 10 and exposes the source / drain electrode 18, and the fourth contact hole T4 penetrates the second dielectric layer 21 in a direction perpendicular to the plane of the substrate 10 and exposes the gate structure 202.

[0121] See also Figure 14a and Figure 14bIn some embodiments, before forming the second contact plug V2, the method further includes forming a metal compound layer 23 at the bottom of the third contact hole T3, the metal compound layer 23 being located between the source / drain electrode 18 and the second contact plug V2. In practice, the metal compound layer 23 can be formed by depositing a metal material at the bottom of the third contact hole T3, the metal material being able to react with the source / drain electrode 18 below to form the metal compound layer 23. For example, if the materials of the source / drain electrode 18 are silicon, germanium, and silicon-germanium, the materials of the metal compound layer 23 are metal silicide, metal germanide, and metal silicon-germaniumide, respectively; wherein the metal material may include nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof.

[0122] In some embodiments, the second contact plug V2 and the third contact plug V3 may each include one or more layers, such as a barrier layer, a diffusion layer, and a conductive filler material. For example, in some embodiments, the second contact plug V2 and the third contact plug V3 each include a barrier layer and a conductive filler material. The material of the barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive filler material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc.

[0123] In subsequent processes, a front interconnect layer that is electrically connected to the second contact plug V2 and the third contact plug V3 can also be formed on the dielectric layer 22.

[0124] Next, proceed to step S103, as follows: Figures 18a to 18b As shown, the implantation region 102 is etched from the side away from the source / drain 18 to form a first contact hole T1 that exposes the source / drain 18; wherein the etching rate of the implantation region 102 is greater than the etching rate of other parts of the substrate 10 excluding the implantation region 102.

[0125] like Figure 16a and Figure 16b As shown, in some embodiments, prior to the etching injection region 102, the following is also included:

[0126] A thinning process is performed on the second surface S2 of the substrate 10 to reduce the substrate 10 to a predetermined thickness.

[0127] like Figure 15a and Figure 15b As shown, in some embodiments, the semiconductor structure can be flipped so that the second surface S2 of the substrate 10 faces upward before performing a thinning process on the second surface S2 of the substrate 10.

[0128] In some embodiments, a thinning process is performed on the second surface S2 of the substrate 10, including a planarization process, an etch-back process, etc., wherein the planarization process includes a mechanical polishing process, a chemical mechanical polishing process, etc., and the mechanical polishing process includes a coarse grinding process, a fine grinding process, etc. In the embodiments of this disclosure, one or more of these processes can be used to thin the second surface S2 of the substrate 10.

[0129] like Figure 16a and Figure 16b As shown, in some embodiments, the implantation region 102 is not exposed after a thinning process is performed on the second surface S2 of the substrate 10; as Figure 17a and Figure 17b As shown, in some embodiments, after the thinning process is performed on the second surface S2 of the substrate 10, and before etching the implantation region 102 to form the first contact hole T1 exposing the source / drain 18, the method further includes etching the substrate 10 from the second surface S2 after the thinning process is performed on the substrate 10 to form the second contact hole T2 exposing the implantation region 102.

[0130] See you again Figure 18a and Figure 18b The implantation region 102 is etched from the side away from the source / drain 18, including: etching the implantation region 102 from the second contact hole T2 to form a first contact hole T1 that exposes the source / drain 18.

[0131] In practice, the second contact hole T2 and the first contact hole T1 can be formed using the same etching process or different etching processes. For example, a mask pattern can be formed on the second surface S2 of the substrate 10, and then an etching process (e.g., anisotropic dry etching process) can be performed using the mask pattern as a mask to sequentially form the first contact hole T1 and the second contact hole T2. However, it is not limited to this. Alternatively, the substrate 10 can be etched first using anisotropic dry etching process with the mask pattern as a mask to form the second contact hole T2, and then a different etching process (e.g., wet process) can be used to form the first contact hole T1.

[0132] In the step of etching the implantation region 102 in this embodiment, the etching rate of the implantation region 102 is greater than the etching rate of other parts of the substrate 10 excluding the implantation region 102. This is due to the effect of ion implantation in the implantation region 102 in this embodiment. In this embodiment, ions are pre-implanted into the substrate 10 below the growth region of the source / drain 18 to form the implantation region 102, and then the source / drain 18 is formed above the implantation region 102, achieving self-alignment between the implantation region 102 and the source / drain 18. When etching the implantation region 102 to form the first contact hole T1, the presence of ions ensures that the etching rate of the implantation region 102 is greater than the etching rate of other parts of the substrate 10 excluding the implantation region 102. This achieves self-alignment between the first contact hole T1 and the source / drain 18, and further achieves self-alignment between the source / drain 18 and the subsequently formed first contact plug V1, avoiding misalignment of the first contact plug V1 and reducing the risk of short circuit between the first contact plug V1 and the gate structure 202 or channel layer 112 in the semiconductor structure.

[0133] In some embodiments, during the etching of the implantation region 102, the etching selectivity ratio of the implantation region 102 to other portions of the substrate 10 excluding the implantation region 102 is greater than or equal to 5:1, such as 5:1, 8:1, 10:1, 20:1, 50:1, 100:1, etc. In this way, the implantation region 102 can be removed quickly without significantly removing other structures outside the implantation region 102, reducing the risk of the first contact hole T1 extending to both sides along the first direction and exposing the channel layer 112 or the gate structure 202.

[0134] In some embodiments, during the step of etching the implantation region 102, the etching rate of the implantation region 102 is also greater than the etching rate of the isolation structure 12, so that the implantation region 102 can be removed quickly without significantly removing the isolation structure 12.

[0135] In some embodiments, during the step of etching the implantation region 102, the etching rate of the implantation region 102 is also greater than the etching rate of the portion of the source / drain 18 (e.g., the first semiconductor material layer 181) that is in direct contact with the implantation region 102. In this way, the implantation region 102 can be removed while the source / drain 18 is not significantly etched, thereby avoiding or reducing damage to the source / drain 18.

[0136] In some embodiments, the ion doping concentration gradually increases in the direction from the first surface S1 to the second surface S2 and parallel to the plane of the substrate 10; during the etching of the implantation region 102, the etching rate of the implantation region 102 gradually decreases with the etching time. Thus, as the etching time increases, the etching rate of the implantation region 102 gradually slows down as it approaches the source / drain 18, thereby avoiding over-etching of the implantation region 102 and thus avoiding damage to the source / drain 18.

[0137] In practice, by controlling parameters such as the dose and energy of the implanted ions, a multi-implantation process can be used to form an implantation region 102 with gradually increasing ion doping concentration. In some embodiments, the ion doping concentration can gradually increase in a uniform, exponential, or gradient manner in the direction from the first surface S1 to the second surface S2 and parallel to the plane of the substrate 10.

[0138] Next, proceed to step S105, as follows: Figure 19a and Figure 19b As shown, a first contact plug V1 is formed in the substrate 10. The first contact plug V1 is at least partially located in the first contact hole T1 and is electrically connected to the source / drain 18.

[0139] In some embodiments, a first contact plug V1 is formed within the substrate 10, including:

[0140] A first contact plug V1 is formed in the first contact hole T1 and the second contact hole T2.

[0141] In practice, one or more thin-film deposition processes can be used to first form a conductive material layer that fills the first contact hole T1 and the second contact hole T2 and covers the second surface S2 of the substrate 10. Then, a planarization process is performed on the conductive material layer to form a first contact plug V1 located within the first contact hole T1 and the second contact hole T2. In some embodiments, the material of the first contact plug V1 includes one or a combination of copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, etc.

[0142] Figure 16a and Figure 16b The implantation region 102 shown is not exposed after a thinning process is performed on the second surface S2 of the substrate 10. However, this is not the only possibility. Figure 20 As shown, in some embodiments, the implantation depth of ions can be controlled by adjusting the ion implantation dose and implantation energy, thereby controlling the thickness of the implantation region 102 so that the implantation region 102 is exposed after a thinning process is performed on the second surface S2 of the substrate 10.

[0143] Next, as Figure 21As shown, in some embodiments, the implantation region 102 is etched from the side opposite to the source / drain 18 to form a first contact hole T1 exposing the source / drain 18, including:

[0144] The second surface S2, after the substrate 10 is thinned, performs an etching process on the implantation region 102 to form the first contact hole T1 that exposes the source / drain 18.

[0145] Next, as Figure 22 As shown, in some embodiments, a first contact plug V1 is formed within the substrate 10, including:

[0146] A first contact plug V1 is formed inside the first contact hole T1.

[0147] Thus, the step of forming the second contact hole T2 is omitted, which simplifies the process steps and further improves the self-alignment accuracy of the first contact plug V1 and the source / drain electrode 18.

[0148] In some embodiments, after forming the first contact plug V1, a back-side interconnect layer electrically connected to the first contact plug V1 may also be formed on the second surface S2 of the substrate 10.

[0149] As can be seen, in this embodiment, an implantation region 102 is formed in the substrate 10 beforehand, such that the etching rate of the implantation region 102 is greater than the etching rate of other parts of the substrate 10 except for the implantation region 102 when etching the implantation region 102. In this way, the self-alignment of the first contact hole T1 and the source / drain 18 is achieved, thereby achieving the self-alignment of the first contact plug V1 with the source / drain 18, avoiding the deviation of the first contact plug V1, and reducing the risk of short circuit between the first contact plug V1 and the gate structure 202 or the channel layer 112 in the semiconductor structure.

[0150] It should be noted that the method for preparing the semiconductor structure provided in this disclosure can be applied to any semiconductor device including the structure, and no further limitations are imposed here.

[0151] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: An initial structure is provided, the initial structure including a substrate and a channel layer located on a first surface of the substrate; Ions are implanted into portions of the substrate located on both sides of the channel layer to form implantation regions; A source / drain electrode is formed on the injection region, and the source / drain electrode covers the sidewall of the channel layer; The implantation region is etched from the side opposite to the source / drain to form a first contact hole exposing the source / drain; wherein the etching rate of the implantation region is greater than the etching rate of other parts of the substrate excluding the implantation region; A first contact plug is formed within the substrate, the first contact plug being at least partially located within the first contact hole and electrically connected to the source / drain.

2. The manufacturing method according to claim 1, characterized in that, In a direction from the first surface toward the interior of the substrate and perpendicular to the plane of the substrate, the doping concentration of the ions gradually increases; during the etching of the implanted region, the etching rate of the implanted region gradually decreases with etching time.

3. The manufacturing method according to claim 1, characterized in that, The substrate further includes a second surface opposite to the first surface; prior to etching the implantation region, it also includes: A thinning process is performed on the second surface of the substrate to reduce the substrate to a predetermined thickness.

4. The manufacturing method according to claim 3, characterized in that, The implantation region is exposed after a thinning process is performed on the second surface of the substrate; Etching the implantation region from the side opposite to the source / drain includes: An etching process is performed on the implantation region from the second surface of the substrate after the thinning process is performed to form a first contact hole exposing the source / drain electrodes; Forming a first contact plug within the substrate includes: The first contact plug is formed within the first contact hole.

5. The manufacturing method according to claim 3, characterized in that, The implanted region is not exposed after a thinning process is performed on the second surface of the substrate; after the thinning process is performed on the second surface of the substrate and before etching the implanted region, the process further includes: The substrate is etched from a second surface after the thinning process is performed on the substrate to form a second contact hole that exposes the injection region; Etching the implantation region from the side opposite to the source / drain includes: The injection region is etched from the second contact hole to form a first contact hole that exposes the source / drain electrodes; Forming a first contact plug within the substrate includes: The first contact plug is formed within the first contact hole and the second contact hole.

6. The manufacturing method according to claim 1, characterized in that, Provide an initial structure, including: A substrate is provided, and a multilayer structure is formed on a first surface of the substrate, the multilayer structure comprising sacrificial layers and channel layers alternately stacked in a direction perpendicular to the plane of the substrate; The multilayer structure and the substrate are patterned to form a stacked structure extending along a first direction and a fin-like structure located below the stacked structure, respectively. Forming an isolation structure between the fin-like structures; A dummy gate structure is formed that extends along a second direction and intersects with the stacked structure; the first direction and the second direction intersect and are parallel to the substrate plane; The stacked structure and the fin structure are etched to form a groove between adjacent dummy gate structures, the groove cutting through the stacked structure along a second direction and penetrating the stacked structure in a direction perpendicular to the substrate plane; Implanting ions into portions of the substrate located on both sides of the channel layer includes: Ions are injected into the substrate from the bottom of the groove.

7. The manufacturing method according to claim 6, characterized in that, After forming the source / drain on the injection region, the method further includes: A gate structure is formed, which replaces the sacrificial layer and the dummy gate structure and is disposed around the channel layer.

8. The manufacturing method according to claim 7, characterized in that, The method further includes: A dielectric layer is formed, which covers the gate structure and the source / drain; The dielectric layer is etched to form a third contact hole and a fourth contact hole, respectively, the third contact hole exposing the source / drain electrode and the fourth contact hole exposing the gate structure; A second contact plug is formed in the third contact hole, and the second contact plug is electrically connected to the source / drain electrode; a third contact plug is formed in the fourth contact hole, and the third contact plug is electrically connected to the gate structure.

9. The manufacturing method according to any one of claims 1-8, characterized in that, The ions include at least one of argon, boron, germanium, phosphorus, helium, nitrogen, and oxygen.

10. The manufacturing method according to any one of claims 1-8, characterized in that, In the step of etching the implanted region, the etching selectivity ratio of the implanted region to other parts of the substrate excluding the implanted region is greater than or equal to 5:1.

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