Semiconductor structure and method of manufacturing the same, electronic device
By forming a doped layer and a barrier layer on a semiconductor material layer and performing thermal annealing, the problem of transistor turn-off difficulty caused by oxygen vacancies is solved, thereby improving the control capability of transistors and device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
Smart Images
Figure CN122248978A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to semiconductor structures and their fabrication methods, and electronic devices. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.
[0003] To meet the demands, it is desirable to maintain good performance of device units while reducing their size. Summary of the Invention
[0004] Based on this, a semiconductor structure, its fabrication method, and an electronic device are provided.
[0005] In a first aspect, this application provides a method for fabricating a semiconductor structure, the method comprising the following steps:
[0006] A substrate is provided, and a semiconductor material layer is formed on the substrate;
[0007] A doped layer is formed on one side of the semiconductor material layer; the doped layer includes a target doping element.
[0008] A barrier layer is formed on the side of the doped layer away from the semiconductor material layer;
[0009] The obtained structure is subjected to thermal annealing to obtain a semiconductor layer doped with the target doping element.
[0010] In one embodiment, providing a substrate and forming a semiconductor material layer on the substrate includes:
[0011] A stacked structure is formed on the substrate, the stacked structure comprising alternating layers of multiple first dielectric layers and multiple layers of second dielectric layers;
[0012] The stacked structure is etched to form a first hole; the first dielectric layer is etched based on the first hole to form a first receiving groove;
[0013] An initial semiconductor material layer, a gate dielectric layer, and a conductive layer are sequentially stacked in the first receiving groove and the first hole;
[0014] The stacked structure is etched to form a first trench located on at least one side of the first receiving groove; wherein, a plurality of the first holes are arranged in a row along a first direction, and the first trench extends along the row direction and penetrates the stacked structure;
[0015] Based on the first trench, the first dielectric layer is etched in a direction close to the first hole, and the initial semiconductor material layer in the first accommodating trench is etched to form a second accommodating trench and the semiconductor material layer separated by the second accommodating trench; the second accommodating trench exposes the gate dielectric layer;
[0016] The doped layer and the barrier layer are sequentially formed in the second accommodating trench and the first trench.
[0017] In one embodiment, providing a substrate and forming a semiconductor material layer on the substrate, and stacking a doped layer and a barrier layer on one side of the semiconductor material layer, includes:
[0018] A stacked structure is formed on the substrate, the stacked structure comprising alternating layers of multiple first dielectric layers and multiple layers of second dielectric layers;
[0019] The stacked structure is etched to form a first hole; the first dielectric layer is etched based on the first hole to form a first receiving groove;
[0020] A semiconductor material layer, a doped layer, and a barrier layer are sequentially stacked in the first receiving groove and the first hole;
[0021] The step of performing thermal annealing on the obtained structure to obtain a semiconductor layer doped with the target doping element includes:
[0022] The obtained structure is subjected to thermal annealing to form an initial semiconductor layer doped with the target doping element;
[0023] Remove the barrier layer and the doped layer;
[0024] Remove the initial semiconductor layer in the first hole, so that the initial semiconductor layer remaining in the first receiving groove forms the semiconductor layer.
[0025] In one embodiment, it further includes:
[0026] A gate dielectric layer and a conductive layer are sequentially stacked within the first receiving groove and the first hole; wherein the gate dielectric layer covers the semiconductor layer.
[0027] In one embodiment, the sequential stacking of a semiconductor material layer, a doped layer, and a barrier layer within the first receiving trench and the first hole further includes:
[0028] A semiconductor material layer, a gate dielectric material layer, a doped layer, and a barrier layer are sequentially stacked in the first accommodating groove and the first hole;
[0029] The formation of the gate dielectric layer in the first receiving groove and the first hole includes: forming a gate dielectric layer integrally connected with the remaining gate dielectric material layer in the first receiving groove.
[0030] In one embodiment, the target doping element includes fluorine.
[0031] In one embodiment, the doping concentration of fluorine in the semiconductor layer is less than or equal to 4E21cm. -3 .
[0032] In one embodiment, the doped layer is a polymer layer comprising fluorine ions, and the doped layer is obtained by initiating chemical vapor deposition or atomic layer deposition.
[0033] The formation process of the barrier layer and / or the doped layer includes: initiation chemical vapor deposition or atomic layer deposition.
[0034] In one embodiment, the temperature range of the heat treatment includes 250°C to 400°C.
[0035] Secondly, this application also provides a semiconductor structure, comprising:
[0036] A stacked structure includes multiple layers of first dielectric layers and multiple layers of second dielectric layers stacked alternately; the stacked structure has a first hole penetrating each of the first dielectric layers and the second dielectric layers, and a first receiving groove located in the first dielectric layer and surrounding the first hole;
[0037] A semiconductor layer is located on the inner wall of the first accommodating trench, or on the inner wall of the first hole between adjacent first accommodating trenches; wherein the material of the semiconductor layer includes a metal oxide material containing the target doping element.
[0038] In one embodiment, the semiconductor layer is located on the inner wall of the first hole between adjacent first receiving trenches; the semiconductor structure further includes:
[0039] A gate dielectric layer covers the semiconductor layer and the inner wall of the first accommodating trench;
[0040] A conductive layer is located on the side of the gate dielectric layer away from the semiconductor layer.
[0041] In one embodiment, the semiconductor structure further includes a doped layer comprising the target doping element, wherein the target doping element is fluorine; the doped layer is located on the side of the semiconductor layer away from the stacked structure.
[0042] In one embodiment, the semiconductor layer is located on the inner wall of the first accommodating trench; the semiconductor structure further includes:
[0043] A gate dielectric layer that covers the semiconductor layer, or covers the semiconductor layer and the inner wall of the first hole;
[0044] A conductive layer covers the gate dielectric layer and fills the first receiving groove and the first hole.
[0045] In one embodiment, the target doping element is fluorine, and the doping concentration of fluorine in the metal oxide material is less than or equal to 4E21cm. -3 .
[0046] Thirdly, this application also provides an electronic device, including a semiconductor structure prepared by the method described above; or the semiconductor structure described above.
[0047] In the above-described semiconductor structure fabrication method, a semiconductor material layer is formed on a substrate. This semiconductor material layer includes an oxygen-vacancy-containing material. A doped layer and a barrier layer are then stacked on the semiconductor material layer. In the repair process, target dopant ions in the doped layer flow into the semiconductor material layer to fill oxygen vacancies, thereby reducing the oxygen vacancy concentration in the semiconductor material layer. Simultaneously, the barrier layer is located on the side of the doped layer furthest from the semiconductor material layer. This barrier layer can block the flow of dopant ions, ensuring that the dopant ions flow into the interior of the semiconductor material layer. In conventional techniques, the presence of oxygen vacancies may make it difficult to turn off transistors. The fabrication method provided in this application enables dopant ions to fill oxygen vacancies, improving the controllability of the transistor. Attached Figure Description
[0048] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure in one embodiment.
[0049] Figure 2 This is an enlarged view of the structure forming the semiconductor material layer in one embodiment.
[0050] Figure 3 for Figure 2 A magnified view of a portion of the semiconductor structure shown.
[0051] Figure 4 This is a schematic diagram of the structure in one embodiment where a doped layer is formed.
[0052] Figure 5 This is a schematic diagram of the structure forming the barrier layer in one embodiment.
[0053] Figure 6 This is a schematic diagram of a semiconductor structure prepared in one embodiment.
[0054] Figure 7 This is a schematic diagram of the structure forming a semiconductor material layer in another embodiment.
[0055] Figure 8 This is a schematic diagram of the structure in another embodiment where a doped layer is formed.
[0056] Figure 9 This is a schematic diagram of the structure forming the barrier layer in another embodiment.
[0057] Explanation of reference numerals in the attached figures:
[0058] 110. Substrate; 120. Stacked structure; 122. First dielectric layer; 124. Second dielectric layer; 126. First via; 128. First accommodating trench; 130. Semiconductor layer; 132. Semiconductor material layer; 134. Gate dielectric layer; 136. Conductive layer; 140. First trench; 142. Doped layer; 144. Barrier layer. Detailed Implementation
[0059] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0061] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When using “comprising,” “having,” and “including” as described herein, another component may be added unless explicitly qualified terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.
[0062] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.
[0063] In the description of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.
[0064] It should be noted that the illustrations provided in this embodiment are only schematic representations of the preferred embodiments of this disclosure. The type, quantity, and proportion of each component in this embodiment may also be changed, and the component layout may be more complex.
[0065] Reference Figure 1 This application discloses a flowchart of a method for preparing a semiconductor structure, including the following steps S12-S18.
[0066] S12, a substrate 110 is provided, and a semiconductor material layer 132 is formed on the substrate 110.
[0067] Exemplarily, substrate 110 may include, but is not limited to, a silicon (Si) substrate 110. Substrate 110 may also include silicon-germanium (SiGe) substrate 110, silicon-germanium-carbon (SiGeC) substrate 110, silicon carbide (SiC) substrate 110, gallium arsenide (GaAs) substrate 110, indium arsenide (InAs) substrate 110, indium phosphide (InP) substrate 110, or other III / V semiconductor substrates 110 or II / VI semiconductor substrates 110. Alternatively, for example, substrate 1101 may also include semiconductor substrates 110 such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 110 should not limit the scope of protection of this application. Exemplarily, substrate 110 may also refer to a dielectric layer formed on silicon.
[0068] For example, the semiconductor material layer 132 can serve as a channel layer.
[0069] For example, the semiconductor material layer 132 includes an oxygen-vacancy material layer, which is composed of a material containing oxygen vacancies. An oxygen vacancy is a vacancy formed by the absence of an oxygen atom in a crystal structure. This absence typically occurs in oxide materials, where the position of an oxygen atom in the crystal lattice is replaced by a vacancy. For example, the oxygen-vacancy material layer may be IGZO (Indium Gallium Zinc Oxide).
[0070] S14, a doped layer 142 is formed on one side of the semiconductor material layer 132; the doped layer 142 includes target dopant ions.
[0071] For example, the doped layer 142 is in direct contact with the semiconductor material layer 132, or indirect contact with the semiconductor material layer 132 through a dielectric layer.
[0072] For example, when the dielectric layer and the semiconductor material layer 132 are in indirect contact, the dielectric layer can be formed on the semiconductor material layer 132 first, and then the doped layer 142 can be formed on the dielectric layer. Optionally, the dielectric layer can be a dielectric material, including but not limited to silicon oxide, silicon oxynitride, or any combination thereof. It is understood that the target dopant ions can flow through the dielectric layer to the semiconductor material layer 132.
[0073] S16, a barrier layer 144 is formed on the side of the doped layer 142 away from the semiconductor material layer 132.
[0074] The barrier layer 144 covers the side of the doped layer 142 away from the semiconductor material layer 132 and is used to block the target doped ions from flowing away from the semiconductor material layer 132.
[0075] S18, the obtained structure is subjected to thermal annealing to obtain a semiconductor layer 130 doped with the target doping element.
[0076] For example, the semiconductor structure is placed in a heat treatment environment to allow target dopant ions to flow into the semiconductor material layer 132 for doping. Further, when the semiconductor material layer 132 contains oxygen-vacancy material, the target dopant ions can flow into the oxygen vacancies in the oxygen-vacancy material to fill some of the oxygen vacancies.
[0077] For example, during the thermal annealing process, target doped ions flow into the semiconductor material layer 132 to fill oxygen vacancies, reduce the oxygen vacancy concentration in the semiconductor material layer 132, and passivate the interface defects of the semiconductor material layer 132, thereby achieving a positive shift of the transistor threshold voltage and improving the gate control effect.
[0078] Meanwhile, since the barrier layer 144 is located on the side of the doped layer 142 away from the semiconductor material layer 132, it can block the target doped ions to restrict their flow in the direction away from the semiconductor material layer 132, thereby increasing the probability of the target doped ions filling oxygen vacancies.
[0079] In the above-described semiconductor structure fabrication method, a semiconductor material layer 132 is formed on a substrate 110, and a doped layer 142 and a barrier layer 144 are stacked on the semiconductor material layer 132. During the doping and thermal annealing processes, target dopant ions in the doped layer 142 flow into the semiconductor material layer 132 to fill oxygen vacancies, thereby reducing the oxygen vacancy concentration in the semiconductor material layer 132. Simultaneously, the barrier layer 144 is located on the side of the doped layer 142 away from the semiconductor material layer 132, thus blocking the flow of dopant ions and ensuring their flow into the semiconductor material layer 132. In conventional techniques, the presence of oxygen vacancies may make it difficult to turn off transistors. The fabrication method provided in this application enables dopant ions to fill oxygen vacancies, improving the controllability of the transistor.
[0080] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0081] In some embodiments, the target doping element includes oxygen or fluorine. Oxygen directly fills oxygen vacancies, reducing the oxygen vacancy concentration in the semiconductor material layer 132. Fluorine, after filling oxygen vacancies, forms stronger ionic bonds with the metal, making the crystal structure of the semiconductor material layer 132 more stable. This is because fluorine is more electronegative than oxygen atoms; filling oxygen vacancies with fluorine can shift the switching voltage of the transistor positively, improving the controllability of the transistor.
[0082] Furthermore, the target doping element is fluorine; the fluorine doping concentration is less than or equal to 4E21cm. -3 Furthermore, the fluorine doping concentration is 1E13 cm⁻¹. -3 ~1E21 cm -3 This is because the doping concentration of fluorine also affects the electron transport capability. If too much fluorine is doped, the electron conductivity of the semiconductor material layer 132 will decrease, and the transistor switching voltage will not change much. Therefore, it is necessary to limit the doping concentration of fluorine.
[0083] The doping concentration of fluorine in semiconductor material layer 132 is controlled to be less than or equal to 4E21cm. -3 Furthermore, the fluorine doping concentration is 1E13 cm⁻¹. -3 ~1E21 cm -3 This allows for the increase of oxygen vacancies, which in turn promotes a positive shift in the transistor switching voltage, while maintaining the conductivity of the semiconductor material layer 132.
[0084] In some embodiments, the doped layer 142 is a polymer layer including fluorine or oxygen elements, and the doped layer 142 is obtained by initiation chemical vapor deposition or atomic layer deposition. Exemplarily, the formation process of the barrier layer 144 and / or the doped layer 142 includes initiation chemical vapor deposition or atomic layer deposition.
[0085] For example, the Initiated Chemical Vapor Deposition (iCVD) process introduces the initiator and functional monomer required for polymerization into the cavity by vaporization, and induces the initiator to decompose at a lower heating temperature, so that the monomer polymerizes into a polymer film and deposits it on the semiconductor material layer 132.
[0086] For example, atomic layer deposition (ALD) is a process in which single-atom films are formed layer by layer on the surface of semiconductor material layer 132.
[0087] In this embodiment, the semiconductor structure is annealed. Under heat treatment conditions, the vibration frequency of the target dopant element increases, tending to diffuse and move towards the oxygen vacancies in the semiconductor material layer 132, thereby filling the oxygen vacancies. For example, the temperature range of the heat treatment includes 250°C to 400°C.
[0088] Alternatively, the barrier layer 144 can be made of aluminum oxide, which can block fluorine.
[0089] In some embodiments, step S12 provides a substrate 110 and forms a semiconductor material layer 132 on the substrate 110, including steps S120 to S128.
[0090] S120, a stacked structure 120 is formed on the substrate 110. The stacked structure 120 includes multiple layers of first dielectric layer 122 and multiple layers of second dielectric layer 124 stacked alternately.
[0091] For example, the stacking direction of the first dielectric layer 122 and the second dielectric layer 124 can be a third direction Z.
[0092] S122, etch the stacked structure 120 to form a first hole 126; based on the first hole 126, etch the first dielectric layer 122 to form a first receiving groove 128.
[0093] For example, the first via 126 extends through the stacked structure 120 along the stacking direction of the first dielectric layer 122 and the second dielectric layer 124, so as to expose each of the first dielectric layer 122 and each of the second dielectric layer 124 within the first via 126. Optionally, the first via 126 can be formed by a dry etching process.
[0094] For example, each of the first dielectric layers 122 is removed by lateral etching based on the first hole 126 to form each of the first receiving trenches 128. Optionally, the first receiving trenches 128 can be formed by a wet etching process.
[0095] S124, an initial semiconductor material layer 132, a gate dielectric layer 134 and a conductive layer 136 are sequentially stacked in the first receiving groove 128 and the first hole 126.
[0096] For example, the first initial semiconductor material layer 132 may be a metal oxide semiconductor material. Alternatively, the first initial semiconductor material layer 132 may be an IGZO material.
[0097] In some embodiments, the metal oxide semiconductor material may comprise one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO, IW). Materials such as O, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.
[0098] These materials have a wide band gap and low leakage current. For example, when the metal oxide semiconductor material is IGZO, the leakage current of the transistor is less than or equal to 10 A to 15 A, which can improve the working performance of dynamic memory.
[0099] Exemplarily, the gate dielectric layer 134 may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.
[0100] For example, the conductive layer 136 can be made of a material with good and stable conductivity, including but not limited to metals, alloys, metal oxides, such as molybdenum (Mo), titanium nitride (TiN), tungsten (W), and indium tin oxide (ITO), to meet the requirements of semiconductor structures for conductivity, thermal stability, etc.
[0101] S126, etching the stacked structure 120 to form a first trench 140 located on at least one side of the first receiving groove 128; wherein, a plurality of first holes 126 are arranged in a row along the first direction Y, and the first trench 140 extends along the row direction and penetrates the stacked structure 120.
[0102] For example, the first direction can be the extending direction of the first dielectric layer 122 and the second dielectric layer 124, and for example, the first dielectric layer 122 and the second dielectric layer 124 also extend in a second direction X. For example, the column direction can be a direction perpendicular to the substrate 110.
[0103] S128, based on the first trench 140, the first dielectric layer 122 is etched along the direction close to the first hole 126, and the initial semiconductor material layer 132 within the first accommodating trench 128 is etched to form a second accommodating trench and a semiconductor material layer 132 separated by the second accommodating trench; the second accommodating trench exposes the gate dielectric layer 134. For example... Figure 2 and Figure 3 As shown, Figure 2 A schematic diagram of the semiconductor structure obtained through steps S121 to S125 in one embodiment is shown. Figure 3 A partially enlarged view of the locations of the first groove 140 and the first hole 126 is shown. See also Figure 4 and Figure 5 , Figure 4 A schematic diagram showing the formation of the doped layer 142 is shown. Figure 5 A schematic diagram of the formation of barrier layer 144 is shown. The doped layer 142 and barrier layer 144 are sequentially formed within the second accommodating trench and the first trench 140.
[0104] For example, the first dielectric layer 122 is etched from the first trench 140 toward the first hole 126 to expose the initial semiconductor material layer 132 and the gate dielectric layer 134. A doped layer 142 can be deposited on the initial semiconductor material layer 132 so that the doping elements in the doped layer 142 fill the oxygen vacancies in the semiconductor material layer 132.
[0105] In the fabrication method provided in this embodiment, a first hole 126 is first formed, a first receiving trench 128 is formed in each dielectric layer, and a semiconductor material layer 132 and a gate dielectric layer 134 are formed in the first receiving trench 128. Then, a first trench 140 is opened in an adjacent region, and the first dielectric layer 122 is etched to expose the gate dielectric layer 134, thereby enabling the deposition of a doped layer 142.
[0106] Further, in step S18, after obtaining the semiconductor layer 130, the barrier layer 144 and the doped layer 142 are removed to facilitate the formation of a gate or word line structure on the gate dielectric layer 134.
[0107] In some other embodiments, step S12 provides a substrate 110, and forms a semiconductor material layer 132 on the substrate 110, and stacks a doped layer 142 and a barrier layer 144 on one side of the semiconductor material layer 132, including steps S121 to S125.
[0108] S121, a stacked structure 120 is formed on the substrate 110. The stacked structure 120 includes multiple layers of first dielectric layers 122 and multiple layers of second dielectric layers 124 stacked alternately.
[0109] For example, the stacking direction of the first dielectric layer 122 and the second dielectric layer 124 can be a third direction Z.
[0110] S123, etch the stacked structure 120 to form a first hole 126; based on the first hole 126, etch the first dielectric layer 122 to form a first receiving groove 128.
[0111] For example, the first via 126 extends through the stacked structure 120 along the stacking direction of the first dielectric layer 122 and the second dielectric layer 124, so as to expose each of the first dielectric layer 122 and each of the second dielectric layer 124 within the first via 126. Optionally, the first via 126 can be formed by a dry etching process.
[0112] For example, each of the first dielectric layers 122 is removed by lateral etching based on the first hole 126 to form each of the first receiving trenches 128. Optionally, the first receiving trenches 128 can be formed by a wet etching process.
[0113] S125, a semiconductor material layer 132, a doped layer 142 and a barrier layer 144 are sequentially stacked in the first receiving trench 128 and the first hole 126.
[0114] See Figures 7-9 , Figure 7 A partially enlarged view of the semiconductor structure obtained through steps S121 and S123 is shown. Figure 7 This illustrates the formation of a semiconductor material layer 132 on a semiconductor structure. Figure 8 This illustrates the formation of a doped layer 142 on a semiconductor material layer 132. Figure 9 A barrier layer 144 is shown formed on the doped layer 142. Figures 7-9 In the semiconductor structure, a gate dielectric layer 134 is also formed on the semiconductor material layer 132. It is understood that the doped layer 142 and the barrier layer 144 can also be directly formed on the semiconductor material layer 132.
[0115] For example, in this embodiment, a semiconductor material layer 132 is formed directly in the first receiving groove 128 and the first hole 126, and a doped layer 142 and a barrier layer 144 are sequentially formed on the semiconductor material layer 132.
[0116] It is understood that the doped layer 142 in this embodiment is formed directly on the semiconductor material layer 132, so that the target dopant element in the doped layer 142 can flow directly to the semiconductor material layer 132.
[0117] Step S18 involves thermal annealing the obtained structure to obtain a semiconductor layer 130 doped with the target doping element, including steps S181-S183.
[0118] S181, the obtained structure is subjected to thermal annealing to form an initial semiconductor layer doped with the target doping element.
[0119] For example, in the thermal annealing process, the barrier layer 144 can block the target dopant element, ensuring that the target dopant element flows to the semiconductor material layer 132 to fill the oxygen vacancies in the semiconductor material layer 132.
[0120] S182, remove the barrier layer 144 and the doped layer 142.
[0121] For example, the barrier layer 144 and the doped layer 142 can be removed by an etching process.
[0122] S183, remove the initial semiconductor layer in the first hole 126, so that the initial semiconductor layer retained in the first receiving trench 128 constitutes the semiconductor layer 130.
[0123] For example, the initial semiconductor layer 130 within the first via 126 can be removed by dry etching. The semiconductor layer 130 retained within the first accommodating trench 128 can be used to form a transistor structure, serving as an element transport channel for the transistor.
[0124] In some embodiments, after step S183, the method for fabricating a semiconductor structure may further include: sequentially stacking a gate dielectric layer 134 and a conductive layer 136 in the first accommodating trench 128 and the first hole 126; wherein the gate dielectric layer 134 covers the semiconductor layer 130.
[0125] For example, after removing the barrier layer 144 and the doped layer 142, a gate dielectric layer 134 and a conductive layer 136 can be formed on the semiconductor material layer 132.
[0126] For example, the conductive layer 136 can serve as a gate / word line structure.
[0127] In some embodiments, a semiconductor material layer 132, a doped layer 142, and a barrier layer 144 are sequentially stacked in the first receiving trench 128 and the first hole 126, and the method further includes: a semiconductor material layer 132, a gate dielectric material layer, a doped layer 142, and a barrier layer 144 are sequentially stacked in the first receiving trench 128 and the first hole 126; wherein, forming the gate dielectric layer 134 in the first receiving trench 128 and the first hole 126 includes: forming a gate dielectric layer 134 integrally connected with the remaining gate dielectric material layer in the first receiving trench 128.
[0128] For example, in this embodiment, a gate dielectric material layer is first formed on the semiconductor material layer 132, and then a doped layer 142 and a barrier layer 144 are formed on the gate dielectric material layer. In the repair process, the target doped element can enter the oxygen vacancy from the region in contact with the semiconductor material layer 132.
[0129] For example, after removing the barrier layer 144 and the doped layer 142, a gate dielectric layer 134 material layer can be formed on the semiconductor material layer 132 to form the gate dielectric layer 134 together with the remaining gate dielectric material layer in the first accommodating trench 128.
[0130] In some embodiments, such as Figure 6 As shown, this application also provides a semiconductor structure, which, by way of example, can be prepared by the above-described semiconductor structure preparation method. In some embodiments, the semiconductor structure includes: a stacked structure 120, including multiple layers of alternating first dielectric layers 122 and multiple layers of second dielectric layers 124; the stacked structure 120 has a first hole 126 penetrating each of the first dielectric layers 122 and the second dielectric layers 124, and a first receiving groove 128 located within the first dielectric layer 122 and surrounding the first hole 126; a semiconductor layer 130 located on the inner wall of the first receiving groove 128, or on the inner wall of the first hole 126 between adjacent first receiving grooves 128; wherein the material of the semiconductor layer 130 includes a metal oxide material containing a target dopant element.
[0131] For example, the metal oxide material may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), and indium gallium silicon oxide (InGaSiO). Materials include indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO).
[0132] Optionally, the target dopant element in the semiconductor layer 130 can be fluorine. Further, the doping concentration of fluorine in the metal oxide material is less than or equal to 4E21cm⁻¹. -3 .
[0133] In some embodiments, the semiconductor layer 130 is located on the inner wall of the first hole 126 between adjacent first accommodating trenches 128; the semiconductor layer 130 further includes: a gate dielectric layer 134 covering the semiconductor layer 130 and the inner wall of the first accommodating trenches 128; and a conductive layer 136 covering the gate dielectric layer 134 and filling the first accommodating trenches 128 and the first hole 126.
[0134] In some embodiments, the semiconductor layer 130 is located on the inner wall of the first accommodating trench 128; the semiconductor structure further includes: a gate dielectric layer 134 covering the semiconductor layer 130, or covering the inner wall of the semiconductor layer 130 and the first hole 126; and a conductive layer 136 located on the side of the gate dielectric layer 134 away from the semiconductor layer.
[0135] In one embodiment, an electronic device is also provided, including one or more semiconductor structures as described in the above embodiments. The electronic device includes, for example, data storage devices, photocopiers, network devices, home appliances, instruments, mobile phones, computers, and other devices with data storage functions. The electronic device may include a housing and a circuit board disposed within the housing, a memory integrated on the circuit board, or data read / write circuitry. The structure of the memory can be referred to the relevant descriptions in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in this disclosure.
[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0137] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The method includes the following steps: A substrate is provided, and a semiconductor material layer is formed on the substrate; A doped layer is formed on one side of the semiconductor material layer; the doped layer includes a target doping element. A barrier layer is formed on the side of the doped layer away from the semiconductor material layer; The obtained structure is subjected to thermal annealing to obtain a semiconductor layer doped with the target doping element.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The provision of a substrate and the formation of a semiconductor material layer on the substrate include: A stacked structure is formed on the substrate, the stacked structure comprising alternating layers of multiple first dielectric layers and multiple layers of second dielectric layers; The stacked structure is etched to form a first hole; the first dielectric layer is etched based on the first hole to form a first receiving groove; An initial semiconductor material layer, a gate dielectric layer, and a conductive layer are sequentially stacked in the first receiving groove and the first hole; The stacked structure is etched to form a first trench located on at least one side of the first receiving groove; wherein, a plurality of the first holes are arranged in a row along a first direction, and the first trench extends along the row direction and penetrates the stacked structure; Based on the first trench, the first dielectric layer is etched in a direction close to the first hole, and the initial semiconductor material layer in the first accommodating trench is etched to form a second accommodating trench and the semiconductor material layer separated by the second accommodating trench; the second accommodating trench exposes the gate dielectric layer; The doped layer and the barrier layer are sequentially formed in the second accommodating trench and the first trench.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The provision of a substrate, the formation of a semiconductor material layer on the substrate, and the deposition of a doped layer and a barrier layer on one side of the semiconductor material layer, comprising: A stacked structure is formed on the substrate, the stacked structure comprising alternating layers of multiple first dielectric layers and multiple layers of second dielectric layers; The stacked structure is etched to form a first hole; the first dielectric layer is etched based on the first hole to form a first receiving groove; A semiconductor material layer, a doped layer, and a barrier layer are sequentially stacked in the first receiving groove and the first hole; The step of performing thermal annealing on the obtained structure to obtain a semiconductor layer doped with the target doping element includes: The obtained structure is subjected to thermal annealing to form an initial semiconductor layer doped with the target doping element; Remove the barrier layer and the doped layer; Remove the initial semiconductor layer in the first hole, so that the initial semiconductor layer remaining in the first receiving groove forms the semiconductor layer.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that, Also includes: A gate dielectric layer and a conductive layer are sequentially stacked within the first receiving groove and the first hole; wherein the gate dielectric layer covers the semiconductor layer.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The method of sequentially stacking a semiconductor material layer, a doped layer, and a barrier layer within the first receiving groove and the first hole further includes: A semiconductor material layer, a gate dielectric material layer, a doped layer, and a barrier layer are sequentially stacked in the first accommodating groove and the first hole; The formation of the gate dielectric layer in the first receiving groove and the first hole includes: forming a gate dielectric layer integrally connected with the remaining gate dielectric material layer in the first receiving groove.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The target doping element includes fluorine.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The doping concentration of the fluorine element in the semiconductor layer is less than or equal to 4E21 cm -3 .
8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The doped layer is a polymer layer containing fluorine ions, and the doped layer is obtained by initiation chemical vapor deposition or atomic layer deposition process; The formation process of the barrier layer and / or the doped layer includes: initiation chemical vapor deposition or atomic layer deposition.
9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The temperature range for the heat annealing process is 250℃ to 400℃.
10. A semiconductor structure, characterized in that, include: A stacked structure includes multiple layers of first dielectric layers and multiple layers of second dielectric layers stacked alternately; the stacked structure has a first hole penetrating each of the first dielectric layers and the second dielectric layers, and a first receiving groove located in the first dielectric layer and surrounding the first hole; A semiconductor layer is located on the inner wall of the first accommodating trench, or on the inner wall of the first hole between adjacent first accommodating trenches; wherein the material of the semiconductor layer includes a metal oxide material containing the target doping element.
11. The semiconductor structure as claimed in claim 10, characterized in that, The semiconductor layer is located on the inner wall of the first hole between adjacent first receiving trenches; the semiconductor structure further includes: A gate dielectric layer covers the semiconductor layer and the inner wall of the first accommodating trench; A conductive layer is located on the side of the gate dielectric layer away from the semiconductor layer.
12. The semiconductor structure as claimed in claim 11, characterized in that, The semiconductor structure further includes a doped layer, which includes the target doping element, which is fluorine; the doped layer is located on the side of the semiconductor layer away from the stacked structure.
13. The semiconductor structure as described in claim 10, characterized in that, The semiconductor layer is located on the inner wall of the first accommodating groove; the semiconductor structure further includes: A gate dielectric layer that covers the semiconductor layer, or covers the semiconductor layer and the inner wall of the first hole; A conductive layer covers the gate dielectric layer and fills the first receiving groove and the first hole.
14. The semiconductor structure as claimed in claim 10, characterized in that, The target doping element is fluorine element, and a doping concentration of the fluorine element in the metal oxide material is less than or equal to 4E21cm -3 .
15. An electronic device, characterized in that, The semiconductor structure includes a semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9; or, a semiconductor structure according to any one of claims 10 to 14.