Method of fabricating a semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a first mask layer, the first mask layer including a first structure and a second structure alternately arranged in a first direction; the first direction intersecting with a thickness direction; doping the first structure to form a plurality of doped regions, the plurality of doped regions being arranged along the first direction; etching the first structure, retaining the doped regions; etching the second structure, penetrating a portion of the second structure to form a plurality of mask blocks; the plurality of mask blocks being arranged along the first direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for fabricating a semiconductor structure. Background Technology

[0002] In some semiconductor fabrication processes, photoresist can be spin-coated onto the wafer surface, followed by photolithography and development. The patterned photoresist is then used as an etching mask to etch the wafer, transferring the photolithographic pattern to the wafer surface to obtain the target device structure. For the fabrication of smaller patterns, high-resolution photolithography equipment is required. When the size of the pattern to be developed is smaller than the resolution of existing photolithography equipment, how to further reduce the pattern size becomes a pressing issue. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a first mask layer, the first mask layer including a first structure and a second structure alternately disposed in a first direction; the first direction intersecting a thickness direction; doping the first structure to form a plurality of doped regions, the plurality of doped regions being arranged along the first direction; etching the first structure, retaining the doped regions; etching the second structure, penetrating a portion of the second structure to form a plurality of mask blocks; the plurality of mask blocks being arranged along the first direction. In some embodiments, the fabrication method further comprises: forming a first barrier layer on the first mask layer; forming a first trench penetrating the first barrier layer and exposing the first mask layer, the first trench extending along the first direction; the method of forming the doped regions comprises: performing ion implantation on the first structure exposed at the bottom of the first trench to form the doped regions.

[0004] In some embodiments, a plurality of the first grooves are spaced apart in the first direction, and the size of the first groove in the first direction is greater than or equal to the sum of the sizes of the first structure and the second structure in the first direction.

[0005] In some embodiments, the first trench includes: a first sidewall extending along the first direction; and a second sidewall disposed opposite to the first sidewall, the second sidewall including a plurality of first portions extending along the first direction, and a second portion connecting two of the first portions, the second portion forming an angle with the connection of the first portion.

[0006] In some embodiments, the fabrication method further includes: forming a second barrier layer on the doped region and the second structure; forming a second trench through the second barrier layer, the second trench extending along the first direction; and forming the mask block by: forming the mask block through the second structure exposed at the bottom of the second trench.

[0007] In some embodiments, the position of the first trench relative to the first mask layer is adjacent to and / or at least partially overlaps with the position of the second trench relative to the first mask layer.

[0008] In some embodiments, the fabrication method further includes: forming a first photoresist layer on the first blocking layer, the first photoresist layer having a first pattern exposing the first blocking layer; forming the first trench includes: etching the first blocking layer exposed by the first pattern to form the first trench; the fabrication method further includes: forming a second photoresist layer on the second blocking layer, the second photoresist layer having a second pattern exposing the second blocking layer; forming the second trench includes: etching the second blocking layer exposed by the second pattern to form the second trench; wherein the first pattern and the second pattern are complementary and / or at least partially overlap.

[0009] In some embodiments, the fabrication method further includes: providing a first film layer and forming a first mask layer on the first film layer; wherein there is a gap between the doped region and the mask block, and the gap exposes a portion of the first film layer; the fabrication method further includes: etching the first film layer exposed by the gap.

[0010] In some embodiments, the method of forming the first mask layer includes: forming a first semiconductor layer; forming a plurality of third trenches penetrating the first semiconductor layer; the third trenches extending along a second direction, the plurality of third trenches dividing the first semiconductor layer into a plurality of first strip structures; the second direction intersecting the first direction; and forming a second strip structure in the third trenches.

[0011] In some embodiments, the first structure includes silicon; the doping element of the doped region includes boron.

[0012] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a first mask layer, including a first structure and a second structure alternately arranged in a first direction intersecting and perpendicular to the thickness direction; doping the first structure to form a plurality of doped regions, the plurality of doped regions being arranged along the first direction; etching the first structure, removing the undoped intrinsic regions of the first structure and retaining the doped regions; etching the second structure, penetrating a portion of the second structure to form a plurality of mask blocks, the plurality of mask blocks being arranged along the first direction; the doped regions and mask blocks can constitute a mask pattern, which can be used to etch or dope a semiconductor structure; by integrating doping processes and selective etching processes to pattern different structures of the first mask layer, the resolution limitations of photolithography processes can be reduced; while achieving size reduction between various sub-patterns in the mask pattern, such as various block patterns and various strip patterns, the application of high-precision photolithography processes can be reduced, photolithography limitations can be reduced, and fabrication costs can be reduced. Attached Figure Description

[0013] Figures 1 to 6 This is a schematic diagram illustrating the fabrication of a semiconductor structure according to an exemplary embodiment;

[0014] Figure 7 This is a schematic diagram of a semiconductor structure fabrication method according to an embodiment of the present disclosure;

[0015] Figures 8 to 29 This is a schematic diagram illustrating the fabrication of a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0016] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0017] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. The phrases "in some embodiments" or "in one embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0018] In some semiconductor structure fabrication methods, photoresist is spin-coated onto the wafer surface, and then photolithography and development are performed on the photoresist to transfer the pattern of the photomask to the photoresist layer. The exposed film layer of the patterned photoresist is then etched to transfer the target pattern onto the film layer of the wafer, thus obtaining the target structure. Due to the resolution limitations of photolithography equipment or processes, the minimum size of the photolithographically developed pattern is limited.

[0019] In some embodiments, photolithography and doping processes can be integrated to perform pattern transfer on the film layer. For example, a mask layer can be patterned and used as an etching mask to etch other film layers, or a patterned mask can be used as a doping mask to dope other film layers. Exemplarily, the etching process may include, but is not limited to, dry etching, wet etching, or a combination thereof. The doping process may include, but is not limited to, ion implantation or diffusion.

[0020] In some embodiments, refer to Figure 1 As shown, a first mask layer 110 is formed on the first film layer 101, a first barrier layer 120 is formed on the first mask layer 110, and photoresist is spin-coated onto the first barrier layer 120 to form a photoresist layer 140. The formation process of the photoresist layer 140 may include, but is not limited to, spin-coating; the photoresist layer 140 is patterned by photolithography and development, and a portion of the patterned area can expose the first barrier layer 120. The formation processes of the first mask layer 110 and the first film layer 101 may include deposition, and the deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In some specific embodiments, the first film layer 101 may also be patterned as a layer of the mask structure.

[0021] In some embodiments, the pattern of the photoresist layer 140 may include, but is not limited to, openings, grooves, trenches, or apertures, and the pattern shape may include, but is not limited to, rectangles, circles, or ellipses. The first barrier layer 120 may include, but is not limited to, spin-coated carbon, amorphous carbon, anti-reflective coatings, or dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. The first barrier layer 120 may include a single film layer or multiple film layers. For example, the first barrier layer 120 may include a first sub-layer 121 and a second sub-layer 122 stacked on the first mask layer 110, with the first sub-layer 121 located between the second sub-layer 122 and the first mask layer 110, and the second sub-layer 122 in contact with the photoresist layer 140. The first sublayer 121 may include carbon, such as spin-coated carbon, which is formed by spin-coating on the first mask layer 110. It can fill or smooth out the depressions on the surface of the first mask layer 110, providing a film surface with high flatness. The second sublayer 122 may include an anti-reflective coating, such as an anti-reflective coating containing silicon components, which is formed by spin-coating on the first sublayer 121. The second sublayer 122 can reduce the reflection of light on the wafer surface, reduce light intensity loss, and improve the photolithography selectivity.

[0022] Reference Figure 2 As shown, the patterned photoresist layer 140 is etched to expose the first barrier layer 120, transferring the pattern of the photoresist layer 140 into the first barrier layer 120 and exposing the first mask layer 110; if a pattern is formed penetrating the first barrier layer 120, it may include, but is not limited to, openings, grooves, trenches, apertures, or combinations thereof, and may include, but is not limited to, rectangular, circular, or elliptical shapes; Figure 2 The opening shown penetrates the first barrier layer 120. After the opening is formed, the photoresist layer 140 can be removed. The removal process may include, but is not limited to, ashing, cleaning, or a combination thereof. The mask pattern in this embodiment can be formed after material removal and may consist of the removed blank portion and the remaining portion. The specific shape corresponds to the photolithographic mask pattern, and there is no limitation on the specific pattern.

[0023] Reference Figure 3As shown, a patterned first barrier layer 120 is used as a doping mask to dope a portion of the first mask layer 110 exposed by the opening to form a doped region 112. The doping process may include, but is not limited to, ion implantation or diffusion. The doped region 112 is in the first mask layer 110 and may be a part of the first mask layer 110. The first mask layer 110 includes the doped region 112 and the undoped intrinsic region 111. The doped region 112, after being doped with different particles or impurities, can exhibit a significant difference in etch selectivity compared to the undoped intrinsic region 111. For example, the doped region 112 may have a higher etch selectivity than the intrinsic region 111, meaning it has a higher etch rate and is easier to remove; or the doped region 112 may have a lower etch selectivity than the intrinsic region 111, meaning it has a lower etch rate and is more resistant to etching. The different etch selectivity ratios of the doped region 112 relative to the intrinsic region 111 can be adjusted by changing the dopant particles and the doping concentration. The first mask layer 110 may include semiconductor materials or dielectric materials. For example, the first mask layer 110 may include semiconductor materials such as silicon to facilitate increasing the doping process window. The first mask layer 110 may include silicon, and there is no limitation on the crystal form of silicon. For example, it may be amorphous silicon or non-crystalline silicon.

[0024] Figure 3 Ion implantation is performed on the first mask layer 110 region exposed by the first opening 12. The ion implantation source may include, but is not limited to, B, BF2, and B2H6. The ion implantation temperature range may be 0–500℃. The ion implantation dose or the doping concentration of the doped region 112 can be measured by areal density, which may include a range of 10. 13 ~10 16 The ion implantation depth can be equal to the thickness of the first mask layer 110 in the z-direction, where the z-direction is the wafer thickness direction or the vertical direction, or slightly greater than the thickness of the first mask layer 110 to reach the first film layer 101. The first film layer 101 can block ion implantation bombardment, ensuring that the thickness of the doped region 112 of the first mask layer 110 is equal to the thickness of the first mask layer 110. Depending on the ion implantation source, the ion implantation energy, temperature, and other parameters of the ion implantation equipment can be adjusted to regulate the doping concentration and ion implantation depth of the doped region 112 to meet the target process parameters.

[0025] In some embodiments, refer to Figure 4 As shown, remove the first barrier layer 120; refer to Figure 5As shown, the first mask layer 110 is etched, specifically, both the intrinsic region 111 and the doped region 112 of the first mask layer 110 are etched. The intrinsic region 111 of the first mask layer 110 has a higher etching rate than the doped region 112. The intrinsic region 111 of the first mask layer 110 is etched away, while the doped region 112 is retained. The etching process may include, but is not limited to, dry etching, wet etching, or a combination thereof. The doped region 112 of the first mask layer 110 has a high etch selectivity compared to the intrinsic region 111. Wet etching can be selected based on the material of the first mask layer 110 to reduce etching costs. For example, the first mask layer 110 may include amorphous silicon, and an etchant including ammonia may be selected to etch the first mask layer 110. The etching temperature range may include 10–100°C. For the same concentration of etchant, the etching rate can be controlled by controlling the etching temperature and etching time, such as increasing the etching temperature and / or increasing the etching time to increase the etching rate. In some specific embodiments, the wafer can be immersed in an acid bath containing ammonia etchant to etch and remove the intrinsic region 111 of the first mask layer 110; the temperature of the etchant and the immersion time are controlled to reduce over-etching of the doped region 112 while removing the intrinsic region 111 of the first mask layer 110; after etching, the wafer is cleaned with pure water.

[0026] Reference Figure 5 As shown, the remaining first doped regions 112 of the first mask layer 110 can form a new mask pattern or a new mask layer, which can be composed of multiple doped regions 112. The gaps between the doped regions 112 expose the first film layer 101, and the exposed first film layer 101 can be etched using the mask pattern as an etching mask. A second film layer 102 can be formed under the first film layer 101. The first film layer 101 and the second film layer 102 can be, but are not limited to, materials such as silicon oxide, silicon nitride, silicon oxynitride, titanium nitride, or aluminum oxide. For example, the first film layer 101 may include silicon oxide, and the second film layer 102 may include titanium nitride. In some embodiments, the first film layer 101 and the second film layer 102 can also be etched to transfer the mask pattern composed of multiple doped regions 112 to the first film layer 101 and the second film layer 102. The first film layer 101, the second film layer 102, and the multiple doped regions 112 can constitute a mask structure or a part of a mask structure. The multiple doped regions 112 can constitute Figure 6 The mask pattern or new mask layer shown exposes the film layer under the doped regions 112 in the region between the multiple first doped regions 112, which may include, but is not limited to, the first film layer 101.

[0027] In some embodiments, Figure 5The first mask layer 110, and / or the first film layer 101 and the second film layer 102 shown can be applied to etching or ion implantation of different semiconductor structures. For example, they can be applied to etching dielectric materials, and after etching, they fill the openings or trenches to form an interconnect layer; they can be applied to etching the active region trench of a transistor, and after etching, active regions are epitaxially grown inside and outside the trench to serve as the source and drain of the transistor; they can be applied to etching the contact openings of various active devices, and after etching, conductive plugs are formed in the openings, such as forming conductive plugs that contact and connect the source, drain and gate of the transistor; they can be applied to cutting etching of continuous conductive structures or continuous non-conductive structures, such as cutting continuous semiconductor strips to form multiple discontinuous semiconductor bodies, and doping different regions of the semiconductor bodies to form the channel region, source and drain of the transistor.

[0028] In some specific embodiments, reference is made to Figure 6 The mask pattern or structure shown has a gap dimension D1 between two doped regions 112. The two doped regions 112 correspond to two photomasks in photolithography. The dimension D1 is limited by the resolution of the photolithography machine, making it difficult to reduce the dimension D1 indefinitely in a single photolithography step. Multiple photolithography overlays can be used to reduce the dimension, but this increases the difficulty of overlay or photolithography alignment, potentially requiring the setting of alignment marks or redesign of alignment marks. Alternatively, an additional material layer can be formed on the sidewalls of the pattern to reduce the pattern size, but this places higher demands on the film thickness control, easily causing uneven size distribution or excessive size deviation from the target control range, leading to a decrease in fabrication yield. In view of this, embodiments of this disclosure provide a method for fabricating a semiconductor structure that, while achieving the relevant dimensions of the mask pattern, reduces the resolution limitations of the photolithography machine, enabling the fabrication of a higher resolution mask using a lower resolution machine.

[0029] According to some aspects of embodiments of this disclosure, Figure 7 A method for fabricating a semiconductor structure is provided, comprising: providing a first mask layer, the first mask layer including a first structure and a second structure alternately arranged in a first direction; the first direction intersects a thickness direction; doping the first structure to form a plurality of doped regions, the plurality of doped regions being arranged along the first direction; etching the first structure, retaining the doped regions; etching the second structure, penetrating a portion of the second structure to form a plurality of mask blocks; the plurality of mask blocks being arranged along the first direction. The first direction may be the x-direction in the figures, the second direction may be the y-direction, and the x-direction and y-direction may intersect or be perpendicular; the third direction may be the thickness direction, which may be the wafer thickness direction or a vertical direction; the z-direction may intersect or be perpendicular to the xoy plane.

[0030] Reference Figure 8As shown, the first mask layer 110 may include a first structure 113 and a second structure 114 alternately arranged in the x-direction, and the strip structures may extend along the y-direction; the first structure 113 and the second structure 114 are made of different materials, and the first structure 113 and the second structure 114 have different etching selectivity or etching rates for the same etchant. By selectively etching the first structure 113 and the second structure 114 with different etchants, the selective removal of a portion of the second structure 114 can be achieved, thus patterning the second structure 114 to form a mask block 115, and... Selectively removing a portion of the first structure 113 to pattern the first structure 113; using a higher resolution photolithography process to pattern the photoresist layer before etching the first structure 113 to transfer the photolithographic pattern, and using a higher resolution photolithography process to pattern the photoresist layer before etching the second structure 114 to transfer the photolithographic pattern, the patterns of the first structure 113 and the second structure 114 are merged to form a mask pattern, increasing the size of the retained mask portion, thereby reducing the mask gap size D1 and improving the mask pattern resolution to accommodate the fabrication of smaller structures. Exemplarily, the etching process may include, but is not limited to, dry etching, wet etching, or a combination thereof.

[0031] In some embodiments, see the following text Figure 14 As shown, when patterning the first structure 113, ion implantation doping can be performed on some regions of the first structure 113 to increase the etching rate between the undoped intrinsic region 111 and the doped region 112 of the first structure 113. The doped region 112 can be retained during etching of the first structure 113. There is a high etch selectivity between the intrinsic region 111 and the doped region 112. A suitable etchant is selected based on the material of the first structure 113 to etch away the intrinsic region 111 while retaining the doped region 112. To improve doping uniformity and expand the ion implantation window, the first structure 113 may include semiconductor materials, such as silicon. The crystal form of silicon is not limited; it may be amorphous silicon or monocrystalline silicon, polycrystalline silicon, or silicon of other crystal forms. The second structure 114 may include silicon nitride or silicon oxynitride to increase the etch selectivity between the second structure 114 and the first structure 113. The second structure 114 and the doped region 112 may be substantially unetched in the etchant. The etchant may include ammonia, and the etching temperature range may include 10 to 100°C. The etching rate can be controlled by controlling the etching temperature and etching time to reduce over-etching of the doped region 112 and the second structure 114 while removing the intrinsic region 111 of the first structure 113. After etching, the wafer is rinsed with pure water.

[0032] In some embodiments, the method of forming the first mask layer 110 includes:

[0033] Reference Figure 9 As shown, a first semiconductor layer 1131 is formed; the first semiconductor layer 1131 may be formed on other film layer structures, such as forming a second film layer 102 and a first film layer 101 stacked together, and the first semiconductor layer 1131 is formed on the first film layer 101; the formation process may include a deposition process;

[0034] Reference Figure 10 As shown, a first barrier layer 120 and a patterned photoresist layer 140 are formed on the first film layer 101. The photoresist layer 140 exposes the first barrier layer 120. The first barrier layer 120 may include a first sub-layer 121 and a second sub-layer 122. The first barrier layer 120 and the first semiconductor layer 1131 exposed by the photoresist layer 140 are etched until they penetrate the first semiconductor layer 1131.

[0035] Reference Figure 11 As shown, multiple trenches are formed penetrating the first semiconductor layer 1131, such as the third trench 104; the third trench 104 extends along the y-direction, and the multiple third trenches 104 divide the first semiconductor layer 1131 into multiple first structures 113; the y-direction intersects the x-direction; refer to Figure 12 As shown, dielectric material is filled in the third trench 104, and the top material of the first structure 113 is removed for planarization, forming the third trench 104. Figure 13 The second structure 114 is shown. Figure 13 The schematic diagram of the first mask layer 110 in the xoy plane is shown below. Figure 8 As shown. Planarization processes may include, but are not limited to: etching, chemical mechanical polishing, or combinations thereof.

[0036] In some embodiments, refer to Figure 14 As shown, for Figure 8 Ion implantation is performed on a portion of the first structure 113 to form spaced doped regions 112. The doped regions 112 on different first structures 113 can be arranged in the x-direction. To adapt to different mask pattern requirements, ion implantation can be performed on any region of the first structure 113 to form doped regions 112. In some specific embodiments, a barrier layer can be formed on the first mask layer 110, forming a trench extending through the barrier layer and along the x-direction, such as a first trench 131. Ion implantation is performed on the first structure 113 exposed at the bottom of the first trench 131 to form doped regions 112. A second structure 114 can be exposed at the bottom of the first trench 131. The second structure 114 has high density and can block ion doping without being doped. Thus, multiple doped regions 112 arranged along the x-direction and spaced by the second structure 114 can be formed with a single ion implantation, improving the fabrication efficiency of the doped regions 112. (Refer to...) Figure 15As shown, etching removes the intrinsic region 111 of the first structure 113, leaving the second structure 114 and the doped region 112, thus exposing the first film layer 101 under the first mask layer 110. The first mask layer 110 may include silicon oxide and has a low etching rate during the etching process. The etching may stop at the upper surface of the first film layer 101, or the first film layer 101 may be over-etched with less etching without penetrating the first film layer 101. Figure 15 Part b also shows Figure 15 The cross-section of AA' in part a on the xoz plane is shown in the figure. The intrinsic region 111 at this location is etched away to expose the first film layer 101.

[0037] In some embodiments, for Figure 14 A portion of the second structure 114 is etched, and any area of ​​the second structure 114 can be etched according to the mask pattern requirements. In some specific embodiments, refer to... Figure 15 As shown, a blocking layer can be applied to the area outside the dashed box in the figure, forming a trench at the location of the dashed box; the bottom of the trench is etched, and the second structure 114 below the bottom of the trench is penetrated, breaking the second structure 114 to form multiple mask blocks 115, as shown in the figure. Figure 16 As shown, along the x-direction, the doped regions 112 are retained due to low or negligible etching rates, while the first film layer 101 is exposed as an etch stop layer. (Refer to...) Figure 16 As shown, the doped region 112 and the mask block 115 can form a mask pattern.

[0038] In some embodiments, the first structure 113 may include silicon, such as amorphous silicon; the doping element of the doped region 112 may include boron. Exemplarily, the ion implantation source may include, but is not limited to, B, BF2, and B2H6. The ion implantation temperature range may be 0–500°C. The ion implantation dose or the doping concentration of the doped region 112 can be measured by areal density, which may range from 10 to 10. 13 ~10 16 The injection source, injection temperature, and concentration can be adjusted to suit different process parameters.

[0039] In some embodiments, the manufacturing method further includes:

[0040] Reference Figure 17As shown, a first barrier layer 120 is formed on the first mask layer 110; a first photoresist layer 141 can be formed by spin-coating photoresist on the first barrier layer 120, and a first pattern 13 exposing the first barrier layer 120 can be formed by photolithography and development of the first photoresist layer 141. The first barrier layer 120 may include a first sub-layer 121 and a second sub-layer 122 stacked together. The first sub-layer 121 may include spin-coated carbon, and the second sub-layer 122 may include a silicon-containing anti-reflective coating; the first pattern 13 may be as follows: Figure 18 The example corresponds to the first groove 131;

[0041] Reference Figure 17 As shown, a first trench 131 is formed that penetrates the first barrier layer 120 and exposes the first mask layer 110, the first trench 131 extending along the x-direction; the method for forming the doped region 112 includes:

[0042] Reference Figure 19 As shown, ion implantation is performed on the first structure 113 exposed at the bottom of the first trench 131 to form a doped region 112; Figure 19 A cross-sectional schematic diagram of the AA' portion in the xoz plane is also shown. After ion implantation of the first structure 113 is completed, the first photoresist layer 141 and the first barrier layer 120 can be removed; the removal process may include, but is not limited to, etching, ashing, cleaning, or a combination thereof.

[0043] Reference Figure 18 As shown, the first pattern 13 includes multiple sub-patterns, corresponding to multiple first grooves 131; Figure 19 The dashed lines illustrate the positions of multiple first trenches 131 relative to the first mask layer 110. (Refer to...) Figure 19 As shown, due to the blocking effect of the second structure 114 on ion implantation, the dimensions of the first trench 131a and the first trench 131b in the x-direction can be larger than the dimensions of the first structure 113 in the x-direction to expose part of the second structure 114. The second structure 114 can be exposed but not doped, so that a smaller doped region 112 can be defined using a larger spot size. Under the premise of ensuring that the first trench 131a and the first trench 131b expose the first structure 113, the distance between the first trench 131a and the first trench 131b in the x-direction can be appropriately increased, which can relatively increase the distance between adjacent spots during photolithography development. This can reduce the interference between spots and reduce the proximity effect of photolithography, so as to achieve the development of smaller pattern sizes using a larger resolution photolithography machine and reduce the limitation of photolithography resolution on the mask pattern size.

[0044] In some embodiments, a plurality of first trenches 131 are spaced apart in the x-direction, and the size of the first trench 131 in the x-direction is greater than or equal to the sum of the sizes of the first structure 113 and the second structure 114 in the first direction. Each first trench 131 exposes at least one first structure 113. When a first trench 131 exposes one first structure 113, the first trench 131 may have a smaller size, such as first trench 131a. Because the second structure 114's blocking effect on ion implantation allows the second structure 114 to be exposed by the first trench 131a, the first trench 131a may have a larger size in the x-direction to reduce the difficulty of photolithography development. For example, it may traverse two second structures 114 and the intermediate first structure 113. A larger development size reduces the difficulty of photolithography while also increasing the photolithography alignment window and improving the photolithography process window.

[0045] In some embodiments, the shape and size of the first trench 131 may vary depending on the size, position, and arrangement of the doped regions 112. It may include a strip-shaped first trench 131a or an irregularly shaped first trench 131c. The first trench 131c has a first sidewall 1311 and a second sidewall 1312 disposed opposite to each other in the y-direction. The shape of the first sidewall 1311 and the shape of the second sidewall 1312 may be... Figure 18 Corresponding to a portion of the first pattern 13, the first sidewall 1311 is a straight line extending along the x direction, and the second sidewall 1312 is composed of multiple short straight lines connected at an angle.

[0046] In some embodiments, the first trench 131c may include: a first sidewall 1311 extending in the x-direction; and a second sidewall 1312 disposed opposite to the first sidewall 1311, the second sidewall 1312 including a plurality of first portions extending in the x-direction, and a second portion connecting two first portions, the connection between the second portion and the first portion forming an angle. Corresponding to a plurality of doped regions 112 spaced apart in the x-direction, the plurality of doped regions 112 having different dimensions in the y-direction, the alignment of one side of the plurality of doped regions 112 in the x-direction such that the first sidewall 1311 of the first trench 131 is a continuous straight line in the x-direction, and the second sidewall 1312 is a plurality of short straight lines spaced apart, the short straight lines being connected by oblique straight lines, constituting a second sidewall 1312 having a plurality of angles.

[0047] In some embodiments, refer to Figure 20 As shown, for Figure 19 The first structure 113 is etched to remove the intrinsic region 111 of the first structure 113. The doped region 112 and the second structure 114 are retained with a small etching rate or with almost no etching. Figure 20A cross-sectional schematic diagram of AA' in the xoz plane is also shown, in which the intrinsic region 111 of the first structure 113 is removed, exposing the first film layer 101.

[0048] In some embodiments, refer to Figure 21 As shown, the first mask layer 110 remaining after removing the intrinsic region 111 of the first structure 113 is etched, specifically in... Figure 21 The dashed frame is etched through the second structure 114 to re-pattern the first mask layer 110; the area outside the dashed frame can be covered by a blocking layer without being etched to form a new mask pattern.

[0049] In some embodiments, the manufacturing method further includes:

[0050] Reference Figure 22 As shown, a second barrier layer 150 is formed on the doped region 112 and the second structure 114. Figure 21 A second barrier layer 150 is formed on the structure shown, and a second photoresist layer 142 is formed by spin-coating photoresist on the second barrier layer 150. The second photoresist layer 142 is then photolithographically etched and developed to form a second pattern 15 exposing the second barrier layer 150. The second pattern 15 can be as follows: Figure 23 The example corresponds to the second trench 151;

[0051] Reference Figure 24 As shown, a second trench 151 is formed penetrating the second barrier layer 150, and the second trench 151 extends along the x-direction; the bottom of the second trench 151 exposes a second structure 114; the position of the second trench 151 relative to the first mask layer 110 is as follows. Figure 24 The example is shown in the dashed box;

[0052] The method for forming the mask block 115 includes: referring to Figure 25 As shown, a second structure 114, exposed at the bottom of the second trench 151, forms a mask block 115. For example, see [reference needed]. Figure 25 The example BB' is a cross-section diagram in the xoz plane. Figure 24 The second structure 114 at BB' is etched through to expose the first film layer 101, and the doped region 112 is etched at a low rate or is not etched at all to be preserved.

[0053] Reference Figure 22 As shown, the composition of the second barrier layer 150 may be the same as that of the first barrier layer 120. The second barrier layer 150 may include a first sublayer 121 and a second sublayer 122 stacked together. The first sublayer 121 may include spin-coated carbon, and the second sublayer 122 may include a silicon-containing anti-reflective coating. Figure 22In the schematic cross-section of the xoz plane at AA' shown, the spin-coated carbon of the first sub-layer 121 can fill the gaps created by the removal of the first mask layer 110, such as filling the gaps between the second structures 114, so as to provide a smoother landing surface for the second photoresist layer 142 and improve the photolithography yield.

[0054] Reference Figure 26 As shown, after etching away a portion of the second structure 114, the removal... Figure 25 The second photoresist layer 142 and the second barrier layer 150 below the second photoresist layer 142. Figure 26 In the schematic diagram of the cross-section of the xoz plane at AA' shown, Figure 22 The portion of the second sublayer 122 filling the space between the second structures 114 is removed, exposing the first membrane layer 101.

[0055] In some embodiments, combined with Figure 19 and Figure 24 As shown, the position of the first trench 131 relative to the first mask layer 110 is adjacent to and / or at least partially overlaps with the position of the second trench 151 relative to the first mask layer 110.

[0056] In some embodiments, the manufacturing method further includes:

[0057] Reference Figure 17 As shown, a first photoresist layer 141 is formed on the first barrier layer 120, and the first photoresist layer 141 has a first pattern 13 exposing the first barrier layer 120; the method of forming the first trench 131 includes: etching the first barrier layer 120 exposed by the first pattern 13 to form the first trench 131; the position of the first trench 131 relative to the first mask layer 110, and the shape of the first trench 131 can be defined by the first pattern 13, which can be as follows: Figure 18 Example, corresponding to the first trench 131;

[0058] The manufacturing method further includes:

[0059] Reference Figure 22 A second photoresist layer 142 is formed on the second barrier layer 150, and the second photoresist layer 142 has a second pattern 15 exposing the second barrier layer 150. The method of forming the second trench 151 includes: etching the second barrier layer 150 exposed by the second pattern 15 to form the second trench 151; the position of the second trench 151 relative to the first mask layer 110, and the shape of the second trench 151, can be defined by the second pattern 15, and the second pattern 15 and the first pattern 13 can be... Figure 23 As shown in the figure; wherein the first pattern is complementary to the second pattern 15 and / or at least partially overlaps.

[0060] The first trench 131 and the second trench 151 exist on the first mask layer 110 in different fabrication steps, and do not exist simultaneously on the first mask layer 110. For example, a first barrier layer 120 and a patterned first photoresist layer 141 are formed on the first mask layer 110. The first trench 131 is formed through the first barrier layer 120, and the first structure 113 exposed in the first trench 131 is doped. The first barrier layer 120 and the first photoresist layer 141 are removed. A second barrier layer 150 and a patterned second photoresist layer 142 are formed on the first mask layer 110 with doped regions 112. The second trench 151 is formed through the second barrier layer 150. The second structure 114 at the bottom of the second trench 151 is etched and penetrated, breaking the second structure 114 to form a mask block 115. The second barrier layer 150 and the second photoresist layer 142 are removed to form a mask block 115. Figure 26 The mask pattern or mask structure shown. The positions and morphologies of the first trench 131 and the second trench 151 can be defined by the pattern of the photoresist layer.

[0061] Reference Figure 23 The example, Figure 23 This shows the second pattern 15 of the second photoresist layer 142 corresponding to the formation of the second trench 151 and the etching of the second structure 114. Figure 23 This illustrates the first pattern 13 of the first photoresist layer 141 corresponding to the formation of the first trench 131 and the doping of the first structure 113; the formed mask pattern or mask structure can be as follows: Figure 26 As shown.

[0062] against Figure 26 The illustrated mask pattern can be formed using a single photolithography patterning process on the first mask layer 110. Some of the light spots projected onto the first mask layer 110 are small in size and have small spacing. Reducing the size and distance of these light spots is limited by the resolution of the photolithography machine. This disclosure applies to embodiments of the invention. Figure 23 The example of two photolithography developments defines a mask pattern. The spot size and spot distance in a single development are larger than in a single development. The overlapping patterns from the two photolithography and development processes can cover the entire area of ​​the first mask layer 110, thereby reducing the resolution limitations of the photolithography machine. For example, a portion of the sub-pattern of the first pattern 13 does not overlap with the second pattern 15 and can be located between the pattern gaps of the second pattern 15; that is, some parts of the first pattern 13 and some parts of the second pattern 15 complement each other and have an adjacent relationship. The defined first trench 131 and second trench 151 can be adjacent; or a portion of the sub-pattern of the second pattern 15 can overlap with a portion of the sub-pattern of the first pattern 13. For example, the patterns corresponding to the first trench 131a and the first trench 131b are located between the second trench 151a and the second trench 151b; the pattern corresponding to the second trench 151b overlaps with the pattern corresponding to the first trench 131c.

[0063] By combining doping and etching of different materials in the first mask, selective patterning can be performed on different materials. For example, selective doping of the first structure 113 can form a doped region 112, and selective etching of the second structure 114 can form a mask block 115. The doped region 112 and the mask block 115 are combined to form a mask pattern, realizing the fabrication of a high-resolution mask pattern by a low-resolution photolithography process.

[0064] In some embodiments, the manufacturing method further includes: referring to Figure 26 As shown, a first film layer 101 is provided, and a first mask layer 110 is formed on the first film layer 101. Different regions of the first mask layer 110 are doped and etched to form doped regions 112 and mask blocks 115. There is a gap 161 between the doped regions 112 and the mask blocks 115, and the gap 161 exposes a portion of the first film layer 101. The first mask layer 110 is located on the first film layer 101. The first mask layer 110 can be used as the first film layer 101 or as an etching mask for a semiconductor structure having the first film layer 101. The fabrication method further includes etching the first film layer 101 exposed by the gap 161.

[0065] Figure 26 The diagram also shows a cross-section of AA' in the xoz plane, illustrating the etching of the exposed film layers beneath the gaps 161 between doped regions 112, between doped regions 112 and mask blocks 115, and between mask blocks 115 and mask blocks 115. This includes etching the first film layer 101 and the second film layer 102 until the second film layer 102 is penetrated. Figure 26 The mask pattern shown is transferred into the first film layer 101 and the second film layer 102; forming Figure 27 The mask structure shown. The first film layer 101 and the second film layer 102 may include silicon oxide, silicon nitride, silicon oxynitride, titanium nitride, aluminum oxide, or combinations thereof; for example, the first film layer 101 may include silicon oxide, the second film layer 102 may include titanium nitride, or only the first film layer 101 may be titanium nitride. Titanium nitride provides a denser film density and better etch-blocking performance.

[0066] Reference Figure 28 As shown, at least the doped regions 112 and mask blocks 115 on the patterned first film layer 101 are removed, leaving the first film layer 101 and the second film layer 102; or the first film layer 101 is further removed, leaving the second film layer 102 as a mask layer or mask structure for subsequent doping or etching masking of semiconductor structures. The second film layer 102 can be disposed on other film layers or structures, such as on a dielectric material.

[0067] In some embodiments, it may be used Figure 26 The mask structure shown is used for etching or ion implantation of some semiconductor structures, specifically for etching the film layer below the void 161; or using... Figure 28 The mask structure shown is used for etching or ion implantation of some semiconductor structures, specifically etching the film layer below the void 161. For example, it can be applied to the etching of dielectric materials, filling the openings or trenches after etching to form an interconnect layer; it can be applied to the etching of active region trenches in transistors, where active regions are epitaxially grown inside and outside the trenches after etching to serve as the source and drain of the transistor; it can be applied to the etching of contact openings of various active devices, forming conductive plugs in the openings after etching; and it can be applied to the cutting etching of continuous conductive structures or continuous non-conductive structures.

[0068] In some embodiments, the transistors mentioned in this disclosure may include, but are not limited to, 3D transistors, multi-channel field-effect transistors, vertical transistors, planar transistors, or other types of transistors; this disclosure does not limit the type of transistor. Figure 29 For illustrative purposes only, a schematic diagram of a semiconductor structure is provided, including: a semiconductor body 210 extending along the x-direction, wherein the semiconductor body 210 may be a strip, ridge, fin, or protrusion structure protruding from a substrate, a semiconductor layer, or other material layer; the cross-sectional shape of the semiconductor body 210 in the yoz plane may include, but is not limited to: rectangles, triangles, or other regular or irregular polygons; and including circles, ellipses, or other regular or irregular arc shapes. Different regions of the semiconductor body 210 may be doped to form the source, drain, and channel of a transistor.

[0069] In some embodiments, refer to Figure 7 As shown, a sacrificial gate 221 extends along the y-direction, covering a portion of the semiconductor body 210. A gate dielectric layer is disposed between the sacrificial gate 221 and the semiconductor body 210. The sacrificial gate 221 can be a single film structure or a multilayer film structure. The sacrificial gate 221 can be replaced by a conductive material to form a gate structure, which serves as the control gate of a transistor. An isolation structure 222 is formed on the sidewalls of the sacrificial gate 221 extending along the z-direction. The isolation structure 222 can be a sidewall structure used to define the location of the sacrificial gate 221 or the gate structure, and to support and isolate the gate structure to reduce leakage current. For example, the semiconductor body 210 may include a semiconductor material, such as silicon; the sacrificial gate 221 may include silicon. The isolation structure 222 may include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The isolation structure 222 may include a single film layer or a multilayer film structure.

[0070] In some embodiments, a plurality of spaced-apart sacrificial gates 221 may be formed. The sacrificial gates 221 cover the protruding and exposed top surface and sidewalls of the semiconductor body 210. The semiconductor body 210 extends through the bottom portion of the sacrificial gates 221 along the x-direction. A portion of the semiconductor body 210 is exposed on both sides of the sacrificial gates 221 or exposed relative to the sacrificial gates 221 between two adjacent sacrificial gates 221. The semiconductor body 210 and the sacrificial gates 221 are isolated by a gate dielectric layer. The gate dielectric layer may exist only at the location of the semiconductor body 210 covered by the sacrificial gates 221 and is not shown; or the gate dielectric layer may cover the top surface and sidewalls of the semiconductor body 210. Exemplarily, the cross-sectional shape of the semiconductor body 210 in the yoz plane may include, but is not limited to, a rectangle or approximately a rectangle. The top surface of the semiconductor body 210 and the two sidewalls in the y-direction are covered by the gate dielectric layer, which is covered by the sacrificial gates 221. The bottom surface of the semiconductor body 210 is not exposed and does not contact the sacrificial gates 221. In other embodiments, the top, bottom, and sidewalls of the semiconductor body 210 may be surrounded by a sacrificial gate 221 to form a multi-channel field-effect transistor.

[0071] In some embodiments, the sacrificial gate 221 is replaced by a conductive material to form a gate structure, the portion of the semiconductor body 210 covered by the gate structure serves as the channel region of the transistor, and the portion of the semiconductor body 210 exposed after penetrating the sacrificial gate 221 along the x-direction, or located between two adjacent sacrificial structures in the x-direction, serves as the source and drain of the transistor, and the positions of the source and drain can be interchanged.

[0072] In some embodiments, it is possible to utilize Figure 26 or Figure 28 The mask structure shown serves as an etching mask, etching downwards along the z-direction until the semiconductor body 210 between two adjacent sacrificial gates 221 is exposed. Ion implantation is then performed on the exposed semiconductor body 210 to form source and drain electrodes. Alternatively, the exposed semiconductor body 210 is etched to form source and drain trenches, and the source and drain electrodes are epitaxially grown in these trenches. During epitaxial growth, dopant gas can be introduced to increase the uniformity of dopant diffusion. Alternatively, it can also serve as an etching mask, etching downwards along the z-direction to cut off at least one sacrificial gate 221.

[0073] In some embodiments, it may be possible to utilize Figure 26 or Figure 28The mask structure shown serves as an etching mask, etching downwards along the z-direction to form openings until the source, drain, and gate structures of the semiconductor body 210 are exposed. Conductive material is filled into the openings to form conductive plugs or contact plugs that respectively contact and connect the source, drain, and gate structures, for powering the transistor. In some other embodiments, the fabrication method provided in this disclosure can be used to form other target patterns for etching or ion implantation of other device structures. This disclosure does not limit the number or arrangement of the doped regions 112 and the mask blocks 115.

[0074] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first mask layer is provided, the first mask layer comprising a first structure and a second structure alternately arranged in a first direction; The first direction intersects with the thickness direction; The first structure is doped to form a plurality of doped regions, and the plurality of doped regions are arranged along the first direction; Etch the first structure, retaining the doped region; The second structure is etched through a portion of the second structure to form multiple mask blocks; The plurality of the mask blocks are arranged along the first direction.

2. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: A first barrier layer is formed on the first mask layer; A first trench is formed that penetrates the first barrier layer and exposes the first mask layer, the first trench extending along the first direction; the method for forming the doped region includes: Ion implantation is performed on the first structure exposed at the bottom of the first trench to form the doped region.

3. The manufacturing method according to claim 2, characterized in that, Multiple first grooves are spaced apart in the first direction, and the size of the first groove in the first direction is greater than or equal to the sum of the sizes of the first structure and the second structure in the first direction.

4. The manufacturing method according to claim 2, characterized in that, The first trench includes: The first sidewall extending along the first direction; and A second sidewall is disposed opposite to the first sidewall. The second sidewall includes a plurality of first portions extending along a first direction and a second portion connecting two of the first portions. The connection between the second portion and the first portion forms an angle.

5. The manufacturing method according to claim 2, characterized in that, The manufacturing method further includes: A second barrier layer is formed on the doped region and the second structure; Forming a second trench penetrating the second barrier layer, the second trench extending along the first direction; the method of forming the mask block includes: The second structure, exposed at the bottom of the second trench, is used to form the mask block.

6. The manufacturing method according to claim 5, characterized in that, The position of the first trench relative to the first mask layer is adjacent to and / or at least partially overlaps with the position of the second trench relative to the first mask layer.

7. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: A first photoresist layer is formed on the first barrier layer, the first photoresist layer having a first pattern that exposes the first barrier layer; the method of forming the first trench includes: The first barrier layer exposed by the first pattern is etched to form the first trench; The manufacturing method further includes: A second photoresist layer is formed on the second barrier layer, the second photoresist layer having a second pattern that exposes the second barrier layer; the method of forming the second trench includes: The second barrier layer exposed by the second pattern is etched to form the second trench; The first pattern is complementary to the second pattern and / or at least partially overlaps with it.

8. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: A first film layer is provided, and a first mask layer is formed on the first film layer; wherein, there is a gap between the doped region and the mask block, and the gap exposes a portion of the first film layer; the fabrication method further includes: The first film layer exposed by the voids is etched.

9. The manufacturing method according to claim 1, characterized in that, The method for forming the first mask layer includes: A first semiconductor layer is formed, and a plurality of third trenches are formed penetrating the first semiconductor layer; the third trenches extend along a second direction, and the plurality of third trenches divide the first semiconductor layer into a plurality of first strip structures; the second direction intersects with the first direction; The second structure is formed in the third trench.

10. The manufacturing method according to claim 1, characterized in that, The first structure includes silicon; the doping element in the doped region includes boron.

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