Wafer local topography risk assessment method and system, device, medium and product
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN ESWIN MATERIAL TECHNOLOGY CO LTD
- Filing Date
- 2026-03-24
- Publication Date
- 2026-06-19
AI Technical Summary
Existing technologies are unable to sensitively and reliably assess the potential risks of local morphological anomalies on wafer surfaces to subsequent photolithography processes, leading to defects such as defocusing and overlay errors in the photolithography process.
By acquiring nanoscale three-dimensional topographic data, dividing it into multiple evaluation regions, calculating the statistical distribution parameters (such as root mean square value) of each region, and comparing them with a preset risk threshold, an evaluation result is generated.
It enables sensitive and quantitative assessment of local morphological risks in wafers, improving the risk identification capability and process defect prevention capability of photolithography processes.
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Figure CN122249026A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor wafer manufacturing technology, and in particular to a method and system for assessing local morphology risks of wafers, electronic devices, computer-readable storage media, and computer program products. Background Technology
[0002] In semiconductor manufacturing processes, the microscopic morphology quality of the wafer surface is a crucial factor affecting the yield of subsequent critical process steps such as photolithography. To assess the adaptability of the wafer surface to photolithography processes, it is typically necessary to measure and analyze its surface morphology. Traditionally, related techniques rely on evaluating the morphology parameters of the entire wafer or a large area, such as calculating global flatness indices. However, these evaluation methods based on macroscopic or global morphology features are often insufficiently sensitive to localized, subtle morphological anomalies on the wafer surface. These local anomalies may originate from front-end processes such as dicing and grinding; although small in scale, they can pose potential risks to the focusing and overlay accuracy of the photolithography process. Therefore, how to effectively and accurately assess the process risks posed by localized wafer morphology anomalies has become a pressing technical problem requiring improvement in this field. Summary of the Invention
[0003] The first aspect of this application provides a method for assessing the local topography risk of a wafer, comprising: acquiring nanoscale three-dimensional topography data of the wafer surface; dividing the three-dimensional topography data into multiple assessment regions; for each assessment region, calculating the statistical distribution parameter of the height data within that region, wherein the statistical distribution parameter characterizes the overall topography fluctuation energy of the corresponding assessment region; comparing the statistical distribution parameter of each assessment region with at least one preset risk threshold to determine the risk level corresponding to the assessment region; and generating an assessment result indicating the risk of the wafer to subsequent photolithography processes based on the risk level of each assessment region.
[0004] Specifically, current technologies rely on global parameters such as overall wafer warpage and total thickness variation for evaluation, making it difficult to capture and quantify localized nanoscale surface anomalies. These local anomalies are precisely the key risk sources causing defects such as defocusing and overlay errors in photolithography. The proposed solution abandons the traditional global perspective and instead focuses on regional evaluation of the wafer surface. By acquiring nanoscale three-dimensional topography data and dividing the evaluation area, it provides a data foundation for local analysis. Specifically, it calculates the statistical distribution parameters of height data within each local area. These parameters (such as the root mean square value) characterize the overall topography fluctuation energy of that area, offering greater stability and comprehensiveness compared to a single extreme point. This allows for a more sensitive reflection of topography anomaly patterns that may lead to photolithography problems. Furthermore, by comparing the calculated statistical parameters with preset risk thresholds, the abstract topography data can be transformed into a clear risk level, ultimately integrating to generate an evaluation result for the entire wafer.
[0005] In one specific embodiment of the first aspect of this application, before calculating the statistical distribution parameters of the height data in each evaluation region, the method further includes applying a high-pass filter to the height data in each evaluation region to remove low-frequency background components introduced by the overall wafer warpage. Thus, by filtering out low-frequency background signals, the evaluation is made more focused on truly harmful local high-frequency fluctuations.
[0006] In one specific embodiment of the first aspect of this application, the statistical distribution parameter is the root mean square (RMS) value. Thus, using the RMS value as the statistical parameter can effectively and stably characterize the overall fluctuation intensity of the local morphology.
[0007] In one specific embodiment of the first aspect of this application, the root mean square value is calculated based on a preset calculation model, wherein the calculation model is: Site_RMS=sqrt((1 / n) Σ(Zi-Z_avg)²), where Zi is the height of the i-th data point within the evaluation region, Z_avg is the average height of all data points within the evaluation region, and n is the total number of data points within the evaluation region. This clarifies the specific mathematical model for calculating the root mean square value, making the technical solution clear and repeatable, and providing a precise numerical basis for threshold setting.
[0008] In one specific embodiment of the first aspect of this application, the preset at least one risk threshold includes a single risk threshold; comparing the statistical distribution parameters of each assessment area with the preset at least one risk threshold to determine the risk level corresponding to the assessment area includes: dividing the assessment area into two risk levels based on the single risk threshold; comparing the statistical distribution parameters of each assessment area with the single risk threshold to determine the assessment area as one of the two risk levels. Thus, using a single threshold for dichotomous risk assessment simplifies the decision-making logic and facilitates rapid identification and location of high-risk areas.
[0009] In one specific embodiment of the first aspect of this application, the preset at least one risk threshold includes multiple risk thresholds; comparing the statistical distribution parameters of each assessment area with the preset at least one risk threshold to determine the risk level corresponding to the assessment area includes: dividing multiple risk levels based on multiple risk thresholds; comparing the statistical distribution parameters of each assessment area with multiple risk thresholds to determine that the assessment area is one of multiple risk levels. Thus, by setting multiple thresholds to achieve fine-grained risk classification, richer assessment information can be provided, supporting differentiated subsequent processing strategies.
[0010] In one specific embodiment of the first aspect of this application, an assessment result indicating the risk of the wafer to subsequent photolithography processes is generated based on the risk level of each assessment area. This further includes assigning different visualization colors to different risk levels and marking them on each assessment area. Thus, visualizing the results through color mapping makes the risk assessment results readily apparent, greatly improving the readability and operability of the results.
[0011] In one specific embodiment of the first aspect of this application, after generating an assessment result indicating the risk of the wafer to subsequent photolithography processes based on the risk level of each assessment area, the method further includes: determining whether the wafer is qualified based on the number or proportion of assessment areas with a specified risk level in the assessment result. Thus, this step elevates the assessment from local risk assessment to overall wafer qualification determination, providing a quantitative basis for wafer release or rejection.
[0012] In one specific embodiment of the first aspect of this application, after generating an assessment result indicating the risk of the wafer to subsequent photolithography processes based on the risk level of each assessment area, the method further includes: feeding the assessment result back to the front-end wafer manufacturing process to adjust the process parameters of the front-end wafer manufacturing process. Thus, by feeding the assessment result back to the front-end process, a closed-loop process control of "detection-analysis-adjustment" is formed, which helps to suppress the recurrence of defects from the source.
[0013] In one specific embodiment of the first aspect of this application, the front-end wafer manufacturing process is a wafer dicing process or a wafer back-side grinding process. This clarifies the key front-end feedback process, making closed-loop control more targeted and operable.
[0014] In one specific embodiment of the first aspect of this application, dividing the three-dimensional topography data into multiple evaluation regions includes: dividing the three-dimensional topography data into multiple evaluation regions based on the size of the lithographic exposure field. This aligns the division of the evaluation regions with the basic units of the lithography process, making the risk assessment results directly related to the actual impact of lithographic imaging, and thus providing more practical guidance for the assessment.
[0015] In one specific embodiment of the first aspect of this application, multiple evaluation regions are distributed in a regular two-dimensional array grid. This regular grid division simplifies the data processing logic, facilitates alignment with the wafer coordinate system and the lithography machine coordinate system, and also facilitates the statistical analysis and presentation of results.
[0016] A second aspect of this application provides a wafer local topography risk assessment system. This system includes an acquisition module, a partitioning module, a calculation module, a judgment module, and an output module. The acquisition module is configured to acquire nanoscale three-dimensional topography data of the wafer surface. The partitioning module is configured to divide the three-dimensional topography data into multiple assessment regions. The calculation module is configured to calculate the statistical distribution parameters of the height data within each assessment region. These statistical distribution parameters characterize the overall topography fluctuation energy of the corresponding assessment region. The judgment module is configured to compare the statistical distribution parameters of each assessment region with at least one preset risk threshold to determine the risk level corresponding to the assessment region. The output module is configured to generate an assessment result indicating the wafer's risk to subsequent lithography processes based on the risk levels of each assessment region. This system achieves automated workflow of the aforementioned assessment method through modular design, providing physical support for integration into the production line.
[0017] In one specific embodiment of the second aspect of this application, a filtering module is also included, configured to apply a high-pass filter to the height data in each evaluation region before the statistical calculation module performs calculations, in order to remove low-frequency background components introduced by the overall wafer warpage. The addition of this filtering module improves the accuracy of the system evaluation, enabling it to eliminate overall topographic interference and focus on local anomalies.
[0018] A third aspect of this disclosure provides an electronic device including a processor and a memory, the memory being used to store processor-executable instructions, and the processor being used to perform the evaluation method described in the first aspect above.
[0019] The fourth aspect of this disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the evaluation method described in the first aspect above.
[0020] The fifth aspect of this disclosure provides a computer program product comprising a computer program that, when executed by a processor, implements the evaluation method described in the first aspect above. Attached Figure Description
[0021] Figure 1 This is one of the schematic flowcharts for a method to assess the local topographic risk of a wafer provided in this application.
[0022] Figure 2 The second schematic flowchart illustrates a method for assessing local morphological risks in wafers provided in this application.
[0023] Figure 3 The third schematic flowchart of a method for assessing local morphological risks in wafers provided in this application.
[0024] Figure 4 The fourth schematic flowchart of a method for assessing local morphological risks in wafers provided in this application.
[0025] Figure 5 Fifth schematic flowchart of a method for assessing local morphological risks of wafers provided in this application.
[0026] Figure 6 One of the risk level maps displayed on the wafer for the wafer local topography risk assessment method provided in this application.
[0027] Figure 7 The second risk level map shown on the wafer, based on the wafer local topography risk assessment method provided in this application.
[0028] Figure 8 This is the sixth schematic flowchart of a method for assessing local morphological risks in wafers provided in this application.
[0029] Figure 9 This is the seventh schematic flowchart of a method for assessing local morphological risks in wafers provided in this application.
[0030] Figure 10 This is the eighth schematic flowchart of a method for assessing local morphological risks in wafers provided in this application.
[0031] Figure 11 The diagram shown is one of the principle block diagrams of an evaluation system provided in an embodiment of this application.
[0032] Figure 12 The diagram shown is a second principle block diagram of an evaluation system provided in an embodiment of this application.
[0033] Figure 13 The diagram shown is the third principle block diagram of an evaluation system provided in an embodiment of this application.
[0034] Figure 14 The diagram shown is a block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0035] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.
[0036] In the field of quality control in semiconductor wafer manufacturing, to ensure the yield of subsequent critical processes such as photolithography, it is usually necessary to evaluate the surface flatness of the wafer. This can be done by evaluating global wafer topography parameters, specifically including global back-side reference readings or flatness at specific sites. This approach measures the overall height variation across the entire wafer surface and calculates a single value or a few macroscopic parameters representing the maximum height difference over the entire area. Its basic principle is to treat the wafer as a whole and extract its macroscopic contour features. This method can reflect the overall warpage or bending of the wafer with simple quantitative indicators, facilitating rapid and preliminary screening on the production line.
[0037] However, when this scheme is applied to evaluate high spatial frequency local topographic anomalies introduced by processes such as dicing and grinding, its performance is not ideal. This is because, in order to optimize its ability to characterize global macroscopic topography, its inherent design based on global averaging or extreme point sampling inevitably masks or smooths out local, minute nanoscale topographic fluctuations, resulting in insufficient sensitivity in evaluating such high-frequency anomalies. When evaluating defects such as wafer dicing marks, changes in global flatness indices are often insignificant, failing to reliably and sensitively indicate the potential risks these local anomalies may pose to the defocusing and overlay accuracy of subsequent photolithography processes. This could lead to wafers with potential defects being introduced into the next process.
[0038] In-depth analysis revealed that the root causes of the aforementioned problems are multifaceted. For example, from an information extraction perspective, global topography parameters essentially compress a large amount of local height data, a process that loses spatial distribution details, particularly the local anomaly information carried by high-frequency components. Furthermore, from a physical mechanism perspective, operations such as exposure and focusing in photolithography are actually performed within finite local exposure fields, and global flatness parameters cannot accurately map to the actual topography state of these local process windows. Additionally, from a signal processing perspective, low-frequency background components such as overall wafer warpage dominate the global parameters, drowning out mid-to-high-frequency topography signals caused by local process defects. These factors collectively limit the accuracy and reliability of the proposed solution in predicting process risks caused by local topography.
[0039] At least one embodiment of this application provides a method and system for assessing local morphology risks on wafers, an electronic device, a computer-readable storage medium, and a computer program product, to at least solve the aforementioned problems. This assessment method can at least address the issue that evaluation methods based on global wafer flatness parameters cannot sensitively and stably assess the risks posed by local morphology anomalies on the wafer surface to subsequent lithography processes. For example, after front-end processes such as dicing and grinding, the wafer surface may develop local undulations with high spatial frequencies (such as dicing marks). These local undulations cannot be effectively identified in evaluations based on global backside reference or front-end reference because the data is averaged or only extreme points are considered, but they pose a significant threat to the defocusing and overlay accuracy of the lithography process. In the assessment method of this application, three-dimensional morphology data with nanometer-level precision is acquired, divided into multiple local assessment units, and a statistical distribution parameter characterizing the overall morphology fluctuation energy within each unit is calculated. The risk is then assessed by comparing this parameter with a preset threshold. This approach shifts the focus of assessment from the macro-level to the micro-level, and from relying on unstable extreme values to relying on stable statistics, thereby achieving a sensitive and quantitative assessment of local morphological risks.
[0040] Figure 1 This is a schematic flowchart illustrating a method for assessing local topographic risks in a wafer according to an embodiment of this application. Figure 1 As shown, the evaluation method may include the following steps S100 to S500.
[0041] S100: Acquire nanoscale three-dimensional topographic data of the wafer surface. This step provides the raw data foundation for the entire evaluation process. Nanoscale three-dimensional topographic data refers to a dataset that reflects the height information of each point on the wafer surface with a vertical resolution at the nanometer (nm) level. For example, high-precision measurement equipment such as white light interferometers, phase-shifting interferometers, or atomic force microscopes can be used to scan and measure the wafer surface. The measured data can be organized into a two-dimensional matrix, where each element corresponds to the height of a sampling point on the wafer surface relative to a reference plane.
[0042] S200 divides the three-dimensional topography data into multiple evaluation regions. For example, this step deconstructs the topography information of the entire wafer into multiple smaller, independently analyzable local units, i.e., evaluation regions, which is key to shifting from global evaluation to local evaluation.
[0043] It should be noted that there are multiple ways to divide the area into grids. For example, the grid can be divided according to fixed geometric dimensions (such as 10mm × 10mm), or it can be customized according to other process requirements (such as the photolithography process mentioned in the following embodiments). By analyzing each evaluation area independently, the specific location of the risk can be pinpointed.
[0044] S300: For each assessment area, calculate the statistical distribution parameters of the height data within that area. These parameters characterize the overall topographic fluctuation energy of the corresponding assessment area. For example, this step quantifies the topographic features of each local area, aiming to use a comprehensive numerical value to represent the undulation intensity of all height data points within that area, i.e., the "fluctuation energy".
[0045] It should be noted that "statistical distribution parameter" refers to a mathematical characteristic that can quantify the degree of dispersion of data, such as the root mean square value or standard deviation. The calculation of this parameter takes into account the contribution of all data points within a region to the overall fluctuation, and is therefore more stable and comprehensive than the "peak-valley" parameter that only focuses on the highest and lowest points.
[0046] S400, compare the statistical distribution parameters of each assessment area with at least one preset risk threshold to determine the risk level corresponding to the assessment area. For example, this step transforms quantified morphological feature parameters into judgments with clear technological significance, and the preset risk threshold is a critical value used to distinguish risk levels. By comparing the statistical distribution parameters calculated for each assessment area with this (or these) thresholds, the area can be divided into different risk levels, such as "low risk" and "high risk," thereby giving abstract morphological data a practical risk meaning.
[0047] S500: Based on the risk level of each assessment area, an assessment result indicating the wafer's risk to subsequent photolithography processes is generated. For example, this step summarizes and presents all the aforementioned local risk assessment information. It should be noted that in the embodiments of this application, the presentation format of the assessment results is not limited. For example, the generated assessment results can be a text report indicating which assessment areas have high risk; or they can be graphical results, such as a visualization map on a wafer schematic showing the risk level of each area. This assessment result provides a direct basis for determining the process suitability of the entire wafer and locating problem areas.
[0048] As mentioned earlier, current technologies rely on global parameters such as overall wafer warpage and total thickness variation for evaluation, making it difficult to capture and quantify local nanoscale surface anomalies. These local anomalies are precisely the key risk sources causing defects such as defocusing and overlay errors in the lithography process. The evaluation method shown in steps S100 to S500 abandons the traditional global perspective and instead performs a zoned evaluation of the wafer surface. By acquiring nanoscale three-dimensional topography data and dividing the evaluation area, a data foundation for local analysis is provided. Specifically, the statistical distribution parameters of the height data in each local area are calculated. These parameters (such as the root mean square value) can characterize the overall topography fluctuation energy of the area, which is more stable and comprehensive than a single extreme point, thus more sensitively reflecting topography anomaly patterns that may lead to lithography problems. Furthermore, by comparing the calculated statistical parameters with preset risk thresholds, the abstract topography data can be transformed into a clear risk level, ultimately integrating to generate an evaluation result for the entire wafer.
[0049] For example, in one application scenario, a silicon wafer that has undergone back-side grinding is sent to an inspection station. First, a white-light interferometer scans the wafer surface, obtaining a 3D topographic map containing millions of height data points. Then, data processing software divides this full-wafer data map into hundreds of evaluation regions according to a preset grid. Next, the software calculates the statistical distribution parameter values of all height points in each region. Then, the system compares the parameter values of each region with a pre-set risk threshold (e.g., 0.8 nm), marking all regions as "qualified" or "out of tolerance." Finally, the system generates a report listing the locations and parameter values of all "out of tolerance" regions and determining whether the wafer can be used for subsequent photolithography. Thus, the entire process is automated, requiring no manual intervention in interpreting the raw data. It should be noted that this process is designed to be completed without human intervention, rather than eliminating human intervention altogether.
[0050] In the embodiments of this application, "lithography process risk" refers to the potential for subsequent lithography process performance to degrade or defects to occur due to abnormal local topography of the wafer. For example, it may include, but is not limited to: optical defocus caused by local topography fluctuations, overlay errors that lead to excessive pattern overlay accuracy, or other imaging defects caused by local topography interference.
[0051] In at least one embodiment of this application, "nanoscale three-dimensional topography data" refers to any dataset capable of characterizing the three-dimensional undulations of a wafer surface with nanoscale precision. For example, it may include, but is not limited to, data containing the three-dimensional coordinates (X, Y, Z) of densely sampled points acquired by nanoscale topography measurement devices such as white light interferometers, phase-shifting interferometers, or atomic force microscopes, or combinations thereof. Specifically, the resolution of the data in the height (Z) direction can reach sub-nanometer to several nanometer levels.
[0052] In at least one embodiment of this application, the "risk level" indicates the degree of risk posed by the corresponding evaluation area to subsequent lithography processes, where a high-risk level indicates that local morphological anomalies in the evaluation area may lead to lithography defects. This clarifies the technical meaning of the risk level, directly linking it to potential lithography defects and emphasizing the ultimate purpose of the evaluation. Specifically, the "risk level" is not an abstract score, but rather a concrete indication of the degree of risk posed by the corresponding evaluation area to subsequent lithography processes. In particular, a "high-risk level" is defined as indicating that local morphological anomalies in the area (i.e., fluctuations characterized by their statistical distribution parameters) have a high probability of causing actual lithography defects, such as pattern blurring due to defocusing or interlayer alignment failure due to overlay errors. This definition directly links morphological feature data to the final process yield loss risk, making the goal of the entire evaluation method very clear: not simply measuring morphology, but assessing the hazard of morphology to specific downstream processes.
[0053] In at least one embodiment of this application, the "preset at least one risk threshold" is determined by correlation analysis between statistical distribution parameters and overlay errors or defocus defects in the lithography process. This reveals the scientific origin of the risk threshold, demonstrating its empirical correlation with process defects and morphology parameters, thereby ensuring the accuracy and effectiveness of risk assessment. Specifically, a large amount of historical or experimental wafer morphology data (calculating its local statistical parameters) and actual measured overlay error data or observed defocus defect information after the lithography process can be collected. Through statistical analysis (such as correlation analysis, regression analysis, ROC curve analysis, etc.), a quantitative or qualitative relationship between morphology statistical parameters (such as local RMS) and the probability or severity of process defects can be identified. Based on this relationship, one or more morphology parameter thresholds that best distinguish between "causing defects" and "not causing defects" are selected as risk thresholds. The thresholds determined by this method have a solid foundation of process data, making risk warnings and classifications based on these thresholds highly confident and able to truly reflect the actual impact of morphology anomalies on the lithography process.
[0054] In at least one embodiment of this application, such as Figure 2 As shown, before step S300 in the above evaluation method, which calculates the statistical distribution parameters of the height data in each evaluation area, an optional preprocessing step S600 can be included to improve the accuracy and specificity of the evaluation. Specifically, the preprocessing step S600 is to apply a high-pass filter to the height data in each evaluation area to remove the low-frequency background component introduced by the overall wafer warping.
[0055] During wafer manufacturing or clamping, overall bending or warping may occur. This macroscopic deformation manifests as a low-frequency, slowly changing background signal in height data. If statistical parameters for local areas are directly calculated from such data, this background signal will mix with high-frequency local fluctuations introduced by process anomalies such as dicing marks, resulting in calculation results that do not purely reflect the degree of local anomalies. Step S600 uses high-pass filtering technology to selectively filter out components with longer spatial wavelengths (corresponding to low frequencies) and retain components with shorter wavelengths (corresponding to high frequencies). After this processing, the impact of overall wafer warping is weakened in the height data of each evaluation area, while local high-frequency morphological features (such as dicing marks) are highlighted. Thus, the statistical distribution parameters calculated based on the filtered data in subsequent step S300 can more accurately characterize the morphological irregularities of that area caused by process fluctuations, thereby making risk assessment more focused on the target defect.
[0056] For example, in one application scenario, a wafer exhibits significant overall "bowl-shaped" warping, along with fine dicing marks on its surface. Without high-pass filtering, when calculating the RMS value of an evaluation region located at the wafer edge, the large contribution of the overall warping would dominate the calculation, resulting in a high RMS value that might be misjudged as high-risk. However, in reality, the dicing marks in that region might have very little variation. After high-pass filtering in step S310, the overall "bowl-shaped" background is removed, and the calculated RMS value will primarily reflect the degree of dicing mark variation, thus providing a more realistic risk assessment.
[0057] In the embodiments of this application, "high-pass filtering" refers to any mathematical processing used to attenuate or remove low-frequency components from a signal or data while preserving or enhancing high-frequency components. For example, it may include, but is not limited to: digital high-pass filters (such as Butterworth or Chebyshev filters), residual data after subtracting the low-frequency background represented by a polynomial fit or moving average, or combinations thereof. Specifically applied to this application, its purpose is to remove low-frequency spatial wavelength components introduced by overall wafer warping, thereby highlighting local mid-to-high frequency topographic features introduced by processes such as dicing lines.
[0058] In at least one embodiment of this application, the statistical distribution parameter calculated in step S300 above can be the root mean square (RMS) value. Among the many statistics that can be used to characterize the degree of data dispersion, the RMS value is a commonly used and standard parameter for measuring surface roughness or fluctuation energy. For the height data point set of a local wafer topography, the RMS value is obtained by calculating the square root of the average of the squares of the deviations of each point's height from the average height. Therefore, it is more sensitive to larger deviations (i.e., larger fluctuations) in the data, and large local fluctuations are often a direct cause of lithography process risks. At the same time, the RMS value is stable in calculation and relatively less affected by individual extreme noise points, and can provide an accurate estimate of the overall topography fluctuation energy of the region.
[0059] In at least one embodiment of this application, the root mean square value is calculated based on a preset calculation model, which is as follows.
[0060] Site_RMS=sqrt((1 / n) Σ(Zi-Z_avg)²) In this calculation model, Zi is the height of the i-th data point in the evaluation area, Z_avg is the average height of all data points in the evaluation area, and n is the total number of data points in the evaluation area.
[0061] This calculation model uses the standard mathematical definition of the root mean square (RMS) value. It first calculates the deviation (Zi - Z_avg) between the height Zi of each data point within the region and the region's average height Z_avg. Then, it squares all deviations and sums them. Dividing the sum by the total number of data points n yields the mean squared deviation. Finally, taking the square root gives the Site_RMS value for the region. This formula is the standard method for calculating the root mean square statistic, with a clear physical meaning: it characterizes the root mean square deviation of height data within a region relative to its average value, intuitively reflecting the root mean square amplitude of topographic fluctuations. In implementation, this calculation is clear and error-free, whether implemented through software algorithms or hardware circuits. Furthermore, the RMS value calculated based on this explicit formula is a deterministic quantity, providing a precise and unified measurement benchmark for subsequent correlation with process experimental data and the setting of scientific risk thresholds, ensuring the consistency of evaluation results across different equipment and wafer batches.
[0062] In the embodiments of this application, "statistical distribution parameter" refers to any mathematical parameter that can quantify the dispersion or fluctuation characteristics of a dataset (especially high-resolution data). For example, it may include, but is not limited to: root mean square value, standard deviation, mean absolute deviation, or combinations thereof. Specifically, the parameter can be expressed by the formula Site_RMS = sqrt((1 / n)). Σ (Zi- Z_avg)² is calculated.
[0063] In the embodiments of this application, there is no limit to the number of risk thresholds set, that is, the number of risk level divisions, and they can be designed according to actual needs.
[0064] In some embodiments of this application, such as Figure 3 As shown, the "preset at least one risk threshold" mentioned in step S400 above includes a single risk threshold, so step S400 may include the following steps S410 and S420.
[0065] S410 divides two risk levels based on a single risk threshold.
[0066] S420 compares the statistical distribution parameters of each assessment area with a single risk threshold to determine whether the assessment area falls into one of two risk levels.
[0067] Figure 3 Steps S410 and S420 shown illustrate a concise and efficient risk dichotomy logic. In initial applications or process scenarios with a clear binary division of risk tolerance, setting a single risk threshold is an efficient and concise implementation method. This threshold is typically determined based on historical process data, simulation analysis, or experimental correlation, representing a critical risk level. By comparing the statistical distribution parameters (such as RMS values) calculated for each assessment region with this single threshold, regions can be directly divided into two levels: "acceptable" (below the threshold) or "high risk" (above or equal to the threshold). This dichotomy logic is clear and quick, making it ideal for applications requiring rapid screening and alarms. It immediately highlights all local areas exceeding safety limits on the wafer map, allowing operators or automated systems to quickly identify problem areas and implement subsequent operations such as re-inspection, marking, or isolation, achieving rapid response in risk management.
[0068] For example, in a rapid screening scenario, the production line sets only one critical risk threshold for each wafer, such as Site_RMS = 1.0 nm. In step S400, the system compares the Site_RMS value of each evaluation area to 1.0 nm. If the RMS value of any area exceeds 1.0 nm, that area is marked red (high risk). Operators can immediately see all red alert areas on a visualization interface and quickly make handling decisions.
[0069] In other embodiments of this application, such as Figure 4 As shown, the "preset at least one risk threshold" mentioned in step S400 above includes multiple risk thresholds, so step S400 may include the following steps S410a and S420a.
[0070] S410a classifies multiple risk levels based on multiple risk thresholds.
[0071] S420a compares the statistical distribution parameters of each assessment area with multiple risk thresholds to determine the assessment area as one of multiple risk levels.
[0072] To achieve more refined management of local topographic risks on wafers, in Figure 3 Steps S410a and S420a introduce multiple risk thresholds. For example, multiple threshold boundaries such as "low risk," "medium risk," and "high risk" can be set to divide the assessment area into three or more risk levels. During the assessment, the statistical parameters of each area are compared with this series of thresholds to determine its specific risk level. The advantage of multi-level risk assessment is that it can not only identify areas that are definitely problematic, but also identify areas that are on the edge or require attention. This provides process engineers with a more detailed quality profile, helping to differentiate the severity and urgency of problems. Based on different risk levels, differentiated measures can be taken, such as scrapping chips corresponding to high-risk areas, focusing on monitoring or downgrading medium-risk areas, thereby ensuring yield while potentially reducing unnecessary material waste and achieving leaner manufacturing process control.
[0073] In at least one embodiment of this application, such as Figure 5 As shown, step S500 above, which generates an assessment result indicating the risk of the wafer to subsequent photolithography processes based on the risk level of each assessment area, can also include a sub-step S510 to enhance the readability of the results: assigning different visualization colors to different risk levels and marking them on each assessment area. Transforming data into intuitive graphics is key to efficient information transmission; this method adds a visualization annotation step when generating risk assessment results. Specifically, as... Figure 6 (Shown in color) and Figure 7 (correspond Figure 6 As shown in the diagram (converted to grayscale or different brightness levels), the system assigns different colors to different risk levels (e.g., green for acceptable, yellow for warning, and red for high risk), and fills or marks these colors on the corresponding evaluation areas on the wafer planar diagram. In this way, the originally abstract numerical and level information is transformed into a color-coded wafer risk map. Process engineers or automated inspection systems no longer need to interpret complex data reports; they can instantly grasp the distribution, clustering, and severity of risk areas on the entire wafer simply by observing the color distribution. This visualization method greatly lowers the barrier to interpretation, accelerates decision-making, and facilitates rapid location of problem areas and analysis of defect patterns (e.g., whether they exhibit edge rings, random distribution, or clustered distribution).
[0074] For example, in one scenario, an engineer views an evaluation report for a wafer on a computer. The most prominent element in the report is a color wafer image, with most areas in green, a few in yellow, and a small, continuous red area at the wafer's edge. This allows the engineer to visually identify that the main risks of the wafer are concentrated in the red area at the edge, and directly click on the red area to view the specific RMS value. Combined with other information, the engineer can then determine whether adjustments to the preceding grinding process parameters are necessary.
[0075] In the embodiments of this application, "visualized color" refers to any presentation method used to intuitively distinguish different categories or numerical ranges through different colors on a graphical interface. For example, this may include, but is not limited to: using green, yellow, and red to represent low, medium, and high risk levels respectively in a risk map; or using a continuous chromatographic gradient from blue to red to map changes in statistical parameters from low to high, or combinations thereof. Specifically, colors are labeled on corresponding assessment areas to generate a wafer-level risk level distribution map.
[0076] In at least one embodiment of this application, see again Figure 6 Multiple evaluation regions are distributed in a regular two-dimensional array grid. Dividing the wafer surface (excluding the exclusion zone) into neatly arranged rectangular or square grid regions of the same size based on the exposure field size or other regular dimensions is an efficient and universal implementation method. This regular grid division gives each evaluation region a clear boundary and center coordinate, facilitating data acquisition planning and data segmentation for topography measurement equipment. During data processing, the algorithm can traverse all regions according to a fixed grid index order, with clear and simple logic. More importantly, the regular grid is easy to match with the wafer's planar coordinate system and the lithography machine's step coordinates, facilitating the direct mapping of risk assessment results to the machine's control system to guide regional adjustments of exposure parameters. Furthermore, when visualizing the results, the regular grid can generate a neat and intuitive risk map, making it easy to observe the distribution patterns of defects and to perform statistical analysis and proportional calculations of the number of regions.
[0077] In at least one embodiment of this application, such as Figure 8 As shown, after step S500, the evaluation method may further include a wafer-level synthesis determination step S700, as detailed below.
[0078] S700 determines whether a wafer is qualified based on the number or proportion of assessment areas with a specified risk level in the assessment results.
[0079] During the risk assessment of each local area, a comprehensive judgment must be made on whether the entire wafer can be used for subsequent photolithography processes. Step S700 provides the specific logic for completing this judgment. After obtaining the risk level of each area, the system counts the number of areas marked with a specific risk level (usually "high risk"), or calculates its proportion of all assessed areas. Then, this number or proportion is compared with a preset wafer-level control limit. For example, it can be stipulated that if the number of high-risk areas exceeds 5, or the proportion of high-risk areas exceeds 1%, the wafer is deemed unqualified. This judgment method aggregates scattered local risk information into a holistic quality indicator, making the qualification judgment based on evidence and avoiding the subjectivity and arbitrariness of human judgment.
[0080] In at least one embodiment of this application, such as Figure 9 As shown, after step S500, a process feedback control step S800 may also be included, as detailed below.
[0081] S800 feeds the evaluation results back to the front-end wafer manufacturing process to adjust the process parameters of the front-end wafer manufacturing process.
[0082] Step S800 elevates this evaluation method from a simple inspection tool to an active link in the process control loop. The evaluation results are not only used for the current wafer's interpretation but, more importantly, are systematically fed back to the upstream manufacturing processes that produced the wafer (e.g., dicing, grinding, polishing). The feedback information can be specific, including the distribution pattern of high-risk areas and the degree to which statistical parameters exceed limits. Upon receiving this feedback, the upstream process control system can automatically or assisted operators adjust relevant process parameters according to preset control rules, such as adjusting the feed rate of the dicing blade, the rotational speed and pressure of the grinding disc, and the flow rate of the polishing slurry. Through this closed-loop feedback mechanism, when the evaluation detects a specific morphological defect pattern caused by a upstream process, the source process can be corrected in a timely manner, thereby preventing the same problem from recurring on subsequent wafers. This achieves a shift from passive detection to proactive prevention, which is of great significance for stabilizing the process and continuously improving yield.
[0083] In at least one embodiment of this application, the front-end wafer manufacturing process is either a wafer dicing process or a wafer back-side grinding process. Wafer dicing and back-side grinding are critical processes in wafer manufacturing that are highly susceptible to introducing localized mechanical stress and morphological anomalies. The dicing process may cause microcracks or undulations in the area near the dicing kerf; back-side grinding directly affects the overall thickness and flatness of the wafer, and improper parameters can easily lead to localized thickness unevenness or subsurface damage. The morphological anomalies introduced by these processes are precisely the risk sources that this evaluation method focuses on capturing. For example, if the evaluation finds that high-risk areas regularly appear around the dicing kerf, the dicing speed, feed force, or cooling parameters can be adjusted accordingly; if the risk is found to be related to the thickness distribution, the grinding process formulation can be adjusted accordingly. This precise feedback makes the process optimization direction of the front-end process clear, and can quickly and effectively eliminate or mitigate the identified morphological risk sources, fully leveraging the effectiveness of closed-loop control.
[0084] In at least one embodiment of this application, such as Figure 10 As shown, step S200 above, which divides the three-dimensional topography data into multiple evaluation regions, may include step S210 as follows.
[0085] S210 divides the 3D topography data into multiple evaluation regions based on the size of the lithography exposure field. The wafer area covered by a lithography machine in a single exposure is called an exposure field, and subsequent processes such as development and etching are typically performed in units of exposure fields. Therefore, the impact of local topography anomalies on chip yield ultimately manifests in its effect on the pattern transfer quality within one or more exposure fields. This scheme defines the size of the evaluation region as corresponding to the size of the lithography exposure field (e.g., equal to or slightly smaller than the size of an exposure field). Thus, each evaluation region essentially corresponds to a potential lithography processing unit. The topography risk level calculated within this region can be directly interpreted as the risk level faced by that exposure field in subsequent lithography processes. This alignment establishes a direct spatial mapping relationship between topography evaluation and the final process. For example, an evaluation region marked as high-risk indicates that the exposure field at that location requires special attention or process compensation, which greatly enhances the practical value of the evaluation results.
[0086] In at least one embodiment of this application, "evaluation region" refers to any sub-region defined for independent analysis of the local morphology of a wafer surface. For example, it may include, but is not limited to: regular grid regions defined on the wafer surface based on the size of the lithography exposure fields, irregular regions defined according to the chip cell layout, or combinations thereof. Specifically, the size of the region may correspond to the size of one or more lithography exposure fields, for example, a rectangular region of 26mm x 33mm or 33mm x 26mm.
[0087] At least one embodiment of this application also provides a wafer local topography risk assessment system, such as Figure 11 As shown, it may include an acquisition module 100, a partitioning module 200, a calculation module 300, a judgment module 400, and an output module 500. The acquisition module 100 is configured to acquire nanoscale three-dimensional topographic data of the wafer surface. The partitioning module 200 is configured to divide the three-dimensional topographic data into multiple evaluation regions. The calculation module 300 is configured to calculate the statistical distribution parameters of the height data within each evaluation region. The statistical distribution parameters characterize the overall topographic fluctuation energy of the corresponding evaluation region. The judgment module 400 is configured to compare the statistical distribution parameters of each evaluation region with at least one preset risk threshold to determine the risk level corresponding to the evaluation region. The output module 500 is configured to generate an assessment result indicating the wafer's risk to subsequent lithography processes based on the risk levels of each evaluation region. The assessment method executed by this assessment system abandons the traditional global perspective and shifts to a partitioned assessment of the wafer surface. By acquiring nanoscale three-dimensional topographic data and partitioning the evaluation regions, it provides a data foundation for local analysis. Specifically, the statistical distribution parameters of the height data in each local area are calculated. These parameters (such as the root mean square value) can characterize the overall morphological fluctuation energy of the area. Compared with a single extreme point, they are more stable and comprehensive, and can more sensitively reflect the morphological anomaly patterns that may cause lithography problems. Furthermore, by comparing the calculated statistical parameters with the preset risk threshold, the abstract morphological data can be transformed into a clear risk level, and finally integrated to generate the evaluation results for the entire wafer.
[0088] In at least one embodiment of this application, such as Figure 12 As shown, the evaluation system may further include a filtering system 600, configured to apply a high-pass filter to the height data in each of the evaluation regions to remove low-frequency background components introduced by overall wafer warpage. Through high-pass filtering, components with longer spatial wavelengths (corresponding to low frequencies) in the data can be selectively filtered out, while components with shorter wavelengths (corresponding to high frequencies) are retained. After this processing, the impact of overall wafer warpage is weakened in the height data of each evaluation region, while local high-frequency topographic features (such as dicing marks) are highlighted.
[0089] In at least one embodiment of this application, such as Figure 13As shown, the evaluation system may also include a judgment module 700, which is configured to determine whether the wafer is qualified based on the number or proportion of evaluation areas with a specified risk level in the evaluation results. During the risk assessment of each local area, an overall judgment must be made on whether the entire wafer can be used for subsequent photolithography processes. The judgment module 700 provides the specific logic for completing this judgment. After obtaining the risk level of each area, the system counts the number of areas marked with a specific risk level (usually "high risk") or calculates its proportion of all evaluation areas. Then, this number or proportion is compared with a preset wafer-level control limit.
[0090] In at least one embodiment of this application, such as Figure 13 As shown, the evaluation system may also include a feedback module 800, configured to feed the evaluation results back to the upstream wafer manufacturing process to adjust its process parameters. The feedback module 800 elevates this evaluation method from a simple inspection tool to an active link in the process control loop. The evaluation results are not only used for the interpretation of the current wafer, but more importantly, are systematically fed back to the upstream manufacturing processes that produced the wafer (e.g., dicing, grinding, polishing). The feedback information can be specific, such as the distribution pattern of high-risk areas and the degree of deviation of statistical parameters. After receiving this feedback, the upstream process control system can automatically or assisted operators in adjusting relevant process parameters according to preset control rules, such as adjusting the feed rate of the dicing blade, the rotation speed and pressure of the grinding disc, and the flow rate of the polishing slurry. Through this closed-loop feedback mechanism, when the evaluation discovers a specific morphological defect pattern caused by a certain upstream process, the source process can be corrected in a timely manner, thereby preventing the same problem from recurring on subsequently produced wafers.
[0091] At least one embodiment of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the evaluation method described in the above embodiments.
[0092] At least one embodiment of this application provides an electronic device, such as... Figure 14 As shown, the electronic device 1 includes a processor 2 (which may be at least one) and a memory 3. The memory 3 is used to store executable instructions (e.g., applications) of the processor 2, and the applications stored in the memory 3 may include one or more modules, each corresponding to a set of instructions. The processor 2 is configured to execute instructions for performing the evaluation method in the above embodiments.
[0093] Electronic device 1 may also include a power supply component configured to perform power management of electronic device 1, a wired or wireless network interface configured to connect electronic device 1 to a network, and an input / output (I / O) interface. Electronic device 1 may operate on an operating system stored in memory 3, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.
[0094] At least one embodiment of this application provides a computer program product, which includes a computer program that, when executed by a processor, implements the evaluation method described in the above embodiments. Specifically, the computer program can be stored in a computer-readable storage medium. When the above evaluation method needs to be executed, the processor can read the computer program from the computer-readable storage medium and load it into memory for execution, thereby driving the relevant hardware devices to complete operations such as control of the cutting process, parameter adjustment, wear compensation (band saw thickness compensation), and thickness monitoring according to the steps, processes, and logic described in the above embodiments.
[0095] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0096] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0097] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0098] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0099] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0100] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program verification codes, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0101] Furthermore, it should be noted that the combination of the various technical features in this case is not limited to the combination methods described in the claims of this case or the combination methods described in the specific embodiments. All technical features described in this case can be freely combined or combined in any way, unless they contradict each other.
[0102] It should be noted that the above examples are merely specific embodiments of the present invention, and the present invention is obviously not limited to the above embodiments, with many similar variations. All modifications that can be directly derived or conceived by those skilled in the art from the content disclosed in this invention should fall within the protection scope of this invention.
[0103] It should be understood that the limiting terms such as "first" and "second" mentioned in the embodiments of the present invention are only for the purpose of more clearly describing the use of the technical solutions of the embodiments of the present invention, and cannot be used to limit the scope of protection of the present invention.
[0104] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications or equivalent substitutions made within the spirit and principles of this specification should be included within the scope of protection of this specification.
Claims
1. A method for assessing local topographic risk in a wafer, characterized in that, include: Acquire nanoscale three-dimensional morphology data of wafer surface; The three-dimensional topography data is divided into multiple evaluation regions; For each of the assessment areas, a statistical distribution parameter of the height data within the assessment area is calculated, and the statistical distribution parameter characterizes the overall topographic fluctuation energy of the corresponding assessment area. The statistical distribution parameters of each of the assessment areas are compared with at least one preset risk threshold to determine the risk level corresponding to the assessment area. as well as Based on the risk level of each of the assessment regions, an assessment result indicating the risk of the wafer to subsequent photolithography processes is generated.
2. The evaluation method according to claim 1, characterized in that, Before calculating the statistical distribution parameters of the height data within each of the assessment areas, the method further includes: A high-pass filter is applied to the height data in each of the evaluation regions to remove low-frequency background components introduced by the overall wafer warping.
3. The evaluation method according to claim 1, characterized in that, The statistical distribution parameter is the root mean square value.
4. The evaluation method according to claim 3, characterized in that, The root mean square value is calculated based on a preset calculation model, wherein the calculation model is: Site_RMS=sqrt((1 / n) Σ(Zi-Z_avg)²) Where Zi is the height of the i-th data point in the evaluation area, Z_avg is the average height of all data points in the evaluation area, and n is the total number of data points in the evaluation area.
5. The evaluation method according to any one of claims 1 to 4, characterized in that, The preset at least one risk threshold includes a single risk threshold, wherein comparing the statistical distribution parameters of each of the assessment areas with the preset at least one risk threshold to determine the risk level corresponding to the assessment area includes: Two risk levels are defined based on the single risk threshold; and The statistical distribution parameters of each assessment area are compared with the single risk threshold to determine whether the assessment area is classified into one of two risk levels.
6. The evaluation method according to any one of claims 1 to 4, characterized in that, The preset at least one risk threshold includes multiple risk thresholds, wherein comparing the statistical distribution parameters of each of the assessment areas with the preset at least one risk threshold to determine the risk level corresponding to the assessment area includes: Multiple risk levels are defined based on the aforementioned multiple risk thresholds; and The statistical distribution parameters of each assessment area are compared with the plurality of risk thresholds to determine the assessment area as one of the plurality of risk levels.
7. The evaluation method according to any one of claims 1 to 4, characterized in that, The process of generating an assessment result indicating the risk of the wafer to subsequent photolithography processes based on the risk level of each of the assessment regions further includes: Different risk levels are assigned different visual colors and marked on each assessment area.
8. The evaluation method according to any one of claims 1 to 4, characterized in that, After generating an assessment result indicating the risk of the wafer to subsequent lithography processes based on the risk levels of each of the assessment regions, the method further includes: Based on the number or proportion of assessment areas with a specified risk level in the assessment results, it is determined whether the wafer is qualified.
9. The evaluation method according to any one of claims 1 to 4, characterized in that, After generating an assessment result indicating the risk of the wafer to subsequent lithography processes based on the risk levels of each of the assessment regions, the method further includes: The evaluation results are fed back to the front-end wafer manufacturing process to adjust the process parameters of the front-end wafer manufacturing process.
10. The evaluation method according to claim 9, characterized in that, The front-end wafer manufacturing process is either a wafer dicing process or a wafer back-side grinding process.
11. The evaluation method according to any one of claims 1 to 4, characterized in that, The step of dividing the three-dimensional topography data into multiple evaluation regions includes: dividing the three-dimensional topography data into multiple evaluation regions based on the size of the lithographic exposure field.
12. The evaluation method according to claim 11, characterized in that, The multiple evaluation regions are distributed in a regular two-dimensional array grid.
13. A system for assessing local topographic risk in wafers, characterized in that, include: The acquisition module is configured to acquire nanoscale three-dimensional topographic data of the wafer surface; The partitioning module is configured to divide the three-dimensional topography data into multiple evaluation regions; The calculation module is configured to calculate the statistical distribution parameters of the height data within each evaluation area, wherein the statistical distribution parameters characterize the overall topographic fluctuation energy of the corresponding evaluation area. The judgment module is configured to compare the statistical distribution parameters of each of the assessment areas with at least one preset risk threshold to determine the risk level corresponding to the assessment area. as well as The output module is configured to generate an assessment result indicating the risk of the wafer to subsequent photolithography processes based on the risk level of each of the assessment regions.
14. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is used to execute the evaluation method according to any one of claims 1 to 12.
15. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that, When the executable instructions are executed by the processor, they implement the evaluation method as described in any one of claims 1 to 12.
16. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the evaluation method as described in any one of claims 1 to 12.