A method for detecting defects in component mounting in chip stacking packages

Abstract

This invention discloses a defect detection method for component mounting in chip stacking packaging, comprising the following steps: before mounting, performing grid scanning and bilinear surface fitting on the substrate to achieve active warpage correction of the mounting head; after mounting, extracting stacking features such as planar offset, tilt angle, adhesive overflow width, and rotation angle of the chip through visual and laser height measurement; during vacuum release, monitoring the springback amount and springback rate through gradient release and continuous height sampling, and determining asymmetric springback; performing closed-loop compensation for the mounting torque and nozzle posture of the next chip based on the springback features; integrating substrate warpage, stacking features, springback monitoring, and compensation process data to calculate a comprehensive defect risk score, classifying the chips into four grades and performing corresponding treatments; finally, generating a full-process data package using the chip's unique identifier as the primary key. This invention achieves full-process perception, closed-loop compensation, and intelligent judgment in the mounting process, significantly improving the yield and reliability of stacked packaging.

Description

Technical Field

[0001] This invention relates to a method for detecting defects in component mounting during chip stacking and packaging, belonging to the field of chip packaging inspection technology. Background Technology

[0002] Traditional chip packaging refers to the process of fixing individual chips (dies) cut from a wafer to a substrate or lead frame by bonding or soldering, using metal leads (such as gold wires or copper wires) or solder balls to achieve electrical connections between the chip pads and external circuits, and finally protecting them with molding compound. Common traditional packaging forms include SOP, QFP, and BGA. In chip stacking packaging, multiple chips are stacked vertically to save substrate area and increase integration density.

[0003] Component placement is a critical step in the packaging process. It involves picking up the chip using a pick-and-place machine's nozzle, applying adhesive to the bottom of the chip or pre-applying it to the substrate, and then placing the chip onto the target mounting area on the substrate with precise positioning and pressure. Through actions such as kneading and holding pressure, the adhesive is spread evenly, ultimately forming a stable mechanical and thermal connection. The quality of placement directly affects the reliability of subsequent wire bonding, the molding filling effect, and the long-term lifespan of the chip.

[0004] Currently, existing defect detection methods for component mounting mainly include: taking chip images with a top-down camera after mounting and using template matching or edge detection algorithms to extract the chip's planar offset and rotation angle; measuring the chip surface height using a laser displacement sensor to calculate the mounting height and tilt angle; and visually inspecting the width of glue overflow. These methods typically use fixed process tolerances for a binary judgment of acceptance or rejection, and use the detection results for immediate screening of the chip.

[0005] However, existing technologies still lack the ability to actively detect and correct substrate warping before mounting, and have limitations such as a single detection dimension and inability to identify process defects.

[0006] When heated, the substrate will warp unevenly (such as saddle shape or bowl shape). Traditional mounting methods use a fixed pressing height and rubbing trajectory, which cannot be dynamically adjusted according to the actual shape of the substrate. This can easily lead to chip mounting offset, tilting or uneven adhesive layer thickness. Furthermore, after vacuum release, the adhesive rebound will cause additional position and orientation deviations.

[0007] Current testing methods only focus on static geometric parameters (offset, tilt, adhesive overflow width) after mounting, neglecting the dynamic rebound behavior of the adhesive during vacuum release (such as rebound rate, rebound increments at each stage, and asymmetric rebound). These process characteristics precisely reflect the presence of air bubbles, uneven filler distribution, or localized curing abnormalities within the adhesive layer, and are crucial for assessing the risk of early chip failure. Traditional methods, lacking monitoring and quantification of such dynamic processes, easily misclassify chips with abnormal processes but acceptable geometric dimensions as good products, leading to latent defects flowing into subsequent processes. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a defect detection method for component mounting in chip stacking packaging that can realize full-process perception, closed-loop compensation, multi-dimensional fusion judgment and data traceability.

[0009] To address the aforementioned technical problems, this invention proposes a method for detecting defects in component mounting during chip stacking and packaging, comprising the following steps: S1. Before mounting, the surface of the heated substrate is scanned in a grid pattern to obtain the height data of multiple sampling points. The bilinear surface equation of the substrate surface is fitted by the least squares method to calculate the maximum warpage height difference. Based on the bilinear surface equation, the starting height of the mounting head, the rubbing trajectory, and the holding torque release curve are actively corrected to complete the chip mounting. During the XY rubbing process, the Z-axis motor is controlled to dynamically follow the bilinear surface equation to make small extensions and retractions, so that the contact pressure between the chip and the substrate remains constant. S2. After mounting, perform in-situ visual inspection and laser height measurement on the chip, and extract the chip's planar offset, average mounting height, tilt angle, adhesive overflow width on all four sides, and relative rotation angle to generate a stacking feature dataset. S3. After mounting, the substrate warpage height value and the preset adhesive rebound sensitivity level are used as joint query conditions to access the preset lookup table to determine the order of gradient release of the nozzle vacuum adsorption force; during the gradient release process, the chip surface height is continuously sampled and monitored; the collected height data is divided into each order, the transition segment data after the start of each order is removed, the arithmetic mean of the retained data is calculated as the steady-state height of that order, the difference between two adjacent steady-state heights is taken as the rebound increment of that order, and the rebound increments of each order are accumulated to obtain the total rebound amount; the height sampling data within a specific time period after each vacuum level switch is fitted with a straight line, and the slope of the fitted straight line is taken as the instantaneous rebound rate of that order; after the vacuum is completely released, the independent rebound amount of the four corners is extracted, the maximum value and minimum value of the independent rebound amount of the four corners are compared to determine whether asymmetric rebound has occurred, and a rebound monitoring dataset is generated. S4. Read the total springback amount and asymmetric springback determination result of the current chip; compare the total springback amount with the target springback amount reference value to obtain the springback amount deviation value ΔR, and use an incremental proportional adjustment algorithm to calculate the correction amount ΔF of the target torque on the Z-axis through the torque compensation proportional coefficient; when asymmetric springback is determined, determine the tilt compensation axis based on the two corner points with the largest springback amount, and calculate the springback difference amount ΔR_x around the X-axis and the springback difference amount ΔR_y around the Y-axis. Convert the springback difference amount into the target attitude compensation angles Δtheta_x and Δtheta_y of the nozzle around the X-axis and Y-axis of the next chip to be mounted through the tilt compensation gain coefficient; send the corrected mounting parameters to the pick-and-place machine motion control system and record the compensation process data; S5. Integrate the substrate warpage data, stacking feature dataset, springback monitoring dataset, and compensation history data generated by the current chip in steps S1 to S4 to calculate a comprehensive defect risk score. The comprehensive defect risk score includes a system state offset sub-score. When calculating the system state offset sub-score, if the current chip triggers torque compensation for the next chip and the correction exceeds a preset compensation threshold, a deduction is applied to the system state dimension. Based on the comprehensive defect risk score, the chip is classified into normal, watch-out, risk, or defective grades, and corresponding handling measures are implemented for each grade. S6. Using the chip's unique identifier as the primary key, aggregate and store the entire process data generated in steps S1 to S5 to generate a full-process process fingerprint data package, and support subsequent processes to perform pre-query and quality traceability based on the chip identifier.

[0010] The specific methods for extracting the plane offset in S2 above include: The chip surface image is captured by a top-down positioning camera. The template image stored before mounting is called up. The central area of ​​the template image is used as the search template. A grayscale template matching algorithm based on normalized cross-correlation is executed on the chip surface image to obtain the integer pixel coordinates of the best matching position. The correlation coefficient values ​​within a preset neighborhood centered on the integer pixel coordinates are fitted with a quadratic surface. The subpixel-level actual position is obtained by solving for the coordinates of the maximum point of the fitted surface, and the planar offset is obtained by subtracting it from the theoretical mounting target position.

[0011] The calculation method for the tilt angle in S2 above specifically includes: The laser displacement sensor is used to measure the height of each point at a fixed coordinate position at one of the four corners of the chip surface in sequence, and four height values ​​are obtained. Based on the four height values ​​and the distance between the X-axis and Y-axis measuring points, the tilt angles of the chip around the X-axis and Y-axis are calculated respectively.

[0012] The specific methods for extracting the width of the overflow adhesive on the four sides in S2 above include: Switch to a low-angle ring light source to capture images of the chip, and delineate rectangular detection areas on the outer sides of the four sides of the chip. In each detection area, a one-dimensional grayscale curve is generated by grayscale projection along the vertical edge direction. The first derivative of the grayscale curve is solved to locate the chip sidewall-colloid transition edge position and the colloid-substrate transition edge position. The distance between the two is the overflow width of the adhesive.

[0013] The specific methods for extracting the relative rotation angle in S2 above include: Edge points are extracted from the left and bottom edges of the chip to obtain the edge pixel set; The equations of the left edge line and the lower edge line were fitted using the least squares method. Calculate the angles between the two fitted lines and the X-axis of the image coordinate system, take the average of the two as the current actual rotation angle of the chip, and subtract the theoretical rotation angle to obtain the relative rotation angle.

[0014] The calculation method for the comprehensive defect risk score in S5 above specifically includes: The geometric feature values ​​extracted by S2 are compared with the preset process tolerances to generate a geometric compliance sub-score. The starting point is the first preset full score. When the plane offset exceeds the preset plane offset threshold, the first preset score is deducted. When the tilt angle exceeds the preset tilt threshold, the second preset score is deducted. When the overflow width on any side exceeds the preset normal overflow range, the third preset score is deducted. When the rotation angle exceeds the preset rotation threshold, the fourth preset score is deducted. The deductions for each item are accumulated until the full score for this dimension is deducted. The rebound monitoring data extracted by S3 is compared with the preset normal range to generate a sub-score for rebound process stability. The starting point is the second preset full score. When the total rebound amount exceeds the preset normal rebound range, the fifth preset score is deducted. When the asymmetric rebound is determined to be true, the sixth preset score is deducted. When any instantaneous rebound rate exceeds the preset rate threshold, the seventh preset score is deducted for each level, and the total deduction does not exceed the preset deduction limit. All deductions are accumulated until the full score of this dimension is deducted. The system state offset sub-score is generated based on the compensation history data of S4. The starting point is the third preset full score. When the chip has received torque compensation as the target and the correction amount exceeds the preset compensation judgment threshold, the eighth preset score is deducted. When the chip triggers torque compensation for the next chip as the source and the correction amount exceeds the preset compensation judgment threshold, the ninth preset score is deducted. When the compensation trigger frequency in the preset monitoring window exceeds the preset frequency threshold, the tenth score is deducted. When the global maximum warpage value of the substrate exceeds the preset warpage threshold, the eleventh score is deducted. All deductions are accumulated until the full score of this dimension is deducted. The comprehensive defect risk score is the sum of the geometric compliance sub-score, the rebound process stability sub-score, and the system state offset sub-score.

[0015] The specific rules for classifying defect risk levels in S5 above are as follows: When the comprehensive defect risk score is greater than or equal to the first preset score threshold, it is judged as normal grade; When the comprehensive defect risk score is within the first preset score range, it is determined to be a quality level of concern; When the comprehensive defect risk score falls within the second preset score range, it is determined to be of a risk level. When the comprehensive defect risk score is less than the second preset score threshold, or when the preset fatal deviation locking condition is triggered during the scoring process, it is directly judged as a defect grade; The preset fatal deviation locking conditions include at least one of the following: the plane offset exceeds the preset fatal offset threshold, the glue overflow width exceeds the preset fatal glue overflow threshold and the distance between the glue front edge and the adjacent pad is less than the preset safe distance threshold, the total rebound amount exceeds the preset fatal rebound range, and the maximum difference in the rebound amount at the four corners exceeds the preset fatal tilt threshold.

[0016] The specific handling measures corresponding to each level in S5 above are as follows: Normal grade and special grade: Send a release signal and the chip will flow normally to the next process. The special grade chip will be marked with its level and specific deduction items in the database. Risk level: Send a diversion re-inspection signal to transfer the chip to the re-inspection station for manual confirmation; Defect level: Send a forced rejection signal to perform a rejection operation on the chip.

[0017] The active correction in S1 mentioned above specifically includes: When the substrate is identified as having a saddle-shaped warp, the mounting head pressing process is divided into a rapid descent segment and a slow contact segment. The starting height of the slow contact segment is determined by adding a preset safety margin to the warp height at the current position calculated by the bilinear surface equation. During the XY kneading process, the Z-axis motor dynamically follows the bilinear surface equation to make minute extensions and contractions, so that the contact pressure between the chip and the substrate remains constant. If the maximum warpage height difference is greater than the preset high warpage risk threshold, after the mounting pressure holding is completed, the Z-axis motor will be controlled to reduce the holding torque linearly from the mounting pressure torque according to the preset gradient within the preset pressure release time, and finally release it completely.

[0018] The gradient release and dynamic monitoring of vacuum adsorption force in S3 above specifically includes: Based on the order of vacuum gradient release determined in S3, the target percentage of vacuum degree and time step corresponding to each order are obtained from the preset lookup table; a laser displacement sensor is configured to continuously sample the height of preset monitoring points on the chip surface at a preset sampling frequency; the vacuum proportional valve is controlled sequentially according to the target percentage of vacuum degree for each order, and height data is continuously recorded during the stabilization period of each order, and a marker signal is sent to the data acquisition system to record the start and end times of gradient release. The instantaneous rebound rates of each order calculated in S3 are compared with the preset standard rate range to determine whether they exceed the limit and generate the corresponding Boolean flags. When determining whether asymmetric rebound occurs, if the difference between the maximum and minimum values ​​of the four independent rebound amounts is greater than the preset rebound tilt determination threshold, then asymmetric rebound is determined to have occurred and the tilt direction is recorded.

[0019] This invention has positive effects: (1) The present invention uses grid scanning and bilinear surface fitting to dynamically adjust the mounting head pressing trajectory, rubbing pressure and torque release curve, effectively suppressing mounting offset and tilt caused by substrate thermal warping, and improving mounting consistency.

[0020] (2) The present invention uses vacuum gradient release and high-speed height sampling to quantify the rebound increment, instantaneous rebound rate and independent rebound amount of each stage, which can identify hidden anomalies such as adhesive layer bubbles and uneven distribution of fillers, and provide reliable process feedback for closed-loop compensation.

[0021] (3) This invention integrates geometric dimensions, springback characteristics and system state offset to construct a comprehensive defect risk scoring model and realize four-level graded disposal of chips; at the same time, based on springback characteristics, it performs closed-loop compensation for mounting torque and nozzle posture, which significantly improves the consistency of mounting multiple chips and the traceability of the whole process. Attached Figure Description

[0022] The invention will now be further described with reference to the accompanying drawings.

[0023] Figure 1 This is a flowchart. Detailed Implementation

[0024] Example

[0025] See Figure 1 This embodiment is a defect detection method for component mounting in chip stacking packaging, including the following steps: S1: Pre-mount thermal warpage sensing and active correction; S2: Multi-dimensional stacking feature extraction after mounting; S3: Dynamic monitoring of vacuum adsorption gradient release and rebound tilt; S4: Closed-loop compensation for mounting torque based on springback characteristics; S5: Defect risk assessment by integrating stacking characteristics and compensation process; S6: End-to-end data binding and traceability.

[0026] This embodiment applies to traditional chip stacking packaging.

[0027] The warp sensing and active correction in S1 are as follows: 1. First, configure the sensing device by mounting the sensor on the side of the Z-axis lifting module of the pick-and-place machine's swing arm, maintaining a fixed X / Y mechanical offset distance from the placement nozzle. Utilize the pick-and-place machine's own X / Y linear motor platform to drive the sensor for grid scanning.

[0028] 2. Next, warp sensing is performed. The pick-and-place machine first moves to a fixed reference block on the track, and the laser head records the reference height value Z_re. A corresponding grid scanning matrix is ​​set for the substrate. The laser head sequentially sweeps across the four corners and the center area of ​​the substrate. Due to the heat of the substrate, the two ends of its diagonals will warp upwards. The sensor controller calculates the height difference ΔZ_i of each point relative to the reference block in real time.

[0029] The host computer software reads the coordinate values ​​X_i, Y_i, and ΔZ_i of 25 points. A bilinear surface equation is fitted using the least squares method: Z(x,y)=a_0+a_1x+a_2y+a_3xy. Finally, the maximum warping height difference W_max is calculated.

[0030] For example, the above formula calculates that the substrate edge warps up 85μm and the center is recessed 20μm.

[0031] 3. Active correction is as follows: In traditional packaging, active correction is achieved by identifying warpage patterns and changing the mounting parameters.

[0032] The correction mechanism in this embodiment is based on the motion compensation of the placement head. When the substrate is identified as having "saddle-shaped warping with a low center and high edges," the placement machine performs the following three-stage active correction action: Correction Action 1: First, targeting the high point of warpage, the Z-axis flexible landing logic is implemented. The placement head pressing process is divided into a rapid descent segment and a slow contact segment. The starting height of the slow contact segment is not set to a fixed value, but is calculated based on the current position warpage height + ΔSafe according to the Z(x,y) model.

[0033] For example, if the substrate edge is raised by 85μm, the nozzle will start to decelerate at a height of 150μm from the substrate surface, and probe the adhesive surface at an extremely low speed of 0.1mm / s to achieve flexible landing on the Z-axis.

[0034] Correction Action 2: Dynamic eccentricity compensation for uneven colloid flow and XY kneading trajectory. During kneading, the Z-axis motor dynamically follows the curved surface model, making minute extensions and contractions.

[0035] For example, when the nozzle is making a horizontal cross-shaped rubbing motion, the Z-axis is simultaneously compensated for by a sine wave according to the Z(x,y) function to ensure that the contact pressure between the die and the substrate is constant at 20g, preventing crushing of the edges and preventing voids in the center.

[0036] Correction Action 3: Gradient release of torque at the end of mounting for springback pre-suppression. If W_max > 60 mm, the substrate is identified as having a high risk of warpage, and the gradient pressure relief mode is activated.

[0037] For example, after the placement is completed and pressure is held for 200ms, the Z-axis motor is not instantly de-energized and released. Instead, the holding torque is linearly reduced from 100% to 20% within 100ms before being fully released. This provides a slow, damped rebound process, significantly reducing the final tilt amount.

[0038] After correction is complete, the nozzle does not immediately return. Instead, a laser sensor scans the die surface height again above the mounting position. If the die surface height change trend is consistent with the substrate warpage model, meaning the die is attached to the warped surface, the active correction is considered successful. If the die surface shows a reverse tilt, the chip is marked as a correction anomaly, a correction anomaly marker is generated and written to the database along with the Chip_UID. This marker will be used as a deduction item in the system status dimension of the S5 defect risk assessment and will be included in the overall score.

[0039] The feature extraction in S2 is as follows: 2.1 Trigger in-situ detection after mounting and establish a temporary data index for the current chip.

[0040] After confirming that the Z-axis has been reset to a safe height and the nozzle vacuum has been completely released, the pick-and-place machine motion controller sends a hardware trigger signal to the vision system. The vision controller reads the substrate barcode Strip_ID corresponding to the current placement station and the matrix coordinates (Row, Col) of the current chip on the substrate, and generates a globally unique identifier Chip_UID for the current chip according to preset rules, in the format Strip_ID+"_R"+Row+"C"+Col. Subsequently, a temporary data container with Chip_UID as the key is created in memory to store all feature values ​​generated in this step.

[0041] 2.2 Perform subpixel-level visual extraction of XY plane offsets.

[0042] Using a 5-megapixel CMOS sensor with a pixel size of 3.45μm, and a top-down positioning camera with coaxial red illumination, a static image Img_Top is captured on the surface of the current chip.

[0043] The program calls the chip template image Img_Template, which was stored before mounting. This template is a standard pose image taken by a reference camera at a low angle after the nozzle picks up the chip. The program uses the central region of Img_Template, with a size of 80% of the theoretical chip size, as the search template. It performs a grayscale template matching algorithm based on normalized cross-correlation (NCC) on Img_Top to obtain the integer pixel coordinates (X_raw, Y_raw) of the best matching position.

[0044] A quadratic surface is fitted to the NCC correlation coefficient values ​​in a 3×3 neighborhood centered at (X_raw, Y_raw) to ensure sub-pixel accuracy. The fitting function for the quadratic surface fitting is: R(x,y)=a_0+a_1x+a_2y+a_3x²+a_4xy+a_5y².

[0045] By solving for the coordinates of the maximum points of the fitted surface, the subpixel-level actual positions (X_actual, Y_actual) are obtained. The planar offsets ΔX and ΔY are calculated by subtracting these from the theoretical mounting target positions (X_target, Y_target), and the results are retained to a minimum of 0.1 μm. ΔX, ΔY, and the peak value of the matching correlation coefficient NCC_Peak are then written into the Chip_UID temporary data container.

[0046] Among them, ΔX=X_actual-X_target; ΔY=Y_actual-Y_target.

[0047] 2.3 Multi-point laser height measurement calculation of Z-axis mounting height and chip tilt angle.

[0048] The laser displacement sensor performs single-point height measurement at four fixed coordinate positions P_TL(X1,Y1), P_TR(X2,Y2), P_BL(X3,Y3), and P_BR(X4,Y4) near the four corners of the chip surface. Each point is sampled 10 times and the average value is taken to obtain four height values ​​Z_TL, Z_TR, Z_BL, and Z_BR.

[0049] Calculate the average mounting height of the chip, which is a representation of the sum of the current adhesive layer thickness and the chip thickness: H_avg=(Z_TL+Z_TR+Z_BL+Z_BR) / 4 The specific calculation steps for the chip's tilt angles Tilt_X and Tilt_Y around the X-axis are as follows: Tilt_X=arctan(((Z_BL+Z_BR)-(Z_TL+Z_TR)) / (2×L_Y_span)) Tilt_Y=arctan(((Z_TR+Z_BR)-(Z_TL+Z_BL)) / (2×L_X_span)) Where L_X_span is the actual physical distance between measurement points P_TL and P_TR, and L_Y_span is the actual physical distance between P_TL and P_BL. The calculation results are expressed in degrees and rounded to 0.001°. H_avg, Tilt_X, Tilt_Y, and the four original height values ​​are written to the Chip_UID temporary data container.

[0050] 2.4 Perform visual quantization of the chip edge adhesive overflow width.

[0051] Switch to a low-angle ring-shaped blue light source and take a second image (Img_Bleed) of the chip from above, with the exposure time adjusted to 150μs to highlight the diffuse reflection texture of the colloidal surface.

[0052] The program defines four rectangular detection areas (ROIs) on the outer sides of the chip's top, bottom, left, and right edges, respectively. Each ROI has dimensions of 500μm vertically to the edge and 200μm horizontally to the edge. Within each ROI, a grayscale projection is performed along the vertical edge direction to generate a one-dimensional grayscale curve G(d), where d is the distance from the theoretical boundary of the chip edge.

[0053] Solving for the first derivative of the grayscale curve G(d), we locate two extreme points d_1 and d_2, corresponding to the transition edges of the chip sidewall and the adhesive, respectively, and the adhesive-substrate transition edge. Then, the width of the adhesive overflow at the current edge is: W_bleed=|d_2-d_1| Perform the above calculations sequentially on the four sides to obtain W_Left, W_Right, W_Top, and W_Bottom. Simultaneously determine whether the overflow width falls within the preset control range [W_min, W_max]. Write the four width values ​​and the out-of-bounds flag into the Chip_UID temporary data container.

[0054] 2.5 Perform visual calculations of the chip's relative rotation angle.

[0055] Based on the actual chip position obtained in section 2.2, the vision program extracts edge points on the left and bottom edges of the chip using Img_Top. The Canny operator (low threshold set to 40, high threshold set to 120) is used to obtain the edge pixel set. Then, the least squares method is used to fit the equations for the left edge line L_left:x=k_1y+b_1 and the bottom edge line L_bottom:y=k_2x+b_2, respectively.

[0056] Calculate the angles theta_left and theta_bottom between the two fitted lines and the X-axis of the image coordinate system: θ_left = arctan(k_1) θ_bottom=arctan(k_2) The average of the two values ​​is taken as the chip's current actual rotation angle theta_actual, and the difference between this and the theoretical rotation angle theta_target is used to obtain the relative rotation offset. Δθ = θ_actual - θ_target The calculation results are retained to 0.001. Δtheta and the correlation coefficient R^2 of the two fitted lines are written into the Chip_UID temporary data container.

[0057] 2.6 Integrate multi-dimensional features to generate stacked feature data packets and complete chip-level binding storage.

[0058] All features collected in the Chip_UID temporary data container, including ΔX, ΔY, H_avg, Tilt_X, Tilt_Y, W_Left, W_Right, W_Top, W_Bottom, Δθ, and intermediate key parameters in each feature extraction process, such as NCC_Peak and edge fitting R^2, are encapsulated according to a predefined JSON data structure to generate an indivisible stacked feature record.

[0059] The JSON record is written in real-time to the Die_Stack_Feature data table in the production line's central database via the industrial control computer's Ethernet interface, using Chip_UID as the primary key and adding a Timestamp field. The write operation employs a database transaction mechanism to ensure that the data is completely committed before proceeding to the next chip's processing flow. The generated data will serve as one of the direct input sources for subsequent S5 fusion determination.

[0060] The dynamic monitoring in S3 is as follows: S3: Dynamic Monitoring of Vacuum Adsorption Gradient Release and Rebound Tilt 3.1 Obtain the process context information of the current placement unit and determine the control parameters for this gradient release.

[0061] Read the following three pieces of information from the data buffer of the current mounting task: The first item is to obtain the measured warpage height value of the substrate surface at the current chip mounting position from the output record of the S1 warpage sensing step. This value is the Z-axis deviation corresponding to the current chip center projection point when the laser displacement sensor scans the substrate before mounting, in μm, accurate to the nearest whole number.

[0062] The second step involves retrieving two characteristic parameters of the chip bonding adhesive currently used from the production formula database for this batch: the rebound sensitivity level corresponding to the adhesive model, and the nominal thixotropic index provided by the supplier. The rebound sensitivity level is pre-entered by the process engineer based on historical production data and is divided into three levels: low, medium, and high. The thixotropic index is an indicator of the adhesive's viscosity recovery rate under shear stress and is a dimensionless value.

[0063] The third item reads the current chip thickness value in μm. This value is automatically retrieved from the pick-and-place machine's material parameter library based on the chip part number.

[0064] The substrate warpage height and adhesive springback sensitivity level are used as joint lookup criteria to access a two-dimensional lookup table stored in local non-volatile memory. This table was experimentally determined and solidified by process engineers during the equipment commissioning phase, and its structure is as follows: If the substrate warpage height is ≤30μm and the adhesive rebound sensitivity is low, a two-stage release strategy will be adopted in this study.

[0065] If the substrate warpage height is between 31μm and 70μm, or the adhesive rebound sensitivity is medium, then a 4-stage release strategy is adopted.

[0066] If the substrate warpage height is ≥71μm, or the adhesive rebound sensitivity is high, a 6-stage release strategy is adopted.

[0067] After determining the table lookup results, the corresponding vacuum degree target value percentage sequence and time step sequence are read from another parameter table. The details are as follows: For the second-order release strategy, the target vacuum values ​​are 50% and 0% of the mounting pressure holding vacuum, respectively. The first step has a time step of 60ms, and the second step has a time step of 40ms.

[0068] For the 4th-order release strategy, the target vacuum values ​​are 75%, 50%, 25%, and 0% of the mounting pressure holding vacuum, respectively. The time step is fixed at 80ms.

[0069] For the 6th-order release strategy, the target vacuum values ​​are 85%, 70%, 55%, 40%, 20%, and 0% of the mounting pressure holding vacuum, respectively. The time step for the first 5 steps is fixed at 100ms, and the time step for the last step is 150ms.

[0070] The aforementioned time step specifically refers to the duration of stability at this vacuum level, excluding the mechanical response transition time of the vacuum proportional valve. The transition time is determined by the characteristics of the proportional valve itself; in this embodiment, the step response time of the proportional valve has been calibrated to ≤12ms.

[0071] 3.2 Configure the laser displacement sensor to enter high-speed continuous sampling mode and determine the spatial coordinates of the monitoring sampling point.

[0072] A configuration command frame is sent to the controller of the laser displacement sensor via the communication interface. The command frame includes the following: setting the sensor trigger mode to internal continuous trigger, the sampling period to 500μs, the measurement data output format to 4-byte floating-point numbers, and the unit to μm.

[0073] Simultaneously, the sensor's measurement spot is positioned at a preset monitoring point on the chip surface. Specifically, this is a position offset 100μm in the positive X direction from the chip's geometric center as the origin. The purpose of choosing this offset point is to avoid any pin marks or nozzle contact marks that may exist at the chip's center. Furthermore, this position has been verified in step S2 to be within the chip's effective area and will not fall into the edge adhesive overflow area.

[0074] After the sensor is configured, it begins continuously sending altitude measurements to the data acquisition card. The data acquisition card receives each sampling point via hardware interrupts, with timestamps automatically appended by the card's μs-level hardware timer. The acquired data stream is written in real-time to a circular buffer in memory, which can store the most recent 5 seconds of sampled data.

[0075] 3.3 Start the gradient control sequence of the vacuum proportional valve and simultaneously mark the start and end times of each stage.

[0076] An electro-proportional valve is connected to the vacuum circuit of the placement head via an analog voltage output module. The control voltage range of the proportional valve is 0V to 10V, corresponding to an output vacuum level of 0kPa to 85kPa. The vacuum level used during the placement holding pressure stage is fixed at 60kPa, corresponding to a control voltage of approximately 7.06V.

[0077] First, a digital marker signal is sent to the data acquisition system to record the start time of gradient release. Then, the analog voltage output value is updated sequentially according to the vacuum target value sequence and time step sequence determined in 3.1.

[0078] Taking the 4th-order release strategy as an example, the specific execution process is as follows: First, the control voltage is adjusted to the value corresponding to 75% vacuum, approximately 5.30V. After the command is issued, the proportional valve internally stabilizes the output vacuum to the target value within ≤12ms through a PID closed loop. A timer starts from the moment the voltage update command is completed, and waits for 80ms. During this waiting period, the laser displacement sensor continuously samples and records height data.

[0079] Next, adjust the control voltage to the value corresponding to 50% vacuum, which is approximately 3.53V. Wait 80ms, during which time continue recording altitude data.

[0080] Then adjust the control voltage to the value corresponding to 25% vacuum, which is approximately 1.76V. Wait 80ms and record the data.

[0081] Finally, the control voltage is adjusted to 0V, and the proportional valve fully connects the suction nozzle vacuum chamber to the atmosphere. After waiting 80ms, a second digital marker signal is sent to the data acquisition system, indicating that the gradient release sequence has been completed. However, the laser sensor does not stop sampling and continues to collect an additional 100ms of data to capture any residual slow rebound that may exist after the vacuum has completely returned to zero.

[0082] 3.4 The continuous height data stream is segmented and the steady-state height value and rebound increment of each segment are extracted.

[0083] After data acquisition is completed, all height-sampled data from the first marker signal to the end of the additional acquisition is read from the circular buffer, resulting in a 1D array containing thousands of data points, each with a μs-level timestamp.

[0084] The processing program first divides the entire data segment into several segments based on the start times of each step recorded in section 3.3. Each segment corresponds to a vacuum plateau period. During segmentation, the data in the first 15ms after the start of each step is discarded to eliminate unsteady fluctuations during the transition phase of the proportional valve response, retaining only the stable data in the latter part of the plateau period.

[0085] For each plateau period's retained data segment, calculate the arithmetic mean of all its height samples as the steady-state height value at that vacuum level. Subtract the steady-state height values ​​of two adjacent plateau periods; the difference is the chip Z-axis lift caused by the decrease in vacuum level at that stage, called the bounce increment for that stage.

[0086] The springback increments at each stage are summed to obtain the total springback at the chip's center monitoring point from the holding vacuum level to complete vacuum release. Simultaneously, the difference between the initial height value at the start of the marking and the final steady-state height value after complete release is used as a redundant calculation value to verify the total springback. If the deviation between two total springback values ​​exceeds 1 μm, the chip is marked as having measurement inconsistency issues, and a warning flag is recorded in subsequent data packets.

[0087] 3.5 Calculate the instantaneous rebound rate at each stage to determine if there are any local anomalies in the adhesive layer.

[0088] The processing program further analyzes the transient characteristics of height after switching vacuum levels at each level. The specific method is as follows: for each level, the height sampling data between 5ms and 15ms after the switching command is issued is taken, and a straight line is fitted using the least squares method. The slope of this straight line is the instantaneous rebound rate of that level, with units of μm / ms.

[0089] The calculated instantaneous rebound rates for each order are compared with the standard rebound rate reference range stored in the process parameter library for this batch of adhesive. The standard range is determined based on historical statistical data of this type of adhesive under normal adhesive layer thickness conditions, with an upper limit of 120% of the historical average.

[0090] If the instantaneous rebound rate of a certain step exceeds the upper limit of the standard range, it is determined that there may be localized excessive thickness or glue accumulation in the adhesive layer beneath the chip. At this time, the system generates an alarm record containing the step number, the measured rate value, and the standard upper limit value, and binds it to the current chip identifier.

[0091] 3.6 Perform a retest of the springback height at the four corners of the chip and calculate the springback tilt.

[0092] After the laser sensor completes continuous monitoring of the center point, the XY motion platform of the placement head is immediately scheduled to move the laser sensor spot sequentially to the four corner positions on the chip surface. The planar coordinates of these four positions are exactly the same as those used in step S2 when measuring the placement tilt angle, namely the upper left corner, upper right corner, lower left corner, and lower right corner of the chip, recessed 100μm from the chip edge to avoid possible adhesive overflow areas.

[0093] At each corner location, the sensor performs single-point static height measurement, continuously collects 20 sample values ​​and averages them to obtain the height value of that corner point after the vacuum is completely released.

[0094] Subtract each of these four height values ​​from the height value recorded at the same position immediately after mounting in step S2 to obtain the independent springback amount at each of the four corner points. Compare these four springback amounts to find the maximum and minimum values.

[0095] If the difference between the maximum and minimum values ​​exceeds the preset rebound tilt detection threshold (set to 6 μm in this embodiment), it is determined that asymmetric rebound has occurred during the placement, meaning that the rebound force of the adhesive is uneven in different areas of the chip bottom, causing the chip to tilt additionally during release. At this time, the system generates a rebound tilt marker and records the positions of the two corner points with the largest difference to indicate the tilt direction.

[0096] If the difference is ≤6μm, the rebound process is considered uniform and no new tilting is introduced.

[0097] 3.7 Package all rebound monitoring data, bind chip identifiers, and complete storage.

[0098] All data generated and calculated during the execution process will be structured and organized, specifically including: Gradient release strategy type, actual vacuum degree target percentage sequence, actual vacuum degree control voltage sequence, actual duration of each order, total rebound amount R_total, rebound increment sequence of each order, instantaneous rebound rate sequence of each order, rebound rate exceeding limit Boolean flag of each order, independent rebound amount in the upper left corner, independent rebound amount in the upper right corner, independent rebound amount in the lower left corner, independent rebound amount in the lower right corner, rebound tilt judgment Boolean flag F_tilt, tilt direction corner point identifier, measurement consistency warning flag.

[0099] The above data is organized into a single data object in JSON format, with predefined fixed field names as keys. This JSON object is then inserted into the chip end-to-end data record table in the production line's central database, using the current chip's unique identifier, Chip_UID, as the primary key.

[0100] The total rebound amount, rebound rate over-limit flag, and rebound tilt flag output will be used as input parameters for step S4 to calculate the mounting torque compensation amount and nozzle posture compensation angle for the next chip.

[0101] The specific details of the mounting torque closed-loop compensation in S4 are as follows: Traditional chip mounters typically use a fixed Z-axis downward pressure or an open-loop setting based solely on chip area during the mounting process. This fails to respond to dynamic changes such as batch differences in adhesive, substrate warpage, and the actual springback feedback after the previous chip is mounted. This often leads to issues in mass production, including poor adhesive thickness consistency within the same batch of chips and cumulative tilt deviations in multi-layer stacking.

[0102] 4.1 Read the rebound characteristic feedback quantity from the S3 monitoring data of the previous chip.

[0103] After step S3 of each chip is completed and the monitoring data is written to the database, the following three key feedback quantities are immediately extracted from the data record of the current chip as input signals for this closed-loop compensation: The first feedback value: the total rebound amount R_total at the chip center monitoring point, in μm. This value is calculated by sub-step 3.4 and represents the cumulative height of the chip lifted by the elastic recovery of the colloidal material from the mounting pressure state to the complete release of vacuum.

[0104] The second feedback quantity is the rebound tilt judgment flag F_tilt, which is a Boolean value. When the maximum difference in the rebound amount at the four corners in sub-step 3.6 is greater than 6μm, F_tilt is set to 1, indicating that asymmetric rebound has occurred; otherwise, it is set to 0, indicating that the rebound process is uniform.

[0105] The third feedback quantity: When F_tilt is 1, the tilt direction information is read from the 3.6 record, specifically the position markers of the two corners with the largest rebound amount, such as the upper left corner and the lower right corner, which are used to determine the sway direction of the nozzle posture compensation.

[0106] 4.2 Calculate the closed-loop correction value of the Z-axis mounting torque.

[0107] The total rebound amount R_total is compared with the preset target rebound amount reference value R_target for this batch. R_target is determined based on historical statistical data of this type of adhesive under standard adhesive layer thickness conditions, and is usually taken as the center value of the empirical process window. The rebound amount deviation is used as the driving signal for torque adjustment.

[0108] First, calculate the rebound deviation value ΔR: ΔR = R_totalR_target A positive deviation value ΔR indicates that the actual rebound amount is greater than the target value, meaning that the adhesive layer rebounds too strongly after the pressure is released, which means that the previous particle's mounting pressure may be insufficient and the adhesive has not been fully pressed to the target thickness. A negative deviation value indicates that the actual rebound amount is less than the target value, meaning that the previous particle was pressed down too much, the adhesive layer is too thin, and the rebound space is limited.

[0109] The correction amount ΔF for the target torque along the Z-axis is calculated using an incremental proportional adjustment algorithm: ΔF=K_p×ΔR Wherein, K_p is the torque compensation proportional coefficient. This coefficient was obtained through previous process experiments and is stored in the batch production formula database.

[0110] The calibration method involves mounting a set of sample chips under the same substrate and adhesive conditions with different mounting torques, measuring the steady-state rebound of each sample, and fitting the ratio between the change in mounting torque and the change in rebound through linear regression. The average value of this ratio is then used as K_p and cured into the formulation. For typical medium-viscosity epoxy resins, the typical value of K_p ranges from 0.08 N / μm to 0.15 N / μm.

[0111] After calculating ΔF, it is added to the current default mounting torque setting F_default to obtain the corrected target mounting torque F_target: F_target = F_default + ΔF To ensure safe chip mounting and prevent microcracks caused by overvoltage or loose connections caused by undervoltage, the calculated F_target is clamped with upper and lower limits. The upper limit F_max is determined by the compressive strength of the chip material, and the lower limit F_min is determined by the minimum pressure required for the adhesive to fully wet the chip.

[0112] In this embodiment, for a silicon-based chip with a thickness of 200μm, F_max is set to 1.2N and F_min is set to 0.3N. If F_target exceeds this range, the boundary value is forcibly taken.

[0113] 4.3 Calculate the tilt compensation value of the nozzle posture.

[0114] This sub-step is executed only when F_tilt is 1. When S3 determines that asymmetric springback has occurred, it means that the chip was pushed up more by the adhesive in a certain diagonal direction during release, reflecting insufficient pressure or uneven adhesive distribution in the adhesive layer below that direction during placement. To actively correct this tendency in the next placement, a slight tilt pre-compensation is needed for the nozzle's contact posture.

[0115] Based on the positions of the two corner points with the largest rebound amount recorded in 3.6, the tilt compensation axis is determined.

[0116] For example, if the rebound amount is the largest at the upper left and lower right corners, it means that the chip is tilted up along the diagonal direction, and the pitch angle and tumble angle of the nozzle need to be adjusted in a certain proportion.

[0117] For example, when it is necessary to adjust the pitch angle theta_x of the nozzle rotating about the X-axis and the roll angle theta_y of the nozzle rotating about the Y-axis: First, calculate the diagonal difference in springback at the four corners. Define the springback at the top left corner as R_TL, the top right corner as R_TR, the bottom left corner as R_BL, and the bottom right corner as R_BR. Calculate the springback difference ΔR_x around the X-axis and the springback difference ΔR_y around the Y-axis: ΔR_x=(R_BL+R_BR)(R_TL+R_TR) ΔR_y=(R_TR+R_BR)(R_TL+R_BL) These two differences reflect the amplitude and direction of the rebound tilt. They are then converted into the target attitude compensation angle of the suction nozzle using another set of scaling factors: Δθ_x=K_tilt×ΔR_x / L_y Δθ_y=K_tilt×ΔR_y / L_x Where L_x and L_y are the X-axis and Y-axis measuring point spacings used in S2, respectively. K_tilt is the tilt compensation gain coefficient, a dimensionless empirical value obtained through experimental calibration. Dividing by the measuring point spacing converts the rebound height difference into an approximate angle.

[0118] The calculated Δtheta_x and Δtheta_y represent the additional attitude deflection angles that the nozzle needs to apply during the mounting contact stage. Positive values ​​indicate that it needs to tilt in the corresponding direction to increase the pressing depth on that side.

[0119] 4.4 Send the revised placement parameters to the pick-and-place machine motion control system.

[0120] It communicates with the multi-axis motion controller of the pick-and-place machine via a real-time industrial Ethernet bus. The motion controller internally maintains a set of process parameter registers to store the currently active placement force control parameters and attitude parameters.

[0121] The calculated F_target from step 4.2 is written into the target force register of the corresponding Z-axis torque control channel in the motion controller. If step 4.3 is triggered, Δtheta_x and Δtheta_y are accumulated into the angle offset register of the nozzle attitude control loop, respectively. The values ​​of these registers will be read and executed by the motion controller during the placement of the next chip.

[0122] After the write operation is completed, the readback value is read from the motion controller and compared with the written target value for verification. If the deviation between the two exceeds the allowable error, the parameter transmission is deemed to have failed, triggering the retransmission mechanism, with a maximum of 3 retries. If all 3 attempts fail, a device alarm is issued and the placement process is suspended.

[0123] 4.5 Record the complete process information of this compensation to form a compensation data chain.

[0124] After the parameters are successfully sent, a compensation history record is generated, which includes the following fields: The unique identifier of the source chip that triggered the compensation is Source_Chip_UID, the total springback amount R_total and the springback tilt flag F_tilt of the source chip, the torque correction amount ΔF calculated this time and the target torque after correction F_target, if there is tilt compensation, record the values ​​of Δtheta_x and Δtheta_y, the timestamp of the compensation parameters being issued and the expected mounting serial number of the target chip for which the compensation takes effect.

[0125] The record is written to the independent data table Compensation_History in the production line central database, with an auto-incrementing record number as the primary key, and a foreign key is established to link the source chip's Chip_UID and the target chip's Chip_UID.

[0126] 4.6 Apply compensation parameters when mounting the next chip and start a new monitoring cycle.

[0127] When the next chip is picked up by the nozzle and moved above the mounting position, the motion controller reads the updated torque target value register and attitude bias register. During the Z-axis descent and mounting pressure holding stages, the servo driver precisely adjusts the actual applied pressure to F_target in closed-loop force control mode. At the same time, at the moment of contact with the substrate, the nozzle adjusts the pitch and roll attitude according to the set values ​​of Δtheta_x and Δtheta_y, so that the chip contacts the adhesive surface and substrate in a slightly tilted attitude, thereby actively counteracting the expected non-uniform rebound tendency during the pressure diffusion process.

[0128] After the chip is mounted, the system sequentially executes S2 feature extraction and S3 springback monitoring. The resulting springback data will then be used as input for the next round of S4 compensation. Thus, S3 and S4 form a real-time closed-loop adjustment loop with each chip as the step size, continuously maintaining the mounting quality within the target process window.

[0129] 4.7 Compensation logic avoidance and alarm under abnormal operating conditions.

[0130] In actual operation, the closed-loop compensation function will be paused and restored to the default fixed parameters when the following two abnormal situations occur, and the corresponding alarm will be triggered: Anomaly 1: The R_total of three consecutive chips exceeds the preset reasonable springback range, for example, less than 5μm or greater than 60μm. This indicates that the adhesive condition or substrate condition has undergone a drastic change beyond the compensation capacity, and continued blind adjustments may introduce even greater fluctuations.

[0131] Anomaly 2: The F_tilt of two consecutive chips is 1, and the tilt directions are inconsistent. This indicates that the direction of the rebound tilt is random rather than systematic, and cannot be effectively improved by nozzle posture compensation. It is necessary to check the nozzle parallelism or the horizontal state of the substrate support platform.

[0132] When the above-mentioned anomaly is triggered, the compensation enable flag will be set to 0, and subsequent mounting will resume using the default torque and zero attitude angle. At the same time, an alarm message will be pushed to the production line management system.

[0133] The specific S5 defect risk assessment is as follows: Defect detection in traditional surface mount packaging (SMT) processes typically relies solely on a single visual inspection or height measurement after mounting, using a binary judgment of pass or fail based on fixed geometric tolerances. This method cannot identify "latent defective chips" that, while currently conforming to geometric dimensions, pose a potential risk of early failure due to process anomalies. Furthermore, it cannot distinguish whether the same appearance deviation is caused by sporadic interference or systemic process drift, leading to a high false positive rate and high re-inspection costs.

[0134] 5.1 Construct a full-dimensional data profile of the current chip.

[0135] Using the Chip_UID of the chip to be evaluated as the primary key, a joint query request is initiated to the central database of the production line to retrieve all associated data generated for that chip in steps S1 to S4, including: Obtain from S1: the local warpage height value W_local of the substrate at the chip mounting location, and the global maximum warpage value W_strip_max of the substrate strip to which the chip belongs.

[0136] Obtain from S2: planar offsets ΔX and ΔY, average mounting height H_avg, tilt angles Tilt_X and Tilt_Y, array of four-sided glue overflow widths, and relative rotation angle Δtheta.

[0137] Obtain from S3: total rebound amount R_total, maximum instantaneous rebound rate of each order V_bounce_max, rebound tilt flag F_tilt, and four corner rebound amount arrays.

[0138] Obtain from S4: the compensation record (torque correction ΔF_applied) received by the chip as the target chip, and the compensation record (torque correction amount ΔF_triggered) triggered by the chip as the source chip for the next chip.

[0139] Obtain auxiliary traceability information from the process, such as adhesive batch number, pick-and-place machine number, placement timestamp, and the cumulative number of chips placed in the current batch.

[0140] 5.2 Perform geometric dimension threshold determination.

[0141] To facilitate subsequent score calculations, this step first converts the original geometric feature values ​​extracted by S2 into the following standardized Boolean notation: Planar offset out-of-tolerance is marked as M_XY, and is true when the absolute value of ΔX or ΔY is greater than 25μm; The tilt error is marked as M_Tilt, and is true when the absolute value of Tilt_X or Tilt_Y is greater than 0.3°; The abnormal glue overflow is marked as M_Bleed, and is true when any of W_Left, W_Right, W_Top, or W_Bottom is less than 30μm or greater than 120μm; The rotational deviation flag is denoted as M_Rotation, and is true when the absolute value of Δθ is greater than 0.1°.

[0142] The geometric feature values ​​extracted by S2 are compared with the preset tolerance to generate geometric defect markers. The specific values ​​of each threshold are as follows: The planar offset exceeding tolerance M_XY is relevant to the packaged product addressed in this embodiment. The bonding wire between the chip pads and the lead frame pins uses gold wire with a diameter of 25μm, and the solder ball diameter at the first solder joint is approximately 50μm to 60μm. The visual alignment system of the wire bonding machine searches a circular area with a radius of 30μm centered on the theoretical pad. When the planar offset exceeds 25μm, the actual landing point of the solder ball will be too close to the edge of the pad, resulting in the solder ball partially suspended outside the pad during wire bonding. Insufficient bonding strength, combined with the offset and the wire bonding machine's own alignment error, may exceed the visual search boundary, causing frequent alarms and shutdowns of the wire bonding machine. Therefore, the threshold is set to 25μm, based on the principle of subtracting a safety margin from the wire bonding machine's alignment tolerance.

[0143] The tilt error M_Tilt refers to the issue where, during wire bonding, the clamping jaws need to press against the chip surface to fix the chip's position and conduct ultrasonic energy. Since the clamping jaws have a planar surface, when the chip surface is tilted, the contact between the clamping jaws and the chip degenerates from surface contact to line contact or point contact. For silicon chips with a thickness of 150μm to 200μm in this embodiment, when the tilt angle exceeds 0.3°, the local pressure on the higher edge of the chip exceeds the safe edge compressive strength of silicon material, and the probability of chip edge chipping during wire bonding increases sharply from the normal level. This threshold of 0.3° was determined by combining finite element simulation of materials mechanics with destructive test data from wire bonding experiments.

[0144] The overflow error M_Bleed indicates that the width of the overflow reflects the degree of spread of the adhesive after it has been pressed out during mounting. In this embodiment, the lower threshold is set to 30μm and the upper threshold is set to 120μm.

[0145] When the adhesive overflow width is less than 30μm, it indicates that the adhesive has not fully filled the gap between the chip and the substrate, and there may be voids below the chip edge. During the high-pressure injection molding process in the subsequent molding process, the molding compound may be squeezed into the void area, causing chip displacement or delamination. When the designed distance between the chip pad and the chip edge is 150μm, when the adhesive overflow width exceeds 120μm, the adhesive front edge is less than 30μm from the pad boundary. During the curing and shrinkage process, the adhesive may further migrate to the pad area, contaminating the bonding surface and causing poor soldering. This threshold is determined jointly by the chip layout design rules and the rheological property data provided by the adhesive supplier.

[0146] Rotation deviation (M_Rotation) has a relatively small impact on chip rotation in single-layer mounting, but it has a cumulative amplification effect in multi-layer stacked packages. For the 4-layer stacked product in this embodiment, if the rotation deviation of each layer is 0.1° and the direction is random, the theoretical upper limit of the cumulative rotation deviation of the top layer chip relative to the bottom layer chip can reach 0.4°. During wire bonding, the bonding pattern is fixed, and rotation deviation will cause a systematic shift in the position of the solder joints corresponding to some pins. Therefore, the threshold of 0.1° is set based on the principle that the maximum allowable deviation of a single layer is equal to the total allowable deviation divided by the number of stacked layers and then multiplied by a safety factor.

[0147] 5.3 Anomaly Detection in the Execution Process Based on the springback monitoring data from S3, determine whether there is unsteady behavior in the mounting process and generate process anomaly markers: The rebound amount is abnormal, P_Rebound, with a lower threshold of 5μm and an upper threshold of 60μm.

[0148] There is a definite physical relationship between total springback and adhesive layer thickness. The adhesive layer thickness is approximately equal to the difference between the chip's lowest pressure point during mounting and the stable springback height after vacuum release, plus the initial wetting thickness of the adhesive due to the roughness of the chip's bottom surface. For the epoxy resin adhesive used in this embodiment, a calibration curve for springback and adhesive layer thickness was established through cross-sectional measurement experiments. When the springback is less than 5 μm, the corresponding average adhesive layer thickness is less than 8 μm. In the 55°C to 125°C temperature cycling aging test, samples at this thickness level showed an interface delamination failure rate exceeding the upper limit allowed by the product's reliability specifications after 500 cycles. When the springback is greater than 60 μm, the corresponding adhesive layer thickness exceeds 45 μm, which not only causes the overall chip height to exceed the thickness control range of the molding process, but also results in excessive elastic sinking of the chip during wire bonding, leading to poor consistency in wire arc height. Therefore, the boundary between 5 μm and 60 μm is based on a combined constraint of reliability testing and process tolerance.

[0149] An abnormal rebound rate, P_ReboundRat, has a threshold of 120% of the standard rate range for this adhesive model. The determination condition is: any instantaneous rebound rate calculated in S3.5 exceeds 120% of the upper limit of the standard rate range for this adhesive model. This standard rate range is predetermined by historical statistical data of this adhesive model under normal adhesive layer thickness conditions and stored in the batch process parameter library. Its upper limit has been calibrated and cured during system deployment.

[0150] Rebound rate reflects the viscosity recovery kinetics of adhesive after pressure release. The standard rate range is the mean and standard deviation range obtained by measuring standard adhesive layer thickness samples under standard conditions using this pick-and-place machine during adhesive factory inspection. When the instantaneous rebound rate of a chip exceeds 120% of the upper limit of the standard range, it indicates that the degree of shear thinning of the adhesive under the chip during the pressure stage or the viscosity recovery rate after pressure deviates significantly from the normal state. Based on the failure analysis case library, such deviations are statistically correlated with abnormal states such as air bubbles, uneven filler distribution, or local pre-curing in the adhesive. This threshold is determined by ROC curve analysis of the rebound rate distribution of normal and abnormal samples in historical production data, taking into account both the detection rate and false alarm rate.

[0151] The springback tilt anomaly, P_Tilt, has a threshold of 6 μm. This threshold was used in step S3 to determine whether asymmetric springback has occurred. From a defect risk assessment perspective, a springback tilt exceeding 6 μm means that the difference in adhesive layer thickness at the four corners of the chip has exceeded the adaptive compensation capability of the wire bonding clamps. Wire bonding clamps typically possess micron-level elastic deformation capabilities to accommodate minute unevenness, but when the height difference exceeds 6 μm, the clamp's elastic compensation margin is exhausted, and the chip will be subjected to ultrasonic vibration in an incompletely fixed state, leading to a decrease in bonding strength consistency. This threshold is determined jointly by the mechanical specifications provided by the clamp supplier and wire bonding process verification tests.

[0152] 5.4 Execution System Dimension State Analysis Based on the S4 compensation history record analysis, the current process system state of the chip is analyzed, and a system state flag is generated: This mounting has been compensated with S_CompReceived, and the threshold is that the absolute value of the torque correction is greater than 0.05N.

[0153] The steady-state control accuracy of the pick-and-place machine's force control system is ±0.03N. When the absolute value of the torque correction exceeds 0.05N, it significantly exceeds the noise level of the force control system, confirming that the correction is an effective compensation actively applied by the S4 closed-loop algorithm, rather than random fluctuations from servo jitter. This marker is used to distinguish between "chips that are successfully placed under natural conditions" and "chips that are successfully placed only after active intervention," as the latter has lower process robustness than the former.

[0154] This mounting triggers a new compensation S_CompTriggered, with a threshold of an absolute value of the triggered torque correction being greater than 0.05N.

[0155] When the springback characteristic of a chip after placement triggers S4 to apply a torque compensation exceeding 0.05N to the next chip, it indicates that there is a deviation between the chip's actual process response and the target value that S4 deems necessary to correct. The chip itself may have all geometric parameters within acceptable limits, but as a "signal source," it indicates the drift direction of the current process state. Incorporating this marker into the judgment logic is one of the core features that distinguishes this method from traditional detection methods that only consider the final result.

[0156] The compensation frequency is too high. The judgment rule is that in the most recent five consecutive chips, three or more chips have S_CompTriggered as 1.

[0157] This rule is based on the "continuous point test" criterion in statistical process control. Under steady-state conditions, the probability of S4 triggering compensation should be less than 10%. If 3 out of 5 consecutive compensation triggers, the random probability of this occurrence, calculated using a binomial distribution, is less than 0.8%, therefore, it can be confidently determined that the system has deviated from statistical control. This threshold combination is determined by calculation using process capability baseline data.

[0158] The substrate warpage high background value S_WarpageHigh is set to a threshold value where the global maximum warpage value of the substrate strip is greater than 70μm.

[0159] In this embodiment, the nominal warpage range of the substrate at the mounting heating temperature is 30μm to 50μm. When the global maximum warpage exceeds 70μm, even if the pick-and-place machine ensures the geometric parameters are within acceptable limits at the moment of mounting through active correction in S1, the residual stress generated by the substrate warpage recovery during the chip curing and cooling process will significantly increase. Finite element thermal stress simulation results show that when the substrate warpage exceeds 70μm, the residual tensile stress of the adhesive layer at the chip corner after curing is close to the lower limit of the safe room temperature shear strength of the adhesive, indicating insufficient long-term reliability margin. This threshold was determined by a combination of simulation analysis and accelerated reliability experiments.

[0160] 5.5 Defect risk level is comprehensively determined based on fusion rules.

[0161] The decision rule base is pre-built before system deployment, based on data accumulation from both historical mass production data and reliability acceleration experiment data: Historical mass production data is collected by gathering full production data for this package model over the past six consecutive months, covering different adhesive batches and different placement machines, with a sample size of no less than 100,000 chips. Each sample must fully include the substrate warpage value (S1), geometric feature value (S2), springback monitoring value (S3), compensation history record (S4), and the pass / fail result of the chip in the final electrical test.

[0162] The reliability accelerated testing data consists of sample chips selected under the boundary conditions of each process window, subjected to accelerated aging tests such as temperature cycling, high temperature and humidity, and vibration, and the failure modes and failure times are recorded to establish a quantitative mapping relationship between process parameter deviations and long-term reliability.

[0163] Based on the above data, a decision tree algorithm was used to rank the failure correlation importance of multidimensional features and search for split points, extracting feature combinations and critical thresholds strongly correlated with the final failure. After the physical interpretability of each candidate rule was reviewed by process engineers and reliability engineers, a fixed rule base file was formed. The main contents of the rule base include: tolerance boundary values ​​of each geometric feature, upper and lower limits of the normal range of each springback feature, warning thresholds of system state features, and deduction weights corresponding to each anomaly.

[0164] Calculation method of comprehensive defect risk score During real-time assessment, the full-dimensional data acquired by S51 is input into the scoring engine to calculate a comprehensive defect risk score between 0 and 100, denoted as S_risk. A higher score indicates better overall quality and a lower potential failure risk. The score is obtained by a weighted sum of the sub-scores from the three dimensions, calculated using the formula: S_risk = S_geo + S_proc + S_sys Among them, S_geo is the geometric compliance sub-score, S_proc is the rebound process stability sub-score, and S_sys is the system state offset sub-score. The specific calculation rules for the three sub-scores are as follows: First Dimension: Geometric Compliance Sub-Score S_geo This dimension assesses whether the current chip's mounting geometry meets the capacity requirements of subsequent processes. The calculation starts with a maximum score of 40 points, and points are deducted item by item according to the following rules: A deduction of 15 points will be made if the absolute value of the planar offset exceeds 25μm. This threshold is determined by the visual search range of the wire bonding machine; exceeding it will lead to difficulties in solder joint alignment.

[0165] A deduction of 10 points will be made if the absolute value of the tilt angle exceeds 0.3°. This threshold is determined by the matching relationship between the wire bonding claw and the compressive strength of the chip edge.

[0166] Deduct 10 points if the adhesive overflow width is less than 30μm or greater than 120μm. A lower limit below the limit indicates insufficient adhesive filling, while an upper limit exceeding the limit indicates a risk of contaminating the solder pads.

[0167] A deduction of 5 points is applied if the absolute value of the rotation angle exceeds 0.1°. This threshold is determined by the cumulative rotation tolerance of the multi-layer stack.

[0168] Points are deducted cumulatively, with a minimum deduction of 0 points. If any of the following fatal deviations occur during the scoring process, the scoring calculation will be terminated immediately, and the defect level will be locked as follows: the absolute value of the plane offset exceeds 50μm; or the glue overflow width is greater than 150μm and the glue front edge is less than 20μm from the adjacent pad.

[0169] Points are deducted cumulatively for each category until the maximum score of 40 points for that dimension is reached. No negative points will be generated.

[0170] Second dimension: Bounce process stability sub-rating S_proc This dimension assesses the smoothness of adhesive layer behavior during the placement and release process. The calculation starts with a maximum score of 40 points, with points deducted item by item according to the following rules: A total rebound exceeding the normal range of 5μm to 60μm will result in a deduction of 20 points. This range is determined by a correlation experiment between adhesive layer thickness and bond strength, as well as the consistency of wire bonding height.

[0171] A boolean value indicating springback tilt is true (i.e., the maximum difference in springback at the four corners exceeds 6μm), deducting 15 points. This threshold is determined by the adaptive compensation stroke of the wire-attaching gripper.

[0172] If any rebound rate exceeds the limit, it will be marked as true (5 points will be deducted for each level, with a maximum deduction of 15 points). Exceeding the limit indicates that there may be air bubbles or uneven filler distribution inside the adhesive.

[0173] Points are deducted cumulatively, with a minimum deduction of 0 points. If any of the following fatal situations occur during the scoring process, the scoring calculation will be terminated immediately, and the product will be directly locked into the defective grade: the total springback amount is less than 2μm or greater than 80μm; or the maximum difference in springback amount at the four corners exceeds 12μm.

[0174] Points are deducted cumulatively for each category until the maximum score of 40 points for that dimension is reached. No negative points will be generated.

[0175] Third dimension: System state offset sub-rating S_sys This dimension assesses whether the current chip's manufacturing process system carries a systemic drift risk. The calculation starts with a maximum score of 20 points, with points deducted item by item according to the following rules: This chip received torque compensation as the target (i.e., the mounting torque of this chip in the S4 record was corrected to exceed 0.05N), deducting 5 points. This indicates that this chip was manufactured under non-default parameters.

[0176] This chip triggered torque compensation for the next chip (i.e., the springback characteristic of this chip caused the torque correction of S4 to the next chip to exceed 0.05N), deducting 10 points. This indicates that the placement result of this chip has significantly deviated from the target value.

[0177] If the compensation trigger frequency is too high in the last 5 consecutive chips (i.e., 3 or more chips trigger compensation), deduct 5 points. This is based on the continuous point testing criteria of statistical process control.

[0178] A maximum global warpage value of more than 70 μm on the substrate strip will result in a deduction of 5 points. This threshold is determined jointly by thermal stress simulation and reliability testing.

[0179] Points are deducted cumulatively for each category until the maximum score of 20 points for that dimension is reached. No negative points will be generated.

[0180] Defect risk level classification rules and judgment logic Based on the calculation results of the defect risk comprehensive score S_risk, the chips are classified into levels as follows: The standard grade comprehensive scoring scheme is S_risk ≥ 85 points. Chips of this grade perform excellently in three dimensions: geometric accuracy, springback process, and system status, with all indicators falling within the middle range of the process window. The expected failure rate of such chips under normal operating conditions is consistent with the process design goals.

[0181] Chips with a comprehensive quality score (S_risk) between 70 and 84 are considered. These chips exhibit slight deviations in a single dimension or warning signals in the system status dimension, but the deviations remain within the safe limits verified by reliability experiments. Such chips can proceed to subsequent processes normally, but their anomalies must be recorded for batch quality trend analysis.

[0182] The overall risk rating (S_risk) is between 50 and 69. Chips in this category exhibit multiple anomalies or significant deviations in a single dimension. Historical failure sample statistics show that chips in this rating range have a significantly higher failure rate in subsequent use than the baseline level. These chips should not be directly processed into high-value-added downstream processes and require manual re-inspection and confirmation.

[0183] Defect levels are defined as follows: a comprehensive score S_risk < 50 points, or the triggering of a fatal deviation lockout condition during the scoring process (i.e., plane offset exceeding 50μm, solder paste contamination of pads, total springback exceeding the limit range of 2μm to 80μm, and springback difference at the four corners exceeding 12μm). Chips of this level have a definite functional defect or an extremely high probability of early failure and should be immediately rejected and scrapped.

[0184] The corresponding treatment measures for each level are as follows: Based on the final determined severity level, the corresponding processing plan instruction is sent to the production line execution system. The specific processing measures for each level are as follows: The normal grade handling procedure is as follows: a release signal is sent. The chip is then conveyed normally to the molding process loading area along with the substrate strip, and its judgment grade and comprehensive score are written into the database for yield statistics.

[0185] The handling scheme for the monitored grade is as follows: a release signal is sent, and the chip's physical flow path is the same as that of the normal grade. However, at the database level, the monitored grade, overall score, and specific deduction items for this chip are additionally marked. The batch quality management system will automatically accumulate the percentage of monitored grades and the main reasons for deductions. When the percentage of this grade exceeds 15% for three consecutive batches, a process optimization prompt will be triggered.

[0186] The risk-level handling procedure is as follows: A diversion and re-inspection signal is sent. The sorting machine transfers the substrate strip containing the chip to the re-inspection buffer track before it enters the encapsulation machine. The production line management system pushes a complete snapshot of S1 to S4 data and comprehensive score details of the chip to the re-inspection station terminal. The re-inspection personnel decide whether to release, scrap, or downgrade the chip based on the re-inspection results and writes the re-inspection conclusion back to the database.

[0187] The defective chip handling scheme is as follows: A forced rejection signal is sent. The sorting machine marks the chip with laser dots or removes it pneumatically at the chip mounter's exit track, and the chip enters the waste bin. The rejection reason and the specific locking conditions that triggered it are written into the database, and the chip is permanently marked as scrap.

[0188] After each substrate strip or production batch completes all mounting, a batch risk summary report is automatically generated. This report includes the percentage of chips of each grade, the score distribution, and the most frequently triggered deduction items. When the combined percentage of risky and defective chips exceeds 5%, the system triggers a batch quality warning and pushes an alarm message to the production line management system. When the frequency of deduction items in the system status sub-score exceeds 30% across the entire batch, equipment maintenance or adhesive re-inspection recommendations are pushed. This summary information is also fed back to the S4 compensation parameter self-tuning module to evaluate the effectiveness of closed-loop control and guide the version iteration of the rule base.

[0189] The complete process data for S6 is as follows: 6.1 Using the chip's unique identifier as the primary key, aggregate data from the entire process.

[0190] Using the chip's unique identifier Chip_UID as the primary key, the complete data record of the chip is extracted from the independent data tables written in each step. Specifically, this includes: the local warpage height value of the substrate and the global maximum warpage value of the substrate strip generated in S1; the plane offset, average mounting height, tilt angle, adhesive overflow width on all four sides, and rotation angle generated in S2; the gradient release strategy type, vacuum degree sequence, springback increment and rate at each level, independent springback amount at each corner, and springback tilt mark generated in S3; the compensation records with the chip as the target and the chip as the source generated in S4; and the comprehensive defect risk score, final judgment level, and trigger condition number generated in S5.

[0191] 6.2 Generate a complete process fingerprint data package.

[0192] The aggregated data is encapsulated into an indivisible full-process fingerprint data package using a predefined JSON template. The data package is segmented according to the source of each step, with each segment containing the original feature values, intermediate computational costs, and decision conclusions. The data package uses Chip_UID as the primary identifier for the filename, supplemented by a timestamp and machine number as secondary identifiers, and is stored in the Full_Process_Fingerprint table of the production line's central database. Write operations employ a database transaction mechanism, configured for one-time writes and subsequent read-only access; any attempt to modify already written records is rejected by the database permission policy.

[0193] 6.3 Supports pre-querying and quality traceability of subsequent processes.

[0194] When the substrate strip flows into the wire bonding machine or molding machine, the downstream equipment scans the substrate barcode and chip matrix coordinates to generate a Chip_UID consistent with the chip mounting process, and then sends a query request to the database. The database returns the S2 geometric offset and S3 springback tilt of the chip, and the downstream equipment automatically adjusts the wire bonding coordinate offset or the pressing height of the clamping jaws accordingly, achieving proactive compensation across processes. Simultaneously, the quality management system can retrieve the entire process fingerprint data package by batch number, time period, machine number, etc., generating quality traceability reports to support failure analysis and process optimization.

[0195] Obviously, the above embodiments are merely examples to clearly illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all embodiments here. However, these obvious variations or modifications derived from the spirit of the present invention are still within the protection scope of the present invention.

Claims

1. A method for detecting defects in component mounting during chip stacking packaging, characterized in that, Includes the following steps: S1. Before mounting, the surface of the heated substrate is scanned in a grid pattern to obtain the height data of multiple sampling points. The bilinear surface equation of the substrate surface is fitted by the least squares method to calculate the maximum warpage height difference. Based on the bilinear surface equation, the starting height of the mounting head, the rubbing trajectory, and the holding torque release curve are actively corrected to complete the chip mounting. During the XY rubbing process, the Z-axis motor is controlled to dynamically follow the bilinear surface equation to make small extensions and retractions, so that the contact pressure between the chip and the substrate remains constant. S2. After mounting, perform in-situ visual inspection and laser height measurement on the chip, and extract the chip's planar offset, average mounting height, tilt angle, adhesive overflow width on all four sides, and relative rotation angle to generate a stacking feature dataset. S3. After mounting, the substrate warpage height value and the preset adhesive rebound sensitivity level are used as joint query conditions to access the preset lookup table to determine the order of gradient release of the nozzle vacuum adsorption force; during the gradient release process, the chip surface height is continuously sampled and monitored; the collected height data is divided into each order, the transition segment data after the start of each order is removed, the arithmetic mean of the retained data is calculated as the steady-state height of that order, the difference between two adjacent steady-state heights is taken as the rebound increment of that order, and the rebound increments of each order are accumulated to obtain the total rebound amount; the height sampling data within a specific time period after each vacuum level switch is fitted with a straight line, and the slope of the fitted straight line is taken as the instantaneous rebound rate of that order; after the vacuum is completely released, the independent rebound amount of the four corners is extracted, the maximum value and minimum value of the independent rebound amount of the four corners are compared to determine whether asymmetric rebound has occurred, and a rebound monitoring dataset is generated. S4. Read the total springback amount and asymmetric springback determination result of the current chip; compare the total springback amount with the target springback amount reference value to obtain the springback amount deviation value ΔR, and use an incremental proportional adjustment algorithm to calculate the correction amount ΔF of the target torque on the Z-axis through the torque compensation proportional coefficient; when asymmetric springback is determined, determine the tilt compensation axis based on the two corner points with the largest springback amount, and calculate the springback difference amount ΔR_x around the X-axis and the springback difference amount ΔR_y around the Y-axis. Convert the springback difference amount into the target attitude compensation angles Δtheta_x and Δtheta_y of the nozzle around the X-axis and Y-axis of the next chip to be mounted through the tilt compensation gain coefficient; send the corrected mounting parameters to the pick-and-place machine motion control system and record the compensation process data; S5. Integrate the substrate warpage data, stacking feature dataset, springback monitoring dataset, and compensation history data generated by the current chip in steps S1 to S4 to calculate a comprehensive defect risk score. The comprehensive defect risk score includes a system state offset sub-score. When calculating the system state offset sub-score, if the springback characteristics of the current chip cause the absolute value of the torque correction to the next chip generated in step S4 to exceed a preset compensation judgment threshold, a deduction is applied to the system state dimension. Based on the comprehensive defect risk score, the chip is classified into normal grade, attention grade, risk grade, or defect grade, and corresponding handling measures are implemented for each grade. S6. Using the chip's unique identifier as the primary key, aggregate and store the entire process data generated in steps S1 to S5 to generate a full-process process fingerprint data package, and support subsequent processes to perform pre-query and quality traceability based on the chip identifier.

2. The defect detection method for component mounting in chip stacking packaging according to claim 1, characterized in that, Extracting the planar offset of the chip in S2 includes the following steps: The chip surface image is captured by a top-down positioning camera. The template image stored before mounting is called up. The central area of ​​the template image is used as the search template. A grayscale template matching algorithm based on normalized cross-correlation is executed on the chip surface image to obtain the integer pixel coordinates of the best matching position. The correlation coefficient values ​​within a preset neighborhood centered on the integer pixel coordinates are fitted with a quadratic surface. The subpixel-level actual position is obtained by solving for the coordinates of the maximum point of the fitted surface, and the planar offset is obtained by subtracting it from the theoretical mounting target position.

3. The defect detection method for component mounting in chip stacking packaging according to claim 1, characterized in that, The tilt angle in S2 includes the following steps: The laser displacement sensor is used to measure the height of each point at a fixed coordinate position at one of the four corners of the chip surface in sequence, and four height values ​​are obtained. Based on the four height values ​​and the distance between the X-axis and Y-axis measuring points, the tilt angles of the chip around the X-axis and Y-axis are calculated respectively.

4. The defect detection method for component mounting in chip stacking packaging according to claim 1, characterized in that, The extraction methods for the width of the overflow adhesive on the four sides in S2 include: Switch to a low-angle ring light source to capture images of the chip, and delineate rectangular detection areas on the outer sides of the four sides of the chip. In each detection area, a one-dimensional grayscale curve is generated by grayscale projection along the vertical edge direction. The first derivative of the grayscale curve is solved to locate the chip sidewall-colloid transition edge position and the colloid-substrate transition edge position. The distance between the two is the overflow width of the adhesive.

5. The defect detection method for component mounting in chip stacking packaging according to claim 1, characterized in that, The specific methods for extracting the relative rotation angle in S2 include: Edge points are extracted from the left and bottom edges of the chip to obtain the edge pixel set; The equations of the left edge line and the lower edge line were fitted using the least squares method. Calculate the angles between the two fitted lines and the X-axis of the image coordinate system, take the average of the two as the current actual rotation angle of the chip, and subtract the theoretical rotation angle to obtain the relative rotation angle.

6. The defect detection method for component mounting in chip stacking packaging according to claim 5, characterized in that, The specific calculation method for the comprehensive defect risk score in S5 includes: The geometric feature values ​​extracted by S2 are compared with the preset process tolerances to generate a geometric compliance sub-score. The starting point is the first preset full score. When the plane offset exceeds the preset plane offset threshold, the first preset score is deducted. When the tilt angle exceeds the preset tilt threshold, the second preset score is deducted. When the overflow width on any side exceeds the preset normal overflow range, the third preset score is deducted. When the rotation angle exceeds the preset rotation threshold, the fourth preset score is deducted. The deductions for each item are accumulated until the full score for this dimension is deducted. The rebound monitoring data extracted by S3 is compared with the preset normal range to generate a sub-score for rebound process stability. The starting point is the second preset full score. When the total rebound amount exceeds the preset normal rebound range, the fifth preset score is deducted. When the asymmetric rebound is determined to be true, the sixth preset score is deducted. When any instantaneous rebound rate exceeds the preset rate threshold, the seventh preset score is deducted for each level, and the total deduction does not exceed the preset deduction limit. All deductions are accumulated until the full score of this dimension is deducted. The system state offset sub-score is generated based on the compensation history data of S4. The starting point is the third preset full score. When the chip has received torque compensation as the target and the correction amount exceeds the preset compensation judgment threshold, the eighth preset score is deducted. When the chip triggers torque compensation for the next chip as the source and the correction amount exceeds the preset compensation judgment threshold, the ninth preset score is deducted. When the compensation trigger frequency in the preset monitoring window exceeds the preset frequency threshold, the tenth score is deducted. When the global maximum warpage value of the substrate exceeds the preset warpage threshold, the eleventh score is deducted. All deductions are accumulated until the full score of this dimension is deducted. The comprehensive defect risk score is the sum of the geometric compliance sub-score, the rebound process stability sub-score, and the system state offset sub-score.

7. The defect detection method for component mounting in chip stacking packaging according to claim 6, characterized in that, The specific rules for classifying defect risk levels in S5 are as follows: When the comprehensive defect risk score is greater than or equal to the first preset score threshold, it is judged as normal grade; When the comprehensive defect risk score is within the first preset score range, it is determined to be a quality level of concern; When the comprehensive defect risk score falls within the second preset score range, it is determined to be of a risk level. When the comprehensive defect risk score is less than the second preset score threshold, or when the preset fatal deviation locking condition is triggered during the scoring process, it is directly judged as a defect grade; The preset fatal deviation locking conditions include at least one of the following: the plane offset exceeds the preset fatal offset threshold, the glue overflow width exceeds the preset fatal glue overflow threshold and the distance between the glue front edge and the adjacent pad is less than the preset safe distance threshold, the total rebound amount exceeds the preset fatal rebound range, and the maximum difference in the rebound amount at the four corners exceeds the preset fatal tilt threshold.

8. The defect detection method for component mounting in chip stacking packaging according to claim 7, characterized in that, The specific handling measures corresponding to each level in S5 are as follows: Normal grade and special grade: Send a release signal and the chip will flow normally to the next process. The special grade chip will be marked with its level and specific deduction items in the database. Risk level: Send a diversion re-inspection signal to transfer the chip to the re-inspection station for manual confirmation; Defect level: Send a forced rejection signal to perform a rejection operation on the chip.

9. The defect detection method for component mounting in chip stacking packaging according to claim 8, characterized in that, The active correction in S1 specifically includes: When the substrate is identified as having a saddle-shaped warp, the mounting head pressing process is divided into a rapid descent segment and a slow contact segment. The starting height of the slow contact segment is determined by adding a preset safety margin to the warp height at the current position calculated by the bilinear surface equation. During the XY kneading process, the Z-axis motor dynamically follows the bilinear surface equation to make minute extensions and contractions, so that the contact pressure between the chip and the substrate remains constant. If the maximum warpage height difference is greater than the preset high warpage risk threshold, after the mounting pressure holding is completed, the Z-axis motor will be controlled to reduce the holding torque linearly from the mounting pressure torque according to the preset gradient within the preset pressure release time, and finally release it completely.

10. The defect detection method for component mounting in chip stacking packaging according to claim 9, characterized in that, The rebound monitoring dataset in S3 includes: The preset lookup table is a two-dimensional control strategy table that has been calibrated and solidified in advance through process experiments. It is used to dynamically select the most suitable vacuum gradient release strategy based on the actual process state of the current mounting position. Based on the order of vacuum gradient release determined in S3, the target percentage of vacuum degree and time step corresponding to each order are obtained from the preset lookup table; a laser displacement sensor is configured to continuously sample the height of preset monitoring points on the chip surface at a preset sampling frequency; the vacuum proportional valve is controlled sequentially according to the target percentage of vacuum degree for each order, and height data is continuously recorded during the stabilization period of each order, and a marker signal is sent to the data acquisition system to record the start and end times of gradient release. The instantaneous rebound rates of each order calculated in S3 are compared with the preset standard rate range to determine whether they exceed the limit and generate the corresponding Boolean flags. When determining whether asymmetric rebound occurs, if the difference between the maximum and minimum values ​​of the four independent rebound amounts is greater than the preset rebound tilt determination threshold, then asymmetric rebound is determined to have occurred and the tilt direction is recorded.

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