Method for manufacturing a semiconductor device

Abstract

This invention discloses a method for fabricating a semiconductor device, comprising the following steps: Providing a semiconductor substrate including a first portion located in a low-voltage device region and a second portion located in a medium-voltage device region. Forming a first pad oxide pattern and a second pad oxide pattern on the first portion and the second portion, respectively. Forming a first trench isolation structure and a second trench isolation structure. At least a portion of the first trench isolation structure is formed in the first portion and adjacent to the first pad oxide pattern. At least a portion of the second trench isolation structure is formed in the second portion and adjacent to the second pad oxide pattern. Performing an etching process, wherein a portion of the second trench isolation structure and the second pad oxide pattern are removed together by the etching process.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including different operating voltage device regions. Background Technology

[0002] In integrated circuits, transistors are designed with different structures to accommodate various operating voltages to meet diverse operational requirements. For example, transistors operating at lower voltages are used in core components and input / output (I / O) devices, while transistors with high-voltage capabilities are used in high-voltage operating environments, such as CPU power supplies, power management systems, AC / DC converters, and power amplifiers. In embedded high-voltage (eHV) manufacturing processes, transistors with different operating voltages can be placed on the same chip to meet product requirements, such as high-voltage, medium-voltage, and low-voltage transistors. Since the structures and fabrication methods of these transistors differ, improving the integration of manufacturing processes between various transistor structures through structural and / or process design to increase production yield and / or ensure product compliance is a continuous research direction for professionals in this field. Summary of the Invention

[0003] The present invention provides a method for fabricating a semiconductor device by using an etching process to remove a portion of the trench isolation structure and the adjacent pad oxide pattern at the same time, thereby simplifying the fabrication process and / or reducing production costs.

[0004] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: Providing a semiconductor substrate, the semiconductor substrate including a first portion located in a low-voltage device region and a second portion located in a medium-voltage device region. Forming a first pad oxide pattern and a second pad oxide pattern on the first portion and the second portion, respectively. Forming a first trench isolation structure and a second trench isolation structure. At least a portion of the first trench isolation structure is formed in the first portion and adjacent to the first pad oxide pattern, and at least a portion of the second trench isolation structure is formed in the second portion and adjacent to the second pad oxide pattern. Performing an etching process, wherein a portion of the second trench isolation structure and the second pad oxide pattern are removed together by the etching process. Attached Figure Description

[0005] Figures 1 to 15 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein...

[0006] Figure 2 for Figure 1 A diagram illustrating the subsequent situation;

[0007] Figure 3 for Figure 2 A diagram illustrating the subsequent situation;

[0008] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0009] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0010] Figure 6 for Figure 5 A diagram illustrating the subsequent situation;

[0011] Figure 7 for Figure 6 A diagram illustrating the subsequent situation;

[0012] Figure 8 for Figure 7 A diagram illustrating the subsequent situation;

[0013] Figure 9 for Figure 8 A diagram illustrating the subsequent situation;

[0014] Figure 10 for Figure 9 A diagram illustrating the subsequent situation;

[0015] Figure 11 for Figure 10 A diagram illustrating the subsequent situation;

[0016] Figure 12 for Figure 11 A diagram illustrating the subsequent situation;

[0017] Figure 13 for Figure 12 A diagram illustrating the subsequent situation;

[0018] Figure 14 for Figure 13 A diagram illustrating the subsequent situation;

[0019] Figure 15 for Figure 14 A diagram illustrating the subsequent situation.

[0020] Explanation of main component symbols

[0021] 22 Semiconductor substrate

[0022] 22A Part 1

[0023] 22B Part 2

[0024] 22C Part 3

[0025] 24 Pad oxide layer

[0026] 24A Pad Oxide Pattern

[0027] 24B pad oxide pattern

[0028] 24C Pad Oxide Pattern

[0029] 24D Pad Oxide Pattern

[0030] 26 Mask layers

[0031] 26A Mask Pattern

[0032] 26B Mask Pattern

[0033] 26C mask pattern

[0034] 26D mask pattern

[0035] 28A Trench Isolation Structure

[0036] 28B Trench Isolation Structure

[0037] 28C Trench Isolation Structure

[0038] 28D trench isolation structure

[0039] 30 mask layers

[0040] 32 Gate oxide layer

[0041] 34A oxide layer

[0042] 34B gate oxide layer

[0043] 34C oxide layer

[0044] 36 Gate oxide layer

[0045] 81 Patterned Mask Layer

[0046] 82 Patterned Mask Layer

[0047] 83 Patterned Mask Layer

[0048] 91 Patterning process

[0049] 92 Etching process

[0050] 93 Etching process

[0051] 94 Cleaning and manufacturing process

[0052] 95. Formation of manufacturing process

[0053] 96 Etching process

[0054] BS bottom surface

[0055] D1 Vertical direction

[0056] D2 Horizontal direction

[0057] DW1 deep trap region

[0058] DW2 deep trap region

[0059] DW3 deep trap region

[0060] FR drift region

[0061] GS1 gate structure

[0062] GS2 gate structure

[0063] GS3 gate structure

[0064] LD1 lightly doped region

[0065] LD2 lightly doped region

[0066] R1 Low Voltage Device Area

[0067] R2 Medium Voltage Device Area

[0068] R3 High Voltage Device Area

[0069] RC dent

[0070] SD1 source / drain region

[0071] SD2 source / drain region

[0072] SD3 source / drain region

[0073] SP1 spacer

[0074] SP2 spacer

[0075] SP3 spacer

[0076] T1 transistor structure

[0077] T2 transistor structure

[0078] T3 transistor structure

[0079] TR1 trench

[0080] TR2 trench

[0081] TR3 trench

[0082] TR4 trench

[0083] TS11 upper surface

[0084] TS12 upper surface

[0085] TS21 upper surface

[0086] TS22 upper surface

[0087] TS31 upper surface

[0088] TS32 upper surface

[0089] TS33 upper surface

[0090] TS34 upper surface

[0091] WR1 well region

[0092] WR2 well region Detailed Implementation

[0093] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0094] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0095] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0096] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0097] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term that includes etching.

[0098] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0099] Please see Figures 1 to 15 . Figures 1 to 15 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 2 It is illustrated Figure 1 A diagram illustrating the subsequent situation. Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 A diagram illustrating the subsequent situation. Figure 7 It is illustrated Figure 6 A diagram illustrating the subsequent situation. Figure 8 It is illustrated Figure 7 A diagram illustrating the subsequent situation. Figure 9 It is illustrated Figure 8 A diagram illustrating the subsequent situation. Figure 10 It is illustrated Figure 9 A diagram illustrating the subsequent situation. Figure 11 It is illustrated Figure 10 A diagram illustrating the subsequent situation. Figure 12 It is illustrated Figure 11 A diagram illustrating the subsequent situation. Figure 13 It is illustrated Figure 12 A diagram illustrating the subsequent situation. Figure 14 It is illustrated Figure 13 A diagram illustrating the subsequent situation. Figure 15 It is illustrated Figure 14 A schematic diagram of the subsequent situation. This embodiment provides a method for manufacturing a semiconductor device, including the following steps. First, as... Figure 1 As shown, a semiconductor substrate 22 is provided, comprising a first portion 10A located in a low-voltage device region R1 and a second portion 10B located in a medium-voltage device region R2. Figure 2As shown, a first pad oxide pattern (e.g., pad oxide pattern 24A) and a second pad oxide pattern (e.g., pad oxide pattern 24B) are formed on the first portion 22A and the second portion 22B, respectively. Figure 2 and Figure 3 As shown, a first trench isolation structure (e.g., trench isolation structure 28A) and a second trench isolation structure (e.g., trench isolation structure 28B) are formed. At least a portion of the trench isolation structure 28A is formed in the first portion 22A and adjacent to the pad oxide pattern 24A, and at least a portion of the trench isolation structure 28B is formed in the second portion 22B and adjacent to the pad oxide pattern 24B. Figure 9 and Figure 10 As shown, an etching process 93 is performed, in which a portion of the trench isolation structure 28B and the pad oxide pattern 24B are removed together. The etching process 93 may include a buffer oxide etching (BOE) process or other suitable etching methods. By removing the pad oxide pattern 24B simultaneously while partially etching the trench isolation structure 28B to adjust its height using the same etching process, the manufacturing process can be simplified and / or production costs can be reduced.

[0100] like Figure 1As shown, a vertical direction D1 can be considered as the thickness direction of the semiconductor substrate 22. The semiconductor substrate 22 may have an upper surface and a bottom surface BS opposite to each other in the vertical direction D1. The aforementioned pad oxide patterns 24A and 24B may be formed on one side of the upper surface of the semiconductor substrate 22, while the trench isolation structures 28A and 28B may extend from the upper surface of the semiconductor substrate 22 along the vertical direction D1 toward the bottom surface BS, but do not penetrate the semiconductor substrate 22. A horizontal direction that is substantially orthogonal to the vertical direction D1 (e.g., but not limited to the horizontal direction D2) may be parallel to the bottom surface BS, but is not limited thereto. In this document, the distance in the vertical direction D1 between a relatively high position and / or component and the bottom surface BS of the semiconductor substrate 22 may be greater than the distance in the vertical direction D1 between a relatively low position and / or component and the bottom surface BS of the semiconductor substrate 22. The lower part or bottom of each component may be closer to the bottom surface BS of the semiconductor substrate 22 in the vertical direction D1 than the upper part or top of that component. Another component above a component may be considered relatively far from the bottom surface BS of the semiconductor substrate 22 in the vertical direction D1, and another component below a component may be considered relatively close to the bottom surface BS of the semiconductor substrate 22 in the vertical direction D1. Furthermore, the upper surface and upper part of a component may include the topmost surface and uppermost part of that component in the vertical direction D1, while the bottom surface and bottom part of a component may include the bottommost surface and bottommost part of that component in the vertical direction D1, but are not limited thereto. The situation described herein, in which a particular component is positioned between two other objects in a certain direction, may include, but is not limited to, the situation in which the component is sandwiched between the two objects in this direction.

[0101] Further explanation: The manufacturing method of this embodiment may include, but is not limited to, the following steps and / or features. For example... Figure 1As shown, the semiconductor substrate 22 may also include a third portion 22C located in a high-voltage device region R3. The semiconductor substrate 22 may include a silicon substrate, a silicon-germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or other suitable materials. Furthermore, a pad oxide layer 24 may be formed on the semiconductor substrate 22 and located in the vertical direction D1 above the first portion 22A, the second portion 22B, and the third portion 22C. A mask layer 26 may be formed on the pad oxide layer 24 and located in the vertical direction D1 above the first portion 22A, the second portion 22B, and the third portion 22C. In some embodiments, prior to the formation of the pad oxide layer 24 and the mask layer 26, the upper surfaces of the second portion 22B and the third portion 22C may be made lower than the upper surface of the first portion 22A by a suitable method (e.g., but not limited to methods of partially oxidizing and removing oxides from the semiconductor substrate 22). Consequently, the upper surfaces of the pad oxide layer 24 and the mask layer 26 located above the second portion 22B and the third portion 22C may be lower than the upper surfaces of the pad oxide layer 24 and the mask layer 26 located above the first portion 22A, respectively. The pad oxide layer 24 may comprise silicon oxide or other suitable oxide materials, and the mask layer 26 may comprise silicon nitride or other suitable mask materials.

[0102] In some embodiments, prior to the formation of the pad oxide layer 24, a first deep well region (e.g., deep well region DW1), a second deep well region (e.g., deep well region DW2), and a third deep well region (e.g., deep well region DW3) may be formed in the first portion 22A, the second portion 22B, and the third portion 22C respectively via an implantation fabrication process, but this is not a limitation. The conductivity types of deep well regions DW1, DW2, and DW3 may be complementary to the conductivity type of the semiconductor substrate 22. For example, when the semiconductor substrate 22 is a P-type semiconductor substrate (e.g., a P-type silicon semiconductor substrate), deep well regions DW1, DW2, and DW3 may be N-type deep well regions, but this is not a limitation. Then, as Figure 1 and Figure 2 As shown, a patterning process 91 can be performed, in which the first part 22A and the deep well region DW1 can be partially removed by the patterning process 91 to form a first trench (e.g., trench TR1) in the first part 22A, the second part 22B and the deep well region DW2 can be partially removed by the patterning process 91 to form a second trench (e.g., trench TR2) in the second part 22B, and the third part 22C and the deep well region DW3 can be partially removed by the patterning process 91 to form a third trench (e.g., trench TR3) and a fourth trench (e.g., trench TR4) in the third part 22C.

[0103] Furthermore, the pad oxide layer 24 can be patterned by patterning process 91 to become pad oxide pattern 24A, pad oxide pattern 24B, a third pad oxide pattern (e.g., pad oxide pattern 24C), and a fourth pad oxide pattern (e.g., pad oxide pattern 24D). Pad oxide pattern 24A is formed on the first portion 22A, pad oxide pattern 24B is formed on the second portion 22B, and pad oxide patterns 24C and 24D are formed on the third portion 22C. The mask layer 26 can be patterned by patterning process 91 to become a first mask pattern (e.g., mask pattern 26A), a second mask pattern (e.g., mask pattern 26B), a third mask pattern (e.g., mask pattern 26C), and a fourth mask pattern (e.g., mask pattern 26D). Mask pattern 26A is formed on the first portion 22A, mask pattern 26B is formed on the second portion 22B, and mask patterns 26C and 26D are formed on the third portion 22C. Pad oxide pattern 24A is sandwiched between mask pattern 26A and first portion 22A in the vertical direction D1; pad oxide pattern 24B is sandwiched between mask pattern 26B and second portion 22B in the vertical direction D1; pad oxide pattern 24C is sandwiched between mask pattern 26C and third portion 22C in the vertical direction D1; and pad oxide pattern 24D is sandwiched between mask pattern 26D and third portion 22C in the vertical direction D1. Pad oxide patterns 24A, 24B, 24C, and 24D can be considered to be formed together using the same manufacturing process; mask patterns 26A, 26B, 26C, and 26D can be considered to be formed together using the same manufacturing process; and trenches TR1, TR2, TR3, and TR4 can be considered to be formed together using the same manufacturing process.

[0104] In some embodiments, the patterning process 91 may include a photolithography process and a corresponding etching process. The patterned photoresist formed in the photolithography process can be used as an etching mask when etching the mask layer 26, and the patterned photoresist and / or the mask pattern formed by etching the mask layer 26 can be used as an etching mask when etching the pad oxide layer 24 and / or the semiconductor substrate 22. The patterned photoresist can be removed after the trenches are formed. Therefore, mask patterns 26A, 26B, 26C, 26D, pad oxide patterns 24A, 24B, 24C, 24D, trenches TR1, TR2, TR3, and TR4 can be formed through the same patterning process 91, but are not limited thereto. In some embodiments, other suitable methods may be used to form patterns separately or together as needed for the design. Figure 2 The trenches, pad oxide patterns, and mask patterns shown are illustrated. Furthermore, due to the fact that the upper surface of the first portion 22A is higher than the upper surface of the second portion 22B and the upper surface of the third portion 22C, the upper surface of the pad oxide pattern 24A may be higher than the upper surfaces of the pad oxide patterns 24B, 24C, and 24D in the vertical direction D1; the upper surface of the mask pattern 26A may be higher than the upper surfaces of the mask patterns 26B, 26C, and 26D in the vertical direction D1; and the bottom of the trench TR1 may be higher than the bottoms of the trenches TR2, TR3, and TR4 in the vertical direction D1, but this is not a limitation.

[0105] like Figure 2 and Figure 3As shown, after the above-described patterning process, trench isolation structures 28A, 28B, a third trench isolation structure (e.g., trench isolation structure 28C), and a fourth trench isolation structure (e.g., trench isolation structure 28D) can be formed. Therefore, each mask pattern (e.g., mask pattern 26A, mask pattern 26B, mask pattern 26C, and mask pattern 26D) and each pad oxide pattern (e.g., pad oxide pattern 24A, pad oxide pattern 24B, pad oxide pattern 24C, and pad oxide pattern 24D) can be formed before each trench isolation structure (e.g., trench isolation structure 28A, trench isolation structure 28B, trench isolation structure 28C, and trench isolation structure 28D). Trench isolation structures 28A, 28B, 28C, and 28D can be formed in trenches TR1, TR2, TR3, and TR4, respectively. At least a portion of trench isolation structure 28C is formed in a third portion 22C and is adjacent to the pad oxide pattern 24C, while at least a portion of trench isolation structure 28D is formed in the third portion 22C and is adjacent to both the pad oxide pattern 24C and the pad oxide pattern 24D. In some embodiments, each trench isolation structure can be formed by filling each trench (e.g., trench TR1, trench TR2, trench TR3, and trench TR4) with a single or multiple layers of insulating material (e.g., oxide insulating material or other suitable insulating material), and performing a planarization and etch-back process on this insulating material. Therefore, trench isolation structures 28A, 28B, 28C, and 28D can be considered to be formed together using the same fabrication process. Furthermore, the upper surface TS11 of the trench isolation structure 28A may be lower than the upper surface of the mask pattern 26A, the upper surface TS21 of the trench isolation structure 28B may be lower than the upper surface of the mask pattern 26B, the upper surface TS31 of the trench isolation structure 28C may be lower than the upper surface of the mask pattern 26C, and the upper surface TS32 of the trench isolation structure 28D may be lower than the upper surfaces of both the mask pattern 26C and the mask pattern 26D. The upper surfaces TS11, TS21, TS31, and TS32 may be substantially coplanar, but are not limited thereto.

[0106] like Figure 3 and Figure 4 As shown, after the trench isolation structures are formed, the mask patterns can be removed to expose the pad oxide patterns. Then, as... Figure 5As shown, a drift region FR can be formed in the third portion 22C. In some embodiments, a deep well region DW3 can be formed in the third portion 22C before the trench isolation structure 28C and the trench isolation structure 28D are formed, and the drift region FR can be formed in the deep well region DW3, and the conductivity type of the drift region FR can be complementary to the conductivity type of the deep well region DW3, but is not limited thereto. In some embodiments, the deep well region DW3 may not be formed in the third portion 22C as required by design, and the drift region FR can be formed directly in the third portion 22C, and the conductivity type of the drift region FR can be complementary to the conductivity type of the semiconductor substrate 22. In some embodiments, two trench isolation structures 28D, two drift regions FR, and two pad oxide patterns 24C may be formed. The trench isolation structures 28C may surround the two trench isolation structures 28D, the two drift regions FR, the two pad oxide patterns 24C, and the pad oxide patterns 24D in the horizontal direction D2. The pad oxide patterns 24D may be located between the two trench isolation structures 28D in the horizontal direction D2, and each pad oxide pattern 24C and each drift region FR may be located between the trench isolation structures 28C and the trench isolation structures 28D in the horizontal direction D2.

[0107] like Figure 6 and Figure 7 As shown, after the drift region FR is formed, a second gate oxide layer (e.g., gate oxide layer 32) may be formed, at least a portion of which is formed in the third portion 22C, and the thickness of the gate oxide layer 32 is greater than the thickness of the pad oxide pattern 24C. In some embodiments, the method of forming the gate oxide layer 32 may include, but is not limited to, the following steps. Figure 6 As shown, a mask layer 30 can be formed to cover each trench isolation structure and each pad oxide pattern. A patterned mask layer 81 is formed on the mask layer 30, and an etching process 92 is performed using the patterned mask layer 81 as an etching mask. The mask layer 30 may include silicon nitride or other suitable mask materials, while the patterned mask layer 81 may include a patterned photoresist layer or other suitable materials. Figure 6 and Figure 7 As shown, an etching process 92 can be used to remove a portion of the semiconductor substrate 22 (e.g., the third portion 22C), a portion of the trench isolation structure 28D, and at least a portion of the pad oxide pattern 24D to form a recess RC. A gate oxide layer 32 can then be formed in the recess RC, and the mask layer 30 can be removed. In some embodiments, the gate oxide layer 32 can be formed by an oxidation process on the semiconductor substrate 22 exposed by the recess RC. This oxidation process may include a thermal oxidation process (e.g., an RTO process) or other suitable oxidation methods.

[0108] like Figure 8As shown, after the trench isolation structures and gate oxide layer 32 are formed, a first well region (e.g., well region WR1) and a second well region (e.g., well region WR2) can be formed in the first portion 22A and the second portion 22B, respectively, and two lightly doped regions LD2 are formed in the well region WR2. The well regions WR1 and WR2 can be formed in the deep well regions DW1 and DW2, respectively. The conductivity types of the well regions WR1 and WR2 can be the same as or complementary to the conductivity types of the deep well regions DW1 and DW2, respectively, depending on the design requirements, while the conductivity type of the lightly doped region LD2 can be complementary to the conductivity type of the well region WR2. In some embodiments, each deep well region, each well region, each lightly doped region, and the drift region FR can each include a doped region formed in the semiconductor substrate 22 by a suitable doping fabrication process (e.g., but not limited to ion implantation fabrication process).

[0109] like Figure 9 and Figure 10As shown, after the formation of well regions WR1, WR2, and the lightly doped region LD2, the aforementioned etching process 93 can be performed. In some embodiments, a patterned mask layer 82 can be formed to cover the gate oxide layer 32, the pad oxide pattern 24A, and the trench isolation structure 28A. The gate oxide layer 32, the pad oxide pattern 24A, and the trench isolation structure 28A can be covered by the patterned mask layer 82 during the etching process 93 without being etched by the etching process 93, and the patterned mask layer 82 can be removed after the etching process 93. The etching process 93 can be used to reduce the height of the trench isolation structure not covered by the patterned mask layer 82 and can also remove the pad oxide pattern not covered by the patterned mask layer 82 to expose a portion of the semiconductor substrate 22 (e.g., a portion of the well region WR2 and a portion of the drift region FR). Therefore, a portion of the trench isolation structure 28B and the pad oxide pattern 24B can be removed together by etching process 93, and a portion of the trench isolation structure 28C, a portion of the trench isolation structure 28D, and the pad oxide pattern 24C can also be removed together by etching process 93. Before etching process 93, the upper surface TS11 of the trench isolation structure 28A, the upper surface TS21 of the trench isolation structure 28B, the upper surface TS31 of the trench isolation structure 28C, and the upper surface TS32 of the trench isolation structure 28D can be substantially coplanar. The upper surface of the trench isolation structure 28B after etching process 93 (e.g., upper surface TS22) may be lower in the vertical direction D1 than the upper surface TS21 of the trench isolation structure 28B before etching process 93 and the upper surface of the trench isolation structure 28A after etching process 93 (e.g., upper surface TS11). The upper surface of the trench isolation structure 28C after etching process 93 (e.g., upper surface TS33) may be lower in the vertical direction D1 than the upper surface TS31 of the trench isolation structure 28C before etching process 93 and the upper surface TS11 of the trench isolation structure 28A after etching process 93. The upper surface of the trench isolation structure 28D after etching process 93 (e.g., upper surface TS34) may be lower in the vertical direction D1 than the upper surface TS32 of the trench isolation structure 28D before etching process 93 and the upper surface TS11 of the trench isolation structure 28A after etching process 93.

[0110] like Figures 9 to 12As shown, after etching process 93, a first gate oxide layer (e.g., gate oxide layer 34B) may be formed on the second portion 22B, an oxide layer 34A may be formed on the first portion 22A, and an oxide layer 34C may be formed on the third portion 22C. The thickness of the gate oxide layer 34B may be greater than the thickness of the pad oxide pattern 24B and less than the thickness of the gate oxide layer 32, but is not limited thereto. In some embodiments, oxide layers 34A, 34B, and 34C may be formed together by a forming process 95, which may include an oxide monoxide process or other suitable fabrication methods. In some embodiments, the pad oxide pattern 24A may remain on the first portion 22A after etching process 93, and the pad oxide pattern 24A may become at least a part of the oxide layer 34A by forming process 95. For example, the semiconductor substrate 22 (or well region WR1) located below the pad oxide pattern 24A may be partially oxidized by the forming process 95 to form an oxide layer 34A together with the original pad oxide pattern 24A, but this is not a limitation. Furthermore, in some embodiments, a cleaning process 94 may be performed on the semiconductor substrate 22 after the etching process 93 and before the forming process 95, and the pad oxide pattern 24A may remain on the first portion 22A after the cleaning process 94. The cleaning process 94 can be considered a pre-cleaning step performed before the forming process 95, and the cleaning process 94 may include standard cleaning 1 (SC-1), standard cleaning 2 (SC-2), or other suitable cleaning methods. Standard cleaning 1 may be performed using a cleaning solution composed of ammonium hydroxide, hydrogen peroxide, and deionized water in a specific ratio, while standard cleaning 2 may be performed using a cleaning solution composed of hydrogen chloride, hydrogen peroxide, and deionized water in a specific ratio. It is worth noting that since the pad oxide patterns 24B and 24C have been removed by the etching process 93, the cleaning process 94 performed before forming the process 95 does not need to include a cleaning step (e.g., DHF cleaning) to remove oxides, thereby avoiding related negative effects (e.g., damage to the trench isolation structure), but this is not a limitation.

[0111] In the manufacturing method of the present invention, an etching process 93 can be performed after the formation of the gate oxide layer 32 and before the formation of the gate oxide layer 34B to remove a portion of the trench isolation structure 28B and the pad oxide pattern 24B located in the medium voltage device region R2, as well as a portion of the trench isolation structure 28C and a portion of the trench isolation structure 28D and the pad oxide pattern 24C located in the high voltage device region R3, thereby simplifying the manufacturing process and / or reducing production costs.

[0112] like Figure 13 and Figure 14 As shown, a patterned mask layer 83 can be formed to cover the trench isolation structure 28B, gate oxide layer 34B, trench isolation structure 28C, trench isolation structure 28D, oxide layer 34C, and gate oxide layer 32. An etching process 96 is performed using the patterned mask layer 83 as an etching mask to remove a portion of the trench isolation structure 28A and the oxide layer 34A. The etching process 96 may include BOE fabrication processes or other suitable etching methods. An upper surface of the trench isolation structure 28A after the etching process 96 (e.g., upper surface TS12) may be lower in the vertical direction D1 than the upper surface TS11 of the trench isolation structure 28A before the etching process 96. Figure 14 and Figure 15 As shown, in some embodiments, the oxide layer 34C can be removed and the upper surfaces of the trench isolation structures 28B, 28C, and 28D can be further reduced, and a gate oxide layer 36, two lightly doped regions LD1, two source / drain regions SD1, two source / drain regions SD2, two source / drain regions SD3, a gate structure GS1, a gate structure GS2, a gate structure GS3, spacers SP1, SP2, and SP3 can be formed. The gate oxide layer 36 is formed on the first portion 22A, the gate structure GS1 is formed on the gate oxide layer 36, the two source / drain regions SD1 can be at least partially formed in the well region WR1 and located on two opposite sides of the gate structure GS1 in the horizontal direction D2, and the lightly doped region LD1 is formed in the well region WR1 and located between the gate structure GS1 and the source / drain regions SD1. Gate structure GS2 is formed on gate oxide layer 34B. Two source / drain regions SD2 may be at least partially formed in well region WR2 and located on opposite sides of gate structure GS1 in the horizontal direction D2. Lightly doped region LD2 is located between gate structure GS2 and source / drain regions SD2. Gate structure GS3 is formed on gate oxide layer 32. Two source / drain regions SD3 may be formed in two drift regions FR and located on opposite sides of gate structure GS2 in the horizontal direction D2.

[0113] Each source / drain region may include a doped region, an epitaxial structure, or other suitable materials and / or structures. Each gate structure may include a gate dielectric layer and a gate electrode. The gate dielectric layer may include a high-k dielectric material or other suitable dielectric material, while the gate electrode may include a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate structure formed by stacking a work function layer and a low-resistance layer, but is not limited thereto. In some embodiments, the above-described gate structure may also be replaced by a metal gate and a gate dielectric layer by subsequent fabrication processes (e.g., alternative metal gate fabrication processes). Therefore, gate structures GS1, GS2, and GS3 may also be considered as dummy gate structures and include dummy gate materials such as polysilicon, but are not limited thereto. Spacers SP1, SP2, and SP3 may be stacked on the sidewalls of gate structures GS1, GS2, and GS3, and spacers SP1, SP2, and SP3 may include nitride insulating materials, oxide insulating materials, or other suitable insulating materials.

[0114] In some embodiments, transistor structure T1 located in low-voltage device region R1 may include gate structure GS1, gate oxide layer 36, lightly doped region LD1, source / drain region SD1, well region WR1, and deep well region DW1; transistor structure T2 located in medium-voltage device region R2 may include gate structure GS2, gate oxide layer 34B, lightly doped region LD2, source / drain region SD2, well region WR2, and deep well region DW2; and transistor structure T3 located in high-voltage device region R3 may include gate structure GS3, gate oxide layer 32, drift region FR, trench isolation structure 28D, and deep well region DW3. The thickness of gate oxide layer 32 is greater than the thickness of gate oxide layer 34B, and the thickness of gate oxide layer 34B is greater than the thickness of gate oxide layer 36. The operating voltage applicable to transistor structure T3 may be higher than the operating voltage applicable to transistor structure T2 and transistor structure T1, while the operating voltage applicable to transistor structure T2 may be higher than the operating voltage applicable to transistor structure T1.

[0115] In summary, in the semiconductor device manufacturing method of the present invention, by coordinating and adjusting the manufacturing process steps, a portion of the trench isolation structure and the pad oxide pattern located in the medium voltage device region and / or high voltage device region can be removed simultaneously using the same etching process, thereby achieving the effect of simplifying the manufacturing process and / or reducing production costs.

[0116] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided, wherein the semiconductor substrate comprises: The first part is located in the low-voltage device area; and The second part is located in the medium voltage device area; A first pad oxide pattern and a second pad oxide pattern are respectively formed on the first part and the second part; A first trench isolation structure and a second trench isolation structure are formed, wherein at least a portion of the first trench isolation structure is formed in the first portion and adjacent to the first pad oxide pattern, and at least a portion of the second trench isolation structure is formed in the second portion and adjacent to the second pad oxide pattern; and An etching process is performed in which a portion of the second trench isolation structure and the second pad oxide pattern are removed together by the etching process.

2. The method of fabricating a semiconductor device as claimed in claim 1, wherein the upper surface of the second trench isolation structure after the etching process is lower than the upper surface of the second trench isolation structure before the etching process and the upper surface of the first trench isolation structure after the etching process.

3. The method for manufacturing a semiconductor device as claimed in claim 2, wherein the upper surface of the first trench isolation structure before the etching process is coplanar with the upper surface of the second trench isolation structure before the etching process.

4. The method for manufacturing a semiconductor device as described in claim 1, further comprising: After the first trench isolation structure and the second trench isolation structure are formed and before the etching process, a first well region and a second well region are formed in the first part and the second part, respectively.

5. The method for manufacturing a semiconductor device as described in claim 4, further comprising: Before the first trench isolation structure and the second trench isolation structure are formed, a first deep well region and a second deep well region are formed in the first part and the second part, respectively, wherein the first well region and the second well region are formed in the first deep well region and the second deep well region, respectively.

6. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising: After the etching process, a first gate oxide layer is formed on the second portion, wherein the thickness of the first gate oxide layer is greater than the thickness of the second pad oxide pattern; as well as After the etching process, an oxide layer is formed on the first portion, wherein the first gate oxide layer and the oxide layer are formed together by the forming process, the first pad oxide pattern is retained on the first portion after the etching process, and the first pad oxide pattern becomes at least a part of the oxide layer by the forming process.

7. The method for fabricating a semiconductor device as claimed in claim 6, wherein the fabrication process includes an oxidation process.

8. The method for manufacturing a semiconductor device as described in claim 6, further comprising: After the etching process and before the formation process, a cleaning process is performed on the semiconductor substrate, wherein the first pad oxide pattern is retained on the first portion after the cleaning process.

9. The method of fabricating a semiconductor device as claimed in claim 1, wherein the semiconductor substrate further includes a third portion located in a high-voltage device region, and the method of fabricating the semiconductor device further includes: A third pad oxide pattern is formed on the third part, wherein the first pad oxide pattern, the second pad oxide pattern, and the third pad oxide pattern are formed together by the same manufacturing process; as well as A third trench isolation structure is formed, wherein at least a portion of the third trench isolation structure is formed in the third portion and is adjacent to the third pad oxide pattern, and the first trench isolation structure, the second trench isolation structure and the third trench isolation structure are formed together by the same manufacturing process.

10. The method of manufacturing a semiconductor device as claimed in claim 9, further comprising: Before the formation of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure, a first mask pattern, a second mask pattern, and a third mask pattern are formed on the first part, the second part, and the third part, respectively. The first pad oxide pattern is sandwiched between the first mask pattern and the first part in a vertical direction, the second pad oxide pattern is sandwiched between the second mask pattern and the second part in the vertical direction, and the third pad oxide pattern is sandwiched between the third mask pattern and the third part in the vertical direction.

11. The method of manufacturing a semiconductor device as claimed in claim 10, further comprising: A first trench, a second trench, and a third trench are formed in the first part, the second part, and the third part, respectively. The first trench isolation structure, the second trench isolation structure, and the third trench isolation structure are formed in the first trench, the second trench, and the third trench, respectively. The first mask pattern, the second mask pattern, the third mask pattern, the first pad oxide pattern, the second pad oxide pattern, the third pad oxide pattern, the first trench, the second trench, and the third trench are formed by a patterning process performed before the formation of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure.

12. The method of fabricating a semiconductor device as claimed in claim 9, wherein a portion of the third trench isolation structure and the third pad oxide pattern are removed together by the etching process.

13. The method of fabricating a semiconductor device as claimed in claim 12, wherein the upper surface of the third trench isolation structure after the etching process is lower than the upper surface of the third trench isolation structure before the etching process and the upper surface of the first trench isolation structure after the etching process.

14. The method of fabricating a semiconductor device as claimed in claim 13, wherein the upper surface of the first trench isolation structure prior to the etching process is coplanar with the upper surface of the third trench isolation structure prior to the etching process.

15. The method of manufacturing a semiconductor device as claimed in claim 9, further comprising: A second gate oxide layer is formed prior to the etching process, wherein at least a portion of the second gate oxide layer is formed in the third portion, and the thickness of the second gate oxide layer is greater than the thickness of the third pad oxide pattern.

16. The method of manufacturing a semiconductor device as claimed in claim 15, further comprising: A fourth pad oxide pattern is formed on the third part, wherein the first pad oxide pattern, the second pad oxide pattern, the third pad oxide pattern and the fourth pad oxide pattern are formed together by the same manufacturing process; A fourth trench isolation structure is formed, wherein at least a portion of the fourth trench isolation structure is formed in the third portion and adjacent to the fourth pad oxide pattern, and the third pad oxide pattern is located between the third trench isolation structure and the fourth trench isolation structure in a horizontal direction; as well as A recess is formed by removing a portion of the semiconductor substrate, a portion of the fourth trench isolation structure, and at least a portion of the fourth pad oxide pattern, wherein the second gate oxide layer is formed in the recess.

17. The method of fabricating a semiconductor device as claimed in claim 16, wherein a portion of the fourth trench isolation structure is removed by the etching process, and the upper surface of the fourth trench isolation structure after the etching process is lower than the upper surface of the fourth trench isolation structure before the etching process and the upper surface of the first trench isolation structure after the etching process.

18. The method of manufacturing a semiconductor device as claimed in claim 15, further comprising: A patterned mask layer is formed to cover the second gate oxide layer, the first pad oxide pattern, and the first trench isolation structure, wherein the second gate oxide layer, the first pad oxide pattern, and the first trench isolation structure are covered by the patterned mask layer in the etching process. as well as The patterned mask layer is removed after the etching process.

19. The method of manufacturing a semiconductor device as claimed in claim 15, further comprising: A drift region is formed in the third portion after the formation of the third trench isolation structure and before the formation of the second gate oxide layer.

20. The method of manufacturing a semiconductor device as claimed in claim 19, further comprising: Before the formation of the third trench isolation structure, a third deep well region is formed in the third part, wherein the drift region is formed in the third deep well region and the conductivity mode of the drift region is complementary to the conductivity mode of the third deep well region.

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