A semiconductor structure and a method of fabricating the same
By forming a protective dielectric layer and a barrier layer in a silicon substrate, the problem of metal ion diffusion during etching is solved, improving the reliability and electrical performance of the device, and enhancing the aspect ratio and integration density of the through-silicon via (TSV) structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SJ SEMICONDUCTOR (JIANGYIN) CORP
- Filing Date
- 2024-12-16
- Publication Date
- 2026-06-19
AI Technical Summary
In the TSV process, there is a risk of etching through the insulating dielectric layer, which can cause metal ions to diffuse into the silicon substrate, resulting in device failure and affecting product reliability and stability.
A first trench is formed in a silicon substrate, a first dielectric layer is deposited as a protective layer, metal wiring is exposed by etching through the first and second trenches to prevent metal ion diffusion, and a barrier layer is formed before the conductive material is deposited to avoid delamination.
It improves the reliability and stability of the device, enhances the aspect ratio of the through-silicon via structure, improves electrical performance and integration density, and reduces signal delay and power consumption.
Smart Images
Figure CN122249037A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing technology, specifically relating to a semiconductor structure and its preparation method. Background Technology
[0002] With increasingly stringent requirements for high performance, small size, high reliability, and ultra-low power consumption in chips and electronic products, advanced packaging technologies are constantly evolving, leading to a growing demand for 3D integrated circuits (3DIC). 3D integrated circuits are a chip stacking technology used in semiconductor packaging, bringing new advantages in efficiency, power, performance, and form factor to the semiconductor industry. Through Silicon Via (TSV) technology is a technique for interconnecting stacked chips in 3D integrated circuits. It achieves electrical interconnection between different chips by creating vertically interconnected TSV structures on a silicon wafer. TSV technology maximizes chip stacking density in three dimensions, minimizes interconnect lines between chips, and minimizes overall form factor. It also significantly improves chip speed and low power consumption performance, making it one of the most promising technologies in electronic packaging today.
[0003] There are various methods for TSV fabrication. For 3DIC integration, TSVs can be fabricated using pre-via, mid-via, and back-via technologies. Currently, advanced packaging commonly uses back-via processes for fabrication. (Refer to...) Figures 1a-1c As shown, the specific steps include: thinning the back side of the silicon substrate 100; forming an interlayer dielectric layer 200 and a photoresist layer 300 on the back side of the silicon substrate 100, performing photolithography and etching to form a patterned interlayer dielectric layer 200, and etching the silicon substrate 100; finally, etching the bottom insulating dielectric layer 400. During the etching of the insulating dielectric layer 400, due to its low light transmittance, the etching depth is controlled by time. However, the thickness of the insulating dielectric layer 400 fluctuates, posing a risk of etching to the bottom metal wiring 500. Sputtered copper ions can easily diffuse into the silicon substrate 100, causing active devices on the silicon substrate 100 to fail. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the present invention provides a semiconductor structure and its fabrication method. First, a first trench is formed in a silicon substrate, exposing a bottom insulating dielectric layer. Then, a first dielectric layer is formed on the sidewall of the first trench. Next, the bottom insulating dielectric layer is etched into the first trench to form a second trench communicating with the first trench. A second dielectric layer is formed on the sidewall of the second trench. Finally, the bottom insulating dielectric layer of the second trench is etched to expose metal wiring. During the etching process, the first dielectric layer acts as a protective layer for the silicon substrate, preventing metal ions from diffusing into the silicon substrate after the insulating dielectric layer is etched through, thereby avoiding device failure caused by this, improving product reliability, ensuring the stability and safety of the device during long-term use, and effectively improving the overall performance and lifespan of the semiconductor device.
[0005] To achieve the above and other related objectives, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:
[0006] A semiconductor substrate is provided, the semiconductor substrate comprising a stacked silicon substrate and a redistribution layer, the redistribution layer comprising an insulating dielectric layer and metal wiring, and the silicon substrate is thinned;
[0007] A first groove is formed in the silicon substrate to expose the surface of the insulating dielectric layer;
[0008] A first dielectric layer is deposited on the sidewalls and bottom surface of the first groove;
[0009] The first dielectric layer at the bottom of the first groove and the insulating dielectric layer at its bottom are etched to form a second groove in the insulating dielectric layer, the second groove communicating with the first groove;
[0010] A second dielectric layer is deposited on the sidewall of the second groove to form a second dielectric layer;
[0011] The insulating dielectric layer at the bottom of the second groove is etched to expose the metal wiring.
[0012] Optionally, forming the first groove in the silicon substrate includes the following steps:
[0013] An interlayer dielectric layer and a patterned photoresist layer are sequentially deposited on the surface of the silicon substrate;
[0014] The patterned photoresist layer is used as a mask to etch the interlayer dielectric layer and the silicon substrate, exposing the surface of the insulating dielectric layer.
[0015] Optionally, after forming the first groove, the process further includes: removing the patterned photoresist layer and cleaning.
[0016] Optionally, after exposing the metal wiring, the process further includes depositing a barrier layer in the first groove and the second groove, the barrier layer covering a first dielectric layer on the sidewall of the first groove, a second dielectric layer on the sidewall of the second groove, and the metal wiring at the bottom of the second groove.
[0017] Optionally, after forming the barrier layer, the process further includes depositing a seed layer on the surface of the barrier layer.
[0018] Optionally, after forming the seed layer, the process further includes: electroplating a conductive material in the first groove and the second groove, wherein the conductive material fills the first groove and the second groove and covers the surface of the interlayer dielectric layer.
[0019] Optionally, the conductive material is metallic copper.
[0020] Optionally, after depositing the conductive material, the process further includes: removing the conductive material located on the surface of the interlayer dielectric layer, as well as a portion of the interlayer dielectric layer.
[0021] Optionally, after removing part of the interlayer dielectric layer, the thickness of the remaining interlayer dielectric layer is between 0.8 μm and 1.2 μm.
[0022] Optionally, the first dielectric layer is one or a combination of silicon oxide and silicon nitride, and the second dielectric layer is one or a combination of silicon oxide and silicon nitride.
[0023] The present invention also provides a semiconductor structure, which is formed by the method for preparing the semiconductor structure described in any one of the preceding claims.
[0024] The semiconductor structure and its preparation method provided by this invention have at least the following beneficial effects:
[0025] 1) During the etching process, the first dielectric layer serves as a protective layer for the silicon substrate, preventing metal ions from diffusing into the silicon substrate after the insulating dielectric layer is etched through, thereby avoiding device failure caused by this and improving product reliability.
[0026] 2) During the process of depositing conductive material to form conductive pillars, the first dielectric layer serves as a backing layer, effectively preventing the conductive material from directly contacting the silicon substrate and causing delamination;
[0027] 3) The first dielectric layer can, to a certain extent, correct the top-wide and bottom-narrow shape of the first groove, effectively improve the aspect ratio of the through-silicon via structure, increase the integration density of the device, reduce signal delay, reduce power consumption, and enhance electrical performance and reliability. Attached Figure Description
[0028] Figures 1a-1c The diagram shows the structural schematics of each step in the fabrication of through-silicon via (TSV) structures in the prior art.
[0029] Figure 2 The diagram shown is a flowchart illustrating the fabrication process of the semiconductor structure provided in the embodiment.
[0030] Figure 3 The diagram shown is a schematic diagram of the structure for forming the first groove provided in step S2 of the embodiment.
[0031] Figure 4 The diagram shown is a schematic diagram of the structure for forming the first dielectric layer provided in step S3 of the embodiment.
[0032] Figure 5 The diagram shown is a schematic diagram of the structure for forming the second groove provided in step S4 of the embodiment.
[0033] Figure 6 The diagram shown is a schematic diagram of the structure for forming the second dielectric layer provided in step S5 of the embodiment.
[0034] Figure 7 The diagram shown is a schematic representation of the structure for forming the barrier layer and conductive pillars provided in step S6 of the embodiment.
[0035] Component designation explanation
[0036] 1 First Groove
[0037] 2 Second groove
[0038] 3 conductive pillars
[0039] 11 First dielectric layer
[0040] 12 Second dielectric layer
[0041] 100 silicon substrate
[0042] 200 interlayer dielectric layer
[0043] 300 photoresist layers
[0044] 400 insulating dielectric layer
[0045] 500 Metal Wiring
[0046] 600 barrier layer Detailed Implementation
[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0048] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.
[0049] Example 1
[0050] This embodiment provides a method for fabricating a semiconductor structure, such as... Figure 2 As shown, it includes the following steps:
[0051] Step S1: Provide a semiconductor substrate, the semiconductor substrate comprising a stacked silicon substrate and a redistribution layer, the redistribution layer comprising an insulating dielectric layer and metal wiring, and thin the silicon substrate;
[0052] Reference Figure 1a As shown, a semiconductor substrate is provided, comprising a stacked silicon substrate 100 and a redistribution layer. As an example, the fabrication of the semiconductor substrate may include bonding the silicon substrate 100 to the redistribution layer; the specific bonding method is not limited here.
[0053] As an example, the size of the silicon substrate 100 may include 6 inches, 8 inches, 12 inches, etc., and the thickness of the silicon substrate 100 is between 10 μm and 15 μm, preferably 12 μm.
[0054] As an example, the redistribution layer includes metal wiring 500 for electrical connection and an insulating dielectric layer 400. In this embodiment, the metal wiring 500 is made of copper, and the number and distribution of the metal wiring 500 layers are not limited here. The insulating dielectric layer 400 may include one or a combination of silicon oxide and silicon nitride. Specifically, when the insulating dielectric layer 400 uses silicon oxide and / or silicon nitride, the diffusion of copper metal formed in subsequent processes can be effectively avoided due to the low diffusion of copper in silicon oxide and silicon nitride, thus achieving a good isolation and insulation effect.
[0055] Next, the silicon substrate 100 is thinned. Specifically, to reduce the size of the final fabricated device, it is preferable to perform a thinning operation on the silicon substrate 100 in the semiconductor substrate. The thinning process may include, but is not limited to, chemical mechanical polishing (CMP), and may also include mechanical polishing, etc. In this embodiment, to improve the flatness of the silicon substrate 100 after polishing, CMP is preferably used for thinning. As an example, the thickness of the thinned silicon substrate 100 may include 5μm to 15μm, such as 5μm, 10μm, 15μm, etc., and can be set as needed, without limitation here.
[0056] Step S2: A first groove is formed in the silicon substrate to expose the surface of the insulating dielectric layer;
[0057] Reference Figure 1b As shown, an interlayer dielectric layer 200 is deposited on the surface of a silicon substrate 100. As an example, the interlayer dielectric layer 200 may include one or a combination of silicon oxide and silicon nitride, and the thickness of the interlayer dielectric layer 200 is between 1.5 μm and 2.5 μm, preferably 2 μm. The interlayer dielectric layer 200 can be used as a hard mask for subsequent etching processes, and it can also be used as an insulating layer.
[0058] Next, a patterned photoresist layer 300 is formed on the interlayer dielectric layer 200. As an example, the patterned photoresist layer 300 can be formed on the interlayer dielectric layer 200 by coating, exposure, and development; the thickness of the photoresist layer 300 is between 8 μm and 12 μm, preferably 10 μm.
[0059] Next, as Figure 3 As shown, inductively coupled plasma etching (ICP) is used to etch the interlayer dielectric layer 200 and the silicon substrate 100 using a patterned photoresist layer 300 as a mask until the surface of the insulating dielectric layer 400 is exposed, forming a first groove 1 that penetrates the interlayer dielectric layer 200 and the silicon substrate 100. As an example, the opening width, opening morphology, and positional distribution of the first groove 1 can all be set according to the requirements of the final through-silicon via (TSV) structure to be fabricated, and are not limited here.
[0060] Next, dry resist removal and wet cleaning are performed. Specifically, dry resist removal utilizes plasma treatment to remove the patterned photoresist layer 300 from the photoresist surface. This method is thorough and fast, does not introduce chemicals, and reduces corrosion and damage to other material layers. Wet cleaning uses chemical reagents to react or dissolve impurities and oil adsorbed on the surface of the object being cleaned, accompanied by physical measures such as ultrasound, heating, and vacuuming, to desorb impurities from the surface of the object being cleaned. Then, a large amount of high-purity deionized water is used for rinsing, resulting in a clean surface. Through these processing steps, contaminants generated during the etching of the silicon substrate 100 can be effectively removed, ensuring that there are no polymer residues in the first groove 1, thus avoiding subsequent contamination of the composite film etching machine.
[0061] Step S3: Deposit and form a first dielectric layer on the sidewalls and bottom surface of the first groove;
[0062] like Figure 4 As shown, a first dielectric layer 11 is deposited on the sidewalls and bottom surface of the first groove 1 using a high-temperature furnace tube oxidation method or an atomic layer deposition (ALD) method. When conductive material is subsequently deposited in the first groove 1, the first dielectric layer 11 can serve as a backing layer to prevent direct contact between the conductive material and the silicon substrate 100, thus avoiding delamination. The first dielectric layer 11 can also act as a protective layer for the sidewall silicon, preventing metal ions from diffusing into the silicon substrate 100 after etching through the insulating dielectric layer 400 during subsequent etching processes, which could cause device failure. Furthermore, the first groove 1 may have a wider top and narrower bottom; the first dielectric layer 11 can, to some extent, correct the morphology of the first groove 1 and improve the aspect ratio of the through-silicon via (TSV) structure.
[0063] As an example, the first dielectric layer 11 may include one or a combination of silicon oxide and silicon nitride; the thickness of the first dielectric layer 11 is set according to the width of the first groove 1. In this embodiment, the thickness of the first dielectric layer 11 is between [missing information - likely a value] and [missing information - likely a value].
[0064] Step S4: Etch the first dielectric layer at the bottom of the first groove and the insulating dielectric layer at its bottom, forming a second groove in the insulating dielectric layer, the second groove communicating with the first groove;
[0065] like Figure 5As shown, a capacitively coupled plasma etching (CAPE) method is used to etch the first dielectric layer 11 on the bottom surface of the first groove 1 and the insulating dielectric layer 400 at its bottom, forming a second groove 2 communicating with the first groove 1 in the insulating dielectric layer 400. As an example, the etching depth is controlled by controlling the etching time, so that the etching stops above the metal wiring 500, that is, the second groove 2 is located above the metal wiring 500.
[0066] Step S5: Deposit a second dielectric layer on the sidewall of the second groove;
[0067] like Figure 6 As shown, a second dielectric layer 12 is deposited on the sidewall of the second groove 2 using either a high-temperature furnace tube oxidation method or an atomic layer deposition (ALD) method. The second dielectric layer 12 can serve as a backing layer for subsequent deposition of conductive materials in the second groove 2, thereby preventing the diffusion of conductive materials and avoiding device failure.
[0068] As an example, the second dielectric layer 12 may include one or a combination of silicon oxide and silicon nitride; the thickness of the second dielectric layer 12 is set according to the width of the second groove 2. In this embodiment, the thickness of the second dielectric layer 12 is equal to that of the first dielectric layer 11, which is between...
[0069] Step S6: Etch the insulating dielectric layer at the bottom of the second groove to expose the metal wiring.
[0070] First, the insulating dielectric layer 400 at the bottom of the second groove 2 is removed by inductively coupled plasma etching (ICP) to expose the metal wiring 500.
[0071] Next, a barrier layer 600 is deposited in the first groove 1 and the second groove 2 using physical vapor deposition (PVD). The barrier layer 600 covers the first dielectric layer 11 on the sidewall of the first groove 1, the second dielectric layer 12 on the sidewall of the second groove 2, and the metal wiring 500 at the bottom of the second groove 2 to prevent the conductive material subsequently plated from interpenetrating with the silicon substrate 100. As an example, the barrier layer 600 is a thin film formed of tantalum nitride and tantalum.
[0072] Next, a seed layer (not shown in the figure) is deposited on the surface of the barrier layer 600 using physical vapor deposition (PVD) to enhance the adhesion of the metal during subsequent electroplating, improve the uniformity and quality of the deposit, thereby avoiding defects such as voids and cracks, and ensuring the integrity and reliability of the electroplated layer. As an example, the seed layer is made of copper.
[0073] Next, conductive material is electroplated in the first groove 1 and the second groove 3 to form conductive pillars 3. The conductive material fills the first groove 1 and the second groove 2 and covers the surface of the interlayer dielectric layer 200. In this embodiment, the conductive material is metallic copper.
[0074] Finally, chemical mechanical polishing (CMP) is used to remove the conductive material on the surface of the interlayer dielectric layer 200, as well as part of the interlayer dielectric layer 200, to form... Figure 7 The structure is shown. As an example, the thickness of the remaining interlayer dielectric layer 200 is between 0.8 μm and 1.2 μm, preferably 1 μm.
[0075] Example 2
[0076] This embodiment provides a semiconductor structure, referring to... Figure 7 As shown, it includes a semiconductor substrate and an interlayer dielectric layer 200 located on its surface, and the semiconductor substrate has a through-silicon via structure.
[0077] As an example, the semiconductor substrate includes a stacked silicon substrate 100 and a redistribution layer, the redistribution layer including metal wiring 500 for electrical connection and an insulating dielectric layer 400.
[0078] As an example, the top surface of the through-silicon via (TSV) structure is flush with the interlayer dielectric layer 200, the bottom surface of the TSV structure is in contact with the metal wiring 500, and the sidewalls of the TSV structure are isolated from the semiconductor substrate through the first dielectric layer 11 and the second dielectric layer 12.
[0079] As an example, the through-silicon via structure includes a barrier layer 600 and a conductive pillar 3 located in a first groove 1 and a second groove 2, with a seed layer (not shown in the figure) also formed between the barrier layer 600 and the conductive pillar 3.
[0080] As an example, the semiconductor structure provided in this embodiment is formed by the method for preparing the semiconductor structure provided in Embodiment 1. Its specific structure can be referred to the description in Embodiment 1, and will not be repeated here.
[0081] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate comprising a stacked silicon substrate and a redistribution layer, the redistribution layer comprising an insulating dielectric layer and metal wiring, and the silicon substrate is thinned; A first groove is formed in the silicon substrate to expose the surface of the insulating dielectric layer; A first dielectric layer is deposited on the sidewalls and bottom surface of the first groove; The first dielectric layer at the bottom of the first groove and the insulating dielectric layer at its bottom are etched to form a second groove in the insulating dielectric layer, the second groove communicating with the first groove; A second dielectric layer is deposited on the sidewall of the second groove to form a second dielectric layer; The insulating dielectric layer at the bottom of the second groove is etched to expose the metal wiring.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the first groove in the silicon substrate includes the following steps: An interlayer dielectric layer and a patterned photoresist layer are sequentially deposited on the surface of the silicon substrate; The patterned photoresist layer is used as a mask to etch the interlayer dielectric layer and the silicon substrate, exposing the surface of the insulating dielectric layer.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, After forming the first groove, the process further includes: removing the patterned photoresist layer and cleaning.
4. The method for preparing a semiconductor structure according to claim 2, characterized in that, After exposing the metal wiring, the process further includes depositing a barrier layer in the first groove and the second groove, the barrier layer covering a first dielectric layer on the sidewall of the first groove, a second dielectric layer on the sidewall of the second groove, and the metal wiring at the bottom of the second groove.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The process further includes: depositing a seed layer on the surface of the barrier layer after forming the barrier layer.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, After forming the seed layer, the process further includes: electroplating a conductive material in the first groove and the second groove, wherein the conductive material fills the first groove and the second groove and covers the surface of the interlayer dielectric layer.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The conductive material is metallic copper.
8. The method for preparing a semiconductor structure according to claim 6, characterized in that, The process further includes: removing the conductive material located on the surface of the interlayer dielectric layer, as well as a portion of the interlayer dielectric layer, after depositing the conductive material.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After removing part of the interlayer dielectric layer, the thickness of the remaining interlayer dielectric layer is between 0.8 μm and 1.2 μm.
10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first dielectric layer is one or a combination of silicon oxide and silicon nitride, and the second dielectric layer is one or a combination of silicon oxide and silicon nitride.
11. A semiconductor structure, characterized in that, The semiconductor structure is formed by the method for preparing the semiconductor structure according to any one of claims 1 to 10.