Wafer level radio frequency module integration method and structure

Abstract

This invention discloses a wafer-level RF module integration method and structure. The method includes the following steps: S10: providing a mother wafer, wherein multiple mother dies are formed inside the mother wafer, and the surface of the mother wafer has a mother core metal electrode array; S20: providing a daughter die, wherein the surface of the daughter die has a daughter core metal electrode array, and the daughter core metal electrodes are made of different materials than the mother core metal electrodes, and one of the daughter die and the mother die is an RF device; S30: forming a transition metal electrode array on either the daughter die or the mother wafer; wherein the material of the transition metal electrodes is different from the material of the metal electrodes on the surface of the daughter die or the mother wafer on which the transition metal electrode array is formed, and they are electrically interconnected. This invention achieves highly reliable, low-loss connection of heterogeneous electrodes through transition metal electrodes and homogeneous metal growth process, and synergistically optimizes electrical, thermal, and magnetic properties, making it suitable for high-density heterogeneous integration systems such as 5G / 6G RF front-end modules.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and microelectronics integration technology, specifically to a wafer-level radio frequency module integration method suitable for three-dimensional heterogeneous integration, and a wafer-level radio frequency module manufactured by this method. Background Technology

[0002] With the rapid development of 5G / 6G communication, autonomous driving, and IoT technologies, radio frequency (RF) front-end modules are trending towards miniaturization, multifunctionality, and high performance. This typically requires high-density three-dimensional integration of RF device chips (such as power amplifiers, low-noise amplifiers, and switches) manufactured based on different semiconductor materials (such as Si, GaAs, and GaN) and process nodes with silicon-based digital baseband or control chips.

[0003] Existing mainstream integration technologies, such as flip-chip technology based on solder microbumps, face the following challenges: Material compatibility and interface reliability issues: Electrodes of RF device chips are typically made of gold-based materials (such as gold bumps), while electrodes of silicon-based chips are typically made of copper or aluminum. Direct gold-copper thermocompression bonding or solder connection can lead to stress under thermal cycling due to factors such as mismatched thermal expansion coefficients and the growth of intermetallic compounds at the interface, resulting in decreased connection reliability.

[0004] High-frequency performance limitations: Solder joints themselves have high resistance and parasitic inductance, and the shape of the solder joint is not easy to control, which is not conducive to the transmission of high-frequency signals and increases insertion loss.

[0005] Incompatible heat dissipation paths: Radio frequency devices, especially power amplifiers, generate a large amount of heat during operation. In traditional conductive interconnect structures, the heat dissipation path is often separated from the electrical signal path, resulting in high thermal resistance in the vertical direction, which cannot meet the heat dissipation requirements of high power density chips.

[0006] Electromagnetic interference issues: Radio frequency signals are susceptible to interference, and effective shielding needs to be considered in the integrated structure.

[0007] Therefore, there is an urgent need for a new wafer-level integration method that can achieve highly reliable, low-loss conductive interconnection of heterogeneous material electrodes, while simultaneously optimizing electrical, thermal, and electromagnetic properties. Summary of the Invention

[0008] This invention aims to overcome the aforementioned deficiencies of the prior art and provide a wafer-level RF module integration method and structure. This invention particularly focuses on solving the problems of electrothermal synergy design and process compatibility in high-density conductive interconnection of different types of chips in systems such as RF front-end modules and millimeter-wave antenna arrays.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: A wafer-level radio frequency module integration method includes the following steps: S10: Provide a master wafer, wherein multiple master cores are formed inside the master wafer, and the surface of the master wafer has a master core metal electrode array; S20: Provide a sub-core, the surface of which has a sub-core metal electrode array, and the sub-core metal electrodes and the mother core metal electrodes are made of different materials, wherein one of the sub-core and the mother core is a radio frequency device; S30: A transition metal electrode array is formed on either the sub-core or the mother wafer; wherein the material of the transition metal electrode is different from the material of the metal electrode on the surface of the sub-core or the mother wafer on which the transition metal electrode array is formed, and they are electrically interconnected. S40: Vertically bond the sub-core particles to the mother wafer, such that the transition metal electrode array is perpendicularly opposite to the sub-core metal electrode array or the mother core metal electrode array on the opposite side; wherein, the material of the transition metal electrode is the same as the material of the metal electrode perpendicularly opposite on the opposite side. S50: Simultaneously grow a metal of the same material as the transition metal electrode on the surface of the transition metal electrode array and the vertically opposite metal electrode array to form metal bumps until the transition metal electrode and the vertically opposite metal electrode are electrically interconnected.

[0010] Preferably, step S30 further includes: A metal transfer layer is formed on either the sub-core and the mother wafer, which is electrically interconnected with the surface metal electrode array; An insulating layer is formed on the metal adapter layer; The insulating layer is etched to expose the position opposite to the metal electrode that will be perpendicular to it, which will serve as the transition metal electrode.

[0011] Preferably, step S30 further includes: A metal heat dissipation layer is formed simultaneously with the metal adapter cable. The metal heat dissipation layer and the metal adapter cable are located on the same layer and are non-conductively interconnected.

[0012] Preferably, step S30 includes: Transition metal electrodes are formed on the mother core metal electrode array or the daughter core metal electrode array, and each metal electrode corresponds to a metal electrode.

[0013] Preferably, the bonding process in step S40 uses a bonding material containing metal.

[0014] Preferably, a back electrode is formed on the back side of the mother wafer or the sub-core.

[0015] Preferably, the sub-core is disposed on a sub-wafer.

[0016] A wafer-level radio frequency module formed according to the above-described wafer-level radio frequency module integration method includes: A master wafer, wherein multiple master cores are formed inside the master wafer, and a master core metal electrode array is formed on the surface of the master wafer; A sub-core and a mother wafer are stacked together. The surface of the sub-core has a sub-core metal electrode array, and the sub-core metal electrodes and the mother core metal electrodes are made of different materials. One of the sub-core and the mother core is a radio frequency device. A transition metal electrode array is disposed on the surface of the sub-core or the mother wafer and is electrically connected to the metal electrode array on the surface. The transition metal electrode array is perpendicular to the metal electrode array on the opposite side, and the material of the transition metal electrode is the same as that of the metal electrode on the opposite side. The vertically opposite transition metal electrodes and the opposite metal electrodes are electrically interconnected by an integrated metal bump made of the same metal material as both.

[0017] Preferably, a back electrode is formed on the back side of the mother wafer or the sub-core.

[0018] Preferably, the back electrode is formed on the back side of the chip where the radio frequency device is located, and the back electrode is configured to be connected to an external reference potential for noise reduction and heat dissipation.

[0019] Preferably, it further includes a partial electromagnetic insulating shell that extends from the surface of the mother core and surrounds at least one side of the daughter core, the partial electromagnetic insulating shell having an opening, and the back electrode being interconnected to the outside via a conductive plug formed in the opening.

[0020] Preferably, the sub-chip includes an RF device chip and a microcapacitor chip, and the parent chip is a logic device chip; the RF device chip and the microcapacitor chip are both bonded to the same parent chip; the microcapacitor chip is located on one side of the RF device chip and is electrically connected to the back electrode through a metal plug, and the system input / output port of the microcapacitor chip serves as the external input / output port of the wafer-level RF module.

[0021] Preferably, the core metal electrode on the front side of the mother wafer, which is conductively interconnected with the microcapacitor chip, is conductively interconnected with the external metal pad through a metal plug that penetrates the mother wafer.

[0022] The beneficial effects of this invention include: High-reliability conductive interconnects: By pre-forming transition electrodes with matching materials and using post-bonding homogeneous metal growth to form connections, problems caused by mismatched thermal expansion coefficients and intermetallic compound growth at heterogeneous metal interfaces are avoided, significantly improving the mechanical strength and long-term reliability of conductive interconnects.

[0023] Excellent high-frequency performance: The connector formed by the same metal material has low resistivity and a pure interface. Furthermore, through selective growth, it can form bumps with regular shape and controllable size, which effectively reduces parasitic resistance and inductance, and is beneficial for high-frequency signal transmission.

[0024] Electrothermal co-design: It enables the simultaneous fabrication of a metal heat dissipation layer and a local electromagnetic insulation shell in the same process step as forming the metal adapter wire, realizing the integrated design of electrical conductive interconnection, thermal management and electromagnetic shielding, and optimizing system-level performance.

[0025] Good process compatibility: The method is based on mature wafer-level thin film deposition, photolithography, electroplating and electroless plating processes, which are easy to implement and integrate in existing semiconductor production lines. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the wafer-level radio frequency module integration method according to Embodiment 1 of the present invention.

[0028] Figures 2 to 6 This is a schematic diagram of the wafer-level radio frequency module integration method of the present invention; Figure 7 This is a schematic cross-sectional view of the wafer-level radio frequency module according to Embodiment 2 of the present invention; Figure 8 This is a schematic cross-sectional view of the wafer-level radio frequency module according to Embodiment 3 of the present invention.

[0029] Label Explanation: 100: Mother wafer; 101: Mother core; 102: Mother core metal electrode; 104: Metal transition line; 105: Transition metal electrode; 20: Sub-core; 22: Sub-core metal electrode; 202: Back electrode; 203: Partial electromagnetic insulation shell; 32: Metal thermally conductive structure; 42: Metal bonding ring; 43: Metal pad; 61: Metal bump. Detailed Implementation

[0030] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0031] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. This invention pertains to electrical devices; therefore, connections and conductive interconnects refer to conductive interconnects. Since the accompanying drawings describe the same device, the same reference numerals denote the same components. The term "chip front" as used herein refers to the side of the wafer used to form the device during chip manufacturing, and "back" refers to the substrate side of the wafer.

[0032] Example 1

[0033] refer to Figure 1 This embodiment provides a wafer-level radio frequency module integration method, including the following steps: S10: Provide a master wafer, wherein multiple master cores are formed inside the master wafer, and the surface of the master wafer has a master core metal electrode array; refer to Figure 2 The mother wafer 100 includes a semiconductor substrate, which is silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. In this embodiment, an 8-inch silicon-based mother wafer 100 is specifically provided, which integrates multiple CMOS mother chips 101 as digital control units via through-silicon via (TSV) technology. The surface of the mother chip 101 has a mother metal electrode array, which can be composed of exposed aluminum pads on an aluminum conductive interconnect layer or the top of exposed TSVs. Semiconductor devices, such as MOSFETs, MEMS, or other functional devices, are fabricated within the chip. Therefore, for signal input and output, signals are transmitted to the surface through TSVs at the device ports. During manufacturing or packaging, pads or other electrode structures can be formed on the TSVs for conductive interconnection of signals.

[0034] The mother wafer 100 can be an uncut silicon wafer that has undergone integrated circuit manufacturing, or a reconstructed wafer formed by temporarily bonding multiple mother cores 101 to other carrier wafers. Each mother core 101 has a mother core metal electrode 102 on its surface, and the surface with the mother core metal electrode 102 is the bonding surface. The mother wafer 100 serves to support the multiple mother cores 101, thereby facilitating subsequent processes and improving their operability. Furthermore, the temporary bonding method also facilitates the subsequent separation of the mother cores 101 and the mother wafer 100. In this embodiment, the mother wafer 100 is a carrier wafer.

[0035] The parent chip 101 is used as the chip to be integrated in a wafer-level system-on-a-package (WAPS). It should be noted that the wafer-level packaging method in this embodiment is used to achieve heterogeneous integration; therefore, the multiple parent chips 101 are chips made of silicon wafers. In other embodiments, the parent chip 101 can also be a chip made of other materials. The functions of the multiple parent chips 101 can be different. The parent chip 101 can be one or more of the following: active components, passive components, microelectromechanical systems (MEMS), optical components, etc. Specifically, the parent chip 101 can be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the parent chip 101 can also be other functional chips. In this embodiment, the wafer-level system-on-a-package (WAPS) is used to combine multiple parent chips 101 with different functions into a single package structure; therefore, the multiple parent chips 101 are obtained by dicing multiple wafers of different functional types. In other embodiments, depending on actual process requirements, the functional types of the multiple parent chips 101 can also be the same. By integrating multiple master chips 101 into the master wafer 100 and completing the packaging integration process on the master wafer 100, the packaging structure area can be significantly reduced, manufacturing costs can be reduced, electrical performance can be optimized, and batch manufacturing can be achieved, which can significantly reduce workload and equipment requirements.

[0036] It should also be noted that, for ease of illustration, this embodiment uses three mother core particles 101 as an example. However, the number of mother core particles 101 is not limited to three.

[0037] S20: Provide a sub-core, the surface of which has a sub-core metal electrode array, and the sub-core metal electrodes and the mother core metal electrode 102 are made of different materials, and one of the sub-core and the mother core is a radio frequency device.

[0038] refer to Figure 3The system provides a sub-core 20 with completed front-end processing. The sub-core 20 can be, for example, a high-power RF amplifier core manufactured using III-V compound semiconductor technology. On its active surface, a sub-core metal electrode array composed of sub-core metal electrodes 22 is formed through a final passivation layer aperture and rewiring process. The material of the sub-core metal electrodes 22 is typically copper or aluminum, but for high-power RF amplifiers it can also be gold, and the surface may have a thin layer to prevent oxidation (such as titanium nitride or tantalum). Simultaneously, in the non-electrode regions of the sub-core 20, a polymer bonding layer (such as polyimide PI or benzocyclobutene BCB) can be pre-formed, with a thickness slightly higher than the sub-core metal electrodes 22, exposing the top of the electrodes. The sub-core can be a pre-cut core, an uncut core located on a wafer, or a core located on a carrier wafer after reconstruction.

[0039] In this embodiment, sub-chips are uncut chips located on a wafer fabricated using integrated circuit manufacturing technology. For example, N-type metal-oxide-semiconductor (NMOS) devices and P-type metal-oxide-semiconductor (PMOS) devices are formed on a semiconductor substrate through processes such as deposition and etching. Dielectric layers, metal conductive interconnect structures, and electrodes electrically connected to the metal conductive interconnects are formed on these devices, resulting in multiple sub-chips 20 within the wafer. These multiple sub-chips 20 can be chips of the same or different types. Alternatively, sub-chips can also be multiple different types of chips located on a reconstructed wafer, such as radio frequency device chips, microcapacitor chips, or control logic chips.

[0040] The sub-core metal electrode 22 on the surface of the sub-core 20 is used to realize the electrical connection between the sub-core 20 and other circuits. In this embodiment, the sub-core metal electrode 22 can be a bond pad, or it can be a through-silicon via without a bond pad, a metal conductive interconnect structure, or an exposed metal conductive interconnect lead.

[0041] In this embodiment, a diced but not cleaved GaN high electron mobility transistor wafer is provided as a sub-core 20, which is an RF power amplifier. Gold bumps are fabricated on its surface as a sub-core metal electrode array 22. The mother core metal electrode 102 (aluminum) and the sub-core metal electrode 22 (gold) are made of different materials.

[0042] Since this invention utilizes in-situ growth of metal on a metal seed layer, the mother core metal electrode 102 and the daughter core metal electrode are made of different materials and have significant differences, which makes it impossible to directly and well grow and form a connection. Therefore, in this invention, a transition metal layer is pre-formed as a transition metal electrode to facilitate subsequent good conductive interconnection.

[0043] S30: A transition metal electrode array is formed on either the sub-core or the mother wafer; wherein the material of the transition metal electrode is different from the material of the metal electrode on the surface of the sub-core or the mother wafer on which the transition metal electrode array is formed, and they are electrically interconnected.

[0044] For details, please refer to Figure 4 Patterning is performed on the surface of the mother wafer 100. A transition metal electrode 105 is fabricated on the mother core metal electrode 102 by sputtering and photolithography. Specifically, the material of the transition metal electrode 105 is different from that of the mother core metal electrode 102, but the material of the transition metal electrode 105 is the same as that of the daughter core metal electrode 22. In this embodiment, the material of the mother core metal electrode 102 is aluminum, the material of the daughter core metal electrode 22 is gold, tantalum, or nickel, and the material of the transition metal electrode is gold, nickel, or tantalum. When the daughter core metal electrode is gold (Au), the transition metal electrode is preferably gold; when the daughter core metal electrode is copper (Cu), the transition metal electrode can be nickel (Ni) or gold. The material selection of the transition metal electrode is based on the principle of ensuring that it can achieve high-quality connection with the opposite electrode through homogeneous metal growth.

[0045] In one embodiment, in this step, two functional structures can be simultaneously formed through a single patterned metal deposition process: Metal adapter cable 104: Its pattern is designed to cover and electrically connect to the sub-core metal electrode 22 as a horizontal extension of the wiring for signal, power and ground.

[0046] Metal thermally conductive structure 32: Its pattern design is located on the same metal layer as the metal adapter wire 104, but is physically insulated from it. This structure is not a simple planar pattern, but a grid-like or solid pattern pre-planned to cover the projection area of ​​high-power units (such as power amplifiers) in the future sub-core 20, laying the foundation for vertical heat dissipation paths.

[0047] Specific process: Vapor deposition combined with etching can be used, for example, on aluminum materials; or photolithography and vapor deposition can be used, for example, on copper materials; or electroplating or electroless plating can also be used. First, a seed layer (such as Ti / Cu copper) is deposited on the entire surface of the mother wafer 100. Then, photoresist is spin-coated and exposed to form a mask that simultaneously defines the metal transition lines 104 and the metal thermal conductivity structure 32. Subsequently, electroplating is performed to thicken the mask (e.g., electroplating copper to 5-10 μm). Finally, the photoresist and the underlying seed layer are removed to obtain the isolated metal structure.

[0048] Through the above steps, the metal adapter 104 connects a portion of the mother core metal electrode 102 to the area below the corresponding transition metal electrode 105. The position of the transition metal electrode 105 is precisely designed to correspond perpendicularly to the daughter core metal electrode 22 on the daughter core granule 20. Simultaneously with the formation of the metal adapter 104, a metal heat dissipation structure 32 is formed in the non-conductive interconnect region and the bonding region, enhancing heat dissipation and facilitating alignment. This also allows the position of the transition metal electrode to be moved from the position of the mother core metal electrode 102 to a position perpendicularly corresponding to the daughter core metal electrode. The transition metal electrode is then formed on the metal adapter 104 at the position corresponding to the daughter core metal electrode. However, this approach is optional and does not constitute a limitation of the present invention.

[0049] In another embodiment, a metal transition line 104 is formed covering the mother core metal electrode 102. The metal transition line 104 is electrically interconnected with the transition metal electrode 105. The metal transition line 104 and the transition metal electrode 105 are located in the same layer, that is, the metal transition line 104 is formed at the same time as the transition metal electrode 105, and the two are electrically interconnected and made of the same material. In addition, an insulating metal thermally conductive structure 32 can also be formed at the same time. For example, step S30 further includes: forming a metal transition line layer electrically interconnected with the surface metal electrode array on either the sub-core 20 or the mother wafer 100; forming an insulating layer on the metal transition line layer; etching the insulating layer to expose the position opposite to the metal electrode to be perpendicularly corresponding as the transition metal electrode 105.

[0050] S40: The sub-core particles are vertically bonded to the mother wafer, and the electrodes of the sub-core metal electrode array and the transition metal electrode array are vertically aligned.

[0051] For details, please refer to Figure 5 A hot-press bonding process is used to align and press the sub-core 20, with its active surface facing down, onto the mother wafer 100. The bonding process uses a metal-containing bonding material. The bonding material is a metal bonding ring 42 (such as gold-tin eutectic solder or copper) pre-placed in the non-electrode region of the sub-core 20 or the mother wafer 100. After bonding, the sub-core metal electrode 22 and the transition metal electrode 105 are perpendicularly aligned, with a small gap between them.

[0052] In this embodiment, a bonding layer is also formed on the surface of the sub-core.

[0053] Optionally, a metal bonding ring 42 can be formed simultaneously with the formation of the transition metal electrode, thereby saving process steps.

[0054] In one embodiment, since a metal material is used for bonding, an insulating dielectric ring is formed on the outside of the metal bonding ring 42 to prevent crosstalk.

[0055] S50: Simultaneously grow a metal of the same material as the transition metal electrode on the surfaces of the transition metal electrode array and the vertically opposite metal electrode array to form metal bumps 61 until the transition metal electrode and the vertically opposite metal electrode are electrically interconnected.

[0056] For details, please refer to Figure 6 The bonded monolithic structure is immersed in a chemical gold plating solution. Gold ions are selectively reduced and deposited on the surfaces of the gold electrodes (core metal electrode 22 and transition metal electrode 105). As the gold grows outward simultaneously from the surfaces of the upper and lower electrodes, they meet and fuse in the gap to form an integral metal bump 61, thereby achieving a low-resistance, highly reliable electrical connection.

[0057] Process preparation: The bonded integral structure is immersed in a chemical plating solution. This plating solution can be a chemical gold plating solution or a chemical nickel plating solution. Due to their metallic properties, the surfaces of the core metal electrode 22 of the core particle 20 and the transition metal electrode 105 of the mother wafer 100 can serve as catalytically active surfaces.

[0058] Selective growth: Metal ions in the electroless plating solution are reduced and deposited only on the catalytically active metal surface (i.e., the exposed tips of the core metal electrode and the transition metal electrode).

[0059] Bridging conduction: Metal grows outward simultaneously from the surfaces of the core metal electrode and the transition metal electrode. Due to the small gap, the metals growing on both sides quickly meet and merge in the gap, eventually forming a complete, low-resistance metal bump 61, which firmly and electrically connects the two.

[0060] Example 2

[0061] refer to Figure 7 Accordingly, the present invention also provides a wafer-level radio frequency module, comprising: A mother wafer 100, wherein multiple mother cores 101 are formed inside the mother wafer 100, and a mother core metal electrode array is provided on the surface of the mother wafer 100; Sub-core 20 and mother wafer 100 are stacked together. The surface of sub-core 20 has a sub-core metal electrode array, and the sub-core metal electrode 22 and mother core metal electrode 102 are made of different materials. One of the sub-core 20 and the mother core 101 is a radio frequency device. A transition metal electrode array is disposed on the surface of the sub-core 20 or the mother wafer 100 and is electrically connected to the metal electrode array on the surface. The transition metal electrode array is perpendicular to the metal electrode array on the opposite side, and the material of the transition metal electrode 105 is the same as that of the metal electrode on the opposite side. The vertically opposite transition metal electrodes 105 and the opposite metal electrodes are electrically interconnected by an integrated metal bump 61 made of the same metal material as both.

[0062] Example 3

[0063] This embodiment demonstrates a more complex radio frequency module that integrates electrical, thermal, and magnetic co-design.

[0064] In this embodiment, the electroplating pattern design is more complex: in addition to the metal adapter 104 and the transition metal electrode 105, a patterned metal thermal conductive structure 32 is also formed in the same copper metal layer. The metal thermal conductive structure 32 can be located in the bonding region as a bonding layer and heat dissipation layer, or located in the non-conductive interconnection region, insulated from the electrode, and used only for heat dissipation.

[0065] Prior to S30, a back electrode 202 was fabricated on the back side of the substrate of the sub-core 20 (GaN RF device). The back electrode 202 also serves as a metal heat dissipation layer, located in the back projection area of ​​the power transistor unit in the sub-core 20. Regarding the back and front sides of the core, in this embodiment, the bonding surface between the sub-core 20 and the parent core 101 is the front side, where the device and electrodes are formed; the back side refers to the substrate side of the wafer. Specifically, after bonding the sub-core 20 to the parent wafer 100, the back electrode 202 can be exposed through molding and grinding, and a thick metal layer can be deposited on it as a local electromagnetic insulation shell 203. This local electromagnetic insulation shell 203 simultaneously serves as electromagnetic shielding and conducts heat upwards, and can also surround the sub-core 20, effectively isolating the high-frequency sub-core 20. Specifically, metal sidewalls can be formed before bonding the sub-core 20.

[0066] In one embodiment, the back electrode 202 is formed on the back side of the chip where the radio frequency device is located. The back electrode is configured to be connected to an external reference potential for noise reduction and heat dissipation.

[0067] In one embodiment, a partial electromagnetic insulating shell 203 is further included, which extends from the surface of the mother core and surrounds at least the side of the daughter core, the back electrode 202 having an opening, and the partial electromagnetic insulating shell 203 being interconnected to the outside via conductive plugs formed in the opening.

[0068] In one embodiment, the sub-chip 20 includes an RF device chip and a microcapacitor chip, and the parent chip 101 is a logic device chip. Both the RF device chip and the microcapacitor chip are bonded to the same parent chip 101. The microcapacitor chip is located on one side of the RF device chip and is electrically connected to the back electrode 202 via a metal plug. The system input / output port of the microcapacitor chip serves as the external input / output port of the wafer-level RF module. The gaps between the sub-chips 20 on the parent chip 101 can be filled with a dielectric material, formed by laser-drilling holes in the dielectric and filling them with metal to create metal plugs. To avoid externalizing the capacitor array in the RF device chip as a sub-chip, for example, HR IPD (High-Resistance Integrated Passive Device) sub-chips with vertical conductive interconnection to the silicon wafer, the large-area microcapacitor array in SOI CMOS (Silicon-on-Insulator Complementary Metal-Oxide Semiconductor) can be externalized. Utilizing the extremely low processing cost of HR IPD, the cost of SOI CMOS can be reduced. The vertically bonded conductive interconnects are extremely short, and the external microcapacitor array in SOI CMOS does not affect chip performance.

[0069] In one embodiment, the core metal electrode 102 on the front side of the mother wafer 100, which is conductively interconnected with the microcapacitor chip, is conductively interconnected with the external metal pad 43 through a metal plug penetrating the mother wafer 100. This structure achieves high-fidelity signal transmission, efficient heat dissipation, and effective shielding of the radio frequency circuit, resulting in excellent overall performance.

[0070] The core of this invention lies in pre-forming a "transition electrode" of the same material as the sub-core electrode on the electrode of the mother wafer, and then achieving a perfect connection between metals of the same material through a selective metal growth process after bonding, thereby significantly improving the reliability and high-frequency performance of conductive interconnects. Simultaneously, this method collaboratively constructs conductive interconnects and heat dissipation / shielding structures in the same process layer, achieving electrothermal synergistic design.

[0071] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A wafer-level radio frequency module integration method, characterized in that, Including the following steps: S10: Provide a master wafer, wherein multiple master cores are formed inside the master wafer, and the surface of the master wafer has a master core metal electrode array; S20: Provide a sub-core, the surface of which has a sub-core metal electrode array, and the sub-core metal electrodes and the mother core metal electrodes are made of different materials, wherein one of the sub-core and the mother core is a radio frequency device; S30: A transition metal electrode array is formed on either the sub-core or the mother wafer; wherein the material of the transition metal electrode is different from the material of the metal electrode on the surface of the sub-core or the mother wafer on which the transition metal electrode array is formed, and they are electrically interconnected. S40: Vertically bond the sub-core particles to the mother wafer, such that the transition metal electrode array is perpendicularly opposite to the sub-core metal electrode array or the mother core metal electrode array on the opposite side; wherein, the material of the transition metal electrode is the same as the material of the metal electrode perpendicularly opposite on the opposite side; S50: Simultaneously grow a metal of the same material as the transition metal electrode on the surfaces of the transition metal electrode array and the vertically opposite metal electrode array to form metal bumps until the transition metal electrode and the vertically opposite metal electrode are electrically interconnected.

2. The wafer-level RF module integration method as described in claim 1, characterized in that, Step S30 also includes: A metal transfer layer is formed on either the sub-core and the mother wafer, which is electrically interconnected with the surface metal electrode array; An insulating layer is formed on the metal adapter layer; The insulating layer is etched to expose the position opposite to the metal electrode that will be perpendicular to it, which will serve as the transition metal electrode.

3. The wafer-level RF module integration method as described in claim 2, characterized in that, Step S30 also includes: A metal heat dissipation layer is formed simultaneously with the metal adapter cable. The metal heat dissipation layer and the metal adapter cable are located on the same layer and are non-conductively interconnected.

4. The wafer-level RF module integration method as described in claim 1, characterized in that, Step S30 includes: Transition metal electrodes are formed on the mother core metal electrode array or the daughter core metal electrode array, and each metal electrode corresponds to a metal electrode.

5. The wafer-level RF module integration method as described in claim 1, characterized in that, The bonding process in step S40 uses a bonding material containing metal.

6. The wafer-level RF module integration method as described in claim 1, characterized in that, A back electrode is formed on the back side of the mother wafer or the sub-core.

7. The wafer-level RF module integration method as described in claim 1, characterized in that, The sub-core is disposed on the sub-wafer.

8. A wafer-level radio frequency module formed by a wafer-level radio frequency module integration method according to any one of claims 1 to 7, characterized in that, include: A master wafer, wherein multiple master cores are formed inside the master wafer, and a master core metal electrode array is formed on the surface of the master wafer; A sub-core and a mother wafer are stacked together. The surface of the sub-core has a sub-core metal electrode array, and the sub-core metal electrodes and the mother core metal electrodes are made of different materials. One of the sub-core and the mother core is a radio frequency device. A transition metal electrode array is disposed on the surface of the sub-core or the mother wafer and is electrically connected to the metal electrode array on the surface. The transition metal electrode array is perpendicular to the metal electrode array on the opposite side, and the material of the transition metal electrode is the same as that of the metal electrode on the opposite side. The vertically opposite transition metal electrodes and the opposite metal electrodes are electrically interconnected by an integrated metal bump made of the same metal material as both.

9. The wafer-level radio frequency module as described in claim 8, characterized in that, A back electrode is formed on the back side of the mother wafer or the sub-core.

10. The wafer-level radio frequency module as described in claim 9, characterized in that, The back electrode is formed on the back side of the chip where the radio frequency device is located. The back electrode is configured to be connected to an external reference potential for noise reduction and heat dissipation.

11. The wafer-level radio frequency module as described in claim 10, characterized in that, It also includes a partial electromagnetic insulating shell that extends from the surface of the mother core and surrounds at least the side of the daughter core, the partial electromagnetic insulating shell having an opening, and the back electrode being interconnected to the outside via a conductive plug formed in the opening.

12. The wafer-level radio frequency module as described in claim 11, characterized in that, The sub-chip includes an RF device chip and a microcapacitor chip, and the parent chip is a logic device chip; the RF device chip and the microcapacitor chip are both bonded to the same parent chip; the microcapacitor chip is located on one side of the RF device chip and is electrically connected to the back electrode through a metal plug, and the system input / output port of the microcapacitor chip serves as the external input / output port of the wafer-level RF module.

13. The wafer-level radio frequency module as described in claim 12, characterized in that, The master core metal electrode on the front side of the master wafer, which is conductively interconnected with the microcapacitor chip, is conductively interconnected with the external metal pad through a metal plug that penetrates the master wafer.

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