A semiconductor device and a manufacturing method thereof

Abstract

A semiconductor device and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate having an interlayer dielectric layer formed thereon; etching the interlayer dielectric layer to form a contact hole penetrating through the interlayer dielectric layer; filling a conductive layer in the contact hole; depositing a filling dielectric layer to fill the contact hole not filled by the conductive layer; performing a planarization process to remove the filling dielectric layer and the conductive layer above the interlayer dielectric layer until the interlayer dielectric layer is exposed and the conductive layer, the filling dielectric layer and an upper surface of the interlayer dielectric layer are flush. The application can improve the reliability of the device by filling the contact hole with the filling dielectric layer and performing the planarization process to form a flat surface.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In BCD (Bipolar-CMOS-DMOS) technology, to balance high breakdown voltage and low on-resistance, laterally diffused metal-oxide-semiconductor (LDMOS) devices often employ a contact field plate (CFP) structure. The CFP structure forms a field plate contact hole on the gate side and fills the contact hole with a conductive material (such as tungsten) as a field electrode. The field electrode is isolated from the semiconductor substrate by an insulating dielectric layer, thereby modulating the surface electric field distribution and improving the device's breakdown voltage.

[0003] As device dimensions continue to shrink, the field contact holes in CFP structures typically have large widths. After filling the field contact holes with conductive materials such as tungsten, the surface of the filled layer is prone to depressions due to the limited step coverage capability of the deposition process. Even with subsequent chemical mechanical polishing (CMP), it is difficult to obtain a completely flat surface. This unevenness further affects the subsequent inter-metal deposition process, resulting in an uneven surface for the inter-metal layer as well. This has a serious negative impact on the performance and reliability of semiconductor chips, such as potentially causing signal instability, electron migration, and other problems, thereby reducing chip yield and lifespan. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising: A semiconductor substrate is provided, on which an interlayer dielectric layer is formed; The interlayer dielectric layer is etched to form contact holes that penetrate the interlayer dielectric layer; A conductive layer is filled into the contact hole; A filling dielectric layer is deposited to fill the contact holes that were not filled by the conductive layer; A planarization process is performed to remove the filling dielectric layer and the conductive layer located above the interlayer dielectric layer until the interlayer dielectric layer is exposed, and the conductive layer, the filling dielectric layer and the upper surface of the interlayer dielectric layer are flush.

[0006] In one embodiment, the contact hole includes a first contact hole and a second contact hole, the size of the second contact hole is smaller than the size of the first contact hole, the conductive layer fills the second contact hole but does not fill the first contact hole, and the filling dielectric layer fills the first contact hole.

[0007] In one embodiment, the first contact hole includes a field plate contact hole that exposes a field plate dielectric layer, a gate structure is formed on the semiconductor substrate, and the field plate dielectric layer extends from the top of the gate structure to the surface of the semiconductor substrate.

[0008] In one embodiment, the second contact hole includes a conventional contact hole that is electrically connected to the gate structure or the semiconductor substrate.

[0009] In one embodiment, after performing the planarization process, a metal interconnect layer is further formed on the interlayer dielectric layer.

[0010] In one embodiment, the material of the filling dielectric layer includes a transparent material, which includes silicon oxide; The conductive layer is made of tungsten.

[0011] In one embodiment, the thickness of the filling dielectric layer is greater than the thickness of the conductive layer.

[0012] Another aspect of this application provides a semiconductor device, including: A semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate; Contact holes penetrating the interlayer dielectric layer; A conductive layer filling the contact hole; A filling dielectric layer is formed on the conductive layer, the filling dielectric layer fills the contact holes that are not filled by the conductive layer, and the upper surfaces of the conductive layer, the filling dielectric layer and the interlayer dielectric layer are flush.

[0013] In one embodiment, the contact hole includes a first contact hole and a second contact hole, the size of the second contact hole is smaller than the size of the first contact hole, the conductive layer fills the second contact hole but does not fill the first contact hole, and the filling dielectric layer fills the first contact hole.

[0014] In one embodiment, the first contact hole includes a field plate contact hole that exposes a field plate dielectric layer, a gate structure is formed on the semiconductor substrate, and the field plate dielectric layer extends from the top of the gate structure to the surface of the semiconductor substrate.

[0015] According to the semiconductor device and manufacturing method provided in the embodiments of this application, by filling the contact holes with a filling dielectric layer and performing a planarization process to form a flat surface, the unevenness of the conductive layer after filling and the unevenness of the subsequent metal interconnect layer deposition caused by deep and large contact holes can be avoided, thereby improving the performance and reliability of the semiconductor device. At the same time, it avoids the burden on the subsequent CMP process due to the excessive thickness of the conductive layer, as well as the impact on the recognition of photolithography alignment marks. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0017] In the attached image: Figures 1A-1D A cross-sectional view of a semiconductor device is shown during an implementation of a semiconductor device manufacturing method in the related art. Figure 1E A schematic diagram is shown of defects caused by incomplete filling of the conductive layer in related technologies; Figure 1F It shows Figure 1E A magnified view of the defect at position A in the middle; Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown; Figures 3A-3E A cross-sectional view of a semiconductor device is shown during the implementation of a semiconductor device manufacturing method according to an embodiment of this application. Detailed Implementation

[0018] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0019] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] like Figures 1A-1D As shown, when forming the field plate structure, firstly as... Figure 1A As shown, a semiconductor substrate 100 is provided, a gate structure 101 is formed on the semiconductor substrate 100, and a field plate dielectric layer 102 covering one side of the gate structure 101 is formed; then an interlayer dielectric layer 103 is formed, and the interlayer dielectric layer 103 is etched to form a field plate contact hole 104, and a conventional contact hole 105 may also be formed; then, as Figure 1B As shown, a conductive layer 106 is filled into the field plate contact hole 104 and the conventional contact hole 105. Because the field plate contact hole 104 is relatively large, the conductive layer 106 cannot completely fill it, leaving a groove in its center. Next, as... Figure 1C As shown, chemical mechanical polishing is performed to remove the excess conductive layer 106 above the interlayer dielectric layer 103. After polishing, grooves remain in the contact holes 104 of the field plate. Next, as... Figure 1D As shown, a metal interconnect layer 107 is formed above the interlayer dielectric layer 103. The presence of the grooves causes bubbles to form in the metal interconnect layer 107, affecting the flatness of the metal interconnect layer and the interlayer dielectric layer. This can lead to photoresist entering the groove area, affecting product reliability, or etchant entering the bubble area and causing etching inside. Figure 1E and Figure 1F The defect caused by the groove is shown, in which Figure 1E The circles represent the locations of defects. Figure 1F for Figure 1E A magnified view of the defect at position A in the middle.

[0025] To address the above problems, embodiments of this application provide a semiconductor device and a method for manufacturing the same. For example... Figure 2 As shown, the manufacturing method mainly includes the following steps: Step S201: Provide a semiconductor substrate, on which an interlayer dielectric layer is formed; Step S202: Etch the interlayer dielectric layer to form a contact hole that penetrates the interlayer dielectric layer; Step S203: Fill the contact hole with a conductive layer; Step S204: Deposit a filling dielectric layer to fill the contact holes that were not filled by the conductive layer; Step S205: Perform a planarization process to remove the filler dielectric layer and conductive layer located above the interlayer dielectric layer until the interlayer dielectric layer is exposed, and make the conductive layer, filler dielectric layer and upper surface of the interlayer dielectric layer flush.

[0026] According to the semiconductor device and manufacturing method provided in the embodiments of this application, by filling the contact holes with a filling dielectric layer and performing a planarization process to form a flat surface, unevenness of the subsequently formed metal interconnect layer can be avoided.

[0027] Below, for reference Figures 3A to 3E The method for fabricating the semiconductor device in this embodiment is described in detail.

[0028] First, such as Figure 3A As shown, a semiconductor substrate 300 is provided, and an interlayer dielectric layer 305 is formed on the semiconductor substrate 300.

[0029] The semiconductor substrate 300 can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, or a compound semiconductor substrate (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, etc.). In this embodiment, the semiconductor substrate 300 is a silicon substrate.

[0030] An active region and an isolation structure defining the active region are formed in a semiconductor substrate 300. The isolation structure can be a shallow trench isolation (STI) structure. Specifically, a patterned mask layer is formed on the semiconductor substrate. The semiconductor substrate is etched using the patterned mask layer as a mask to form isolation trenches. An isolation material (such as silicon oxide) is filled into the isolation trenches to form the isolation structure, and then the patterned mask layer is removed. The region isolated by the isolation structure is the active region. Subsequently, the structures required for semiconductor devices, such as well regions and drift regions, can be formed in the active region using an ion implantation process.

[0031] Next, a gate structure 301 is formed on the surface of the semiconductor substrate 300. The gate structure 301 is located on the active region. Exemplarily, the method for forming the gate structure 301 includes: firstly, forming a gate dielectric layer on the semiconductor substrate 300. The gate dielectric layer can be formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition, and its material can be silicon oxide, silicon oxynitride, or a high-k dielectric material. Then, forming a gate electrode layer on the gate dielectric layer. The gate electrode layer can be a polysilicon layer, a metal layer, or a combination thereof. Next, forming a patterned mask layer on the gate electrode layer, and using the patterned mask layer as a mask, etching the gate electrode layer and the gate dielectric layer to form the gate structure 301. Finally, removing the patterned mask layer.

[0032] Next, a gate sidewall 302 is formed on the sidewall of the gate structure 301. Specifically, a sidewall material layer is first deposited, covering the gate structure 301 and the semiconductor substrate 300. The sidewall material can be silicon oxide, silicon nitride, or a combination thereof. Then, the sidewall material layer is anisotropically etched to remove the horizontal sidewall material, leaving only the sidewall material on the sidewall of the gate structure 301, forming the gate sidewall 302. The gate sidewall 302 can be a single-layer structure or a multi-layer structure (such as a three-layer structure of silicon oxide-silicon nitride-silicon oxide). In this embodiment, the gate sidewall 302 is a stacked structure of silicon oxide and silicon nitride.

[0033] Next, source and drain regions are formed on both sides of the gate structure 301 by ion implantation. These regions are formed by ion implantation and then rapidly heated and annealed to activate doped impurities and simultaneously repair the lattice structure of the semiconductor substrate 300 surface damaged in each ion implantation process.

[0034] Next, a field plate dielectric layer 303 is formed, which extends from the top of the gate structure 301 to the surface of the semiconductor substrate 300 and covers the gate sidewall 302 on one side.

[0035] Specifically, a metal silicide barrier layer is first formed covering the gate structure 301 and the semiconductor substrate 300. In one embodiment, the metal silicide barrier layer is a stacked structure, including a silicon oxide layer and a silicon nitride layer stacked sequentially from bottom to top. Next, the metal silicide barrier layer is etched to remove the metal silicide barrier layer in the areas where the metal silicide layer needs to be formed, and a portion of the metal silicide barrier layer constitutes the field plate dielectric layer 303.

[0036] Next, a metal silicide process is performed to form a metal silicide layer 304 on the surface of the semiconductor substrate 300 and gate structure 301 exposed by the remaining metal silicide barrier layer after etching. The metal silicide layer 304 is used to reduce contact resistance and improve device performance. Specifically, a metal material, such as cobalt, nickel, titanium, or platinum, is first deposited on the entire semiconductor substrate 300. The deposition method can be a physical vapor deposition (PVD) process, such as sputtering. Then, an annealing process is performed to react the metal with silicon, forming metal silicide in the areas in contact with silicon. In the areas not in contact with silicon, i.e., covered by the remaining metal silicide barrier layer, the metal does not react. Then, a wet etching process is used to remove the unreacted metal.

[0037] Next, an interlayer dielectric layer 305 is formed. The interlayer dielectric layer 305 can be formed using a chemical vapor deposition process, and its material can be silicon oxide, a low-dielectric-constant material, etc. In this embodiment, the interlayer dielectric layer is a silicon oxide layer with a thickness greater than 5000 Å, for example, 6500 Å. After forming the interlayer dielectric layer, chemical mechanical polishing (CMP) can be performed to planarize the surface.

[0038] Next, the interlayer dielectric layer 305 is etched to form contact holes. These contact holes include a first contact hole and a second contact hole, with the second contact hole being smaller than the first contact hole. Specifically, the first contact hole can be a field plate contact hole 306, exposing the field plate dielectric layer 303. Exemplarily, the second contact hole can be a conventional contact hole 307, exposing the metal silicide layer 304.

[0039] Next, as Figure 3BAs shown, conductive material is deposited to form a conductive layer 308 within the field plate contact hole 306 and the conventional contact hole 307. The conductive material includes, but is not limited to, tungsten, and its deposition thickness can be set between 2000 Å and 4000 Å as needed. The conductive layer 308 within the field plate contact hole 306, together with the field plate dielectric layer 303, constitutes a contact field plate (CFP). The contact field plate is mainly used in laterally diffused metal-oxide-semiconductor (LDMOS) devices in BCD processes. It can control the electric field distribution on the device surface by applying an appropriate voltage, thereby reducing the electric field strength at the device edges. Under reverse bias conditions, the CFP attracts free carriers (such as electrons) in the semiconductor to the insulating layer interface, causing the electric field at the interface to be redistributed. Due to the presence of the floating field plate, the electric field lines on the device surface are stretched, resulting in a more uniform distribution of the field strength throughout the entire terminal region, avoiding the problem of excessively high local electric fields. Without a CFP, the breakdown voltage (BV) of a DMOS device cannot be reached. The uneven electric field between the gate and drain causes discharge at the corner where the gate contacts the gate oxide on the drain side. This results in an excessively high local electric field, which may lead to breakdown at a relatively low bias voltage. The floating field plate reduces the peak value of the surface electric field by adjusting the electric field distribution, allowing the device to withstand a higher reverse bias voltage, thereby improving the breakdown voltage.

[0040] Because the field plate contact hole 306 is relatively large, the conductive layer 308 is only formed on the bottom and sidewalls of the field plate contact hole 306, not completely filling it, thus forming a groove on the top of the field plate contact hole 306. In tungsten filling processes, deposition is usually stopped when the conventional contact hole 307 is completely filled to avoid increasing the burden on subsequent CMP processes, affecting the identification of photolithography alignment marks, and avoiding material waste caused by excessive tungsten deposition. Because the conventional contact hole 307 is relatively small, the top opening closes quickly during deposition, resulting in complete filling with no or minimal depressions. However, the field plate contact hole 306 is relatively large, and the top opening closes more slowly while the bottom and sidewalls are deposited, resulting in incomplete filling and leaving a groove in the middle.

[0041] Next, as Figure 3C As shown, a filling dielectric layer 309 is deposited to fill the contact holes not filled by the conductive layer 308. Exemplarily, the filling dielectric layer 309 completely fills the groove at the top of the field plate contact hole 306.

[0042] The filling dielectric layer 309 can be made of a transparent material, such as silicon oxide, to avoid affecting the identification of photolithographic alignment marks. Specifically, a chemical vapor deposition process is used to deposit a silicon oxide layer to fill the portion of the field plate contact hole 306 that is not filled by the conductive layer 308. The thickness of the filling dielectric layer 309 is greater than the thickness of the conductive layer 308 to ensure complete filling of the groove. During the deposition process, silane (SiH4) and oxygen (O2) are used as reactant gases. Under preset temperature (e.g., 400℃-600℃) and pressure (e.g., 1 Torr - 10 Torr) conditions, silane and oxygen undergo a chemical reaction to deposit a layer of silicon oxide on the surface of the field plate contact hole 306 filled with the conductive layer 308 and the interlayer dielectric layer 305. The deposition thickness is controlled between 4000 Å and 7000 Å according to actual requirements.

[0043] Next, as Figure 3D As shown, a planarization process is performed to remove the filling dielectric layer 309 and the conductive layer 308 located above the interlayer dielectric layer 305 until the interlayer dielectric layer 305 is exposed, and the conductive layer 308 and the filling dielectric layer 309 are flush with the upper surface of the interlayer dielectric layer 305.

[0044] Specifically, the semiconductor structure with the deposited dielectric layer 309 is placed on a chemical mechanical polishing (CMP) apparatus, and a suitable polishing pad and polishing slurry are selected. The polishing slurry typically contains abrasives (such as cerium dioxide or colloidal silica), oxidants (such as iron compounds or hydrogen peroxide), and additives. During the polishing process, the polishing pressure can be controlled at 1.03 N / cm. 2 Up to 4.14 N / cm 2 The grinding disc rotates at 60 rpm to 400 rpm, and the grinding fluid flow rate is 150 ml / min to 500 ml / min. The grinding time can be controlled according to the grinding rate. The grinding rates of the conductive layer 308 and the interlayer dielectric layer 305 are different. After a certain grinding time, the upper surface of the interlayer dielectric layer 305 is exposed, and a smooth surface is finally obtained, which meets the smoothness requirements of subsequent intermetallic dielectric deposition.

[0045] Next, as Figure 3E As shown, a metal interconnect layer 310 is formed over the interlayer dielectric layer 305, the filling dielectric layer 309, and the conductive layer 308. Exemplarily, an interlayer dielectric layer, made of silicon oxide, is deposited on a planar surface after CMP using a chemical vapor deposition (CVD) process. Next, trenches or vias for metal interconnects are etched into the interlayer dielectric layer using photolithography and etching processes. Then, a metal layer is filled into the trenches or vias. Because the metal interconnect layer is formed on the planar surface obtained in the previous steps, the dielectric layer can be precisely deposited and photolithography performed, ultimately forming a high-quality metal interconnect layer 310.

[0046] In summary, the semiconductor device manufacturing method of this application, by filling the contact holes with a dielectric layer and performing a planarization process to form a flat surface, can avoid the problems of unevenness after the conductive layer is filled and unevenness of the subsequent metal interconnect layer deposition caused by the deep and large contact holes of the field plate, thereby improving the performance and reliability of the semiconductor device.

[0047] This application also provides a semiconductor device that can be prepared by the method described in the first embodiment above.

[0048] Below, for reference Figure 3E The semiconductor devices of this application are described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description is given for the same components and structures as in the foregoing embodiments. For specific explanations and descriptions, please refer to the descriptions in the foregoing embodiments.

[0049] Specifically, such as Figure 3E As shown, the semiconductor device in this embodiment includes a semiconductor substrate 300, on which an interlayer dielectric layer 305 is formed; a contact hole penetrating the interlayer dielectric layer; a conductive layer 308 filling the contact hole; and a filling dielectric layer 309 formed on the conductive layer 308, the filling dielectric layer 309 filling the contact hole not filled by the conductive layer 308, and the conductive layer 308, the filling dielectric layer 309 and the upper surface of the interlayer dielectric layer 305 are flush.

[0050] For example, the contact hole includes a first contact hole and a second contact hole, the size of the second contact hole being smaller than the size of the first contact hole. The conductive layer 308 fills the second contact hole but does not fill the first contact hole. The filling dielectric layer 309 fills the first contact hole.

[0051] The first contact hole includes a field plate contact hole 306, in which a conductive layer 308 is filled and connected to a field plate dielectric layer 303. A gate structure 301 is formed on the semiconductor substrate 300, and the field plate dielectric layer 303 extends from the top of the gate structure 301 to the surface of the semiconductor substrate 300. The second contact hole includes a conventional contact hole 307, which is electrically connected to the gate structure 301 or the semiconductor substrate 300.

[0052] For example, the material of the dielectric layer 309 includes a transparent material, such as silicon oxide, and the material of the conductive layer 308 includes tungsten.

[0053] The semiconductor device in this embodiment forms a flat surface by filling the contact holes with the filling dielectric layer 309, which enables the subsequent metal interconnect layer to have higher flatness, improves the reliability of the semiconductor device, and avoids the burden on the subsequent CMP process and the impact on the recognition of photolithography alignment marks caused by excessively thick conductive layers.

[0054] In another embodiment of this application, an electronic device is provided, including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0055] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment, due to the use of the aforementioned semiconductor devices, has better performance.

[0056] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A method of manufacturing a semiconductor device, characterized by, include: A semiconductor substrate is provided, on which an interlayer dielectric layer is formed; The interlayer dielectric layer is etched to form a contact hole penetrating the interlayer dielectric layer. The contact hole includes a first contact hole and a second contact hole, wherein the size of the second contact hole is smaller than the size of the first contact hole. A conductive layer is filled into the contact hole, wherein the conductive layer fills the second contact hole but does not fill the first contact hole; A filling dielectric layer is deposited to fill the first contact hole that was not filled by the conductive layer; A planarization process is performed to remove the filling dielectric layer and the conductive layer located above the interlayer dielectric layer until the interlayer dielectric layer is exposed, and the conductive layer, the filling dielectric layer and the upper surface of the interlayer dielectric layer are flush.

2. The method of claim 1, wherein, The first contact hole includes a field plate contact hole that exposes the field plate dielectric layer of the semiconductor device. A gate structure is formed on the semiconductor substrate, and the field plate dielectric layer extends from the top of the gate structure to the surface of the semiconductor substrate.

3. The method of claim 1, wherein, The second contact hole includes a conventional contact hole that is electrically connected to the gate structure or the semiconductor substrate.

4. The method of claim 1, wherein, After performing the planarization process, a metal interconnect layer is formed on the interlayer dielectric layer.

5. The method according to claim 1, characterized in that, The material of the filling dielectric layer includes a transparent material, which includes silicon oxide.

6. The method of claim 1, wherein, The thickness of the filling dielectric layer is greater than the thickness of the conductive layer.

7. A semiconductor device, characterized in that, include: A semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate; A contact hole penetrating the interlayer dielectric layer, the contact hole including a first contact hole and a second contact hole, the size of the second contact hole being smaller than the size of the first contact hole; A conductive layer is filled in the contact hole, wherein the conductive layer fills the second contact hole but does not fill the first contact hole; A filling dielectric layer is formed on the conductive layer, the filling dielectric layer fills the first contact hole that is not filled by the conductive layer, and the upper surfaces of the conductive layer, the filling dielectric layer and the interlayer dielectric layer are flush.

8. The semiconductor device according to claim 7, characterized in that, The first contact hole includes a field plate contact hole that exposes the field plate dielectric layer of the semiconductor device. A gate structure is formed on the semiconductor substrate, and the field plate dielectric layer extends from the top of the gate structure to the surface of the semiconductor substrate.

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