Optoelectronic integrated package structure based on core particle stacking and method of manufacturing the same
The metal interconnect bumps formed by the chip stacking structure and selective chemical plating process solve the problems of complex structure, long interconnect path and high thermal resistance in optoelectronic co-packaging, realize compact high-density optoelectronic integrated packaging, reduce signal delay and power consumption, and improve process reliability.
CN122249041APending Publication Date: 2026-06-19上海曜感科技有限公司
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 上海曜感科技有限公司
- Filing Date
- 2026-02-03
- Publication Date
- 2026-06-19
Smart Images
Figure CN122249041A_ABST
Abstract
This invention discloses a photonic integrated packaging structure based on chip stacking and its fabrication method. The structure includes: a photonic integrated circuit chip with at least one vertically penetrating through-silicon via (TSV) electrically connected to the packaging substrate; the photonic integrated circuit chip has a first main surface, which includes an optical functional region and multiple first main surface electrode pads located around the optical functional region; at least one electrical functional chip directly disposed on the first main surface of the photonic integrated circuit chip; and the electrical functional chip has multiple back electrode pads corresponding vertically to the first main surface electrode pads. This invention achieves ultra-short-pitch electrical interconnection through a direct stacking architecture, eliminating the need for traditional silicon substrates, and offers advantages such as compact structure, excellent performance, and good process compatibility, making it suitable for high-speed optoelectronic co-packaging.
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