Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The structure includes: a substrate comprising a capacitor region and power terminals located on both sides of the capacitor region, the power terminals having a voltage difference and used to provide power to the circuit structure; multiple layers of capacitor plates stacked from bottom to top on the substrate of the capacitor region; a dielectric layer located between adjacent capacitor plates; a first interconnect via structure penetrating the capacitor plates of the odd-numbered layers and electrically connected to the capacitor plates of the odd-numbered layers; a second interconnect via structure penetrating the capacitor plates of the even-numbered layers and electrically connected to the capacitor plates of the even-numbered layers; a fusible structure located on the side of the capacitor plates in the capacitor region, one end of the fusible structure being electrically connected to the first interconnect via structure or the second interconnect via structure; and a third interconnect via structure being electrically connected to the other end of the fusible structure. This invention is beneficial for improving the operational stability of the circuit structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in materials and design have led to generation after generation of integrated circuits. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of fabricating and manufacturing integrated circuits, requiring similar developments in IC fabrication and manufacturing to match these advancements.

[0003] In circuit system design, a high-density capacitor is usually connected in parallel with the power rail. Its main purpose is to stabilize the supply voltage, reduce voltage fluctuations and noise, thereby ensuring the stability and reliability of the circuit. Summary of the Invention

[0004] The problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which is beneficial for improving the operational stability of circuit structures.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a capacitor region and power terminals located on both sides of the capacitor region, the power terminals on both sides of the capacitor region having a voltage difference and used to provide power to the circuit structure; multiple layers of capacitor plates stacked from bottom to top, located on the substrate of the capacitor region; a dielectric layer located between adjacent capacitor plates; a first interconnect via structure penetrating the capacitor plates of the odd-numbered layers and electrically connected to the capacitor plates of the odd-numbered layers; a second interconnect via structure penetrating the capacitor plates of the even-numbered layers and electrically connected to the capacitor plates of the even-numbered layers; a fuse structure located on the side of the capacitor plates in the capacitor region, one end of the fuse structure being electrically connected to the first interconnect via structure or the second interconnect via structure; and a third interconnect via structure being electrically connected to the other end of the fuse structure; wherein, the first interconnect via structure or the second interconnect via structure electrically connected to the fuse structure serves as the first electrical connection structure, and the other of the first and second interconnect via structures serves as the second electrical connection structure, the second electrical connection structure being electrically connected to the power terminal on one side of the capacitor region, and the third interconnect via structure being electrically connected to the power terminal on the other side of the capacitor region.

[0006] Optionally, two adjacent capacitor plates may overlap, and the non-overlapping portions may serve as extensions, with the extensions of adjacent capacitor plates stacked sequentially from bottom to top.

[0007] Optionally, the first interconnect via structure penetrates the extension of the capacitor plates in the odd-numbered layers and is electrically connected to them; the second interconnect via structure penetrates the extension of the capacitor plates in the even-numbered layers and is electrically connected to them.

[0008] Optionally, when the number of layers of the multilayer capacitor plate is odd, the semiconductor structure further includes: a first pseudo capacitor plate located on the extension of the top even-numbered capacitor plate; and a second interconnect via structure extending through the first pseudo capacitor plate.

[0009] Optionally, the dielectric layer is also located between the first pseudo-capacitor plate and the topmost even-numbered capacitor plate.

[0010] Optionally, the semiconductor structure further includes: one or more stacked second pseudo-capacitor plates located on a substrate on the side of the capacitor plate, wherein the number of layers of the second pseudo-capacitor plates is the same as the number of layers of the odd-numbered capacitor plates; and a third interconnect via structure penetrating the second pseudo-capacitor plates.

[0011] Optionally, the dielectric layer is also located between adjacent second pseudo-capacitor plates.

[0012] Optionally, the fused structure is located in the substrate; the semiconductor structure further includes: a first interconnect layer structure, penetrating the substrate from the bottom of the first electrical connection structure to the top of the fused structure, and electrically connected to the first electrical connection structure and the fused structure; and a second interconnect layer structure, penetrating the substrate from the bottom of the third interconnect via structure to the top of the fused structure, and electrically connected to the third interconnect via structure and the fused structure.

[0013] Optionally, the second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region via the top, and the third interconnect via structure is electrically connected to the power supply terminal on the other side of the capacitor region via the top.

[0014] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including a capacitor region and power supply terminals located on both sides of the capacitor region, the power supply terminals located on both sides of the capacitor region having a voltage difference and used to provide power to a circuit structure; forming a multilayer capacitor plate stacked from bottom to top on the substrate of the capacitor region, and a dielectric layer located between adjacent capacitor plates; forming a first interconnect via structure penetrating the odd-numbered capacitor plates, the first interconnect via structure being electrically connected to the odd-numbered capacitor plates; forming a second interconnect via structure penetrating the even-numbered capacitor plates, the second interconnect via structure being electrically connected to the even-numbered capacitor plates. Several layers of capacitor plates are electrically connected; a fusible structure is formed on the side of the capacitor plates in the capacitor region, one end of the fusible structure is electrically connected to a first interconnecting via structure or a second interconnecting via structure; a third interconnecting via structure is formed to be electrically connected to the other end of the fusible structure; wherein, the first interconnecting via structure or the second interconnecting via structure electrically connected to the fusible structure is used as the first electrical connection structure, the other of the first interconnecting via structure and the second interconnecting via structure is used as the second electrical connection structure, the second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region, and the third interconnecting via structure is electrically connected to the power supply terminal on the other side of the capacitor region.

[0015] Optionally, in the step of forming a multilayer capacitor plate stacked from bottom to top on the substrate of the capacitor region, and a dielectric layer located between adjacent capacitor plates, two adjacent capacitor plates partially overlap, and the non-overlapping parts serve as extensions, and the extensions of adjacent capacitor plates are stacked sequentially from bottom to top.

[0016] Optionally, in the step of forming a first interconnect via structure penetrating the capacitor plates of the odd-numbered layers, the first interconnect via structure penetrates the extension portion of the capacitor plates of the odd-numbered layers and is electrically connected thereto; in the step of forming a second interconnect via structure penetrating the capacitor plates of the even-numbered layers, the second interconnect via structure penetrates the extension portion of the capacitor plates of the even-numbered layers and is electrically connected thereto.

[0017] Optionally, when the number of layers of the multilayer capacitor plate is odd, the forming method further includes: forming a first pseudo capacitor plate on the extension of the top even-numbered capacitor plate; in the step of forming a second interconnecting via structure that penetrates the even-numbered capacitor plates, the second interconnecting via structure also penetrates the first pseudo capacitor plate.

[0018] Optionally, the dielectric layer is also located between the first pseudo-capacitor plate and the topmost even-numbered capacitor plate.

[0019] Optionally, the forming method further includes: forming one or more stacked second pseudo-capacitor plates on a substrate located on the side of the capacitor plate, wherein the number of layers of the second pseudo-capacitor plates is the same as the number of layers of the odd-numbered capacitor plates; in the step of forming a third interconnecting via structure electrically connected to the other end of the fused structure, the third interconnecting via structure penetrates through the second pseudo-capacitor plate.

[0020] Optionally, the dielectric layer is also located between adjacent second pseudo-capacitor plates.

[0021] Optionally, the fusible structure is formed in the substrate; the forming method further includes: forming a first interconnect layer structure through the substrate from the bottom of the first electrical connection structure to the top of the fusible structure, the first interconnect layer structure being electrically connected to the first electrical connection structure and to the fusible structure; forming a second interconnect layer structure through the substrate from the bottom of the third interconnect via structure to the top of the fusible structure, the second interconnect layer structure being electrically connected to the third interconnect via structure and to the fusible structure.

[0022] Optionally, the second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region via the top, and the third interconnect via structure is electrically connected to the power supply terminal on the other side of the capacitor region via the top.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0024] In the semiconductor structure provided by this invention, a multilayer capacitor plate constitutes a capacitor. One end of the fusible structure is electrically connected to either the first interconnect via structure or the second interconnect via structure, i.e., the fusible structure is connected in series with the capacitor. The first interconnect via structure or the second interconnect via structure electrically connected to the fusible structure serves as the first electrical connection structure, and the other of the first and second interconnect via structures serves as the second electrical connection structure. The second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region, and the third interconnect via structure is electrically connected to the power supply terminal on the other side of the capacitor region. That is, the fusible structure and the capacitor are connected in series and then in parallel at the power supply terminal used to supply power to the circuit structure. During the operation of the circuit structure, the capacitor connected in parallel at the power supply terminal helps to stabilize the supply voltage. At the same time, the fusible structure connected in series with the capacitor can melt and prevent short circuits at the power supply terminal from affecting the operation of the circuit structure if the capacitor breaks down due to defects in the process or after long-term load use, thus improving the working stability of the circuit structure.

[0025] In the semiconductor structure formation method provided in this embodiment of the invention, a multilayer capacitor plate constitutes a capacitor. One end of the fusible structure is electrically connected to a first interconnect via structure or a second interconnect via structure, that is, the fusible structure is connected in series with the capacitor. The first interconnect via structure or the second interconnect via structure electrically connected to the fusible structure serves as the first electrical connection structure, and the other of the first interconnect via structure and the second interconnect via structure serves as the second electrical connection structure. The second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region, and the third interconnect via structure is electrically connected to the power supply terminal on the other side of the capacitor region. That is, the fusible structure is connected in series with the capacitor and then in parallel at the power supply terminal used to supply power to the circuit structure. During the operation of the circuit structure, the capacitor connected in parallel at the power supply terminal is beneficial to stabilizing the supply voltage. At the same time, the fusible structure connected in series with the capacitor can melt and prevent short circuit at the power supply terminal from affecting the operation of the circuit structure if the capacitor breaks down due to defects in the process or after long-term load use. This is beneficial to improving the working stability of the circuit structure. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a circuit structure corresponding to a semiconductor structure;

[0027] Figures 2 to 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0028] Figures 5 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0029] Currently, improving the operational stability of circuit structures is difficult. This paper analyzes the reasons why the operational stability of circuit structures needs improvement, using a semiconductor structure as an example.

[0030] Figure 1 This is a schematic diagram of a circuit structure corresponding to a semiconductor structure.

[0031] refer to Figure 1 In a semiconductor structure, a capacitor 11 is connected in parallel with the power rail of the internal circuit 10 to stabilize the power supply voltage to the internal circuit 10. However, due to defects in the process or aging after long-term load use, the capacitor 11 may break down and fail, resulting in a power short circuit, that is, the positive terminal (VDD) of the power supply and the negative terminal or ground terminal (VSS) are shorted, which in turn affects the normal operation of the internal circuit.

[0032] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a capacitor region and power terminals located on both sides of the capacitor region, the power terminals on both sides of the capacitor region having a voltage difference and used to provide power to the circuit structure; multiple layers of capacitor plates stacked from bottom to top, located on the substrate of the capacitor region; a dielectric layer located between adjacent capacitor plates; a first interconnect via structure penetrating the capacitor plates of the odd-numbered layers and electrically connected to the capacitor plates of the odd-numbered layers; a second interconnect via structure penetrating the capacitor plates of the even-numbered layers and electrically connected to the capacitor plates of the even-numbered layers; a fusible structure located on the side of the capacitor plates in the capacitor region, one end of the fusible structure being electrically connected to either the first interconnect via structure or the second interconnect via structure; and a third interconnect via structure being electrically connected to the other end of the fusible structure; wherein, the first interconnect via structure or the second interconnect via structure electrically connected to the fusible structure serves as the first electrical connection structure, and the other of the first and second interconnect via structures serves as the second electrical connection structure, the second electrical connection structure being electrically connected to the power terminal on one side of the capacitor region, and the third interconnect via structure being electrically connected to the power terminal on the other side of the capacitor region.

[0033] In the semiconductor structure provided by this invention, a multilayer capacitor plate constitutes a capacitor. One end of the fusible structure is electrically connected to either the first interconnect via structure or the second interconnect via structure, i.e., the fusible structure is connected in series with the capacitor. The first interconnect via structure or the second interconnect via structure electrically connected to the fusible structure serves as the first electrical connection structure, and the other of the first and second interconnect via structures serves as the second electrical connection structure. The second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region, and the third interconnect via structure is electrically connected to the power supply terminal on the other side of the capacitor region. That is, the fusible structure and the capacitor are connected in series and then in parallel at the power supply terminal used to supply power to the circuit structure. During the operation of the circuit structure, the capacitor connected in parallel at the power supply terminal helps to stabilize the supply voltage. At the same time, the fusible structure connected in series with the capacitor can melt and prevent short circuits at the power supply terminal from affecting the operation of the circuit structure if the capacitor breaks down due to defects in the process or after long-term load use, thus improving the working stability of the circuit structure.

[0034] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 2 to 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0036] For clarity of illustration, Figure 3 This is a top view. Figure 2 for Figure 3 Partial sectional view in Figure 4 for Figure 3 The circuit diagram.

[0037] Reference Figures 2 to 4The semiconductor structure includes: a substrate 100, including a capacitor region 100C and power supply terminals 100V located on both sides of the capacitor region 100C, the power supply terminals 100V on both sides of the capacitor region 100C having a voltage difference and used to provide power to the circuit structure; multilayer capacitor plates 200 stacked from bottom to top, located on the substrate 100 of the capacitor region 100C; a dielectric layer 210 located between adjacent capacitor plates 200; a first interconnect via structure 310 penetrating through the odd-numbered capacitor plates 200 and electrically connected to the odd-numbered capacitor plates 200; a second interconnect via structure 320 penetrating through the even-numbered capacitor plates 200 and electrically connected to the even-numbered capacitor plates 200; and a fuse structure 500 located in the capacitor region. In the capacitor region 100C, on the side of the capacitor plate 200, one end of the fuse structure 500 is electrically connected to either the first interconnecting via structure 310 or the second interconnecting via structure 320; the third interconnecting via structure 330 is electrically connected to the other end of the fuse structure 500. The first interconnecting via structure 310 or the second interconnecting via structure 320, which is electrically connected to the fuse structure 500, serves as the first electrical connection structure 410. The other of the first interconnecting via structure 310 and the second interconnecting via structure 320 serves as the second electrical connection structure 420. The second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C, and the third interconnecting via structure 330 is electrically connected to the power supply terminal 100V on the other side of the capacitor region 100C.

[0038] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0039] In this embodiment, the substrate 100 includes a capacitor region 100C and a power supply terminal 100V located on both sides of the capacitor region 100C.

[0040] The capacitor region 100C is used to form a capacitor connected in parallel with the circuit structure. The power supply terminal 100V is used to provide power to the circuit structure. There is a voltage difference between the high voltage terminal VDD and the low voltage terminal VSS.

[0041] Multiple layers of capacitor plates 200 are alternately stacked from bottom to top as electrode plates for the MIM capacitor structure.

[0042] In this embodiment, in the multilayer capacitor plates 200, two adjacent layers of capacitor plates 200 partially overlap, and the non-overlapping parts serve as extensions 200e. The extensions 200e of adjacent capacitor plates 200 are stacked sequentially from bottom to top.

[0043] Two adjacent capacitor plates 200 partially overlap, with the overlapping portions facing each other to form a capacitor structure. The non-overlapping portions serve as extensions 200e, which are used for external electrical connection, thereby loading an electrical signal onto each capacitor plate 200. The extensions 200e of adjacent capacitor plates 200 are stacked sequentially from bottom to top, allowing electrical signals to be loaded onto adjacent capacitor plates 200 simultaneously through the extensions 200e. This simplifies the structure, streamlines the process, and improves the integration density of the semiconductor structure.

[0044] In this embodiment, the capacitor plate 200 is made of a conductive material. As an example, the material of the capacitor plate 200 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0045] The dielectric layer 210 serves as an insulating layer in the formation of the MIM capacitor, used to isolate adjacent capacitor plates 200.

[0046] In this embodiment, the dielectric layer 210 is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0047] Specifically, dielectric layer 210 is a high-k dielectric layer formed by stacking, i.e., dielectric layer 210 is a high-k composite dielectric layer. Once the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of dielectric layer 210 can meet process requirements while maintaining good formation quality. For this purpose, the high-k dielectric material includes one or more of the following: HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0048] In this embodiment, the dielectric layer 210 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, depending on process requirements, the dielectric layer material may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0049] The first interconnect via structure 310 is used to electrically connect to the odd-numbered layer capacitor plates 200, thereby loading an electrical signal onto the odd-numbered layer capacitor plates 200.

[0050] In this embodiment, the material of the first interconnect via structure 310 is a conductive material. As an example, the material of the first interconnect via structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0051] In this embodiment, the first interconnect via structure 310 penetrates the extension 200e of the capacitor plate 200 of the odd-numbered layers and is electrically connected to it.

[0052] The first interconnect via structure 310 penetrates the extension 200e of the odd-numbered capacitor plates 200 and is electrically connected to it, thereby loading an electrical signal onto the capacitor plates 200 through the extension 200e.

[0053] The second interconnect via structure 320 is used to electrically connect to the capacitor plates 200 of the even-numbered layers, thereby loading an electrical signal onto the capacitor plates 200 of the even-numbered layers.

[0054] In this embodiment, the material of the second interconnect via structure 320 is a conductive material. As an example, the material of the second interconnect via structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0055] In this embodiment, the second interconnect via structure 320 penetrates the extension 200e of the even-numbered capacitor plates 200 and is electrically connected to it.

[0056] The second interconnect via structure 320 penetrates the extension 200e of the even-numbered capacitor plates 200 and is electrically connected to it, thereby loading an electrical signal onto the capacitor plates 200 through the extension 200e.

[0057] The 500 fuse structure is used to break the circuit when the current is large.

[0058] In this embodiment, the multilayer capacitor plates 200 constitute a capacitor. One end of the fuse structure 500 is electrically connected to either the first interconnect via structure 310 or the second interconnect via structure 320, i.e., the fuse structure 500 is connected in series with the capacitor. The first interconnect via structure 310 or the second interconnect via structure 320 electrically connected to the fuse structure 500 serves as the first electrical connection structure 410, and the other of the first interconnect via structure 310 and the second interconnect via structure 320 serves as the second electrical connection structure 420. The second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C. The third interconnect via structure 310... 30 is electrically connected to the 100V power supply terminal on the other side of the capacitor area 100C. That is, the fuse structure 500 is connected in series with the capacitor and then in parallel to the 100V power supply terminal used to supply power to the circuit structure. During the operation of the circuit structure, the capacitor connected in parallel to the 100V power supply terminal helps to stabilize the supply voltage. At the same time, the fuse structure 500 connected in series with the capacitor can melt and prevent the 100V power supply terminal from short-circuiting and affecting the operation of the circuit structure if the capacitor breaks down due to defects in the process or after long-term load use. This helps to improve the working stability of the circuit structure.

[0059] Specifically, in this embodiment, one end of the fuse structure 500 is electrically connected to either the first interconnect via structure 310 or the second interconnect via structure 320, and the other end is electrically connected to the third interconnect via structure 330. The other of the first interconnect via structure 310 and the second interconnect via structure 320 serves as the second electrical connection structure 420. The second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C, and the third interconnect via structure 330 is electrically connected to the power supply terminal 100V on the other side of the capacitor region 100C. That is, the fuse structure 500 and the MIM capacitor are connected in series in the power supply terminals 100V at both ends. Figure 4 As shown, capacitor 102 and fuse 101 are connected in series in the high voltage terminal VSS and the low voltage terminal VDD, and in parallel with the circuit structure. Thus, when the MIM capacitor is broken down, the fuse structure 500 melts, so that the two power supply terminals 100V will not be short-circuited.

[0060] As an example, in this embodiment, the fusion structure 500 includes a fuse.

[0061] The fuse can automatically blow when the current passing through it is too large, so that the 100V power supply terminals will not be short-circuited when the MIM capacitor is broken down.

[0062] As an example, in this embodiment, one end of the fused structure 500 is electrically connected to the second interconnect via structure 320, the second interconnect via structure 320 serves as the first electrical connection structure 410, and the first interconnect via structure 310 serves as the second electrical connection structure 420.

[0063] In this embodiment, the fusible structure 500 is located in the substrate 100.

[0064] The fusible structure 500 is located in the substrate 100, that is, the fusible structure 500 is formed in the metal wire structure of the previous layer.

[0065] In this embodiment, the semiconductor structure further includes: a first interconnect layer structure 340, which extends through the substrate 100 from the bottom of the first electrical connection structure 410 to the top of the fuse structure 500, and is electrically connected to the first electrical connection structure 410 and to the fuse structure 500.

[0066] The first interconnect layer structure 340 is used to electrically connect the fuse structure 500 and the first electrical connection structure 410 to realize the series connection of the fuse structure 500 and the MIM capacitor composed of multiple capacitor plates 200.

[0067] In this embodiment, the material of the first interconnect layer structure 340 is a conductive material. As an example, the material of the first interconnect layer structure 340 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0068] In this embodiment, the semiconductor structure further includes: a second interconnect layer structure 350, a substrate 100 extending through the bottom of the third interconnect via structure 330 to the top of the fuse structure 500, and electrically connected to the third interconnect via structure 330 and the fuse structure 500.

[0069] The second interconnect layer structure 350 is used to electrically connect the fuse structure 500 and the third interconnect via structure 330 to achieve a 100V electrical connection at the power supply terminal of the fuse structure 500.

[0070] In this embodiment, the material of the second interconnect layer structure 350 is a conductive material. As an example, the material of the second interconnect layer structure 350 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0071] In this embodiment, both the first interconnect layer structure 340 and the second interconnect layer structure 350 include one or more metal layers. In this embodiment, there is no limitation on the number of metal layers.

[0072] In other embodiments, the fusible structure may be formed on the upper metal layer of the third interconnect via structure and the first electrical connection structure, and the fusible structure and the MIM capacitor composed of multiple capacitor plates may be connected in series through the upper metal layer of the third interconnect via structure and the first electrical connection structure.

[0073] The third interconnecting via structure 330 is used to electrically connect to the fuse structure 500, thereby connecting the fuse structure 500 in series to the two power supply terminals 100V.

[0074] In this embodiment, the material of the third interconnect via structure 330 is a conductive material. As an example, the material of the third interconnect via structure 330 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0075] In this embodiment, the second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C via its top, and the third interconnecting via structure 330 is electrically connected to the power supply terminal 100V on the other side of the capacitor region 100C via its top.

[0076] In this embodiment, when the number of layers of the multilayer capacitor plate 200 is odd, the semiconductor structure further includes: a first pseudo capacitor plate 220, located on the extension 200e of the top even-numbered capacitor plate 200.

[0077] The first pseudo-capacitor plate 220 is used to balance the formation process of the second interconnect via structure 320 and the first interconnect via structure 310.

[0078] Accordingly, in this embodiment, the second interconnect via structure 320 also penetrates the first pseudo capacitor plate 220.

[0079] In this embodiment, adjacent capacitor plates 200 partially overlap, with the non-overlapping portion serving as an extension 200e. The extensions 200e of adjacent capacitor plates 200 are stacked sequentially from bottom to top. This allows for the simultaneous loading of electrical signals onto adjacent capacitor plates 200 through the extensions 200e. When the number of capacitor plate layers is odd, the extensions 200e of odd-numbered layers have one more stacked layer than the extensions 200e of even-numbered layers. Therefore, in this embodiment, a first pseudo-capacitor plate 220 is formed on the topmost even-numbered layer extension 200e, making the extensions 200e of odd-numbered layers... The number of metal film layers at position 00e is equal to the number of metal film layers at position 200e of the extension of capacitor plate 200 with even-number layers. This ensures that the number of etched metal film layers is consistent when the first interconnect via structure 310, which is formed as an odd-number layer capacitor plate 200, is loaded with an electrical signal, and when the second interconnect via structure 320, which is formed as an even-number layer capacitor plate 200, is loaded with an electrical signal. Consequently, the thickness of the etched metal film layers tends to be consistent. This allows the etching process for forming the first interconnect via structure 310 to be performed with the same etching process parameters as the etching process for forming the second interconnect via structure 320. In other words, the first interconnect via structure 310 and the second interconnect via structure 320 can be formed in the same step, improving process efficiency.

[0080] In this embodiment, in order to make the thickness of the etched metal film layer more consistent when the first interconnect via structure 310, which is formed as an odd-layer capacitor electrode 200, loads an electrical signal, and the second interconnect via structure 320, which is formed as an even-layer capacitor electrode 200, loads an electrical signal, the top odd-layer capacitor electrode 200 and the first pseudo capacitor electrode 220 are patterned through the same electrode material layer, so that the top odd-layer capacitor electrode 200 and the first pseudo capacitor electrode 220 have the same thickness. This also helps to simplify the process flow and improve process efficiency.

[0081] Accordingly, in this embodiment, the dielectric layer 210 is also located between the first pseudo capacitor plate 220 and the topmost even-numbered capacitor plate 200.

[0082] In this embodiment, the semiconductor structure further includes: one or more stacked second pseudo capacitor plates 230 located on the substrate 100 on the side of the capacitor plate 200, wherein the number of layers of the second pseudo capacitor plate 230 is the same as the number of layers of the odd-numbered capacitor plates 200.

[0083] The second pseudo-capacitor plate 230 is used to balance the formation processes of the third interconnect via structure 330, the second interconnect via structure 320, and the first interconnect via structure 310.

[0084] Accordingly, in this embodiment, the third interconnect via structure 330 penetrates the second pseudo capacitor plate 230.

[0085] In this embodiment, the first interconnect via structure 310 penetrates the extension 200e of the odd-numbered capacitor plates 200. The second interconnect via structure 310 penetrates the extension 200e of the even-numbered capacitor plates 200. When the number of layers of the multilayer capacitor plates 200 is odd, the second interconnect via structure 310 penetrates the extension 200e of the even-numbered capacitor plates 200 and the first pseudo capacitor plate 220. That is, the number of capacitor plates 200 penetrated by the first interconnect via structure 310 and the second interconnect via structure 320 is the same as the number of layers of the odd-numbered capacitor plates 200. Therefore, in this embodiment, a second pseudo capacitor plate 230 with the same number of layers as the odd-numbered capacitor plates 200 is formed, so that when forming... When forming the third interconnect via structure 330, the number of etched metal film layers is the same as when forming the second interconnect via structure 320 and the first interconnect via structure 310. Consequently, the thickness of the etched metal film layers tends to be consistent. This allows the etching process for forming the third interconnect via structure 330 to use the same etching process parameters as the etching processes for forming the first interconnect via structure 310 and the second interconnect via structure 320. In other words, the first interconnect via structure 310, the second interconnect via structure 320, and the third interconnect via structure 330 can be formed in the same step, improving process efficiency.

[0086] In this embodiment, in order to make the thickness of the etched metal film layer tend to be consistent when forming the first interconnect via structure 310, the second interconnect via structure 320 and the third interconnect via structure 330, each second pseudo capacitor plate 230 is patterned sequentially through the same electrode material layer of each capacitor plate from bottom to top, until the number of second pseudo capacitor plates 230 that meet the process requirements is formed, so that the thickness of the second pseudo capacitor plate 230 is the same as that of the capacitor plate 200. This makes the thickness of the etched metal film layer tend to be consistent when forming the first interconnect via structure 310, the second interconnect via structure 320 and the third interconnect via structure 330, and also helps to simplify the process flow and improve process efficiency.

[0087] Accordingly, in this embodiment, the dielectric layer 210 is also located between adjacent second pseudo-capacitor plates 230.

[0088] Figures 5 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0089] refer to Figure 5 A substrate 100 is provided, including a capacitor region 100C and power supply terminals 100V located on both sides of the capacitor region 100C. The power supply terminals 100V located on both sides of the capacitor region 100C have a voltage difference and are used to provide power to the circuit structure.

[0090] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0091] In this embodiment, the substrate 100 includes a capacitor region 100C and a power supply terminal 100V located on both sides of the capacitor region 100C.

[0092] The capacitor region 100C is used to form a capacitor connected in parallel with the circuit structure. The power supply terminal 100V is used to provide power to the circuit structure. There is a voltage difference between the high voltage terminal VDD and the low voltage terminal VSS.

[0093] In this embodiment, during the step of providing the substrate 100, a fusible structure 500 is formed on the side of the capacitor plate subsequently formed in the capacitor region 100C.

[0094] The 500 fuse structure is used to break the circuit when the current is large.

[0095] As an example, in this embodiment, the fusion structure 500 includes a fuse.

[0096] The fuse can automatically melt when the current passing through it is too large, so that when the MIM capacitor formed by the capacitor plates formed later is broken down, the 100V power supply terminals will not be short-circuited.

[0097] In this embodiment, the forming method further includes: forming a first interconnect layer structure 340 that extends through the bottom of the subsequently formed first electrical connection structure to the top of the fuse structure 500, wherein the first interconnect layer structure 340 is electrically connected to the first electrical connection structure and to the fuse structure 500.

[0098] The first interconnect layer structure 340 is used to electrically connect the fuse structure 500 and the first electrical connection structure to realize the series connection of the fuse structure 500 and the MIM capacitor composed of multiple capacitor plates.

[0099] In this embodiment, the material of the first interconnect layer structure 340 is a conductive material. As an example, the material of the first interconnect layer structure 340 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0100] In this embodiment, the forming method further includes: forming a second interconnect layer structure 350 that extends through the bottom of the subsequently formed third interconnect via structure to the top of the fuse structure 500, wherein the second interconnect layer structure 350 is electrically connected to the third interconnect via structure and to the fuse structure 500.

[0101] The second interconnect layer structure 350 is used to electrically connect the fuse structure 500 and the third interconnect via structure to achieve a 100V electrical connection at the power supply terminal of the fuse structure 500.

[0102] In this embodiment, the material of the second interconnect layer structure 350 is a conductive material. As an example, the material of the second interconnect layer structure 350 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0103] In this embodiment, both the first interconnect layer structure 340 and the second interconnect layer structure 350 include one or more metal layers. In this embodiment, there is no limitation on the number of metal layers.

[0104] In other embodiments, the fusible structure may be formed on the upper metal layer of the third interconnect via structure and the first electrical connection structure, i.e., subsequently formed on the substrate, and the fusible structure is connected in series with the MIM capacitor composed of multiple capacitor plates through the upper metal layer of the third interconnect via structure and the first electrical connection structure.

[0105] Reference Figures 6 to 8 On the substrate 100 of the capacitor region 100C, a multilayer capacitor plate 200 stacked from bottom to top and a dielectric layer 210 located between adjacent capacitor plates 200 are formed.

[0106] For clarity of illustration, Figure 7 This is a top view. Figure 6 for Figure 7Partial sectional view in Figure 8 for Figure 7 The circuit diagram.

[0107] Multiple layers of capacitor plates 200 are alternately stacked from bottom to top as electrode plates for the MIM capacitor structure.

[0108] In this embodiment, in the step of forming a multilayer capacitor plate 200 stacked from bottom to top on the substrate 100 of the capacitor region 100C, and a dielectric layer 210 located between adjacent capacitor plates 200, in the multilayer capacitor plate 200, two adjacent capacitor plates 200 partially overlap, and the non-overlapping part serves as an extension 200e, and the extensions 200e of adjacent capacitor plates 200 are stacked sequentially from bottom to top.

[0109] Two adjacent capacitor plates 200 partially overlap, with the overlapping portions facing each other to form a capacitor structure. The non-overlapping portions serve as extensions 200e, which are used for external electrical connection, thereby loading an electrical signal onto each capacitor plate 200. The extensions 200e of adjacent capacitor plates 200 are stacked sequentially from bottom to top, allowing electrical signals to be loaded onto adjacent capacitor plates 200 simultaneously through the extensions 200e. This simplifies the structure, streamlines the process, and improves the integration density of the semiconductor structure.

[0110] In this embodiment, the capacitor plate 200 is made of a conductive material. As an example, the material of the capacitor plate 200 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0111] The dielectric layer 210 serves as an insulating layer in the formation of the MIM capacitor, used to isolate adjacent capacitor plates 200.

[0112] In this embodiment, the dielectric layer 210 is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0113] Specifically, dielectric layer 210 is a high-k dielectric layer formed by stacking, i.e., dielectric layer 210 is a high-k composite dielectric layer. Once the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of dielectric layer 210 can meet process requirements while maintaining good formation quality. For this purpose, the high-k dielectric material includes one or more of the following: HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0114] In this embodiment, the dielectric layer 210 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, depending on process requirements, the dielectric layer material may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0115] In this embodiment, when the number of layers of the multilayer capacitor plate 200 is odd, the forming method further includes: forming a first pseudo capacitor plate 220 on the extension 200e of the top even-numbered layer capacitor plate 200.

[0116] The first pseudo-capacitor plate 220 is used to balance the formation process of the subsequently formed second interconnect via structure and the first interconnect via structure.

[0117] In this embodiment, in order to make the thickness of the etched metal film layer more consistent when the first interconnect via structure for loading electrical signals in the capacitor electrode 200 formed as an odd-numbered layer and the second interconnect via structure for loading electrical signals in the capacitor electrode 200 formed as an even-numbered layer, the top odd-numbered layer capacitor electrode 200 and the first pseudo capacitor electrode 220 are patterned through the same electrode material layer, so that the thickness of the top odd-numbered layer capacitor electrode 200 and the first pseudo capacitor electrode 220 is the same, which also helps to simplify the process flow and improve process efficiency.

[0118] Accordingly, in this embodiment, the dielectric layer 210 is also located between the first pseudo capacitor plate 220 and the topmost even-numbered capacitor plate 200.

[0119] In this embodiment, the forming method further includes: forming one or more layers of second pseudo capacitor plates 230 on the substrate 100 on the side of the capacitor plate 200, wherein the number of layers of the second pseudo capacitor plates 230 is the same as the number of layers of the odd-numbered capacitor plates 200.

[0120] The second pseudo-capacitor plate 230 is used to balance the subsequent formation of the third interconnect via structure, as well as the formation process of the second interconnect via structure and the first interconnect via structure.

[0121] In this embodiment, in order to make the thickness of the etched metal film layer tend to be consistent when forming the first interconnect via structure, the second interconnect via structure, and the third interconnect via structure, each second pseudo capacitor plate 230 is patterned sequentially through the same electrode material layer of each capacitor plate from bottom to top, until the number of second pseudo capacitor plates 230 that meet the process requirements is formed, so that the thickness of the second pseudo capacitor plate 230 is the same as that of the capacitor plate 200. This makes the thickness of the etched metal film layer tend to be consistent when forming the first interconnect via structure, the second interconnect via structure, and the third interconnect via structure, and also helps to simplify the process flow and improve process efficiency.

[0122] Accordingly, in this embodiment, the dielectric layer 210 is also located between adjacent second pseudo-capacitor plates 230.

[0123] Continue to refer to Figures 6 to 8 A first interconnecting via structure 310 is formed, penetrating the capacitor plates 200 of the odd-numbered layers, and electrically connected to the capacitor plates 200 of the odd-numbered layers; a second interconnecting via structure 320 is formed, penetrating the capacitor plates 200 of the even-numbered layers, and electrically connected to the capacitor plates 200 of the even-numbered layers; a third interconnecting via structure 330 is formed, electrically connected to the other end of the fuse structure 500; wherein, the first interconnecting via structure 310 or the second interconnecting via structure 320 electrically connected to the fuse structure 500 serves as the first electrical connection structure 410, and the other of the first interconnecting via structure 310 and the second interconnecting via structure 320 serves as the second electrical connection structure 420, the second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C, and the third interconnecting via structure 330 is electrically connected to the power supply terminal 100V on the other side of the capacitor region 100C.

[0124] The first interconnect via structure 310 is used to electrically connect to the odd-numbered layer capacitor plates 200, thereby loading an electrical signal onto the odd-numbered layer capacitor plates 200.

[0125] In this embodiment, the material of the first interconnect via structure 310 is a conductive material. As an example, the material of the first interconnect via structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0126] In this embodiment, in the step of forming the first interconnect via structure 310 that penetrates the odd-numbered layers of the capacitor plate 200, the first interconnect via structure 310 penetrates the extension 200e of the odd-numbered layers of the capacitor plate 200 and is electrically connected to it.

[0127] The first interconnect via structure 310 penetrates the extension 200e of the odd-numbered capacitor plates 200 and is electrically connected to it, thereby loading an electrical signal onto the capacitor plates 200 through the extension 200e.

[0128] The second interconnect via structure 320 is used to electrically connect to the capacitor plates 200 of the even-numbered layers, thereby loading an electrical signal onto the capacitor plates 200 of the even-numbered layers.

[0129] In this embodiment, the material of the second interconnect via structure 320 is a conductive material. As an example, the material of the second interconnect via structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0130] In this embodiment, in the step of forming the second interconnecting via structure 320 that penetrates the capacitor plate 200 of the even-numbered layers, the second interconnecting via structure 320 penetrates the extension 200e of the capacitor plate 200 of the even-numbered layers and is electrically connected to it.

[0131] The second interconnect via structure 320 penetrates the extension 200e of the even-numbered capacitor plates 200 and is electrically connected to it, thereby loading an electrical signal onto the capacitor plates 200 through the extension 200e.

[0132] In this embodiment, the multilayer capacitor plates 200 constitute a capacitor. One end of the fuse structure 500 is electrically connected to either the first interconnect via structure 310 or the second interconnect via structure 320, i.e., the fuse structure 500 is connected in series with the capacitor. The first interconnect via structure 310 or the second interconnect via structure 320 electrically connected to the fuse structure 500 serves as the first electrical connection structure 410, and the other of the first interconnect via structure 310 and the second interconnect via structure 320 serves as the second electrical connection structure 420. The second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C. The third interconnect via structure 310... 30 is electrically connected to the 100V power supply terminal on the other side of the capacitor area 100C. That is, the fuse structure 500 is connected in series with the capacitor and then in parallel to the 100V power supply terminal used to supply power to the circuit structure. During the operation of the circuit structure, the capacitor connected in parallel to the 100V power supply terminal helps to stabilize the supply voltage. At the same time, the fuse structure 500 connected in series with the capacitor can melt and prevent the 100V power supply terminal from short-circuiting and affecting the operation of the circuit structure if the capacitor breaks down due to defects in the process or after long-term load use. This helps to improve the working stability of the circuit structure.

[0133] Specifically, in this embodiment, one end of the fuse structure 500 is electrically connected to either the first interconnect via structure 310 or the second interconnect via structure 320, and the other end is electrically connected to the third interconnect via structure 330. The other of the first interconnect via structure 310 and the second interconnect via structure 320 serves as the second electrical connection structure 420. The second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C, and the third interconnect via structure 330 is electrically connected to the power supply terminal 100V on the other side of the capacitor region 100C. That is, the fuse structure 500 and the MIM capacitor are connected in series in the power supply terminals 100V at both ends. Figure 4 As shown, capacitor 102 and fuse 101 are connected in series in the high voltage terminal VSS and the low voltage terminal VDD, and in parallel with the circuit structure. Thus, when the MIM capacitor is broken down, the fuse structure 500 melts, so that the two power supply terminals 100V will not be short-circuited.

[0134] As an example, in this embodiment, one end of the fused structure 500 is electrically connected to the second interconnect via structure 320, the second interconnect via structure 320 serves as the first electrical connection structure 410, and the first interconnect via structure 310 serves as the second electrical connection structure 420.

[0135] The third interconnecting via structure 330 is used to electrically connect to the fuse structure 500, thereby connecting the fuse structure 500 in series to the two power supply terminals 100V.

[0136] In this embodiment, the material of the third interconnect via structure 330 is a conductive material. As an example, the material of the third interconnect via structure 330 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0137] In this embodiment, the second electrical connection structure 420 is electrically connected to the power supply terminal 100V on one side of the capacitor region 100C via its top, and the third interconnecting via structure 330 is electrically connected to the power supply terminal 100V on the other side of the capacitor region 100C via its top.

[0138] Accordingly, in this embodiment, in the step of forming the second interconnect via structure 320 that penetrates the even-numbered layers of the capacitor plate 200, the second interconnect via structure 320 also penetrates the first pseudo capacitor plate 220.

[0139] In this embodiment, adjacent capacitor plates 200 partially overlap, with the non-overlapping portion serving as an extension 200e. The extensions 200e of adjacent capacitor plates 200 are stacked sequentially from bottom to top. This allows for the simultaneous loading of electrical signals onto adjacent capacitor plates 200 through the extensions 200e. When the number of capacitor plate layers is odd, the extensions 200e of odd-numbered layers have one more stacked layer than the extensions 200e of even-numbered layers. Therefore, in this embodiment, a first pseudo-capacitor plate 220 is formed on the topmost even-numbered layer extension 200e, making the extensions 200e of odd-numbered layers... The number of metal film layers at position 00e is equal to the number of metal film layers at position 200e of the extension of capacitor plate 200 with even-number layers. This ensures that the number of etched metal film layers is consistent when the first interconnect via structure 310, which is formed as an odd-number layer capacitor plate 200, is loaded with an electrical signal, and when the second interconnect via structure 320, which is formed as an even-number layer capacitor plate 200, is loaded with an electrical signal. Consequently, the thickness of the etched metal film layers tends to be consistent. This allows the etching process for forming the first interconnect via structure 310 to be performed with the same etching process parameters as the etching process for forming the second interconnect via structure 320. In other words, the first interconnect via structure 310 and the second interconnect via structure 320 can be formed in the same step, improving process efficiency.

[0140] Accordingly, in this embodiment, in the step of forming the third interconnecting via structure 330 which is electrically connected to the other end of the fused structure 500, the third interconnecting via structure 330 penetrates the second pseudo capacitor plate 230.

[0141] In this embodiment, the first interconnect via structure 310 penetrates the extension 200e of the odd-numbered capacitor plates 200. The second interconnect via structure 310 penetrates the extension 200e of the even-numbered capacitor plates 200. When the number of layers of the multilayer capacitor plates 200 is odd, the second interconnect via structure 310 penetrates the extension 200e of the even-numbered capacitor plates 200 and the first pseudo capacitor plate 220. That is, the number of capacitor plates 200 penetrated by the first interconnect via structure 310 and the second interconnect via structure 320 is the same as the number of layers of the odd-numbered capacitor plates 200. Therefore, in this embodiment, a second pseudo capacitor plate 230 with the same number of layers as the odd-numbered capacitor plates 200 is formed, so that when forming... When forming the third interconnect via structure 330, the number of etched metal film layers is the same as when forming the second interconnect via structure 320 and the first interconnect via structure 310. Consequently, the thickness of the etched metal film layers tends to be consistent. This allows the etching process for forming the third interconnect via structure 330 to use the same etching process parameters as the etching processes for forming the first interconnect via structure 310 and the second interconnect via structure 320. In other words, the first interconnect via structure 310, the second interconnect via structure 320, and the third interconnect via structure 330 can be formed in the same step, improving process efficiency.

[0142] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a capacitor region and power supply terminals located on both sides of the capacitor region, the power supply terminals located on both sides of the capacitor region having a voltage difference and used to provide power to the circuit structure; The multilayer capacitor plates are stacked from bottom to top and are located on the substrate of the capacitor region. A dielectric layer is located between adjacent capacitor plates; The first interconnect via structure penetrates the capacitor plates of the odd-numbered layers and is electrically connected to the capacitor plates of the odd-numbered layers. The second interconnecting via structure penetrates the capacitor plates of the even-numbered layers and is electrically connected to the capacitor plates of the even-numbered layers. A fusible structure is located on the side of the capacitor plate in the capacitor region, and one end of the fusible structure is electrically connected to the first interconnecting via structure or the second interconnecting via structure. The third interconnecting via structure is electrically connected to the other end of the fusible structure; Specifically, a first interconnect via structure or a second interconnect via structure electrically connected to the fuse structure is used as the first electrical connection structure, and the other of the first and second interconnect via structures is used as the second electrical connection structure. The second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region, and the third interconnect via structure is electrically connected to the power supply terminal on the other side of the capacitor region.

2. The semiconductor structure as described in claim 1, characterized in that, The capacitor plates of two adjacent layers overlap, and the non-overlapping parts serve as extensions. The extensions of the capacitor plates are stacked sequentially from bottom to top, spaced apart from each other.

3. The semiconductor structure as described in claim 2, characterized in that, The first interconnect via structure penetrates the extension of the capacitor plates in the odd-numbered layers and is electrically connected to them; The second interconnect via structure penetrates the extension of the capacitor plates in the even-numbered layers and is electrically connected to them.

4. The semiconductor structure as described in claim 3, characterized in that, When the number of layers of the multilayer capacitor plates is odd, the semiconductor structure further includes: a first pseudo capacitor plate located on the extension of the top even-numbered capacitor plate. The second interconnect via structure also extends through the first pseudo capacitor plate.

5. The semiconductor structure as described in claim 4, characterized in that, The dielectric layer is also located between the first pseudo capacitor plate and the top even-numbered capacitor plate.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: one or more stacked second pseudo capacitor plates on a substrate located on the side of the capacitor plate, wherein the number of layers of the second pseudo capacitor plate is the same as the number of layers of the odd-numbered capacitor plates. The third interconnecting via structure penetrates the second pseudo-capacitor plate.

7. The semiconductor structure as described in claim 6, characterized in that, The dielectric layer is also located between adjacent second pseudo-capacitor plates.

8. The semiconductor structure as described in claim 1, characterized in that, The fusible structure is located in the substrate; The semiconductor structure further includes: a first interconnect layer structure, extending through the substrate from the bottom of the first electrical connection structure to the top of the fused structure, and electrically connected to the first electrical connection structure and the fused structure; The second interconnect layer structure extends through the substrate from the bottom of the third interconnect via structure to the top of the fuse structure, and is electrically connected to both the third interconnect via structure and the fuse structure.

9. The semiconductor structure as described in claim 1, characterized in that, The second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region via its top, and the third interconnecting via structure is electrically connected to the power supply terminal on the other side of the capacitor region via its top.

10. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a capacitor region and power supply terminals located on both sides of the capacitor region, the power supply terminals located on both sides of the capacitor region having a voltage difference and used to provide power to the circuit structure; A multilayer capacitor plate stacked from bottom to top and a dielectric layer located between adjacent capacitor plates are formed on the substrate of the capacitor region. A first interconnect via structure is formed that penetrates the capacitor plates of the odd-numbered layers, and the first interconnect via structure is electrically connected to the capacitor plates of the odd-numbered layers; A second interconnecting via structure is formed that penetrates the capacitor plates of the even-numbered layers, and the second interconnecting via structure is electrically connected to the capacitor plates of the even-numbered layers; A fusible structure is formed on the side of the capacitor plate in the capacitor region, and one end of the fusible structure is electrically connected to the first interconnecting via structure or the second interconnecting via structure. A third interconnect via structure is formed that is electrically connected to the other end of the fusible structure; Specifically, a first interconnect via structure or a second interconnect via structure electrically connected to the fuse structure is used as the first electrical connection structure, and the other of the first and second interconnect via structures is used as the second electrical connection structure. The second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region, and the third interconnect via structure is electrically connected to the power supply terminal on the other side of the capacitor region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of forming a multilayer capacitor plate stacked from bottom to top on the substrate of the capacitor region, and a dielectric layer located between adjacent capacitor plates, two adjacent capacitor plates partially overlap, and the non-overlapping portions serve as extensions, and the extensions of adjacent capacitor plates are stacked sequentially from bottom to top.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming a first interconnect via structure that penetrates the capacitor plates of the odd-numbered layers, the first interconnect via structure penetrates the extension of the capacitor plates of the odd-numbered layers and is electrically connected thereto. In the step of forming a second interconnect via structure that penetrates the capacitor plates of the even-numbered layers, the second interconnect via structure penetrates the extension of the capacitor plates of the even-numbered layers and is electrically connected thereto.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, When the number of layers of the multilayer capacitor plates is odd, the forming method further includes: forming a first pseudo capacitor plate on the extension of the top even-numbered layer of capacitor plates. In the step of forming the second interconnect via structure that penetrates the even-numbered layers of the capacitor plate, the second interconnect via structure also penetrates the first pseudo capacitor plate.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The dielectric layer is also located between the first pseudo capacitor plate and the top even-numbered capacitor plate.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, The forming method further includes: forming one or more stacked second pseudo capacitor plates on a substrate located on the side of the capacitor plate, wherein the number of layers of the second pseudo capacitor plate is the same as the number of layers of the odd-numbered capacitor plates. In the step of forming a third interconnecting via structure electrically connected to the other end of the fused structure, the third interconnecting via structure penetrates the second pseudo-capacitor plate.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The dielectric layer is also located between adjacent second pseudo-capacitor plates.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, The fusion structure is formed in the substrate; The forming method further includes: forming a first interconnect layer structure through a substrate extending from the bottom of the first electrical connection structure to the top of the fuse structure, wherein the first interconnect layer structure is electrically connected to the first electrical connection structure and to the fuse structure; A second interconnect layer structure is formed, extending through the bottom of the third interconnect via structure to the top of the fuse structure. The second interconnect layer structure is electrically connected to the third interconnect via structure and to the fuse structure.

18. The method for forming a semiconductor structure as described in claim 10, characterized in that, The second electrical connection structure is electrically connected to the power supply terminal on one side of the capacitor region via its top, and the third interconnecting via structure is electrically connected to the power supply terminal on the other side of the capacitor region via its top.

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