Semiconductor element with landing pad and method of making the same

Abstract

This disclosure provides a semiconductor device with a landing pad and a method for fabricating the same. The semiconductor device includes a substrate; a landing pad located on the substrate; and an electrode layer located on the landing pad. A bottom surface of the electrode layer is substantially flat.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 979,919 (priority date December 13, 2024), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, it relates to a semiconductor device having a landing pad and a method for fabricating the same. Background Technology

[0004] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, various problems arise during miniaturization, and these problems are constantly increasing. Therefore, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The prior art description above is merely to provide background information and does not acknowledge that the prior art description above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the prior art above should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device comprising: a substrate; a landing pad disposed on the substrate; and an electrode layer disposed on the landing pad. A bottom surface of the electrode layer is substantially flat.

[0007] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; a landing pad disposed on the substrate; and an electrode layer disposed on the landing pad. No residual bumps exist between the landing pad and the electrode layer.

[0008] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate and forming a pad material on the substrate; forming a second mask layer on the pad material; performing a first planarization process on the second mask layer and patterning the second mask layer; using the second mask layer as a hard mask to perform a pad-forming etching process to form a valley and transform the pad material into a landing layer; forming a top dielectric layer that covers the landing pad and partially fills the valley; forming a fill layer on the top dielectric layer and filling the valley; performing a second planarization process on the fill layer; performing a pad-exposing etching process to expose the landing pad; and forming an electrode layer on the landing pad. A bottom surface of the electrode layer is substantially flat.

[0009] Due to the design of the semiconductor element disclosed herein, there are no residual bumps (or other insulating material) between the landing pad and the electrode layer. The absence of residual insulating material prevents interference with the electrical characteristics of the semiconductor element, thereby improving its overall performance.

[0010] The technical features and advantages of this disclosure have been summarized quite extensively above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages forming the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0011] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims when considered in conjunction with the accompanying drawings, wherein similar reference numerals represent similar elements throughout the drawings, and:

[0012] Figure 1 A method for preparing a semiconductor device is shown in flowchart form according to an embodiment of the present disclosure.

[0013] Figure 2 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0014] Figure 3 For along Figure 2 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0015] Figure 4 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0016] Figure 5 For along Figure 4 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0017] Figure 6 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0018] Figure 7 For along Figure 6 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0019] Figure 8 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0020] Figure 9 and Figure 10 For along Figure 8 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 11 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0022] Figure 12 and Figure 13 For along Figure 11 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 14 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0024] Figure 15 and Figure 16 For along Figure 14 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 17 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0026] Figure 18 For along Figure 17 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0027] Figure 19 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0028] Figure 20 For along Figure 19 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0029] Figure 21 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0030] Figures 22 to 27 For along Figure 21 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 28 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0032] Figure 29 For along Figure 28 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0033] Figure 30 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0034] Figure 31 For along Figure 30 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0035] Figure 32 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure.

[0036] Figures 33 to 40 For along Figure 32 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0037] Figure 41 This invention discloses a comparative example of a semiconductor device, which is shown in a cross-sectional schematic diagram.

[0038] Figure 42 A schematic cross-sectional view of a semiconductor device is shown according to another embodiment of this disclosure.

[0039] The reference numerals in the attached figures are explained as follows:

[0040] 1A: Semiconductor components

[0041] 1B: Semiconductor components

[0042] 10: Method

[0043] 101: Substrate

[0044] 103: Isolation layer

[0045] 105: Impurity Region

[0046] 105a: Shared source region

[0047] 105b: Drain region

[0048] 107: Bottom Insulation Layer

[0049] 109: Separator Layer

[0050] 109TS: Top surface

[0051] 210: First Spacing Structure

[0052] 210TS: Top surface

[0053] 211: First internal spacer

[0054] 213: First intermediate spacer

[0055] 215: First external spacer

[0056] 217: First Space

[0057] 219: Air gap

[0058] 220: Second Spacing Structure

[0059] 220TS: Top Surface

[0060] 221: Second internal spacer

[0061] 223: Second intermediate spacer

[0062] 225: Second external spacer

[0063] 227: The Second Space

[0064] 229: Air gap

[0065] 301: Landing mat

[0066] 301TS: Top surface

[0067] 310: Unit contact structure

[0068] 311: Bottom unit contact

[0069] 313: Top unit contact

[0070] 330: Electrode layer

[0071] 330BS: Bottom surface

[0072] 410: Top dielectric layer

[0073] 411: Horizontal section

[0074] 411TS: Top surface

[0075] 413: Cavity section

[0076] 420: Filler layer

[0077] 420TS: Top surface

[0078] 510: Character Line Structure

[0079] 511: Character line dielectric layer

[0080] 513: Character line conductive layer

[0081] 515: Character Line Overlay

[0082] 520: Bitline Structure

[0083] 520TS: Top Surface

[0084] 521: Bottom conductive layer of bit line

[0085] 523: Top conductive layer of bit line

[0086] 525: Bitline overlay

[0087] 527: Bit line contact

[0088] 701: Protective Component

[0089] 703: Sacrificial Layer

[0090] 705: Separating Material

[0091] 707: Bottom conductive material

[0092] 709: Padding Material

[0093] 711: First mask layer

[0094] 713: Second mask layer

[0095] 713TS: Top Surface

[0096] 715: Third mask layer

[0097] 731: Bump

[0098] A-A': line

[0099] B-B': Line

[0100] C1: Semiconductor element

[0101] C2: Semiconductor components

[0102] CY1: Cavity

[0103] OP1: Separating opening

[0104] OP2: Unit contact opening

[0105] OP3: Opening

[0106] OP4: Widened opening

[0107] OP5: Opening

[0108] P1: Linear pattern

[0109] S1: First side

[0110] S2: Second side

[0111] S11: Steps

[0112] S13: Steps

[0113] S15: Steps

[0114] S17: Steps

[0115] S19: Steps

[0116] S21: Steps

[0117] S23: Steps

[0118] S25: Steps

[0119] SP: Space

[0120] TR: Trench

[0121] VY1: Valley

[0122] W1: Width

[0123] W2: Width

[0124] W3: Width

[0125] X: Direction

[0126] Y: direction

[0127] Z: Direction Detailed Implementation

[0128] The following disclosure provides numerous different embodiments or examples of various components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to define relationships between the different embodiments and / or structures discussed.

[0129] Furthermore, spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate the description of the relationship between one element or component and another shown in the accompanying drawings. These spatial relation terms are used to cover different orientations of the elements in use or operation, beyond those depicted in the drawings. Elements may be rotated to different orientations (90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted in the same way.

[0130] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be a direct connection or coupling to another component or layer, or there may be an intermediate component or layer.

[0131] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0132] Unless the context otherwise indicates, the use of terms such as “same,” “equal,” “planar,” or “coplanar” in reference to orientation, layout, location, shape, size, quantity, or other measures does not necessarily imply identical orientation, layout, location, shape, size, quantity, or other measures, but is intended to cover orientation, layout, location, shape, size, quantity, or other measures that are substantially identical within acceptable variations, for example, due to manufacturing processes. The term “substantially” may be used in this document to reflect this meaning. For example, items described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations, for example, due to manufacturing processes.

[0133] In this disclosure, a semiconductor element generally refers to an element that can perform a function by utilizing the properties of a semiconductor, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0134] It should be noted that in the description of this disclosure, "above" or "up" corresponds to the direction of the arrow in the Z direction, and "below" or "down" corresponds to the direction of the arrow opposite to the Z direction.

[0135] Figure 1 A method 10 for preparing a semiconductor element 1A is shown in flowchart form according to an embodiment of the present disclosure. Figure 2 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 3 For along Figure 2 A schematic diagram of the cross-section drawn using lines A-A' and B-B'. Figure 4 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 5 For along Figure 4 A schematic diagram of the cross-section drawn using lines A-A' and B-B'. Figure 6 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 7 For along Figure 6 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0136] Reference Figures 1 to 7 In step S11, a substrate 101 can be provided, in which multiple common source regions 105a and multiple drain regions 105b can be formed, multiple word line structures 510 can be formed in the substrate 101, and multiple bit line structures 520 can be formed on the substrate 101.

[0137] Reference Figure 2 and Figure 3 The substrate 101 may include a bulk semiconductor substrate. The bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0138] In some embodiments, substrate 101 may include a semiconductor-on-insulator structure comprising, from bottom to top, a processing substrate, an insulating layer, and a top semiconductor material layer. The processing substrate and the top semiconductor material layer may comprise the same materials as the aforementioned bulk semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The thickness of the insulating layer may be between about 10 nm and about 200 nm. The insulating layer can eliminate leakage current between adjacent elements in substrate 101 and reduce parasitic capacitance associated with the source / drain.

[0139] It should be noted that the term "about" used to modify the amount of ingredients, components, or reactants used in this disclosure refers to quantitative variations that may occur, for example, through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to negligence or errors in measurement procedures, or differences in the manufacture, source, or purity of the ingredients used in the production of the composition or the implementation of the method. On one hand, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. Furthermore, the term "about" also means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0140] Reference Figure 2 and Figure 3 An isolation layer 103 may be formed in a substrate 101. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. Photolithography and subsequent etching processes, such as anisotropic dry etching, may be performed to form trenches that penetrate the pad oxide layer, the pad nitride layer, and extend into the substrate 101. An insulating material may be deposited into the trenches, followed by a planarization process, such as chemical mechanical polishing, until the top surface of the substrate 101 is exposed to remove excess filler material, providing a substantially flat surface for subsequent processing steps, and simultaneously forming the isolation layer 103. The insulating material may be, for example, silicon oxide or other applicable insulating materials. The isolation layer 103 may define these active regions (not shown) in the substrate 101.

[0141] It should be noted that, in the description of this disclosure, the surface of an element (or feature) located at the highest vertical level along the Z-direction (or axis) is referred to as the top surface of the element (or feature). The surface of an element (or feature) located at the lowest vertical level along the Z-direction is referred to as the bottom surface of the element (or feature).

[0142] Reference Figure 2 and Figure 3 Multiple impurity regions (not shown) can be formed correspondingly within the active regions. In some embodiments, the fabrication technique for these impurity regions may include an implantation process. That is, these impurity regions may be transformed from a portion of the active regions. The dopant in the implantation process may include p-type impurities (dopants) or n-type impurities (dopants). P-type impurities can be added to the intrinsic semiconductor to generate valence electron defects. Examples of p-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium. n-type impurities can be added to the intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. Examples of n-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the dopant concentration of these impurity regions 105 may be between about 1E19 atoms / cm³. 3 Approximately 1E21 atoms / cm 3 Between. After the implantation process, these impurity regions 105 may have an electrical type such as p-type or n-type.

[0143] Reference Figure 2 and Figure 3 Multiple character line trenches (TRs) can be formed in the substrate 101 to define the positions of the character line structures 510. The fabrication techniques for these character line trenches (TRs) may include photolithography and subsequent etching processes. In some embodiments, the character line trenches (TRs) may have a linear cross-sectional profile and extend along the Y direction, traversing (or intersecting) the impurity regions in a top perspective view. For example, each impurity region may intersect with two character line trenches (TRs). The character line trenches (TRs) may divide the impurity regions into multiple common source regions 105a and multiple drain regions 105b. For one impurity region, a common source region 105a may be formed between two character line trenches (TRs), and two drain regions 105b may be formed correspondingly between the isolation layer 103 and the two character line trenches (TRs).

[0144] Reference Figure 2 and Figure 3 The character line structures 510 (e.g., two character line structures 510) can be respectively formed in the character line trenches TR (e.g., two character line trenches TR). For the sake of brevity, clarity, and convenience, only one character line structure 510 is described. The character line structure 510 may include a character line dielectric layer 511, a character line conductive layer 513, and a character line capping layer 515.

[0145] Reference Figure 2 and Figure 3The character line dielectric layer 511 may be conformally formed on the inner surface of the character line trench TR. The character line dielectric layer 511 may have a U-shaped cross-sectional profile. In other words, the character line dielectric layer 511 may be formed inward in the active region. In some embodiments, the fabrication technique of the character line dielectric layer 511 may include a thermal oxidation process. For example, the character line dielectric layer 511 may be formed by oxidizing the inner surface of the character line trench TR. In some embodiments, the fabrication technique of the character line dielectric layer 511 may include a deposition process such as chemical vapor deposition or atomic layer deposition. The character line dielectric layer 511 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, the character line dielectric layer 511 may be formed by radical oxidation of the pad polysilicon layer after depositing a pad polysilicon layer (not shown for clarity). In some embodiments, after forming the pad silicon nitride layer (not shown for clarity), the word line dielectric layer 511 can be formed by free radical oxidation of the pad silicon nitride layer.

[0146] In some embodiments, the high dielectric constant material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium oxynitride, or a combination thereof. In some embodiments, the high dielectric constant material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium oxynitride, aluminum oxide, or a combination thereof.

[0147] Reference Figure 2 and Figure 3 A character line conductive layer 513 may be formed on the character line dielectric layer 511 and within the character line trench TR. In some embodiments, to form the character line conductive layer 513, a conductive layer (not shown for clarity) may be formed to fill the character line trench TR, followed by a recess process. The recess process may be performed as an etch-back process or sequentially as a planarization process and an etch-back process. The character line conductive layer 513 may have a recessed shape that partially fills the character line trench TR. That is, the top surface of the character line conductive layer 513 may be lower than the top surface of the substrate 101.

[0148] In some embodiments, the character line conductive layer 513 may include a metal, a metal nitride, or a combination thereof. For example, the character line conductive layer 513 may include titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, titanium nitride / tungsten may have a structure in which tungsten partially fills the character line trench TR. Titanium nitride or tungsten may be used alone in the character line conductive layer 513. In some embodiments, the character line conductive layer 513 may include a conductive material such as doped polycrystalline silicon, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the character line conductive layer 513 may include, for example, tungsten, aluminum, titanium, copper, similar materials, or a combination thereof.

[0149] Reference Figure 2 and Figure 3 A dielectric material (not shown) can be deposited, for example, by chemical vapor deposition, to completely fill the word line trench TR and cover the top surface of the substrate 101. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent processing steps and form the word line capping layer 515. In some embodiments, the word line capping layer 515 may include, for example, silicon nitride or other applicable dielectric materials.

[0150] Reference Figure 4 and Figure 5 A bottom insulating layer 107 may be formed (not shown in the top view for clarity). In some embodiments, the bottom insulating layer 107 may include a material that is etch-selective to the substrate 101 and the isolation layer 103. In some embodiments, the bottom insulating layer 107 may include, for example, silicon nitride, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or a combination thereof. In some embodiments, the bottom insulating layer 107 may include, for example, silicon nitride. In some embodiments, the fabrication technique of the bottom insulating layer 107 may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0151] Reference Figure 4 and Figure 5Multiple bit line contacts 527 can be formed, which penetrate the bottom insulating layer 107 and extend correspondingly to the common source regions 105a. In some embodiments, the bit line contacts 527 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the bit line contacts 527 may have a square cross-sectional profile in a top perspective view, but are not limited to this shape. In some embodiments, the bit line contacts 527 may have a rectangular, circular, or other applicable shape cross-sectional profile in a top perspective view.

[0152] Reference Figure 6 and Figure 7 The bit line structures 520 may be formed on the bottom insulating layer 107 and electrically connected to the bit line contacts 527 respectively. In a top perspective view, the bit line structures 520 may extend along the X direction and be separated from each other. In other words, in a top perspective view, the bit line structures 520 may intersect with the word line structures 510. For the sake of brevity, clarity and convenience, only one bit line structure 520 is described. In some embodiments, the bit line structure 520 may include a bottom conductive layer 521, a top conductive layer 523, and a bit line cover layer 525.

[0153] A bottom conductive layer 521 may be formed on the bit line contact 527. In some embodiments, the bottom conductive layer 521 may include, for example, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the dopant of the bottom conductive layer 521 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus.

[0154] The top conductive layer 523 of the bit line may be formed on the bottom conductive layer 521 of the bit line. In some embodiments, the top conductive layer 523 of the bit line may include, for example, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other applicable conductive materials, or combinations thereof.

[0155] Bit line capping layer 525 may be formed on top of the conductive layer 523 of the bit line. In some embodiments, bit line capping layer 525 may include, for example, silicon nitride or other applicable insulating materials.

[0156] Figure 8 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 9 and Figure 10 For along Figure 8The schematic cross-sectional view drawn along lines A-A' and B-B' shows a portion of the process for fabricating semiconductor element 1A according to an embodiment of this disclosure. It should be noted that, for clarity, some components (e.g., bottom insulating layer 107) are omitted in the top view.

[0157] Reference Figure 1 and Figures 8 to 10 In step S13, a plurality of first spacing structures 210 and a plurality of second spacing structures 220 may be formed on the first side S1 and the second side S2 of the bit line structures 520, and a sacrificial layer 703 may be formed on the substrate 101 and adjacent to the first spacing structures 210 and the second spacing structures 220.

[0158] Reference Figure 8 and Figure 9 The first spacer structures 210 may be formed on the first side S1 of the bit line structures 520. In other words, in a top perspective view, the first spacer structures 210 may extend along the X direction. For the sake of brevity, clarity and convenience, only one first spacer structure 210 is described. In some embodiments, the first spacer structure 210 may include a first inner spacer 211, a first intermediate spacer 213, and a first outer spacer 215.

[0159] The first internal spacer 211 may be formed on the first side S1 of the bit line structure 520. In some embodiments, the first internal spacer 211 may comprise the same material as the bit line cover layer 525. In some embodiments, the first internal spacer 211 may comprise, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication technique of the first internal spacer 211 may include conformally depositing a layer of insulating material (not shown) on the bottom insulating layer 107 and a subsequent anisotropic etching process.

[0160] The first intermediate spacer 213 may be conformally formed on the first inner spacer 211. In some embodiments, the first intermediate spacer 213 may include, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication technique of the first intermediate spacer 213 may include conformally depositing a layer of insulating material (not shown) on the bottom insulating layer 107 and a subsequent anisotropic etching process.

[0161] The first outer spacer 215 may be conformally formed on the first intermediate spacer 213. In some embodiments, the first outer spacer 215 may comprise the same material as the first inner spacer 211 or the bit line overlay 525. In some embodiments, the first outer spacer 215 may comprise, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication technique for the first outer spacer layer 215 may include conformally depositing an insulating material (not shown) on the bottom insulating layer 107 and subsequently performing an anisotropic etching process.

[0162] In some embodiments, the first internal spacer 211 may be selective. That is, the first intermediate spacer 213 may be formed directly on the first side S1 of the bit line structure 520.

[0163] Reference Figure 8 and Figure 9 The second spacing structures 220 may be formed on the second side S2 of the bit line structures 520. The second side S2 may be parallel to the first side S1. The second spacing structures 220 may be opposite to the first spacing structure 210 across the bit line structures 520. In a top perspective view, the second spacing structures 220 may extend along the X direction. In some embodiments, each of the second spacing structures 220 may include a second inner spacer 221, a second intermediate spacer 223, and a second outer spacer 225.

[0164] The second internal spacer 221 may be formed on the second side S2 of the bit line structure 520. The second intermediate spacer 223 may be conformally formed on the second internal spacer 221. The second external spacer 225 may be conformally formed on the second intermediate spacer 223. The second internal spacer 221, the second intermediate spacer 223, and the second external spacer 225 may each and correspondingly include the same material as the first internal spacer 211, the first intermediate spacer 213, and the first external spacer 215. In some embodiments, the first spacer structure 210 and the second spacer structure 220 may be formed simultaneously, and a space SP may be formed between the first spacer structure 210 and the second spacer structure 220.

[0165] Reference Figure 10A sacrificial layer 703 may be formed over the bottom insulating layer 107 to completely fill the space SP and cover the bit line structure 520, the first spacer structure 210, and the second spacer structure 220. In some embodiments, the sacrificial layer 703 may include a material, for example, having etch selectivity for the first outer spacer 215, the second outer spacer 225, or the bit line cover layer 525. In some embodiments, the sacrificial layer 703 may include, for example, silicon oxynitride, silicon nitride oxide, or other applicable materials. In some embodiments, the fabrication technique of the sacrificial layer 703 may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed until the top surface 520TS of the bit line structures 520 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0166] It should be noted that, in the description of this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0167] Figure 11 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 12 and Figure 13 For along Figure 11 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating semiconductor device 1A according to an embodiment of the present disclosure. Figure 14 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 15 and Figure 16 For along Figure 14 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating semiconductor device 1A according to an embodiment of the present disclosure. Figure 17 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 18 For along Figure 17 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0168] Reference Figure 1 and Figures 11 to 18In step S15, a first mask layer 711 including a linear pattern P1 can be formed on the sacrificial layer 703 to partially expose the sacrificial layer 703, the bit line structures 520, the first spacing structures 210, and the second spacing structures 220. The sacrificial layer 703 can be selectively removed to form a plurality of partition openings OP1, and a plurality of partition layers 109 can be formed in the partition openings OP1.

[0169] Reference Figure 11 and Figure 12 A first mask layer 711 can be formed on the substrate 101. In some embodiments, the first mask layer 711 may be a photoresist layer. In a top perspective view, the linear pattern P1 of the first mask layer 711 may include a plurality of rectangular spaces extending along the Y direction and alternately arranged along the X direction. Through these spaces, the sacrificial layer 703, the bit line structure 520, the first spacer structure 210, and the second spacer structure 220 can be partially exposed.

[0170] Reference Figure 13 The sacrificial layer 703 exposed by the linear pattern P1 of the first mask layer 711 can be selectively removed. In some embodiments, the removal of the sacrificial layer 703 can be achieved by an anisotropic etching process (such as an anisotropic dry etching process). After the sacrificial layer 703 is removed, the separation openings OP1 can be formed at the locations where the sacrificial layer 703 was exposed by the linear pattern P1 of the first mask layer 711.

[0171] Reference Figure 14 and Figure 15 After these partition openings OP1 are formed, the first mask layer 711 can be removed.

[0172] Reference Figure 16 A layer of separator material 705 may be formed on the sacrificial layer 703 to completely fill the separator openings OP1. In some embodiments, the separator material 705 may be a material that has etch selectivity for the sacrificial layer 703. In some embodiments, the separator material 705 may be the same material as the bit line cover layer 525 or the first external spacer 215 (or the second external spacer 225). In some embodiments, the separator material 705 may be, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication technique of the separator material 705 may include, for example, chemical vapor deposition or other applicable deposition processes.

[0173] Reference Figure 17 and 18A planarization process, such as chemical mechanical polishing, can be performed to remove excess material, providing a substantially flat surface for subsequent processing steps, and transforming the separating material 705 into multiple separating layers 109. In a top perspective view, each of these separating layers 109 may have a linear (or rectangular or square) cross-sectional profile extending along the Y direction. These separating layers 109 may be alternately arranged along the Y direction, with each corresponding bit line structure 520 located between two adjacent separating layers 109. Along the X direction, these separating layers 109 may be alternately arranged, with the sacrificial layer 703 interposed therebetween. In a top perspective view, the arrangement of these separating layers 109 and the bit line structures 520 divides the sacrificial layer 703 into multiple segments.

[0174] For the sake of brevity, clarity, and convenience, only one separator layer 109 is described. In some embodiments, after a planarization process, the first spacer structure 210 and the second spacer structure 220 may be exposed. The top surface 109TS of the separator layer 109, the top surface 210TS of the first spacer structure 210, the top surface 220TS of the second spacer structure 220, and the top surface 520TS of the bit line structure 520 may be substantially coplanar.

[0175] Figure 19 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 20 For along Figure 19 A schematic diagram of the cross-section drawn using lines A-A' and B-B'. Figure 21 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figures 22 to 27 For along Figure 21 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating semiconductor device 1A according to an embodiment of the present disclosure. Figure 28 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 29 For along Figure 28 A schematic diagram of the cross-section drawn using lines A-A' and B-B'. Figure 30 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 31 For along Figure 30 A schematic diagram of the cross-section drawn using lines A-A' and B-B'.

[0176] Reference Figure 1 and Figures 19 to 25 In step S17, the sacrificial layer 703 may be selectively removed to form a plurality of unit contact openings OP2, and a plurality of unit contact structures 310 may be formed within the unit contact openings OP2.

[0177] Reference Figure 19 and Figure 20The sacrificial layer 703 can be selectively removed via an etching process. For example, the sacrificial layer 703 can be removed via an anisotropic etching process. After the sacrificial layer 703 is removed, the cell contact openings OP2 can be formed in the locations previously occupied by the sacrificial layer 703 (in multiple segments). For the sake of brevity, clarity, and convenience, only one cell contact opening OP2 is described. In a cross-sectional perspective view, the cell contact opening OP2 can be disposed on the bottom insulating layer 107. In a top perspective view, the cell contact opening OP2 can be closed by two adjacent separator layers 109 along the X direction and two adjacent first spacer structures 210 and second spacer structures 220 along the Y direction.

[0178] Reference Figure 21 and Figure 22 A punch-through etching process can be performed to remove portions of the bottom insulating layer 107 exposed through the cell contact openings OP2. In some embodiments, the punch-through etching process can be an isotropic dry etching process. The punch-through etching process can extend the cell contact openings OP2 downward to the substrate 101. After the punch-through etching process, the drain regions 105b can be exposed through the cell contact openings OP2.

[0179] Reference Figure 23 A bottom conductive material 707 can be formed to cover the substrate 101, bit line structure 520, first spacer structure 210, second spacer structure 220, and separator layer 109. In some embodiments, the bottom conductive material 707 may be, for example, doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. In some embodiments, the bottom conductive material 707 may include a p-type dopant or an n-type dopant. In some embodiments, the fabrication technique of the bottom conductive material 707 may include, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. By using doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium as the unit contact, junction leakage can be reduced. As a result, the performance of semiconductor device 1A can be improved.

[0180] Reference Figure 24 A back-etch process can be performed to remove a portion of the bottom conductive material 707. After the back-etch process, the remaining bottom conductive material 707 can be transformed into multiple bottom unit contacts 311 within the unit contact openings OP2.

[0181] Reference Figure 25A conductive material (not shown) can be formed on the substrate 101. The conductive material may include, for example, titanium, nickel, platinum, tantalum, or cobalt. A heat treatment may then be performed. During the heat treatment, the metal atoms of the conductive material can chemically react with the silicon atoms of the bottom unit contacts 311 to form a plurality of top unit contacts 313. These top unit contacts 313 may include titanium silicide, nickel silicide, nickel-platinum silicide, tantalum silicide, or cobalt silicide. The heat treatment may be a dynamic surface annealing process. After the heat treatment, a cleaning process may be performed to remove unreacted conductive material. The cleaning process may use etchants such as hydrogen peroxide and SC-1 solution. In some embodiments, the thickness of the top unit contacts 313 may be between about 2 nm and about 20 nm. The bottom unit contacts 311 and the top unit contacts 313 together constitute the unit contact structure 310.

[0182] Reference Figure 1 and Figures 26 to 31 In step S19, a plurality of landing pads 301 separated by valleys VY1 can be formed within the unit contact openings OP2.

[0183] Reference Figure 26 A layer of padding material 709 can be formed to completely fill the cell contact openings OP2 and cover the bit line structure 520, the first spacer structure 210, the second spacer structure 220, and the separator layer 109. In some embodiments, the padding material 709 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. In some embodiments, the padding material 709 may be, for example, titanium nitride, titanium, tungsten, or combinations thereof. In some embodiments, the fabrication technique of the padding material 709 may include multiple deposition processes. For example, the padding material 709 (e.g., tungsten) may be deposited using a chemical vapor deposition process known for its excellent gap-filling capabilities. Subsequently, a planarization process is performed to achieve a substantially flat surface. Subsequently, a physical vapor deposition process may be applied to further deposit the padding material 709 onto the bit line structure 520. The pad material 709 formed by physical vapor deposition process is expected to exhibit improved resistivity characteristics.

[0184] Reference Figure 27 A second mask layer 713 may be formed on the pad material 709. In some embodiments, the second mask layer 713 may be a hard mask layer. In some embodiments, the second mask layer 713 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable materials. In some embodiments, the fabrication techniques for the second mask layer 713 may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0185] Reference Figure 27 A planarization process, such as chemical mechanical polishing (also known as a first planarization process), can be performed on the second mask layer 713. It should be noted that even after the planarization process, residual bumps 731 may remain on the top surface 713TS of the second mask layer 713, resulting in an uneven top surface and causing additional thickness of the second mask layer 713.

[0186] Reference Figure 27 A third mask layer 715 may be formed on the second mask layer 713. In some embodiments, the third mask layer 715 may be a photoresist layer and may include the pattern of the landing pads 301. The pattern may overlap with the residual bumps 731.

[0187] Reference Figure 28 and Figure 29 A third mask layer 715 can be used as a mask for an etching process (also known as a pattern transfer etching process) to remove a portion of the second mask layer 713, thereby transferring the pattern of the third mask layer 715 onto the second mask layer 713. It should be noted that even after the etching process, the residual bumps 731 may remain on the top surface 713TS of the second mask layer 713 due to the overlap between the pattern of the third mask layer 715 and the residual bumps 731. In some embodiments, the etching process may be an anisotropic etching process, such as an anisotropic dry etching process.

[0188] Reference Figure 30 and Figure 31 An etching process (also known as a pad forming etching process) can be performed to remove a portion of the pad material 709, bit line overlay 525, separator layer 109, and first spacer structure 210, thereby forming valley VY1. This process transforms the pad material 709 into the landing pads 301. It should be noted that the second mask layer 713 may be exhausted during the etching process. However, some residual bumps 731 may remain on the top surface 301TS of the landing pad 301. In some embodiments, the etching process may be an anisotropic etching process, such as an anisotropic dry etching process.

[0189] In some embodiments, the bitline overlay layer 525, the first spacing structure 210, the second spacing structure 220, and the separator layer 109 may be exposed via valley VY1. In some embodiments, such as Figure 31 As shown, the separator layer 109 and the first spacer structure 210 are fully exposed through valley VY1. The bit line cover layer 525 and the second spacer structure 220 are partially exposed through valley VY1. The landing pad 301 can partially cover the bit line cover layer 525 and the second spacer structure 220.

[0190] Figure 32A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figures 33 to 40 For along Figure 32 The schematic cross-sectional view drawn by lines A-A' and B-B' in the figure shows a portion of the process for fabricating a semiconductor device according to an embodiment of the present disclosure. Figure 41 This disclosure shows a comparative cross-sectional schematic diagram of a semiconductor device C1.

[0191] Reference Figure 1 and Figures 32 to 34 In step S21, a top dielectric layer 410 may be formed on the landing pads 301 and partially fill the valley VY1, thereby creating a cavity CY1 with an opening OP3.

[0192] Reference Figure 32 and Figure 33 The first intermediate spacer 213 and the second intermediate spacer 223 can be selectively removed to form a first space 217 and a second space 227 communicating with valley VY1. In some embodiments, the selective removal of the first intermediate spacer 213 and the second intermediate spacer 223 can be achieved by using a vapor hydrogen fluoride that has etching selectivity for oxides.

[0193] Reference Figure 34 A top dielectric layer 410 may be formed on the top surface 301TS of the landing pad 301 and partially fill valley VY1. Specifically, the top dielectric layer 410 may include a horizontal portion 411 and a cavity portion 413. The horizontal portion 411 is formed on the top surface 301TS of the landing pad 301, while the cavity portion 413 extends from the horizontal portion 411 into valley VY1, thereby forming a cavity CY1 including an opening OP3. In some embodiments, the top dielectric layer 410 may include, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication techniques of the top dielectric layer 410 may include, for example, chemical vapor deposition, physical vapor deposition, or a combination thereof.

[0194] It should be noted that residual bumps 731 remaining on the top surface 301TS of the landing pad 301 may also be covered by the horizontal portion 411 of the top dielectric layer 410. This coverage may cause unevenness on the top surface 411TS of the horizontal portion 411 and result in increased thickness.

[0195] In some embodiments, the width W1 of the opening OP3 may be smaller than the width W2 of the cavity CY1. A smaller opening OP3 may increase the difficulty of filling the cavity CY1.

[0196] In some embodiments, the top dielectric layer 410 may not be a conformal layer to provide better sealing for valley VY1 and the first space 217 and the second space 227. The sealed first space 217 may be referred to as the first air gap 219, and the sealed second space 227 may be referred to as the second air gap 229. The first internal spacer 211, the first air gap 219, and the first external spacer 215 constitute the first spacer structure 210. The second internal spacer 221, the second air gap 229, and the second external spacer 225 constitute the second spacer structure 220. The first air gap 219 and the second air gap 229 can reduce the parasitic capacitance between adjacent bit line structures 520.

[0197] When cavity CY1 is not properly filled, cavity portion 413 may be consumed in subsequent processes to create a channel connecting cavity CY1 to air gaps 219 and 229. This increases the risk of side etching of the first internal spacer 211 and the second internal spacer 221. Consequently, it also increases the risk of leakage between the capacitor and the bit line structure 520.

[0198] Reference Figure 1 and Figures 35 to 37 In step S23, a protective element 701 is formed to partially fill the cavity CY1, the opening OP3 can be widened to form a widened opening OP4, the protective element 701 can be removed, and a filling layer 420 can be formed to fill the cavity CY1.

[0199] Reference Figure 35 The protective element 701 can partially fill the bottom portion of the cavity CY1, providing temporary protection. This ensures that the bottom portion of the cavity CY1 remains unaffected during subsequent widening processes. In some embodiments, the protective element 701 may include a highly viscous and high-density chemical to facilitate its entry into the narrow opening OP3 to partially fill the cavity CY1. Examples of such chemicals may include sulfuric acid, phosphoric acid, or similar substances. In some embodiments, the protective element 701 may be injected into... Figure 34 On the top surface of the intermediate semiconductor element shown, a spin-off process is then performed to facilitate its entry into the cavity CY1.

[0200] Reference Figure 36An etching process can be performed to widen the opening OP3 to form a widened opening OP4. In some embodiments, the etching process may be a wet etching process. In some embodiments, the etching process may include applying a diluted hydrofluoric acid solution to the cavity CY1. Since the protective element 701 occupies the bottom of the cavity CY1, only the top of the cavity CY1 (i.e., near the opening OP3) can be removed. As a result, the opening OP3 is widened to form a widened opening OP4. In some embodiments, the width W2 of the cavity CY1 and the width W3 of the widened opening OP4 may be substantially the same. In some embodiments, the width W2 of the cavity CY1 may be smaller than the width W3 of the widened opening OP4. In some embodiments, the width ratio of the width W3 of the widened opening OP4 to the width W2 of the cavity CY1 may be between about 0.80 and about 1.20, between about 0.85 and about 1.05, or between about 0.90 and about 1.00.

[0201] Reference Figure 36 After the widened opening OP4 is formed, the protective element 701 can be removed. In some embodiments, removing the protective element 701 may include applying deionized water to the cavity CY1.

[0202] Reference Figure 37 A filling layer 420 may be formed on the top dielectric layer 410 and fill the cavity CY1. In some embodiments, the filling layer 420 may completely fill the cavity CY1. In some embodiments, the filling layer 420 may include the same material as the top dielectric layer 410. In some embodiments, the filling layer 420 may include, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication technique of the filling layer 420 may include, for example, chemical vapor deposition, atomic layer deposition, or other applicable deposition processes.

[0203] It should be noted that due to the presence of the residual bump 731, the filler layer 420 formed on the horizontal portion 411 may exhibit an uneven top (or bottom) surface. In other words, when the residual bump 731 is present on the landing pad 301, additional insulating (or dielectric) material, including the residual bump 731, the horizontal portion 411, and the filler layer 420, is deposited on the landing pad 301. This results in an increased thickness compared to other areas where the filler layer 420 is not formed on the residual bump 731.

[0204] Because the cavity CY1 is completely filled, the air gaps 219 and 229 below are properly protected, thereby eliminating the risk of exposure during subsequent processes (such as capacitor formation). Therefore, defects such as leakage between capacitors and bit line structures in semiconductor device 1A can be reduced.

[0205] Furthermore, due to the widened opening OP4, the filling layer 420 can easily fill the cavity CY1. For example, the cavity CY1 can be filled using only one deposition process, instead of multiple deposition and etching cycles. As a result, the complexity and time required to fabricate the semiconductor device 1A can be reduced.

[0206] Reference Figure 1 and Figures 38 to 40 In step S25, a planarization process can be performed to planarize the filler layer 420, and multiple electrode layers 330 can be formed on the landing pads 301.

[0207] Reference Figure 38 A planarization process, such as chemical mechanical polishing (also known as a second planarization process), can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. The second planarization process reduces the thickness variation of the insulating material above the top surface 301TS of the landing pad 301. In some embodiments, the deviation of the top surface 420TS of the filler layer 420 can be less than three times its root mean square roughness.

[0208] Reference Figure 39 An etching process (also known as a pad exposure etching process) can be performed to remove a portion of the filler layer 420 and the top dielectric layer 410. After the etching process, multiple openings OP5 can be formed. These landing pads 301 can be exposed respectively through these openings OP5. Furthermore, by means of… Figure 38 The planarization process described herein can completely eliminate residual bumps 731 during the pad exposure etching process. In other words, there is no residual insulating material on the landing pad 301, thereby ensuring that the electrical characteristics of the semiconductor device 1A are not affected. In some embodiments, the etching process may be an anisotropic etching process, such as anisotropic dry etching.

[0209] Reference Figure 40 The electrode layers 330 may be formed in the openings OP5 to be electrically connected to the landing pads 301 respectively. For the sake of brevity, clarity and convenience, only one electrode layer 330 is described. In some embodiments, the electrode layer 330 may be part of a capacitor. In some embodiments, there are no residual bumps 731 between the landing pad 301 and the electrode layer 330. In some embodiments, the bottom surface 330BS of the electrode layer 330 may be substantially flat. In some embodiments, the electrode layer 330 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0210] It should be noted that, in the description of this disclosure, a surface is described as "substantially flat" or "substantially planar" if there is a horizontal plane and the deviation of a surface from the plane does not exceed three times the root mean square roughness of the surface.

[0211] Reference Figure 41 Unprocessed Figure 38 The semiconductor device C1 in the second planarization process described herein may experience an increase in thickness due to residual bumps 731. This increase will affect... Figure 39 The pad-exposed etching process shown results in residual bumps 731 remaining between the electrode layer 330 and the landing pad 301, which may affect the electrical characteristics of the semiconductor device C1. For example, if the pad-exposed etching process relies on a predetermined process time rather than endpoint detection, the residual bumps 731 may remain on the landing pad 301 after the etching process. The electrode layer 330 formed on the residual bumps 731 may include an uneven bottom surface.

[0212] In some embodiments, after the formation of the fill layer 420, the remaining bumps 731 and the increase in thickness can be identified as bump-type defects. The number of defects in semiconductor device 1A (with an additional second planarization process) can be significantly reduced compared to the number of defects in semiconductor device C1 (without an additional second planarization process). In other words, the defect density of semiconductor device 1A can be less than the defect density of semiconductor device C1.

[0213] Figure 42 A schematic cross-sectional view of a semiconductor element 1B is shown according to another embodiment of the present disclosure.

[0214] Reference Figure 42 The first intermediate spacer 213 of the first spacer structure 210 and the second intermediate spacer 223 of the second spacer structure 220 may not be removed, such as Figure 33 As shown. These intermediate spacers provide additional protection against leakage of conductive material from the landing pad 301, unit contact structure 310, or electrode layer 330 into the unit wire structure 520.

[0215] One aspect of this disclosure provides a semiconductor device comprising: a substrate; a landing pad disposed on the substrate; and an electrode layer disposed on the landing pad. A bottom surface of the electrode layer is substantially flat.

[0216] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; a landing pad disposed on the substrate; and an electrode layer disposed on the landing pad. No residual bumps exist between the landing pad and the electrode layer.

[0217] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate and forming a pad material on the substrate; forming a second mask layer on the pad material; performing a first planarization process on the second mask layer and patterning the second mask layer; using the second mask layer as a hard mask to perform a pad forming etching process to form a valley and transform the pad material into a landing layer; forming a top dielectric layer that covers the landing pad and partially fills the valley; forming a fill layer on the top dielectric layer and filling the valley; performing a second planarization process on the fill layer; performing a pad exposure etching process to expose the landing pad; and forming an electrode layer on the landing pad. A bottom surface of the electrode layer is substantially flat.

[0218] Due to the design of the semiconductor element disclosed herein, there are no residual bumps 731 (or other insulating material) between the landing pad 301 and the electrode layer 330. The absence of residual insulating material prevents interference with the electrical characteristics of the semiconductor element 1A, thereby improving its overall performance.

[0219] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0220] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; A landing pad is located on the base plate; as well as An electrode layer is located on the landing pad. One of the bottom surfaces of this electrode layer is substantially flat.

2. The semiconductor device of claim 1, further comprising: A top dielectric layer includes a cavity portion surrounding the landing pad, wherein the top dielectric layer is recessed toward the substrate and includes a U-shaped cross-sectional profile to form a cavity with a widened opening; as well as A filling layer is located on the top dielectric layer and fills the cavity. The width of the cavity and the width of the widened opening are substantially the same.

3. The semiconductor element of claim 2 further includes a unit contact structure located between the substrate and the landing pad.

4. The semiconductor element of claim 3, wherein the unit contact structure comprises: A bottom unit contact is located between the substrate and the landing pad; as well as A top unit contact is located between the bottom unit contact and the landing pad.

5. The semiconductor device of claim 4, wherein the bottom unit contact comprises doped polysilicon, doped polygermanium, or doped polysilicon-germanium.

6. The semiconductor device of claim 4, wherein the top unit contact comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

7. The semiconductor element of claim 4 further includes a bit line structure adjacent to the landing pad and located between the cavity portion and the substrate.

8. The semiconductor element of claim 7, further comprising a first spacer structure located on a first side of the bit line structure, between the landing pad and the bit line structure, and between the cavity portion and the substrate.

9. The semiconductor element of claim 8, wherein the first spacer structure comprises: A first internal spacer is located on the first side of the bit line structure and between the landing pad and the bit line structure; A first external spacer, located between the first internal spacer and the landing pad; and A first air gap is located between the first internal spacer and the first external spacer.

10. The semiconductor element of claim 8, wherein the first spacer structure comprises: A first internal spacer is located on the first side of the bit line structure and between the landing pad and the bit line structure; A first external spacer, located between the first internal spacer and the landing pad; and A first intermediate spacer is located between the first inner spacer and the first outer spacer.

11. The semiconductor device of claim 8, wherein the bit line structure comprises: A bottom conductive layer for a single-element line is located on the substrate. A top conductive layer for a bit line is located on the bottom conductive layer of that bit line; as well as A bit line overlay is located on the top conductive layer of the bit line.

12. The semiconductor element of claim 8, further comprising a separator layer adjacent to the landing pad and located between the top dielectric layer and the substrate.

13. The semiconductor device of claim 10, wherein the first intermediate spacer comprises silicon oxide.

14. The semiconductor element of claim 8, wherein the landing pad comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof.

15. The semiconductor element of claim 9, wherein the first internal spacer and the first external spacer comprise the same material.

16. The semiconductor device of claim 8, wherein the top dielectric layer and the fill layer comprise the same material.

Images