Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate chip, a first chip, and a second chip. The first chip is bonded to the substrate chip. The first chip includes an integrated circuit. The second chip is located on the same side of the substrate chip as the first chip and is spaced apart from the first chip. The second chip includes a channel. The channel includes an inner wall partially formed by a portion of the surface of the substrate chip. The channel includes a first opening and a second opening; at least one target side of the second chip is coplanar with an edge of the substrate chip, and the side of the second chip coplanar with the edge of the substrate chip is the target side, with the first opening and the second opening located on the target side.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As semiconductor devices acquire more functions and higher performance, the number of chips within them increases, resulting in higher integration density and increasingly stringent requirements for heat dissipation. If accumulated heat cannot be dissipated in time to keep the chip temperature below safe levels, it can affect chip performance or even cause it to burn out. Chip heat dissipation is one of the key factors restricting the development of high-performance computers. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor structure and a method for preparing the same.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows: In a first aspect, embodiments of this disclosure provide a semiconductor structure. The semiconductor structure includes: Base chip; A first chip is bonded to the substrate chip; the first chip includes an integrated circuit. The second chip is located on the same side of the substrate chip as the first chip and is spaced apart from the first chip; the second chip includes a channel; the channel includes an inner wall partially formed by a portion of the surface of the substrate chip; the channel includes a first opening and a second opening; at least one side of the second chip is coplanar with the edge of the substrate chip, the side of the second chip coplanar with the edge of the substrate chip is a target side, and the first opening and the second opening are located on the target side.

[0005] In some embodiments, the target side includes a first side; The first opening and the second opening are located on the first side.

[0006] In some embodiments, the second chip includes a plurality of the channels; The first opening and the second opening of the plurality of channels are both located on the first side of the second chip.

[0007] In some embodiments, the target side includes a first side and a second side; the first opening is located on the first side, and the second opening is located on the second side.

[0008] In some embodiments, the second chip includes a plurality of the channels; The first openings of the plurality of channels are all located on the first side, and the second openings of the plurality of channels are all located on the second side.

[0009] In some embodiments, the channel is a continuously undulating curve parallel to the plane of the substrate chip.

[0010] In some embodiments, the substrate chip includes a first semiconductor substrate and a first functional layer and a first interconnect layer located on the first semiconductor substrate; The first chip includes a second semiconductor substrate and a second functional layer and a second interconnect layer located on the second semiconductor substrate; The first interconnect layer is coupled to the second interconnect layer; along the direction perpendicular to the plane of the substrate chip, the size of the channel is greater than the sum of the sizes of the second functional layer and the second interconnect layer.

[0011] In some embodiments, the surface area of ​​the first chip is greater than the surface area of ​​the second chip; The semiconductor structure includes a plurality of second chips, at least two of which have different surface areas.

[0012] In some embodiments, the semiconductor structure further includes a top chip disposed on the side of the first chip away from the substrate chip, and the top chip covers at least one of the first chip and at least one of the second chip.

[0013] In the semiconductor structure provided in this disclosure, a first chip and a second chip are located on the same side of a substrate chip. The second chip, having a channel, is spaced apart from the first chip, and the channel of the second chip can be used to dissipate heat generated by the first chip and the substrate chip. Specifically, the channel within the second chip includes an inner wall partially formed by a portion of the surface of the substrate chip, i.e., the channel has an initial opening located on one side of the second chip, which contacts the substrate chip. The outline of the initial opening is the same as the cross-sectional shape of the channel along a direction parallel to the plane of the second chip, meaning the channel is not a tubular structure embedded inside the second chip. When the first opening and the second opening serve as the inlet and outlet for coolant or cooling gas to be introduced into the channel, respectively, the coolant or cooling gas introduced into the channel can directly contact the substrate chip, which is beneficial to enhancing the heat dissipation efficiency of the second chip for the first chip and the substrate chip. Furthermore, this disclosure uses a second chip instead of a channel within the first chip, which not only facilitates the layout and extension design of the channel but also enables the second chip with heat dissipation function to be compatible in the chip-wafer bonding process, simplifying the semiconductor structure fabrication process.

[0014] Secondly, this disclosure provides a method for fabricating a semiconductor structure. The method includes: A first wafer is formed; the first wafer includes a plurality of bonding regions and a dicing region surrounding the bonding regions; A first chip is formed, the first chip including an integrated circuit; An initial second chip is formed; the initial second chip includes an initial channel; the initial opening of the initial channel is located on one side of the initial second chip, and the outline of the initial opening is the same as the cross-sectional shape of the initial channel along the direction parallel to the plane where the initial second chip is located; The first chip is disposed in the bonding area and bonded to the first wafer; The initial second chip and the first chip are disposed on the same side of the first wafer and spaced apart from each other; the initial second chip is bonded to the first wafer to form a bonding structure; the side where the initial opening is located is in contact with the first wafer; a portion of the initial second chip is located in the bonding area, the other portion of the initial second chip is located in the dicing area, and both ends of the initial channel extend to the dicing area; The bonding structure is cut along the cutting region to obtain a semiconductor structure; wherein, the initial second chip after cutting is a second chip; the first wafer after cutting is a substrate chip; at least one side of the second chip is coplanar with the edge of the substrate chip, and the side of the second chip that is coplanar with the edge of the substrate chip is a target side; the initial channel after cutting includes a first opening and a second opening that extend to both ends of the cutting region, and the first opening and the second opening are located on the target side.

[0015] In some embodiments, forming the initial second chip includes: A substrate is provided; the substrate includes a plurality of etched regions; An initial channel is formed within each of the etched areas; the initial channel includes a continuous uneven structure and is located within the etched area; The substrate is cut along the edge of the etched area to obtain the initial second chip.

[0016] In some embodiments, forming the first wafer includes: Provide the first initial wafer; A first functional layer is formed on the first initial wafer; A first interconnect layer is formed on the first functional layer to obtain the first wafer; The formation of the first chip includes: Provide a second initial wafer; A second functional layer is formed on the second initial wafer; A second interconnect layer is formed on the second functional layer to obtain the first chip.

[0017] In some embodiments, the step of placing the first chip in the bonding region and bonding it to the first wafer includes: The first chip is disposed in the bonding region, and the first interconnect layer is coupled to the second interconnect layer; The step of placing the initial second chip on one side of the first chip and bonding it to the first wafer to obtain a bonding structure includes: After placing the initial second chip on one side of the first chip, the gap between the first chip and the initial second chip is filled to obtain an initial semiconductor structure; The bonding structure is obtained by thinning the side of the initial semiconductor structure away from the first wafer.

[0018] In the semiconductor structure fabrication method provided in this disclosure, based on the initial second chip being inverted on the first wafer, the surface where the initial opening of the initial channel is located is in contact with the first wafer. This avoids the problem of the dielectric material subsequently filling the space between the first chip and the initial second chip blocking the channel, and also avoids the problem of impurities blocking the channel during the subsequent thinning of the dielectric material. Furthermore, in the step of dicing the bonding structure, the channel is obtained by dicing the portion of the initial second chip located in the dicing region, i.e., dicing the initial channel extending to both ends of the dicing region, forming two corresponding openings (e.g., a first opening and a second opening). This eliminates the need to separately fabricate the first and second openings of the channel, simplifying the channel fabrication process. Attached Figure Description

[0019] Figure 1 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 1 ; Figure 2 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 2 ; Figure 3 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 3 ; Figure 4 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 4 ; Figure 5 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 5 ; Figure 6 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 6 ; Figure 7A schematic diagram of the structure of the first chip and the substrate chip of the semiconductor structure provided for the embodiments of this disclosure; Figure 8 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 7 ; Figure 9 A schematic diagram of the structure of the top chip, the first chip, and the substrate chip of the semiconductor structure provided for embodiments of this disclosure; Figure 10 Schematic diagram of the method for fabricating the semiconductor structure provided in this disclosure Figure 1 ; Figure 11 (a) to (g) are schematic diagrams of the fabrication process of the semiconductor structure provided in this disclosure. Figure 12 A schematic diagram of the structure of the uncut first wafer, the first chip, and the initial second chip provided for the implementation of this disclosure; Figure 13 Schematic diagram of the method for fabricating the semiconductor structure provided in this disclosure Figure 2 ; Figure 14 (a) to (d) are schematic diagrams of the fabrication process of the initial second chip provided in this disclosure. Detailed Implementation

[0020] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0022] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0027] In some embodiments, as semiconductor devices acquire more functions and higher performance, the number of chips within the devices increases, resulting in higher integration density and increasingly stringent requirements for heat dissipation. If the accumulated heat cannot be dissipated in time to ensure that the chip temperature remains below a safe level, it can affect chip performance or even cause the chip to burn out and malfunction, severely hindering the development of high-performance computers.

[0028] In some embodiments, the semiconductor structure includes multiple stacked chips, one chip directly connected to the wafer, and the stacked chips connected to the wafer via through-silicon vias (TSVs). This arrangement can easily lead to heat accumulation from multiple stacked chips, causing thermal management problems. For example, the power consumption of stacked chips increases exponentially, and the stacked structure is not easy to dissipate heat; furthermore, the stacked chips are connected by TSV points, and the TSV material has low thermal conductivity (much lower than that of silicon), and the dense TSV array can block lateral heat diffusion paths, making heat dissipation even more difficult.

[0029] For example, tiny flow channels can be created inside or on the back of the chip to dissipate heat through liquid cooling. This method is widely used in high-power chips, such as graphics processing units (GPUs) or high-performance computing (HPC) chips.

[0030] However, heat dissipation using "microchannels inside the chip" requires the fabrication of individual microchannels for each wafer or chip. Different microchannels need to be designed based on the circuit layout and structure of different wafers or chips, making the process complex. Furthermore, even after fabricating tiny channels inside or on the back of the chip, heat accumulation still exists when multiple chips are stacked. Moreover, the different power consumption of the chips leads to unstable heat dissipation results and low reliability of the heat dissipation structure.

[0031] In view of this, the present disclosure provides a semiconductor structure and a method for preparing the same.

[0032] Figure 1 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 1 .like Figure 1 As shown, the semiconductor structure 100 includes a substrate chip 110, a first chip 120, and a second chip 130.

[0033] The first chip 120 is bonded to the substrate chip 110; the first chip 120 includes an integrated circuit. For example, the first chip 120 has an integrated circuit, which is a chip capable of performing a specific function, such as one or more of a laser chip, a radio frequency device chip, or a power device chip.

[0034] The second chip 130 is located on the same side of the substrate chip 110 as the first chip 120 and is spaced apart from the first chip 120. For example, the second chip 130 is a dummy chip used to provide non-functional structural support or process assistance. For instance, the second chip 130 may include a silicon wafer and does not contain an integrated circuit that implements signal transmission functions.

[0035] like Figure 1 As shown, the second chip 130 includes a channel 131. Channel 131 includes an inner wall partially formed by a portion of the surface of the substrate chip 110 (see [reference]). Figure 1 (Opening A1 in the middle). It is understood that the channel 131 includes an inner wall partially formed by a portion of the surface of the substrate chip 110, that is, the channel 131 has an initial opening A1, and the side of the initial opening A1 is in contact with the surface of the substrate chip 110.

[0036] Figure 2 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 2 .like Figure 2 As shown, channel 131 includes a first opening A2 and a second opening A3. At least one side of the second chip 130 is coplanar with the edge of the substrate chip 110, and the side of the second chip 130 that is coplanar with the edge of the substrate chip 110 is the target side M, and the first opening A2 and the second opening A3 are located on the target side M.

[0037] In the aforementioned semiconductor structure 100, the first chip 120 and the second chip 130 are located on the same side of the substrate chip 110. The second chip 130, having a channel 131, is spaced apart from the first chip 120. The channel of the second chip 130 can be used to dissipate heat generated by the first chip 120 and the substrate chip 110. Specifically, the channel 131 within the second chip 130 includes an inner wall partially formed by a portion of the surface of the substrate chip 110. That is, the channel 131 has an initial opening A1 located on one side of the second chip 130, which contacts the substrate chip 110. The outline of the initial opening A1 is the same as the cross-sectional shape of the channel 131 along the direction parallel to the plane of the second chip 130. In other words, the channel 131 is not a tubular structure embedded inside the second chip 130. With the first opening A2 and the second opening A3 serving as the inlet and outlet for coolant or cooling gas to be introduced into the channel 131, respectively, the coolant or cooling gas introduced into the channel 131 can directly contact the substrate chip 110, which is beneficial to enhancing the heat dissipation efficiency of the second chip 130 on the first chip 120 and the substrate chip 110. Furthermore, this disclosure provides the second chip 130, instead of providing the channel within the first chip 120, which not only facilitates the layout and extension design of the channel 131, but also enables the second chip with heat dissipation function to be compatible in the chip-wafer bonding process, simplifying the semiconductor structure fabrication process.

[0038] In some embodiments, the channel 131 is a continuous undulating curve along the plane parallel to the substrate chip 110.

[0039] Example, Figure 4 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 4 .like Figure 2 and Figure 4 As shown, channel 131 is shaped like an "S" or an "M" along the plane parallel to the substrate chip 110. The examples provided in this disclosure do not require the dimensions and extension length of the uneven structure of channel 131, which can be set according to actual needs.

[0040] It should be noted that channel 131 can also be other shapes with the initial opening A1, the first opening A2, and the second opening A3 set in different positions and relative positions on the second chip 130. For example, channel 131 is a maze-like structure with one passageway.

[0041] In this way, the channel 131 is set on the virtual second chip 130. The second chip 130 provides enough space to set the channel 131, which enhances the residence time of the coolant or cooling gas entering the channel 131 in the second chip 130 and improves the heat exchange efficiency.

[0042] like Figures 2-6As shown, at least one side of the second chip 130 is coplanar with the edge of the substrate chip 110, and the side of the second chip 130 that is coplanar with the edge of the substrate chip 110 is the target side M.

[0043] In some embodiments, one side of the second chip 130 is coplanar with the edge of the substrate chip 110. For example, as Figure 2 As shown, the target side M includes a first side M1. A first opening A2 and a second opening A3 are located on the first side M1.

[0044] For example, such as Figure 2 As shown, the semiconductor structure 100 includes two first chips 120, and a second chip 130 is disposed between the two adjacent first chips 120. One side of the second chip 130 is coplanar with the edge of the substrate chip 110, and this side is a target side M. The target side M includes a first side M1. A first opening A2 and a second opening A3 are located on the first side M1.

[0045] Another example, Figure 3 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 3 .like Figure 3 As shown, the second chip 130 may include multiple channels 131. The first opening A2 and the second opening A3 of the multiple channels 131 are both located on the first side M1 of the second chip 130.

[0046] For example, such as Figure 3 As shown, the second chip includes two channels 131. The two channels 131 have the same structure. The first opening A2 and the second opening A3 of the same channel 131 are both located on the first side M1. Furthermore, the first opening A2 of both channels 131 is located on the first side M1, and the second opening A3 of both channels 131 is located on the first side M1.

[0047] In other examples, two sides of the second chip 130 are coplanar with the edges of the substrate chip 110. For example, as shown... Figure 4 As shown, the target side M includes a first side M1 and a second side M2. A first opening A2 is located on the first side M1, and a second opening A3 is located on the second side M2.

[0048] For example, such as Figure 4 As shown, the semiconductor structure 100 includes two first chips 120, and a second chip 130 is disposed between two adjacent first chips 120, which is beneficial for isolating heat transferred between the two adjacent first chips 120. Moreover, the second chip 130 may have two sides coplanar with the edge of the substrate chip 110, and the first opening A2 and the second opening A3 of the channel 131 are respectively located on two opposite sides of the second chip 130 that are coplanar with the edge of the substrate chip 110.

[0049] Another example, Figure 5 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 5 .like Figure 5 As shown, the semiconductor structure 100 includes two first chips 120. The two first chips 120 have different dimensions along a direction parallel to the substrate chip 110. After setting the arrangement of the two first chips 120, a corner area remains on the surface of the substrate chip 110, where a second chip 130 can be placed. Moreover, the second chip 130 may have two sides coplanar with the edge of the substrate chip 110. The first opening A2 and the second opening A3 of the channel 131 are respectively located on two adjacent sides of the second chip 130 that are coplanar with the edge of the substrate chip 110.

[0050] For example, the second chip 130 may include multiple channels 131. The first openings A2 of the multiple channels 131 are all located on the first side M1, and the second openings A3 of the multiple channels 131 are all located on the second side M2.

[0051] For example, Figure 6 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 6 .like Figure 6 As shown, the second chip 130 includes two channels 131. The two channels 131 have the same structure. The first opening A2 of one channel 131 is located on the first side M1, and the second opening A3 is located on the second side M2. The first opening A2 of both channels 131 is located on the first side M1, and the second opening A3 of both channels 131 is located on the second side M2.

[0052] The two sides of the second chip 130 and the substrate chip 110 that are coplanar can be opposite sides (e.g., Figure 4 The second chip 130 shown can also be two adjacent sides (e.g., Figure 5 The second chip 130 shown can be configured with the positions of the first opening A2 and the second opening A3 of the channel 131 on the second chip 130 according to the relative positional relationship, quantity and size of the multiple first chips 120 and the second chip 130, which is beneficial to expanding the applicable scenarios of the second chip 130 with the channel 131.

[0053] Furthermore, the first opening A2 and the second opening A3 of channel 131 are obtained during the dicing operation in the subsequent semiconductor structure fabrication process. This allows for the fabrication of a heat dissipation structure (such as the first opening A2 and the second opening A3 of channel 131) without adding an additional step in the wafer-to-chip bonding process. This achieves compatibility between the wafer-to-chip bonding process and the fabrication of a heat dissipation structure, simplifying the process steps of the semiconductor structure 100.

[0054] It is understood that the examples provided in this disclosure do not limit "first opening A2" to be an inlet for coolant or cooling gas in channel 131 and "second opening A3" to be an outlet for coolant or cooling gas in channel 131, as long as one of "first opening A2" and "second opening A3" in the same channel 131 serves as an outlet of channel 131 and the other as an inlet of channel 131. For example, as Figure 3 and Figure 6 As shown, in the two channels 131 included in the second chip 130, the first opening A2 of the left channel 131 serves as the inlet of the channel 131, and the second opening A3 serves as the outlet of the channel 131; the first opening A2 of the right channel 131 serves as the outlet of the channel 131, and the second opening A3 serves as the inlet of the channel 131.

[0055] In this way, during the subsequent process of introducing coolant or cooling gas into different channels 131, the coolant or cooling gas is introduced from the side closer to the first chip 120 and the coolant or cooling gas carrying heat is output from the side farther away from the first chip 120, which helps to quickly remove the heat generated by the first chip 120 and improve heat dissipation efficiency.

[0056] In some embodiments, Figure 7 A schematic diagram of the structure of the first chip and the substrate chip of the semiconductor structure provided for embodiments of this disclosure. (See attached diagram.) Figure 7 As shown, the substrate chip 110 includes a first semiconductor substrate 111 and a first functional layer 112 and a first interconnect layer 113 located on the first semiconductor substrate 111.

[0057] For example, the first semiconductor substrate 111 of the substrate chip 110 is used to provide support for the first functional layer 112 and the first interconnect layer 113. For example, the first semiconductor substrate 111 is made of silicon.

[0058] The first functional layer 112 includes a single layer or a stack of multiple functional layers forming a semiconductor device. For example, the multiple functional layers of the first functional layer 112 include a CMOS circuit layer sequentially stacked on the first semiconductor substrate 111 for forming a silicon-based CMOS, etc. This disclosure does not limit the scope of the invention.

[0059] The first interconnect layer 113 is disposed on the side of the first functional layer 112 away from the first semiconductor substrate 111. For example, the first interconnect layer 113 provides an interface for hybrid bonding in subsequent chip-wafer bonding processes to facilitate electrical connections between different chips.

[0060] And, such as Figure 7 As shown, the first chip 120 includes a second semiconductor substrate 121 and a second functional layer 122 and a second interconnect layer 123 located on the second semiconductor substrate 121.

[0061] For example, the material of the second semiconductor substrate 121 of the first chip 120 includes a non-silicon material, specifically a compound semiconductor material. Exemplarily, the material of the second semiconductor substrate 121 includes one or more of silicon, gallium nitride (GaN), silicon carbide (SiC), and indium phosphide (InP).

[0062] The second functional layer 122 includes a single layer or a stack of multiple functional layers forming a semiconductor device. For example, the multiple functional layers of the second functional layer 122 include one or more functional layers selected from a first electrode layer, a piezoelectric layer, a second electrode layer, and a waveguide layer, which are sequentially stacked on the second semiconductor substrate 121, for forming functional devices such as lasers, amplifiers, or resonators. This disclosure does not limit this aspect.

[0063] The second interconnect layer 123 is disposed on the side of the second functional layer 122 away from the second semiconductor substrate 121. For example, the second interconnect layer 123 provides an interface for hybrid bonding in subsequent chip-wafer bonding processes to facilitate electrical connections between different chips.

[0064] The first interconnect layer 113 of the substrate chip 110 is coupled to the second interconnect layer 123 of the first chip 120. For example... Figure 7 As shown, the dimension L1 of channel 131 along the first direction X is greater than the sum of the dimensions L2 of the second functional layer 122 and the second interconnect layer 123 along the first direction X; the first direction X is perpendicular to the plane where the substrate chip 110 is located.

[0065] For example, such as Figure 7 As shown, the semiconductor structure 100 includes a plurality of first chips 120. The sum L2 of the dimensions L2 of the second functional layers 122 and the second interconnect layers 123 of the plurality of first chips 120 along the first direction X can be different. Therefore, the dimension L1 of the channel 131 along the first direction X is greater than the maximum value of the sum L2 of the dimensions L2 of the second functional layers 122 and the second interconnect layers 123 along the first direction X of the plurality of first chips 120 adjacent to this second chip 130. This is beneficial to improving the heat dissipation efficiency of the channel 131 of the second chip 130 on the adjacent first chips 120.

[0066] It is understood that the dimensions of the channel 131 provided in this disclosure along the first direction X can also be adjusted according to actual needs. For example, multiple channels 131 can be set in a second chip 130, and the dimensions L1 of different channels 131 along the first direction X can be different (appropriately reduced) to improve the stability of the structure of the second chip 130.

[0067] and, Figure 9 A schematic diagram of the structure of the top chip, the first chip, and the substrate chip of the semiconductor structure provided for embodiments of this disclosure. (See attached diagram.) Figure 9As shown, the dimension of the second chip 130 along the first direction X is smaller than the maximum dimension among the dimensions of the plurality of first chips 120 along the first direction X, reducing the adverse effect on the surface planarization of the structure after packaging the second chip 130 and the plurality of first chips 120; especially for subsequent stacking of other chips (e.g., on the side of the first chip 120 away from the substrate chip 110) Figure 9 In the structure of the top chip 140 shown, the flatness of the surface of the first chip 120 after packaging (on the side away from the base chip 110) is improved to enhance the structural stability of the semiconductor structure 100.

[0068] In some embodiments, Figure 8 Structural schematic of the semiconductor structure provided for embodiments of this disclosure Figure 7 .like Figure 8 As shown, the surface area of ​​the first chip 120 is larger than the surface area of ​​the second chip 130. The semiconductor structure 100 includes a plurality of second chips 130, at least two of which have different surface areas.

[0069] For example, such as Figure 8 As shown, the semiconductor structure 100 includes a plurality of first chips 120 and a plurality of second chips 130. A second chip 130 is disposed between two adjacent first chips 120. Second chips 130 of different sizes or surface areas can be disposed according to the space between two adjacent first chips 120, and at least two of the plurality of second chips 130 have different surface areas.

[0070] Thus, under the condition that the first chip 120 and the substrate chip 110 are bonded, there will be remaining space on the substrate chip 110. Not only can the second chip 130 be placed in the remaining space, but also, if the remaining space cannot meet the space requirements of the first chip 120 (for example, in the direction parallel to the plane where the substrate chip 110 is located, the surface area of ​​the first chip 120 is larger than the surface area of ​​the second chip 130, and combined with the required gap between different chips, it indicates that the remaining space cannot accommodate the first chip 120), the second chip 130, which matches the size of the remaining space, can be placed in the remaining space to achieve the heat dissipation function of the semiconductor structure 100. In this way, by setting a channel 131 on the newly added second chip 130, and the size of the second chip 130 and the structure and size of the channel 131 can be adjusted according to the requirements, it is beneficial to improve the heat dissipation performance of the semiconductor structure 100.

[0071] In some embodiments, such as Figure 9 As shown, the semiconductor structure 100 also includes a top chip 140, which is disposed on the side of the first chip 120 away from the base chip 110, and the top chip 140 covers at least one first chip 120 and at least one second chip 130.

[0072] For example, such as Figure 9 As shown, the top chip 140 can be a functional chip, stacked on the base chip 110 with the first chip. In this way, the second chip 130 can dissipate heat from the multiple first chips 120 disposed on the same layer, as well as the base chip 110 and the top chip 140 located on both sides of the second chip 130 along the first direction X, which is beneficial to improving the heat dissipation efficiency and reliability of the stacked chips.

[0073] This disclosure also provides a method for fabricating a semiconductor structure. Figure 10 Schematic diagram of the method for fabricating the semiconductor structure provided in this disclosure Figure 1 .like Figure 10 As shown, the preparation method includes steps S100 to S600. Figure 11 (a) to (g) are schematic diagrams of the fabrication process of the semiconductor structure provided in this disclosure.

[0074] Step S100: As Figure 11 As shown in (a), a first wafer 10 is formed; the first wafer 10 includes a plurality of bonding regions S1 and a dicing region S2 surrounding the bonding regions S1.

[0075] Step S200: As Figure 11 As shown in (b) of the diagram, a first chip 120 is formed. The first chip 120 includes an integrated circuit. For example, the first chip 120 includes one or more of a laser chip, a radio frequency device chip, or a power device chip. Different first chips 120 may have the same function or different size, and the examples provided in this disclosure do not limit this.

[0076] Step S300: As Figure 11 As shown in (c), an initial second chip 20 is formed, which includes an initial channel 21. An initial opening A1 of the initial channel 21 is located on one side of the initial second chip 20 along a first direction X, and the outline of the initial opening A1 is the same as the cross-sectional shape of the initial channel 21 along a direction parallel to the plane of the initial second chip 20. For example, the initial second chip 20 does not include an integrated circuit.

[0077] Step S400: As Figure 11 As shown in (d), the first chip 120 is disposed in the bonding region S1 and bonded to the first wafer 10. For example, different first chips 120 can be bonded to the first wafer 10 using covalent bonding or hybrid bonding methods.

[0078] Step S500: As Figure 11As shown in (e), the initial second chip 20 and the first chip 120 are disposed on the same side of the substrate chip 110 and spaced apart from the first chip 120; the initial second chip 20 is bonded to the first wafer 10 to obtain a bonding structure 30. The side where the initial opening A1 is located is in contact with the first wafer 10; a portion of the initial second chip 20 is located in the bonding region S1, the other portion of the initial second chip 20 is located in the dicing region S2, and both ends of the initial channel 21 extend to the dicing region S2.

[0079] For example, the initial second chip 20 is placed upside down on the first wafer 10, and the surface where the initial opening A1 of the initial channel 21 is located is in contact with the surface of the first wafer 10; and the two ends of the extension path of the initial channel 21 are located in the dicing area S2.

[0080] Step S600: As Figure 11 As shown in (e), (f), and (g), the bonding structure 30 is cut along the cutting region S2 to obtain the semiconductor structure 100; wherein, the initial second chip 20 after cutting is the second chip 130; the first wafer 10 after cutting is the substrate chip 110; at least one side of the second chip 130 is coplanar with the edge of the substrate chip 110, and the side of the second chip 130 that is coplanar with the edge of the substrate chip 110 is the target side M. The initial channel 21 after cutting includes a first opening A2 and a second opening A3 that extend to both ends of the cutting region S2, and the first opening A2 and the second opening A3 are located on the target side M.

[0081] For example, the bonding structure 30 is cut using a laser cutting process to obtain multiple semiconductor structures 100. The dimensions of the different semiconductor structures 100 can be set according to actual needs.

[0082] In the fabrication method of the semiconductor structure 100 described above, the second chip 130 is provided instead of the channel 131 within the first chip 120. This not only facilitates the layout and extension design of the channel 131 but also allows for the implementation of a heat dissipation structure compatible with the chip-wafer bonding process, simplifying the fabrication process of the semiconductor structure 100. Specifically, since the initial second chip 20 is inverted on the first wafer 10, the surface containing the initial opening A1 of the initial channel 21 is in contact with the first wafer 10. This avoids the problem of the dielectric material subsequently filling the space between the first chip 120 and the initial second chip 20 blocking the initial channel 21, and also avoids the problem of impurities blocking the initial channel 21 during the subsequent thinning of the dielectric material. Furthermore, in the step of cutting the bonding structure, the portion of the initial second chip 20 located in the cutting region S2 is cut, i.e., the initial channel 21 is cut to extend to both ends of the cutting region S2, forming two corresponding openings (e.g., the first opening A2 and the second opening A3), thus obtaining the channel 131. This eliminates the need to separately fabricate the first opening A2 and the second opening A3 of the channel 131, simplifying the fabrication process of the channel 131.

[0083] In some embodiments, Figure 12 A schematic diagram of the structure of an uncut first wafer, a first chip, and an initial second chip provided for embodiments of this disclosure. (See attached diagram.) Figure 12 As shown, multiple semiconductor structures 100 can be diced on a first wafer 10. The number and arrangement of the first chips 120 and the initial second chips 20 on different semiconductor structures 100 can be different. For example, two first chips 120 and one second chip 130 (the initial second chip 20 before dicing) are integrated on a portion of a semiconductor structure 100. A portion of the second chip is located in the bonding region S1, and another portion is located in the dicing region S2. Thus, after dicing the bonding structure 30 along the dicing region extension direction, a first opening A2 and a second opening A3 of a channel 131 are formed on one side of the second chip 130 (e.g., ...). Figure 2 (As shown).

[0084] Alternatively, two first chips 120 and one second chip 130 (the initial second chip 20 before dicing) are integrated on a portion of the semiconductor structure 100. A portion of the second chip is located in the bonding region S1, and the other two portions are located in the dicing region S2. Thus, after dicing the bonding structure 30 along the extension direction of the dicing region S2, the second chip 130 forms a first opening A2 and a second opening A3 of a channel 131 on its opposite side surfaces (e.g., Figure 4 (As shown).

[0085] This disclosure provides, as follows: Figure 11 The process steps of the semiconductor structure 100 shown are to obtain the following: Figure 2 The semiconductor structure shown is used as an example for illustration. Specifically, the formation positions of the first opening A2 and the second opening A3 of the channel 131 of the second chip 130 can be adjusted according to the number of first chips 120 and the relative positions of the multiple first chips 120 and the second chip 130. The example provided in this disclosure does not limit this.

[0086] Figure 13 Schematic diagram of the method for fabricating the semiconductor structure provided in this disclosure Figure 2 . Figure 14 (a) to (d) are schematic diagrams of the fabrication process of the initial second chip provided in this disclosure.

[0087] In some embodiments, such as Figure 13 As shown, the above step S300 includes: steps S310 to S330.

[0088] Step S310: As Figure 14 As shown in (a) and (b), a substrate 40 is provided; the substrate 40 includes a plurality of etched regions S3. For example, the substrate 40 may be a silicon substrate.

[0089] Step S320: As Figure 14 As shown in (b), an initial channel 21 is formed within each etched region S3; the initial channel 21 includes a continuous convex-concave structure and is located within the etched region S3. For example, the initial channel 21 is a continuous groove structure located within the etched region S3, and the opening of the groove structure is the initial opening A1.

[0090] Step S330: As Figure 14 As shown in (c) and (d), the substrate 40 is cut along the edge of the etched area S3 to obtain the initial second chip 20.

[0091] For example, a substrate 40 with an initial channel 21 is placed upside down on a support plate, and the substrate 40 is cut along the edge of the etched area S3 to obtain multiple initial second chips 20. In this way, the flat surface of the initial second chip 20 is on top. Based on the flatness of the force-bearing surface and the large force-bearing area, it is easier to pick up the initial second chip 20 subsequently, thus improving the reliability of picking up the initial second chip 20.

[0092] In some embodiments, such as Figure 13 As shown, the above step S100 includes: steps S110 to S130.

[0093] Step S110: Provide a first initial wafer. For example, the first initial wafer is a 6-inch or 8-inch circular semiconductor material film.

[0094] Step S120: Form the first functional layer 112 on the first initial wafer (see...) Figure 7 For example, the first functional layer 112 may include one or more stacked functional layers. For instance, multiple functional layers may include films such as a first electrode, a second electrode, and a waveguide layer disposed on the second initial wafer, and this disclosure is not limited thereto. For example, multiple functional layers may be formed using a deposition process.

[0095] Step S130: Form a first interconnect layer 113 on the first functional layer 112 (see...) Figure 7 ), to obtain the first wafer 10. For example, using a deposition process and sputtering and electroplating processes, a dielectric layer and a conductive structure for electrical connection with other chips are formed on the side of the first functional layer 112 away from the first initial wafer, forming the first interconnect layer 113, to obtain the first wafer 10 (e.g. Figure 11 As shown in (a), the conductive structure within the first interconnect layer 113 that interconnects with the first chip 120 is not shown.

[0096] Continue reading Figure 13 The above step S200 includes: steps S210 to S230.

[0097] Step S210: Provide a second initial wafer.

[0098] Step S220: Form the second functional layer 122 on the second initial wafer (see...) Figure 7 ).

[0099] Step S230: Form a second interconnect layer 123 on the second functional layer to obtain the first chip 120 (see...) Figure 7 ).

[0100] The steps for forming the first chip 120 described above can be the same as the steps for forming the first wafer 10. The specific structures of the functional layers and interconnect layers can be different. The examples provided in this disclosure do not limit this and can be set according to the actual situation.

[0101] In some embodiments, such as Figure 13 As shown, step S400 above includes step S410.

[0102] Step S410: As Figure 11 (d) and Figure 7 As shown, the first chip 120 is disposed in the bonding region S1, and the first interconnect layer 113 is coupled to the second interconnect layer 123.

[0103] For example, the first chip 120 is disposed in the bonding region S1 of the first wafer 10, and the first interconnect layer 113 of the first chip 120 is coupled to the second interconnect layer 123 of the first wafer (i.e., the substrate chip 110).

[0104] Continue reading Figure 13 The above step S500 includes steps S510 and S520.

[0105] Step S510: As Figure 11 As shown in (d), after the initial second chip 20 is placed on one side of the first chip 120, the gap between the first chip 120 and the initial second chip 20 is filled to obtain the initial semiconductor structure 50.

[0106] For example, the initial second chip 20 is disposed on one side of the first chip 120. Since the initial second chip 20 is inverted on the first wafer 10, the initial opening A1 of the initial channel 21 of the initial second chip 20 contacts the first wafer 10, thus avoiding the problem of the filling dielectric material clogging the initial channel 21. A portion of the initial second chip 20 is located in the bonding region S1, and the other portion is located in the dicing region S2, with the opposite ends of the initial channel 21 located in the dicing region S2 (see...). Figure 12 ).

[0107] Step S520: As Figure 11 As shown in (e), the initial semiconductor structure 50 is thinned on the side away from the first wafer 10 to obtain the bonding structure 30.

[0108] For example, such as Figure 11 As shown in (e), a chemical mechanical polishing process can be used to thin the side of the dielectric material filling between the first chip 120 and the initial second chip 20 away from the first wafer 10, and to planarize the surface of the initial semiconductor structure 50, resulting in a bonding structure 30. Since the initial second chip 20 is inverted on the first wafer 10, the initial opening A1 of the initial channel 21 of the initial second chip 20 is in contact with the first wafer 10, which avoids the problem of the dielectric material clogging the initial channel 21 during the thinning process.

[0109] In some embodiments, prior to step S600 described above, the semiconductor structure 100 further includes forming a top chip 140 (see [reference]). Figure 9 The top chip 140 is disposed on the side of the first chip 120 away from the base chip 110, and the top chip 140 covers at least one first chip 120 and at least one second chip 130.

[0110] For example, in Figure 11 After step (e) shown in the figure and in the following Figure 11 Prior to step (f) shown in the diagram, a top chip 140 is formed on one side of the initial semiconductor structure 50. The top chip 140 can be a chip with the same structure and process as the first chip 120; the examples provided in this disclosure do not limit the structure of the top chip 140. Thus, the second chip 130 can dissipate heat from the multiple first chips 120 disposed on the same layer, as well as the substrate chips 110 and top chip 140 located on both sides of the second chip 130 along the first direction X, thereby improving the heat dissipation efficiency and reliability of the stacked chips.

[0111] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0112] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Base chip; A first chip is bonded to the substrate chip; the first chip includes an integrated circuit. The second chip is located on the same side of the substrate chip as the first chip and is spaced apart from the first chip; the second chip includes a channel; the channel includes an inner wall partially formed by a portion of the surface of the substrate chip; the channel includes a first opening and a second opening; at least one side of the second chip is coplanar with the edge of the substrate chip, the side of the second chip coplanar with the edge of the substrate chip is a target side, and the first opening and the second opening are located on the target side.

2. The semiconductor structure according to claim 1, characterized in that, The target side includes a first side; The first opening and the second opening are located on the first side.

3. The semiconductor structure according to claim 2, characterized in that, The second chip includes multiple channels; The first opening and the second opening of the plurality of channels are both located on the first side of the second chip.

4. The semiconductor structure according to claim 1, characterized in that, The target side includes a first side and a second side; the first opening is located on the first side, and the second opening is located on the second side.

5. The semiconductor structure according to claim 4, characterized in that, The second chip includes multiple channels; The first openings of the plurality of channels are all located on the first side, and the second openings of the plurality of channels are all located on the second side.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The channel is a continuous convex-concave curve parallel to the plane of the substrate chip.

7. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The substrate chip includes a first semiconductor substrate and a first functional layer and a first interconnect layer located on the first semiconductor substrate; The first chip includes a second semiconductor substrate and a second functional layer and a second interconnect layer located on the second semiconductor substrate; The first interconnect layer is coupled to the second interconnect layer; along the direction perpendicular to the plane of the substrate chip, the size of the channel is greater than the sum of the sizes of the second functional layer and the second interconnect layer.

8. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The surface area of ​​the first chip is larger than the surface area of ​​the second chip; The semiconductor structure includes a plurality of second chips, at least two of which have different surface areas.

9. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The semiconductor structure further includes a top chip disposed on the side of the first chip away from the base chip, and the top chip covers at least one of the first chip and at least one of the second chip.

10. A method for fabricating a semiconductor structure, characterized in that, include: A first wafer is formed; the first wafer includes a plurality of bonding regions and a dicing region surrounding the bonding regions; A first chip is formed, the first chip including an integrated circuit; An initial second chip is formed; the initial second chip includes an initial channel; the initial opening of the initial channel is located on one side of the initial second chip, and the outline of the initial opening is the same as the cross-sectional shape of the initial channel along the direction parallel to the plane where the initial second chip is located; The first chip is disposed in the bonding area and bonded to the first wafer; The initial second chip and the first chip are disposed on the same side of the first wafer, and are spaced apart from the first chip; the initial second chip is bonded to the first wafer to obtain a bonding structure; the side where the initial opening is located is in contact with the first wafer; A portion of the initial second chip is located in the bonding region, other portions of the initial second chip are located in the dicing region, and both ends of the initial channel extend to the dicing region; The bonding structure is cut along the cutting region to obtain a semiconductor structure; wherein, the initial second chip after cutting is a second chip; the first wafer after cutting is a substrate chip; at least one side of the second chip is coplanar with the edge of the substrate chip, and the side of the second chip that is coplanar with the edge of the substrate chip is a target side; the initial channel after cutting includes a first opening and a second opening that extend to both ends of the cutting region, and the first opening and the second opening are located on the target side.

11. The preparation method according to claim 10, characterized in that, The formation of the initial second chip includes: A substrate is provided; the substrate includes a plurality of etched regions; An initial channel is formed within each of the etched areas; the initial channel includes a continuous uneven structure and is located within the etched area; The substrate is cut along the edge of the etched area to obtain the initial second chip.

12. The preparation method according to claim 10, characterized in that, The formation of the first wafer includes: Provide the first initial wafer; A first functional layer is formed on the first initial wafer; A first interconnect layer is formed on the first functional layer to obtain the first wafer; The formation of the first chip includes: Provide a second initial wafer; A second functional layer is formed on the second initial wafer; A second interconnect layer is formed on the second functional layer to obtain the first chip.

13. The preparation method according to claim 12, characterized in that, The step of placing the first chip in the bonding region and bonding it to the first wafer includes: The first chip is disposed in the bonding region, and the first interconnect layer is coupled to the second interconnect layer; The step of placing the initial second chip on one side of the first chip and bonding it to the first wafer to obtain a bonding structure includes: After placing the initial second chip on one side of the first chip, the gap between the first chip and the initial second chip is filled to obtain an initial semiconductor structure; The bonding structure is obtained by thinning the side of the initial semiconductor structure away from the first wafer.

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