Alignment mark manufacturing method of light emitting chip and manufacturing method of display backplane

Abstract

This application discloses a method for fabricating alignment marks for a light-emitting chip and a method for manufacturing a display backplane, comprising: providing a driving substrate and depositing a first bonding metal layer on the surface of the driving substrate; processing the first bonding metal layer located in the marking area into a plurality of spaced alignment mark points; providing an epitaxial wafer, the epitaxial wafer comprising a substrate, a buffer layer and an epitaxial layer stacked sequentially, and depositing a first electrode layer and a second bonding metal layer sequentially on the side of the epitaxial layer away from the substrate; bonding the epitaxial wafer to the driving substrate under a preset temperature and pressure, causing the stacked structure of the epitaxial wafer away from the marking area and the driving substrate to be bonded together and located above the marking area to undergo metal brittle fracture; removing the substrate and the buffer layer to expose the epitaxial layer; and removing the fractured stacked structure above the alignment mark points to expose the plurality of alignment mark points. This method for fabricating alignment marks reduces problems such as misalignment or repeated blind exposure caused by blind exposure, and improves manufacturing efficiency and yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating alignment marks for a light-emitting chip and a method for manufacturing a display backplane. Background Technology

[0002] There are currently two fabrication methods for vertically oriented light-emitting chips: Chip Bond and Wafer Bond. Chip Bond involves first creating a pattern on an epitaxial wafer, then aligning and bonding it to a driver backplane. This approach places extremely high demands on bonding technology, and with miniaturization, alignment bonding carries risks such as incomplete transfer and chip damage. Wafer Bond involves surface bonding a sapphire-based epitaxial wafer to a silicon-based driver backplane, flipping the epitaxial layer onto the silicon backplane, and then fabricating patterns on the epitaxial layer to obtain a micro-display device, resulting in higher integration. Before bonding, alignment marks need to be protected to complete subsequent pattern overlay. Currently, the well-known method for protecting alignment marks is blind exposure and etching to expose them. However, blind exposure during manufacturing can lead to misalignment, which is unpredictable and undetectable. If the misalignment extends to the die area, it directly results in wasted exposure (shot), requiring repeated blind exposure and etching until the alignment marks are exposed, significantly reducing manufacturing efficiency and yield. Summary of the Invention

[0003] In view of the shortcomings of the above-mentioned related technologies, the purpose of this application is to provide a method for making alignment marks for light-emitting chips and a method for manufacturing display backplanes, so as to reduce problems such as offset or repeated blind exposure caused by blind exposure, and improve manufacturing efficiency and yield.

[0004] This application provides a method for fabricating alignment marks on a light-emitting chip, the steps of which include: A driving substrate and an epitaxial wafer are provided. The epitaxial wafer includes a substrate, a buffer layer and an epitaxial layer stacked sequentially. A first electrode layer and a second bonding metal layer are stacked sequentially on the side of the epitaxial layer away from the substrate. A first bonding metal layer is disposed on the surface of the driving substrate. The driving substrate includes a display area and a non-display area. The non-display area includes a marking area. The first bonding metal layer located in the marking area is processed to form a plurality of spaced alignment marking points; Under preset temperature and preset pressure, the epitaxial wafer and the driving substrate are bonded together by the second bonding metal layer and the first bonding metal layer, causing the stacked structure of the epitaxial wafer and the driving substrate, which is far from the marked area and located above the marked area, to undergo metal embrittlement fracture; the stacked structure includes the second bonding metal layer, the first electrode layer and the epitaxial layer stacked in sequence. Remove the substrate and buffer layer to expose the epitaxial layer; Remove the broken layered structure above the alignment mark to expose multiple alignment mark points used for pattern overlay alignment in each process segment.

[0005] Optionally, both the first bonding metal layer and the second bonding metal layer include an adhesive layer, a barrier layer and a diffusion layer stacked sequentially.

[0006] Optionally, the barrier layer includes at least one of a Ti barrier layer, a Pt barrier layer, a Ni barrier layer, and an Al barrier layer.

[0007] Optionally, the diffusion layer includes at least two of the following: Au metal layer, Sn metal layer, Ag metal layer, Cu metal layer, Al metal layer, and Pb metal layer.

[0008] Optionally, the material of the adhesive layer includes at least one of Cr adhesive layer and Ti adhesive layer.

[0009] Optionally, removing the broken stacked structure above the alignment mark includes performing the following steps: The layered structure that broke above the alignment mark was removed by blue film adhesion.

[0010] Optionally, the step of processing the first bonding metal layer located in the marking area to form a plurality of spaced alignment marks includes performing the following steps: depositing the first bonding metal layer on the driving substrate by vapor deposition, and after vapor deposition, removing the first bonding metal layer around the alignment marks on the driving substrate by a gold stripping machine to form a plurality of spaced alignment marks.

[0011] Optionally, the alignment markers may include at least one of circles, squares, letters, and irregular shapes.

[0012] Optionally, the preset pressure ranges from 6000KG to 12000KG, and the preset temperature ranges from 260℃ to 320℃.

[0013] This application also provides a method for manufacturing a display backplane, the steps of which include: preparing a plurality of alignment mark points, wherein the alignment mark points are obtained by the alignment mark fabrication method of the light-emitting chip; fabricating the bonded driving substrate through multiple process segments to obtain an LED chip, wherein the film layer patterning in each process segment is obtained by respectively grasping the corresponding alignment mark points and aligning the corresponding mask with the driving substrate to perform pattern overlay; the multiple process segments include a mesa process segment, a bonding metal etching process segment, a passivation layer process segment, and an electrode process segment.

[0014] The method for fabricating alignment marks for light-emitting chips and the method for manufacturing display backplanes disclosed in this application involve fabricating alignment marks on a bonding metal layer. During bonding, the bonding metal layer forms an alloy, causing metal brittleness, which breaks the stacked structure above the alignment marks. After removing the substrate, the alignment marks are taken away to expose them. This reduces problems such as misalignment or repeated blind exposure caused by blind exposure, and improves manufacturing efficiency and yield. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure for aligning the first bonding metal layer with the marker points, provided in an embodiment of this application. Figure 2 This is a schematic diagram of the structure of an epitaxial wafer having a first electrode layer and a second bonding metal layer provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the first bonding metal layer provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the second bonding metal layer provided in an embodiment of this application; Figure 5 This is a schematic diagram of the bonding structure between the epitaxial wafer and the driving substrate provided in an embodiment of this application; Figure 6 A schematic diagram of the structure with the substrate and buffer layer (not shown) removed, provided for an embodiment of this application; Figure 7 This is a schematic diagram of the structure for removing the fractured laminated structure provided in an embodiment of this application; Figure 8 This is a schematic diagram of the alignment of marker points within the marked area provided in the embodiments of this application; Figure 9 A flowchart illustrating the method for fabricating alignment marks for a light-emitting chip according to an embodiment of this application; Figure 10 A flowchart illustrating a method for manufacturing a display backplate provided in an embodiment of this application; Figure 11 A schematic diagram of a tabletop process section provided in an embodiment of this application; Figure 12 A schematic diagram of a passivation layer process segment provided in an embodiment of this application; Figure 13 A schematic diagram of removing the mezzanine planarization layer in a planarization process segment provided in an embodiment of this application; Figure 14 A schematic diagram of an exposed platform in a planarization process section provided in an embodiment of this application; Figure 15 This is a schematic diagram showing the removal of the non-display area epitaxial layer according to an embodiment of this application; Figure 16 This is a schematic diagram of the preparation of a common electrode according to an embodiment of this application; Figure 17 This is a schematic diagram of the formation of a control electrode according to an embodiment of this application.

[0016] Explanation of reference numerals in the attached figures: 1-Driving substrate; 1C-Marking area; 2-First bonding metal layer; 21-Alignment mark; 3-Epiaxial wafer; 31-Substrate; 32-Epiaxial layer; 321-Sub-epiaxial layer; 4-First electrode layer; 5-Second bonding metal layer; C-Layered structure; N1-Adhesive layer; N2-Barrier layer; N3-Eurometallic diffusion layer; 6-Passivation layer; 7-Planarization layer; 8-Common electrode layer; P1-First pad; P2-Second pad; P3-Third pad. Detailed Implementation

[0017] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0019] In the description of this application, the terms "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0022] See Figures 1 to 9 As shown in the figure, this application discloses a method for fabricating alignment marks for a light-emitting chip, the steps of which include: A driving substrate 1 and an epitaxial wafer 3 are provided. The epitaxial wafer 3 includes a substrate 31, a buffer layer and an epitaxial layer 32 stacked sequentially. A first electrode layer 4 and a second bonding metal layer 5 are stacked sequentially on the side of the epitaxial layer 32 away from the substrate 31. A first bonding metal layer 2 is disposed on the surface of the driving substrate 1. The driving substrate 1 includes a display area and a non-display area. The non-display area includes a marking area 1C. The first bonding metal layer 2 located in the marking region 1C is processed to form a plurality of spaced alignment marking points 21; Under preset temperature and preset pressure, the epitaxial wafer 3 is bonded to the driving substrate 1 through the second bonding metal layer 5 and the first bonding metal layer 2, causing the stacked structure C, which is located above the marking region 1C and bonded to the driving substrate 1, to undergo metal embrittlement fracture; the stacked structure C includes the second bonding metal layer 5, the first electrode layer 4 and the epitaxial layer 32 stacked sequentially. Remove the substrate 31 and the buffer layer to expose the epitaxial layer 32; Remove the broken layered structure C above the alignment mark point 21 to expose multiple alignment mark points 21 used for pattern overlay alignment in each process segment.

[0023] The method for fabricating alignment marks for light-emitting chips and the method for manufacturing display backplanes disclosed in this application involve fabricating alignment marks 21 on a bonding metal layer. During bonding, the bonding metal layer forms an alloy, causing metal brittleness, which breaks the stacked structure C above the alignment marks 21. After removing the substrate, the C is taken away to expose the alignment marks 21. This reduces problems such as misalignment or repeated blind exposure caused by blind exposure, and improves manufacturing efficiency and yield.

[0024] Because the first bonded metal layer 2 has reflective properties, it is more conducive to identifying the alignment mark point 21. See also Figure 2 As shown, the second bonding metal layer 5 can be deposited on the epitaxial wafer 3 by vapor deposition. The bonding metal layer includes a first bonding metal layer 2 and a second bonding metal layer 5; the second bonding metal layer 5 bonds with the first bonding metal layer 2 to form a metal bonding layer. An excimer laser or solid-state laser is used to separate the substrate 31 from the epitaxial layer 32, removing the substrate 31 and flipping the epitaxial layer 32 onto the driving substrate 1. The buffer layer and other components can be removed by ICP dry etching, using a full-surface etching process with gases such as Ar / Cl2 / BCl3, exposing the epitaxial layer 32.

[0025] See Figure 1As shown, the process of forming a plurality of spaced alignment marks 21 by processing the first bonding metal layer 2 located in the marking region 1C includes performing the following steps: depositing the first bonding metal layer 2 on the driving substrate 1 by vapor deposition, and after vapor deposition, removing the first bonding metal layer 2 around the alignment marks 21 on the driving substrate 1 by a gold stripping machine to form a plurality of spaced alignment marks 21; or, patterning the first bonding metal layer 2 by patterning photoresist to form a plurality of spaced alignment marks 21.

[0026] In this embodiment, the epitaxial layer 32 can be a single-color epitaxial layer or a multi-color stacked epitaxial layer. For example, the epitaxial layer 32 can be a red epitaxial layer, a green epitaxial layer, or a blue epitaxial layer; the epitaxial layer 32 can also be a two-color stacked epitaxial layer or a three-color stacked epitaxial layer. The two-color stacked epitaxial layer includes a blue-green stacked epitaxial layer, a red-green stacked epitaxial layer, and a red-blue stacked epitaxial layer. The three-color stacked epitaxial layer includes a red-green-blue stacked epitaxial layer and a red-green-violet stacked epitaxial layer. The epitaxial layer 32 can be selected as needed and is not limited here.

[0027] See Figure 3 and Figure 4 As shown, both the first bonding metal layer 2 and the second bonding metal layer 5 include an adhesive layer N1, a barrier layer N2, and a eutectic alloy diffusion layer N3 stacked sequentially. The first bonding metal layer 2 and the second bonding metal layer 5 have multiple structures, which form an alloy during bonding. Therefore, metal brittleness occurs around the bonding markers during bonding, and the stacked structure C above the bonding markers is crushed. The eutectic alloy diffusion layer N3 can be made of a series of metals capable of forming a eutectic alloy system, i.e., an alloy system that undergoes a eutectic transformation during crystallization. The conditions can be set starting from the eutectic point in the binary metal phase diagram.

[0028] In this embodiment, the barrier layer N2 includes at least one of a Ti barrier layer, a Pt barrier layer, a Ni barrier layer, and an Al barrier layer. The barrier layer N2 can be a single-layer structure or a multi-layer structure, which is not limited here and can be selected according to actual needs.

[0029] In this embodiment, the eutectic alloy diffusion layer N3 includes at least two of the following: Au metal layer, Sn metal layer, Ag metal layer, Cu metal layer, Al metal layer, and Pb metal layer. This is not limited to these two types, and other metal layers may also be included, which will not be elaborated upon here. Exemplarily, the eutectic alloy diffusion layer N3 is a multilayer structure including Au metal layers and Sn metal layers. Both the first bonding metal layer 2 and the second bonding metal layer 5 are AuSnAu eutectic alloy diffusion layers N3. Bonding involves pressure and temperature increases, and an AnSn alloy will form under high temperature and pressure. The AuSnAu structure consists of two Au metal layers and one Sn metal layer located between the two Au metal layers. This is not a limitation, and combinations can be selected according to actual needs.

[0030] In this embodiment, the material of the adhesive layer N1 includes at least one of Cr adhesive layer and Ti adhesive layer. The adhesive layer N1 can be a single-layer structure or a multi-layer structure, which is not limited here and can be selected according to actual needs.

[0031] See Figure 6 As shown, removing the broken layered structure C above the alignment mark 21 includes performing the following steps: The layered structure C that broke above the alignment mark 21 was removed by blue film adhesion.

[0032] In this embodiment, the first electrode layer 4 is ITO. The thickness of the first electrode layer 4 ranges from 1000 Å to 1300 Å. In some embodiments, the first electrode layer 4 may be an electrode made of a metallic material, which can be selected according to actual needs and is not limited here.

[0033] In this embodiment, the alignment mark 21 includes at least one of circles, squares, letters, and irregular shapes.

[0034] In this embodiment, the preset pressure ranges from 6000KG to 12000KG, and the preset temperature ranges from 260℃ to 320℃.

[0035] See Figures 1 to 10 As shown, this application discloses a method for manufacturing a display backplane, the steps of which include: preparing a plurality of alignment marks 21, wherein the alignment marks 21 are obtained by the above-mentioned method for fabricating alignment marks of light-emitting chips; fabricating an LED chip by performing multiple process segments on the bonded driving substrate 1, wherein the film layer patterning in each process segment is obtained by respectively grasping the corresponding alignment marks 21, aligning the corresponding mask with the driving substrate 1, and performing pattern overlay; the multiple process segments include a mesa process segment, a bonding metal etching process segment, a passivation layer process segment, and an electrode process segment. For example, Figure 10The marking area 1C has four types of alignment markers 21, which can be used to accurately identify the corresponding alignment markers 21 in different process sections, thereby improving the accuracy of film patterning in each process section.

[0036] The coating layers in each process stage have a certain degree of transparency and will not affect the identification of alignment mark 21, so alignment mark 21 is generally not etched.

[0037] For example, in this embodiment, the LED chip is obtained by fabricating the bonded driving substrate 1 through multiple process stages. The patterning of the film layer in each process stage is obtained by grabbing the corresponding alignment mark points 21 and aligning the corresponding mask with the driving substrate 1 to perform pattern overlay. The multiple process stages include a mesa process stage, a bonding metal etching process stage, a passivation layer process stage, and an electrode process stage, and include the following steps: The steps of the mesa process segment and the bonding metal etching process segment include: setting a seventh photoresist layer on the epitaxial layer 32 on the bonded driving substrate 1, picking up the corresponding seventh alignment mark points, aligning the corresponding seventh mask with the driving substrate 1, patterning the seventh photoresist layer, etching the epitaxial layer 32 up to the driving substrate 1, obtaining multiple sub-epitaxy layers 321 with a stepped structure and first sub-electrodes corresponding one-to-one with the sub-epitaxy layers 321; removing the patterned seventh photoresist layer; the alignment mark point 21 includes the seventh alignment mark point, and the mask includes the seventh mask; The passivation layer process includes the following steps: depositing a passivation layer 6, setting an eighth photoresist layer on the surface of the passivation layer 6, picking up the corresponding eighth alignment marks, aligning the corresponding eighth mask with the driving substrate 1, patterning the eighth photoresist layer, etching the passivation layer 6 around each sub-epipolar layer 321 and opening holes on the mesa of the sub-epipolar layer 321, so that the passivation layer 6 covers the outer wall of the sub-epipolar layer 321, the driving substrate 1 around the sub-epipolar layer 321, and the mesa of the exposed sub-epipolar layer 321; The electrode process includes the following steps: depositing a common electrode layer 8 to connect each sub-epipolar layer 321; setting a ninth photoresist layer on the surface of the common electrode layer 8; picking up the corresponding ninth alignment marks; aligning the corresponding ninth mask with the driving substrate 1; patterning the ninth photoresist layer; etching the common electrode layer 8 around each sub-epipolar layer 321 to form a groove; connecting the common electrode layer 8 with the driving substrate 1 to achieve chip conduction; and the driving substrate 1 can drive each light-emitting structure individually or control it row-wise or column-wise to display the light emission.

[0038] In this embodiment, the multiple process segments also include a planarization layer 7 process segment.

[0039] For example, see Figures 11 to 17As shown, the LED chip is obtained by fabricating the bonded driving substrate 1 through multiple process stages. The patterning of the film layer in each process stage is obtained by grabbing the corresponding alignment mark points 21 and aligning the corresponding mask with the driving substrate 1 to perform pattern overlay. The multiple process stages include a mesa process stage, a bonding metal etching process stage, a passivation layer 6 process stage, and an electrode process stage. The multiple process stages also include a planarization layer 7 process stage, which includes the following steps: The mesa process section includes the following steps: depositing a first photoresist layer on the epitaxial layer 32 on the bonded driving substrate 1; grasping the corresponding first alignment mark points; aligning the corresponding first mask with the driving substrate 1; patterning the first photoresist layer; etching the epitaxial layer 32 up to the first electrode layer 4 to obtain multiple sub-epitaxy layers 321 with a stepped structure; and removing the patterned first photoresist layer. The alignment mark points 21 include first alignment mark points, and the mask includes a first mask, such as... Figure 11 As shown, the first photoresist layer disposed on the epitaxial layer 32 is patterned by grabbing the corresponding first alignment mark point, aligning the corresponding mask with the preset pattern on the driving substrate 1 and exposing it, so that the first photoresist layer forms a pattern complementary to the recessed area at the position corresponding to the recessed area. After development, the epitaxial layer 32 in the groove is etched by ICP dry etching, and the sub-epitaxy layer 321 is isolated to the first electrode layer 4.

[0040] The bonding metal etching process segment and the passivation layer 6 process segment include the following steps: See [link to relevant documentation] Figure 12 As shown, a passivation layer 6 is deposited, a second photoresist layer is formed on the surface of the passivation layer 6, corresponding second alignment marks 21 are picked up, the corresponding second mask is aligned with the driving substrate 1, the second photoresist layer is patterned, and the passivation layer 6 around each sub-epitaxial layer 321 is etched up to the driving substrate 1 to divide the first electrode layer 4 into first sub-electrodes corresponding one-to-one with the sub-epitaxial layer 321 and sub-passivation layers 6 covering the outer wall of the sub-epitaxial layer 321. A first pad P1 corresponding one-to-one with the first sub-electrodes is formed on the display area of ​​the driving substrate 1; the patterned first... Two photoresist layers; wherein, the outer wall of the sub-epitaxial layer 321 includes the sidewall and mesa of the sub-epitaxial layer 321, the alignment mark point 21 further includes a second alignment mark point, and the mask further includes a second mask; a passivation layer 6 is deposited by PECVD to passivate the sidewall of the sub-epitaxial layer 321, a second photoresist layer of uniform thickness is spin-coated on the surface of the passivation layer 6, the second photoresist layer is patterned, and the passivation layer 6, the first electrode layer 4 and the metal bonding layer in the groove are etched by ICP dry etching, so that the first electrode layer 4 and the metal bonding layer under each sub-epitaxial layer 321 are disconnected, forming an independent P electrode for each pixel.

[0041] See Figure 13 and Figure 14 As shown, the planarization layer 7 process includes the following steps: depositing the planarization layer 7; depositing a third photoresist layer on the surface of the planarization layer 7; picking up corresponding third alignment marks; aligning the corresponding third mask with the driving substrate 1; patterning the third photoresist layer; etching the planarization layer 7 down to the mesa of the sub-epitaxial layer 321 to expose the sub-epitaxial layer 321; and removing the patterned third photoresist layer. The alignment marks 21 also include the third alignment marks, and the mask also includes the third mask. The planarization layer 7 is deposited using ALD to passivate the sidewalls of the sub-epitaxial layer 321 to prevent damage to the sidewall passivation layer 6 caused by dry etching, which could lead to GaN exposure and leakage, short circuits, etc. The third photoresist layer is spin-coated onto the surface of the planarization layer 7, patterned, and then etched away the planarization layer 7 down to the mesa of the sub-epitaxial layer 321 using ICP dry etching to expose the mesa of the sub-epitaxial layer 321.

[0042] The electrode process segment includes the following steps: (See below) Figure 15 As shown, a fourth photoresist layer is formed on the surface of the planarization layer 7. The corresponding fourth alignment mark is picked up, and the corresponding fourth mask is aligned with the driving substrate 1. The fourth photoresist layer is patterned, and the layer structure on the non-display area of ​​the driving substrate 1 is etched away to expose the second pad P2 and the third pad P3 located on the non-display area of ​​the driving substrate 1 for power input. The second pad P2 and the third pad P3 have different polarities, and the second pad P2 is connected to the first pad P1. The patterned fourth photoresist layer is removed. The fourth photoresist layer, planarization layer 7, passivation layer 6, sub-epipolar layer 321, first electrode layer 4 and bonding metal layer around the display area (AA) on the driving substrate 1 are etched by ICP dry etching to expose the cathode ring and anode ring on the surface of the driving substrate 1.

[0043] See Figure 16 As shown, a common electrode layer 8 is disposed on the third pad P3, the planarization layer 7, and the exposed sub-epitaxial layer 321. A fifth photoresist layer is disposed on the surface of the common electrode layer 8. The corresponding fifth alignment mark points are picked up, and the corresponding fifth mask is aligned with the driving substrate 1. The fifth photoresist layer is patterned, and the non-display area of ​​the driving substrate 1 is etched to expose the second pad P2 and connect each of the sub-epitaxial layers 321 to the third pad P3 through the common electrode layer 8. The patterned fifth photoresist layer is then removed. See Figure 17As shown, a sixth photoresist layer is formed on the driving substrate 1. This sixth photoresist layer is located on the side of the common electrode layer 8 away from the driving substrate 1. A corresponding sixth alignment mark is picked up, and the corresponding sixth mask is aligned with the driving substrate 1. The sixth photoresist layer is patterned to expose the second pad P2, and a control electrode is formed on the exposed second pad P2. The patterned sixth photoresist layer is then removed. The alignment mark 21 also includes the fourth, fifth, and sixth alignment marks, and the mask also includes the fourth, fifth, and sixth masks. After patterning the sixth photoresist layer, a control electrode is deposited by vapor deposition. The control electrode is made of a metal material, including at least one of Cr, Al, Ti, Pt, and Au. After the control electrode is deposited, a blue film adheres to remove the metal outside the pattern, completing the fabrication of the P electrode.

[0044] The first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth photoresist layers are all applied by spin coating.

[0045] Wherein, the first photoresist layer, the second photoresist layer, the third photoresist layer, the fourth photoresist layer, the fifth photoresist layer, the seventh photoresist layer, the eighth photoresist layer, and the ninth photoresist layer are all positive photoresists, and the sixth photoresist layer is a negative photoresist layer.

[0046] In this embodiment, all common electrode layers 8 are ITO. In some embodiments, the first electrode layer 4 and the common electrode layer 8 can be electrodes made of metallic materials, and the choice is made according to actual needs, without limitation.

[0047] In this embodiment, the passivation layer 6 includes at least one of SiO2, silicon nitride, silicon oxide, and silicon oxynitride, but is not limited thereto.

[0048] In this embodiment, the planarization layer 7 includes at least one of Al2O3, SiO2, silicon nitride, silicon oxide, and silicon oxynitride, but is not limited thereto.

[0049] In this embodiment, the display back panel can be used as a direct display or a backlight, and is not limited thereto.

[0050] In this embodiment, the driving substrate 1 can be a circuit board, an array substrate, a glass driving substrate, a flexible driving substrate, a lamp board, a semiconductor driving substrate, or other types of driving substrates, and is not specifically limited in this embodiment; the material of the driving substrate 1 can be glass, transparent plastic, acrylic, quartz, sapphire, semiconductor materials, etc., and can be selected according to the actual situation, and is not specifically limited in this embodiment.

[0051] In this embodiment, the LED chip can be a MiniLED, MicroLED, nano-sized LED, or LED of other sizes. No limitation is made here, and the specific selection can be made according to the actual situation.

[0052] As one implementation method, the display back panel can be a TV, VR / AR device, smart wearable device, mobile phone, vehicle display, etc.

[0053] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for fabricating alignment marks for a light-emitting chip, characterized in that the steps include... include: A driving substrate and an epitaxial wafer are provided. The epitaxial wafer includes a substrate, a buffer layer and an epitaxial layer stacked sequentially. A first electrode layer and a second bonding metal layer are stacked sequentially on the side of the epitaxial layer away from the substrate. A first bonding metal layer is disposed on the surface of the driving substrate. The driving substrate includes a display area and a non-display area. The non-display area includes a marking area. The first bonding metal layer located in the marking area is processed to form a plurality of spaced alignment marking points; Under preset temperature and preset pressure, the epitaxial wafer and the driving substrate are bonded together by the second bonding metal layer and the first bonding metal layer, causing the stacked structure of the epitaxial wafer and the driving substrate, which is far from the marked area and located above the marked area, to undergo metal embrittlement fracture; the stacked structure includes the second bonding metal layer, the first electrode layer and the epitaxial layer stacked in sequence. Remove the substrate and the buffer layer to expose the epitaxial layer; Remove the broken layered structure above the alignment mark to expose multiple alignment mark points used for pattern overlay alignment in each process segment.

2. The method for fabricating alignment marks for a light-emitting chip as described in claim 1, characterized in that, Both the first bonding metal layer and the second bonding metal layer include an adhesive layer, a barrier layer and a diffusion layer stacked sequentially.

3. The method for fabricating alignment marks for a light-emitting chip as described in claim 2, characterized in that, The barrier layer includes at least one of a Ti barrier layer, a Pt barrier layer, a Ni barrier layer, and an Al barrier layer.

4. The method for fabricating alignment marks for a light-emitting chip as described in claim 2 or 3, characterized in that, The diffusion layer includes at least two of the following: Au metal layer, Sn metal layer, Ag metal layer, Cu metal layer, Al metal layer, and Pb metal layer.

5. The method for fabricating alignment marks for a light-emitting chip as described in claim 4, characterized in that, The adhesive layer is made of at least one of Cr adhesive layer and Ti adhesive layer.

6. The method for fabricating alignment marks for a light-emitting chip as described in claim 1, 2, 3, or 5, characterized in that, Removing the broken stacked structure above the alignment mark includes performing the following steps: The layered structure that broke above the alignment mark was removed by blue film adhesion.

7. The method for fabricating alignment marks for a light-emitting chip as described in claim 1, 2, 3, or 5, characterized in that, The step of processing the first bonding metal layer located in the marking area to form a plurality of spaced alignment marks includes performing the following steps: depositing the first bonding metal layer on the driving substrate by vapor deposition, and after vapor deposition, removing the first bonding metal layer around the alignment marks on the driving substrate by a gold stripping machine to form a plurality of spaced alignment marks.

8. The method for fabricating alignment marks for a light-emitting chip as described in claim 1, 2, 3, or 5, characterized in that, The alignment markers include at least one of the following: circles, squares, letters, and irregular shapes.

9. The method for fabricating alignment marks for a light-emitting chip as described in claim 1, 2, 3, or 5, characterized in that, The preset pressure ranges from 6000KG to 12000KG, and the preset temperature ranges from 260℃ to 320℃.

10. A method for manufacturing a display back panel, characterized in that the step include: Prepare a plurality of alignment mark points, wherein the alignment mark points are prepared by the alignment mark fabrication method for a light-emitting chip as described in any one of claims 1 to 9; The bonded driving substrate is processed through multiple process stages to obtain an LED chip. The patterning of the film layer in each process stage is obtained by grabbing the corresponding alignment mark points and aligning the corresponding mask with the driving substrate to perform pattern overlay. The multiple process stages include a mesa process stage, a bonding metal etching process stage, a passivation layer process stage, and an electrode process stage.

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