Semiconductor structure

Abstract

The present invention discloses a semiconductor structure comprising a semiconductor wafer having a plurality of integrated circuit die regions and at least one dicing channel located between the plurality of integrated circuit die regions; and a first monitoring structure disposed in the dicing channel, wherein the first monitoring structure is composed of n consecutive metal-oxide-metal capacitors disposed in a multilayer metal layer.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more specifically, to a metal-oxide-metal (MOM) capacitor monitoring structure. Background Technology

[0002] The miniaturization of integrated circuit (IC) components has led to an increase in the number of metal layers in interconnects. This trend poses significant challenges to the quality and reliability of interconnect manufacturing processes. Existing monitoring systems and technologies are insufficient to ensure the required quality and yield levels.

[0003] Chemical mechanical polishing (CMP) is a critical step in semiconductor manufacturing used to smooth the surfaces between metal deposition layers. However, CMP can sometimes lead to dishing, where the center of the interlayer dielectric (IMD) layer between adjacent metal lines is polished more than the edges, creating a concave surface profile. This can negatively impact the performance and reliability of interconnects within the chip. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor monitoring structure to overcome the shortcomings and disadvantages of the prior art.

[0005] Another objective of this invention is to monitor the difference in CMP shallow dishing caused by the loading effect between dense and iso patterns of metal wires.

[0006] The present invention provides a semiconductor structure comprising a semiconductor wafer having a plurality of integrated circuit die regions and at least one dicing channel located between the plurality of integrated circuit die regions; and a first monitoring structure disposed in the dicing channel, wherein the first monitoring structure is composed of n consecutive metal-oxide-metal capacitors disposed in a multilayer metal layer.

[0007] According to an embodiment of the present invention, the semiconductor structure further includes a second monitoring structure disposed in the dicing channel and spaced apart from the first monitoring structure, wherein the second monitoring structure is composed of m consecutive metal-oxide-metal capacitors disposed in the multilayer metal layers, wherein m is less than n.

[0008] According to an embodiment of the present invention, n and m are both integers between 3 and 12.

[0009] According to an embodiment of the present invention, n = 6 and m is between 2 and 5.

[0010] According to an embodiment of the present invention, one of the continuous m-layer metal-oxide-metal capacitors of the second monitoring structure is disposed in the uppermost metal layer of the multilayer metal layers.

[0011] According to an embodiment of the present invention, each of the n-layer metal-oxide-metal capacitors or each of the m-layer metal-oxide-metal capacitors includes a pair of comb-shaped elements, each having a plurality of fine fingers arranged in parallel in an interdigitated manner and separated from each other by a dielectric layer.

[0012] According to an embodiment of the present invention, each of the plurality of fingers has a length of 18 micrometers and a width of 0.0405 micrometers, wherein the distance between two adjacent plurality of fingers is 0.0405 micrometers. Attached Figure Description

[0013] Figure 1 A top view of a wafer is shown as an example;

[0014] Figure 2 for Figure 1 A top view of the monitoring structure in the middle;

[0015] Figure 3 and Figure 4 Examples are shown respectively Figure 2 A three-dimensional cross-sectional view of a selected portion of the MOM capacitor monitoring structure, indicated by the dashed rectangular area marked "C".

[0016] Figure 5 This is a three-dimensional cross-sectional schematic diagram of a semiconductor monitoring structure according to another embodiment of the present invention.

[0017] Explanation of main component symbols

[0018] W silicon wafer

[0019] DR integrated circuit die region

[0020] SR cutting channel

[0021] T1, T2, T2a-T2d monitoring structure

[0022] M1-M6 metal layers

[0023] C. Dashed rectangular area

[0024] 100 base

[0025] 400MOM Capacitor Monitoring Structure

[0026] 410, 412 Metal comb-shaped elements

[0027] 420, 422 (thin fingers)

[0028] 430 Dielectric Material Detailed Implementation

[0029] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0030] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0031] Please see Figure 1 and Figure 2 , Figure 1 Taking a top view of a wafer as an example, Figure 2 for Figure 1 A top view of the monitoring structure. (Example) Figure 1 As shown, multiple integrated circuit die regions DR (indicated by dashed lines) can be formed on a silicon wafer W, and dicing tracks SR can be provided between the multiple integrated circuit die regions DR. According to an embodiment of the present invention, multiple monitoring structures (also known as test keys) can be formed on the dicing tracks SR. For simplicity, only monitoring structures T1 and T2 are shown in the figure. According to an embodiment of the present invention, for example, monitoring structures T1 and T2 are metal-oxide-metal (MOM) capacitor monitoring structures.

[0032] like Figure 2 As shown, monitoring structures T1 and T2, for example, MOM capacitor monitoring structure 400, contain capacitor elements formed in a series of n metal layers, such as six metal layers, which may be referred to as "Metal-1 (or M1)" to "Metal-6 (or M6)". Figure 2 Only the top metal layer M6 is shown. Each metal layer M1-M6 can have a similar structure, such that each metal layer M1-M6 can have the same... Figure 2 The top metal layer M6 shown has a similar structure. Metal layer M6 includes a pair of metal comb elements 410 and 412, each of which has a plurality of fine fingers 420 and 422 arranged in a cross-digital (interlaced) manner and spaced apart from each other by a dielectric material 430. According to an embodiment of the invention, the fine fingers 420 and 422 may be copper metal fingers, electrically connected to the positive and negative electrodes, respectively.

[0033] According to an embodiment of the present invention, for example, each of the fine fingers 420 and 422 has a length of 18 micrometers and a width of 0.0405 micrometers, and wherein the distance between two adjacent fine fingers 420 and 422 is, for example, 0.0405 micrometers.

[0034] Please also refer to Figure 3 and Figure 4 The examples illustrate monitoring structures T1 and T2 respectively. Figure 2 A three-dimensional cross-sectional view of a selected portion of the MOM capacitor monitoring structure 400, indicated by the dashed rectangular area marked "C". Figure 3 As shown, the monitoring structure T1 comprises n consecutive metal layers distributed on a substrate 100, such as the fine fingers 420 and 422 in metal layers M1-M6, arranged in parallel in an interdigitated manner and spaced apart from each other by a dielectric material 430. According to an embodiment of the invention, the substrate 100 is, for example, a silicon substrate, but is not limited thereto. Figure 4 As shown, the monitoring structure T2 includes m consecutive layers (m is less than n) of multiple metal layers distributed on the substrate 100, such as fine fingers 420 and 422 in metal layers M2-M6, which are also arranged in parallel in an interdigitated manner and spaced apart from each other by dielectric material 430.

[0035] It should be understood that the six metal layers M1-M6 in the figure are merely illustrative examples. In other embodiments, n and m can both be integers between 3 and 12. According to some embodiments of the present invention, for example, n = 6 and m is between 2 and 5. According to embodiments of the present invention, one of the continuous m-layer metal-oxide-metal capacitors of the monitoring structure T2 must be the uppermost metal layer disposed in the multilayer metal layers.

[0036] Please see Figure 5 This is a three-dimensional cross-sectional schematic diagram of a semiconductor monitoring structure according to another embodiment of the present invention. Figure 5 As shown in the embodiment of the present invention, in addition to the monitoring structure T1, multiple monitoring structures T2a-T2d can also be provided on the cutting track SR, including fine fingers 420 and 422 distributed in m consecutive layers (m < n) of the multilayer metal layers on the substrate 100, which are arranged in parallel in an interdigitated manner and spaced apart from each other by dielectric material 430. According to the embodiment of the present invention, for example, the capacitor structure 400 of the monitoring structure T1 is distributed in n consecutive layers of the multilayer metal layers on the substrate 100, for example, n = 6; the capacitor structure 400 of the monitoring structures T2a-T2d is distributed in m consecutive layers (m < n) of the multilayer metal layers on the substrate 100, for example, m = 5 for monitoring structure T2a, m = 4 for monitoring structure T2b, m = 3 for monitoring structure T2c, and m = 2 for monitoring structure T2d.

[0037] In other implementations, any two or three combinations of monitoring structures T2a-T2d can be selected. The sensitivity of monitoring structures T2a-T2d is the highest, followed by monitoring structure T2c, then monitoring structure T2b, and finally monitoring structure T2a. If there is insufficient space on the cutting track SR, only the monitoring structure T2d with the highest sensitivity can be set.

[0038] This invention utilizes a MOM capacitor monitoring structure with different numbers of capacitors 400 on the dicing path to effectively monitor metal brokenness or metal bridging issues caused by shallow dishing of the previous CMP layer during the final wafer acceptability test (FWAT). It also achieves the objective of monitoring the differences in shallow dishing of CMP caused by the loading effect between dense and iso patterns of metal lines.

[0039] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising: A semiconductor wafer having a plurality of integrated circuit die regions and at least one cleavage track located between the plurality of integrated circuit die regions; and a first monitoring structure disposed in the kerf, wherein The first monitoring structure consists of n consecutive layers of metal-oxide-metal capacitors disposed in multiple metal layers.

2. The semiconductor structure of claim 1, wherein, It also includes a second monitoring structure, which is disposed in the cutting channel and separated from the first monitoring structure. The second monitoring structure is composed of m consecutive layers of metal-oxide-metal capacitors disposed in the multilayer metal layer, wherein m is less than n.

3. The semiconductor structure of claim 2, wherein, Both n and m are integers between 3 and 12.

4. The semiconductor structure of claim 2, wherein, n = 6 and m is between 2 and 5.

5. The semiconductor structure of claim 2, wherein, One of the continuous m-layer metal-oxide-metal capacitors in the second monitoring structure is disposed in the uppermost metal layer of the multi-layer metal structure.

6. The semiconductor structure as claimed in claim 2, wherein, Each of the n-layer metal-oxide-metal capacitors or each of the m-layer metal-oxide-metal capacitors includes a pair of comb-shaped elements, each having multiple fine fingers arranged in parallel in an interdigitated manner and separated from each other by a dielectric layer.

7. The semiconductor structure as claimed in claim 6, wherein, Each of the plurality of fingers has a length of 18 micrometers and a width of 0.0405 micrometers, and the distance between two adjacent plurality of fingers is 0.0405 micrometers.

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