Package substrate and method of manufacturing the same
By embedding the interposer layer into the dielectric layer of the substrate and directly connecting it to the substrate, the problems of increased thickness and low signal transmission efficiency in traditional packaging are solved, realizing a thin and efficient EMIB packaging structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LEADING INTERCONNECT SEMICON TECH SHENZHEN CO LTD
- Filing Date
- 2024-12-13
- Publication Date
- 2026-06-19
AI Technical Summary
In traditional packaging processes, the interposer layer located on top of the substrate increases the thickness of the packaging substrate, and the bump connections affect signal transmission efficiency.
The interposer is embedded into the dielectric layer of the substrate and directly connected to the substrate through the conductive circuit layer, eliminating the need for bump connections. By adopting a multilayer conductive circuit layer and dielectric layer structure, direct electrical connection between electronic components and the interposer is achieved.
The thickness of the packaging substrate was reduced, signal transmission efficiency was improved, and multi-functional loads and multi-chip interconnects were realized, thus constructing the EMIB packaging structure.
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Figure CN122249056A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of packaging technology, and in particular to a packaging substrate and its manufacturing method. Background Technology
[0002] An interposer is an intermediate layer located between an electronic component (e.g., a chip) and a substrate. It is used to redistribute and connect circuitry on the electronic component. The interposer connects the electronic component to the substrate via bumps or pins, providing electrical connectivity and signal transmission.
[0003] In traditional packaging processes, the interposer is typically located on top of the substrate, with the chip or other electronic components mounted on top of it, and the layers connected by bumps. Therefore, the introduction of the interposer increases the overall thickness of the packaging substrate, and the introduction of bumps also affects signal transmission efficiency. Summary of the Invention
[0004] In view of this, this application proposes a packaging substrate and a method for manufacturing the same, so as to reduce the thickness of the packaging substrate and improve signal transmission efficiency.
[0005] One embodiment of this application provides a method for manufacturing a packaging substrate, comprising the following steps: forming an electrical connection portion on the surface of a carrier plate; wherein the carrier plate includes an insulating layer, a first copper layer, and a second copper layer, the first copper layer being located between the insulating layer and the second copper layer, and the electrical connection portion being located on the surface of the second copper layer opposite to the first copper layer; disposing an interposer layer on the surface of the carrier plate; laminating a dielectric layer onto the surface of the carrier plate, the dielectric layer covering the electrical connection portion and the interposer layer; forming a multilayer conductive circuit layer on the surface of the dielectric layer opposite to the carrier plate; separating the second copper layer from the first copper layer; removing the second copper layer to expose the interposer layer and the electrical connection portion; and disposing electronic components on the interposer layer and the electrical connection portion respectively, such that the electronic components are electrically connected to the interposer layer and the electrical connection portion respectively, thereby obtaining the packaging substrate.
[0006] In one embodiment, the interposer layer includes a substrate layer and a conductor layer formed therein, wherein the substrate layer comprises an inorganic material or an organic material, and the inorganic material includes silicon or glass.
[0007] In one embodiment, the step of "forming a multilayer conductive circuit layer on the surface of the dielectric layer away from the carrier plate" further includes: forming a plurality of blind vias on the dielectric layer, with the electrical connection portion and the intermediate layer exposed through the blind vias; laminating a film on the surface of the dielectric layer away from the carrier plate, and performing exposure, development, electroplating, film removal, and etching steps to form a conductive circuit layer on the surface of the dielectric layer away from the carrier plate, and forming conductive vias from the blind vias; repeating the steps of laminating the dielectric layer, forming blind vias, laminating, exposure, development, electroplating, film removal, and etching multiple times to form a multilayer conductive circuit layer.
[0008] In one embodiment, the step of "forming an electrical connection on the surface of a carrier board" further includes: laminating a resist film onto the surface of the second copper layer away from the first copper layer; exposing and developing the resist film to form multiple openings; electroplating metal within the openings to form the electrical connection; and removing the resist film.
[0009] In one embodiment, before the step of respectively setting electronic components on the intermediate layer and the electrical connection portion, the manufacturing method further includes: performing a surface treatment on the electrical connection portion to form a protective layer on the surface of the electrical connection portion.
[0010] In one embodiment, the manufacturing method further includes: providing a solder resist layer on the surface of the outermost conductive circuit layer.
[0011] One embodiment of this application provides a packaging substrate, which includes a substrate, an electrical connection portion, an interposer layer, and electronic components. The substrate includes multiple dielectric layers and multiple conductive line layers, with a dielectric layer disposed between adjacent conductive line layers. The electrical connection portion is located in the outermost dielectric layer and is exposed from within the outermost dielectric layer. The interposer layer is located in the outermost dielectric layer and is exposed from within the outermost dielectric layer. The electronic components are located on the surface of the substrate and are electrically connected to the substrate through the electrical connection portion and the interposer layer, respectively.
[0012] In one embodiment, the surface of the electrical connection portion is provided with a protective layer.
[0013] In one embodiment, the packaging substrate further includes a solder resist layer disposed on the surface of the outermost conductive circuit layer.
[0014] In one embodiment, the interposer layer includes a substrate layer and a conductor layer formed on the substrate layer, wherein the substrate layer comprises an inorganic material or an organic material, and the inorganic material includes silicon or glass.
[0015] This application embeds the interposer into the dielectric layer of the substrate, which improves the flatness of the connection area between the electronic components and the interposer, while also reducing the thickness of the packaging substrate, thus facilitating its thinning. Furthermore, this application directly connects the interposer to the substrate, eliminating the need for bumps for connection and reducing the spacing between them, thereby effectively improving signal transmission speed. In addition, both the electrical connections and the interposer in this application's packaging substrate are exposed from the substrate, allowing for the connection of electronic components and enabling the packaging substrate to handle multiple loads. The embedded interposer also enables the interconnection of multiple chips, effectively constructing an EMIB (Embedded Multi-die Interconnect Bridge) packaging structure. Attached Figure Description
[0016] Figures 1A to 1C A cross-sectional view of an electrical connection portion formed on the surface of a carrier plate, provided in one embodiment of this application.
[0017] Figure 2 In order to be in Figure 1C The cross-sectional view shown shows an intermediate layer on the surface of the carrier plate.
[0018] Figure 3 In order to be in Figure 2 The cross-sectional view of the dielectric layer laminated on the surface of the carrier plate is shown.
[0019] Figures 4A to 4C In order to be in Figure 3 The diagram shows a cross-sectional view of a structure with multiple conductive circuit layers.
[0020] Figure 5 In order to be in Figure 4C The diagram shows a cross-sectional view of the structure in which a solder resist layer is formed.
[0021] Figure 6 To be Figure 5 A cross-sectional view of the structure obtained after the second copper layer is separated from the first copper layer.
[0022] Figure 7 To be Figure 6 A cross-sectional view of the structure shown, showing the removal of the second copper layer.
[0023] Figure 8 To Figure 7 A cross-sectional view of the structure shown after surface treatment.
[0024] Figure 9 In order to be in Figure 8 A cross-sectional view of the packaging substrate obtained after setting electronic components on the structure shown in one embodiment.
[0025] Explanation of main component symbols
[0026] Packaging substrate 100
[0027] Carrier plate 10
[0028] Insulation layer 11
[0029] First copper layer 12
[0030] Second copper layer 13
[0031] Anti-corrosion film 14
[0032] 140° window opening
[0033] Electrical connection part 20
[0034] Intermediate layer 30
[0035] Substrate layer 31
[0036] Conductor layer 32
[0037] Adhesive layer 33
[0038] Substrate 40
[0039] Dielectric layer 41
[0040] Conductive circuit layer 42
[0041] Pad 43
[0042] Solder resist layer 44
[0043] Protective layer 45
[0044] Blind hole 410
[0045] Conductive hole 411
[0046] Electronic Components 50
[0047] The following detailed description, in conjunction with the accompanying drawings, further illustrates the embodiments of this application. Detailed Implementation
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application pertain. The terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the embodiments of this application. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.
[0049] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0050] It will be understood that when a layer is referred to as "on" another layer, it can be directly on that other layer or there can be an intermediate layer in between. Conversely, when a layer is referred to as "directly on" another layer, there is no intermediate layer. When a component is referred to as "fixed to," "mounted to," "set on," or "connected to" another component, it can be directly on the other component or there can be an intermediate component.
[0051] Embodiments of this application are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate configurations) of this application. Therefore, variations in the shapes illustrated due to manufacturing processes and / or tolerances are foreseeable. Consequently, embodiments of this application should not be construed as limited to the specific shapes of the areas illustrated herein, but should include, for example, deviations in shape due to manufacturing processes. The areas shown in the figures are merely illustrative, and their shapes are not intended to represent the actual shapes of the illustrated devices, nor are they intended to limit the scope of this application.
[0052] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0053] Please see Figures 1A to 9 The first aspect of this application provides a method for manufacturing a packaging substrate 100, which includes the following steps: S10 to S90. It is understood that the steps are numbered to clearly describe the specific manufacturing method, and does not imply a limitation on the order of the steps.
[0054] Please see Figures 1A to 1C S10, an electrical connection portion 20 is formed on the surface of the carrier plate 10.
[0055] Figure 1A A cross-sectional view of the carrier plate 10 is shown. (As shown) Figure 1A As shown, the carrier board 10 includes an insulating layer 11 and a first copper layer 12 and a second copper layer 13 located on the surface of the insulating layer 11. The first copper layer 12 is located between the insulating layer 11 and the second copper layer 13. The carrier board 10 may be a peelable copper foil. The second copper layer 13 and the first copper layer 12 are bonded together in a peelable state. Under the action of external force, the second copper layer 13 can be peeled off from the first copper layer 12.
[0056] In some embodiments, such as Figure 1AAs shown, the insulating layer 11 has a first copper layer 12 and a second copper layer 13 on both opposite surfaces; in other embodiments, the first copper layer 12 and the second copper layer 13 may be located on only one surface of the insulating layer 11.
[0057] In some embodiments, the electrical connection portion 20 can be formed by the following steps. First, as... Figure 1B As shown, a resist film 14 is laminated onto the surface of the second copper layer 13 facing away from the first copper layer 12. The resist film 14 can be, but is not limited to, a dry film. Then, the resist film 14 is exposed and developed, forming multiple spaced openings 140, through which a portion of the surface of the second copper layer 13 facing away from the first copper layer 12 is exposed. The shape of the openings 140 can be, but is not limited to, regular or irregular shapes such as cylinders or prisms. Next, as... Figure 1C As shown, metal (e.g., copper) is electroplated within the opening 140 to form an electrical connection 20. The electrical connection 20 may be formed of copper. Finally, the remaining resist film 14 is removed.
[0058] like Figure 1C As shown, the electrical connection portion 20 is located on the surface of the second copper layer 13 opposite to the first copper layer 12, and the electrical connection portion 20 is in contact with the second copper layer 13. There can be multiple electrical connection portions 20, which can be spaced apart on the second copper layer 13. The shape of the electrical connection portion 20 can be, but is not limited to, regular or irregular shapes such as cylinders or prisms.
[0059] Please see Figure 2 S20, an intermediary layer 30 is provided on the surface of the carrier plate 10.
[0060] In some embodiments, such as Figure 2 As shown, the interposer 30 includes a substrate layer 31 and a conductor layer 32 formed in the substrate layer 31. The conductor layer 32 is used to connect the electronic component 50 (see Figure 50). Figure 9 ) and substrate 40 (refer to) Figure 9 The conductor layer 32 provides signal transmission between electronic component 50 and substrate 40. The wiring density of the conductor layer 32 can be adjusted according to actual needs. The substrate layer 31 can be made of, but is not limited to, inorganic or organic materials; inorganic materials can be, but are not limited to, silicon or glass. When the substrate layer 31 is silicon, the interposer layer 30 is called a silicon interposer. The conductor layer 32 of the silicon interposer has a higher wiring density, which can achieve higher I / O (input / output) density and lower transmission delay and power consumption.
[0061] In some embodiments, such as Figure 2 As shown, the intermediate layer 30 can be fixed to the surface of the second copper layer 13 facing away from the first copper layer 12 by the adhesive layer 33, and the intermediate layer 30 is spaced apart from the electrical connection portion 20. The adhesive layer 33 can be formed by conventional or unconventional adhesives in the art, and this application is not limited thereto.
[0062] Please see Figure 3 S30, a dielectric layer 41 is pressed onto the surface of the carrier plate 10, and the dielectric layer 41 covers the electrical connection portion 20 and the intermediate layer 30.
[0063] In some embodiments, such as Figure 3 As shown, the dielectric layer 41 is located on the surface of the second copper layer 13 away from the first copper layer 12, and covers the surface of the second copper layer 13 exposed from the electrical connection portion 20 and the intermediate layer 30.
[0064] In some embodiments, the dielectric layer 41 may be epoxy resin (EP), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate dimethyl acid glycol ester (PEN), polydimethylsiloxane (PDMS), liquid crystal polymer (LCP), modified polyimide (MPI), etc.
[0065] Please see Figures 4A to 4C S40, a multilayer conductive circuit layer 42 is formed on the surface of the dielectric layer 41 away from the carrier plate 10.
[0066] In some embodiments, the conductive line layer 42 can be formed by a semi-additive (SAP) process. Specifically, S40 may further include S41 to S43.
[0067] Please see Figure 4A S41, a plurality of blind vias 410 may be formed on the dielectric layer 41 by means of, but not limited to, laser. Electrical connection portions 20 are exposed from the blind vias 410, and a portion of the surface of the interposer layer 30 is exposed from the blind vias 410. The blind vias 410 may be regular or irregular shapes such as round holes or square holes, and this application does not impose any limitations.
[0068] Please see Figure 4B In step S42, a conductive circuit layer 42 can be formed on the surface of the dielectric layer 41 facing away from the carrier plate 10 (second copper layer 13) through steps such as lamination, exposure, development, electroplating (copper), film removal, and etching. These steps are common techniques in the field and will not be described in detail here. It is understood that during electroplating, copper will also be plated inside the blind vias 410, thereby forming conductive vias 411. The conductive circuit layer 42 can be electrically connected to the electrical connection portion 20 through the conductive vias 411, and can also be electrically connected to the interposer layer 30 through the conductive vias 411.
[0069] Please see Figure 4C S43, the steps of laminating dielectric layer 41, forming blind via 411, laminating film, exposure, development, electroplating (copper), film removal, and etching can be repeated multiple times to form more conductive circuit layers 42.
[0070] like Figure 4C As shown, both the conductive circuit layer 42 and the dielectric layer 41 are multi-layered, and the multi-layered dielectric layer 41 and the multi-layered conductive circuit layer 42 together constitute the substrate 40. The substrate 40 is a coreless substrate. In the substrate 40, a dielectric layer 41 is provided between two adjacent conductive circuit layers 42, and each dielectric layer 41 may have a conductive via 411. Two adjacent conductive circuit layers 42 can be electrically connected through the conductive via 411. The outermost conductive circuit layer 42 may include pads 43.
[0071] Please see Figure 5 S50, a solder resist layer 44 is provided on the surface of the outermost conductive line layer 42. The solder pads 43 can be exposed from the solder resist layer 44.
[0072] Please see Figure 6 S60, the second copper layer 13 is separated from the first copper layer 12. The second copper layer 13 forms an intermediate structure with the substrate 40, electrical connection portion 20 and interposer layer 30 thereon, which will be used in subsequent steps.
[0073] In some embodiments, the order of S50 and S60 can also be interchanged. That is, the second copper layer 13 can be separated from the first copper layer 12 (i.e., board separation) first, and then the solder resist layer 44 can be provided on the surface of the outermost conductive line layer 42.
[0074] Please see Figure 7 S70, the second copper layer 13 can be removed by means of etching, but not limited to etching, and the adhesive layer 33 can be removed, so that the interposer layer 30 and the electrical connection portion 20 are exposed from the dielectric layer 41.
[0075] Please see Figure 8 In step S80, surface treatment is performed on the electrical connection portion 20 and the pad 43 to form a protective layer 45 on the surfaces of the electrical connection portion 20 and the pad 43, respectively. The protective layer 45 can ensure that the electrical connection portion 20 and the pad 43 have good solderability and electrical performance. In some embodiments, step S80 may be omitted.
[0076] In some embodiments, the surface treatment may be immersion gold, tin plating, or electroless nickel / palladium / immersion gold (ENEPIG) processes. In this embodiment, the surface treatment process is electroless nickel / palladium / immersion gold, that is, nickel, palladium, and gold are plated on the surface of the electrical connection portion 20, and nickel, palladium, and gold are plated on the surface of the pad 43. The protective layer 45 formed by nickel-palladium / immersion gold has advantages such as stable durability, excellent solderability, good compatibility, high plating flatness, and suitability for high-density pads.
[0077] Please see Figure 9 S90, electronic components 50 are respectively disposed on the interposer 30 and the electrical connection portion 20 to obtain a packaging substrate 100. There are multiple electronic components 50, some of which are electrically connected to the interposer 30 and others are electrically connected to the electrical connection portion 20.
[0078] In some embodiments, the electronic component 50 electrically connected to the interposer 30 may be a chip, and the electronic component 50 electrically connected to the electrical connection portion 20 may be an active component (e.g., a vacuum tube, a transistor, an integrated circuit, etc.) or a passive component (e.g., a resistor, an inductor, a capacitor, etc.). This application does not impose any limitations.
[0079] Please continue reading. Figure 9 The second aspect of this application provides a packaging substrate 100 manufactured by the above-described manufacturing method, which includes a substrate 40, an electrical connection portion 20, an interposer layer 30, and an electronic component 50.
[0080] The substrate 40 includes multiple dielectric layers 41 and multiple conductive lines 42, with a dielectric layer 41 disposed between two adjacent conductive lines 42. Each dielectric layer 41 may have a conductive via 411, and two adjacent conductive lines 42 may be electrically connected through the conductive via 411. The outermost conductive line layer 42 may include pads 43.
[0081] The electrical connection portion 20 is located in the outermost dielectric layer 41, and is exposed from this dielectric layer 41. The surface of the electrical connection portion 20 away from the center of the substrate 40 may be flush with the surface of the dielectric layer 41 away from the center of the substrate 40. The electrical connection portion 20 may be, but is not limited to, a regular or irregular shape such as a cylinder or prism. There may be multiple electrical connections 20, which may be spaced apart in the dielectric layer 41. The electrical connection portion 20 may be formed of copper.
[0082] Intermediate layer 30 is located in the outermost dielectric layer 41 and is spaced apart from electrical connection portion 20. Intermediate layer 30 is exposed from dielectric layer 41. The surface of intermediate layer 30 away from the center of substrate 40 may be slightly lower than the surface of dielectric layer 41 away from the center of substrate 40, or flush with the surface of dielectric layer 41 away from the center of substrate 40.
[0083] Electronic components 50 are located on the surface of substrate 40 and are electrically connected to substrate 40 through electrical connection portion 20 and interposer layer 30, respectively. Among them, electronic components 50 electrically connected to interposer layer 30 may be chips, and electronic components 50 electrically connected to electrical connection portion 20 may be active components (e.g., electron tubes, transistors, integrated circuits, etc.) or passive components (e.g., resistors, inductors, capacitors, etc.).
[0084] In some embodiments, such as Figure 9 As shown, the packaging substrate 100 also includes a solder resist layer 44. The solder resist layer 44 is located on the surface of the outermost conductive line layer 42 away from the center of the substrate 40, and the solder pads 43 can be exposed from the solder resist layer 44.
[0085] In some embodiments, such as Figure 9 As shown, the package substrate 100 also includes a protective layer 45. The protective layer 45 is formed on the surface of the electrical connection portion 20 away from the center of the substrate 40 and on the surface of the pad 43.
[0086] The packaging substrate 100 and its fabrication method provided in this application embed the interposer 30 into the dielectric layer 41 of the substrate 40 (coreless substrate), which can improve the flatness of the connection area between the electronic component 50 and the interposer 30, and at the same time reduce the thickness of the packaging substrate 100, which is beneficial to the thinning of the packaging substrate 100. Furthermore, in this application embodiment, the interposer 30 is directly connected to the substrate 40, eliminating the need for bumps for connection, and the spacing between the interposer 30 and the substrate 40 can also be reduced, thus effectively improving the signal transmission rate. In addition, in this application embodiment, both the electrical connection portion 20 and the interposer 30 of the packaging substrate 100 are exposed from the substrate 40, and both the electrical connection portion 20 and the interposer 30 can connect to the electronic component 50, enabling the packaging substrate 100 to perform multi-functional loads. Moreover, the embedded interposer 30 can achieve interconnection of multiple chips, which is equivalent to constructing an EMIB (Embedded Multi-die Interconnect Bridge) packaging structure.
[0087] The above description describes some specific embodiments of this application, but in actual applications, the application should not be limited to these embodiments. For those skilled in the art, other modifications and alterations made based on the technical concept of this application should fall within the protection scope of this application.
Claims
1. A method for manufacturing a packaging substrate, characterized in that, Includes the following steps: An electrical connection portion is formed on the surface of a carrier board; wherein the carrier board includes an insulating layer, a first copper layer and a second copper layer, the first copper layer is located between the insulating layer and the second copper layer, and the electrical connection portion is located on the surface of the second copper layer opposite to the first copper layer; An intermediate layer is provided on the surface of the carrier plate; A dielectric layer is laminated onto the surface of the carrier plate, the dielectric layer covering the electrical connection portion and the intermediate layer; A multilayer conductive circuit layer is formed on the surface of the dielectric layer opposite to the carrier plate. Separate the second copper layer from the first copper layer; Remove the second copper layer to expose the interposer and the electrical connection. Electronic components are disposed on the interposer layer and the electrical connection portion, respectively, and the electronic components are electrically connected to the interposer layer and the electrical connection portion, respectively, to obtain the packaging substrate.
2. The method for manufacturing a packaging substrate as described in claim 1, characterized in that, The interposer layer includes a substrate layer and a conductor layer formed therein. The substrate layer includes inorganic or organic materials, and the inorganic material includes silicon or glass.
3. The method for manufacturing a packaging substrate as described in claim 1, characterized in that, The step of "forming a multilayer conductive circuit layer on the surface of the dielectric layer opposite to the carrier substrate" further includes: Multiple blind vias are formed on the dielectric layer, and the electrical connection portion and the intermediate layer are exposed through the blind vias; A conductive circuit layer is formed on the surface of the dielectric layer away from the carrier plate by pressing a film onto it, and then performing exposure, development, electroplating, film removal, and etching steps to form a conductive circuit layer on the surface of the dielectric layer away from the carrier plate, and blind vias are fabricated to form conductive vias. The process of laminating dielectric layers, forming blind vias, laminating films, exposing, developing, electroplating, removing films, and etching is repeated multiple times to create a multilayer conductive circuit layer.
4. The method for manufacturing a packaging substrate as described in claim 1, characterized in that, The step of "forming an electrical connection on the surface of a carrier plate" further includes: A resist film is laminated onto the surface of the second copper layer away from the first copper layer, and the resist film is exposed and developed to form multiple windows in the resist film. Metal is electroplated inside the window to form the electrical connection portion; Remove the resist film.
5. The method for manufacturing a packaging substrate as described in claim 1, characterized in that, Before the step of setting electronic components on the intermediate layer and the electrical connection portion respectively, the manufacturing method further includes: performing surface treatment on the electrical connection portion to form a protective layer on the surface of the electrical connection portion.
6. The method for manufacturing a packaging substrate as described in claim 1, characterized in that, The manufacturing method further includes: setting a solder resist layer on the surface of the outermost conductive circuit layer.
7. A packaging substrate, characterized in that, include: The substrate includes multiple dielectric layers and multiple conductive circuit layers, with a dielectric layer disposed between two adjacent conductive circuit layers. An electrical connection portion is located in the outermost dielectric layer, and the electrical connection portion is exposed from the outermost dielectric layer; An interposer layer, located within and exposed from the outermost dielectric layer; and Electronic components are located on the surface of the substrate and are electrically connected to the substrate through the electrical connection portion and the interlayer, respectively.
8. The packaging substrate as described in claim 7, characterized in that, The surface of the electrical connection is provided with a protective layer.
9. The packaging substrate as described in claim 7, characterized in that, The packaging substrate also includes a solder resist layer, which is disposed on the surface of the outermost conductive circuit layer.
10. The packaging substrate as claimed in claim 7, characterized in that, The interposer layer includes a substrate layer and a conductor layer formed on the substrate layer. The substrate layer includes inorganic or organic materials, and the inorganic material includes silicon or glass.