Electronic device and method of manufacturing the same

Abstract

This disclosure provides an electronic device and a method for manufacturing the same, comprising the following steps: providing a substrate having opposing first and second surfaces; forming through-holes through the substrate; forming add-on structures on the first and second surfaces of the substrate; and simultaneously cutting the add-on structures disposed on the first and second surfaces such that the add-on structures respectively form a first groove and a second groove. The yield and / or reliability of the electronic device manufactured according to this disclosure can be improved.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to the design and manufacturing method of an electronic device having a through-hole substrate. Background Technology

[0002] During the manufacturing process of electronic devices, the components located on both sides of the mother substrate have different physical properties (such as the coefficient of thermal expansion). Therefore, the mother substrate of electronic devices is prone to warping due to stress mismatch. In addition, stress mismatch can also cause the mother substrate to crack during cutting, resulting in a decrease in the yield and / or reliability of the final electronic device. Summary of the Invention

[0003] This disclosure relates to a method for manufacturing an electronic device that can improve the yield and / or reliability of the manufactured electronic device.

[0004] According to some embodiments disclosed herein, a method for manufacturing an electronic device includes the following steps: Providing a substrate; Forming through-holes through the substrate; Forming a build-up structure on both sides of the substrate; Simultaneously cutting the build-up structure to expose a portion of the substrate surface.

[0005] This disclosure relates to an electronic device that has improved yield and / or reliability.

[0006] According to some embodiments disclosed herein, an electronic device includes a substrate, a through-hole, a connecting element, and an add-on structure. The through-hole penetrates the substrate. The connecting element is disposed in the through-hole. The add-on structure is disposed on both sides of the substrate and electrically connected to the connecting element. The surfaces on both sides of the substrate are rough surfaces, and the add-on structure exposes at least a portion of the rough surfaces. Attached Figure Description

[0007] Figure 1 This is a schematic flowchart of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2 This is a schematic diagram of an intermediate process of manufacturing an electronic device according to an embodiment of the present disclosure;

[0009] Figure 3 This is a schematic diagram of an intermediate process of a method for manufacturing an electronic device according to another embodiment of this disclosure;

[0010] Figure 4 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 5 A flowchart illustrating the manufacturing steps of an electronic device according to an embodiment of this disclosure;

[0012] Figure 6This is a cross-sectional schematic diagram of an electronic device according to another embodiment of this disclosure. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0014] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0015] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0016] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, and / or structures may be reduced or enlarged.

[0017] When a component (e.g., a membrane or region) is referred to as "on another component," it can be directly on that component, or there may be other components between them. Conversely, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when a component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, depending on the orientation of the device.

[0018] The terms “equal to” or “same as”, “substantially” or “approximately” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0019] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0020] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0021] The electrical connections or couplings described in this disclosure can refer to direct or indirect connections. In the case of a direct connection, the endpoints of the components in two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, other suitable component, or combination of the above components between the endpoints of the components in two circuits, but not limited to these.

[0022] In this disclosure, the thickness, length, width, and area can be measured using an optical microscope, and the thickness can be measured from a cross-sectional image using an electron microscope, but these are not limitations. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the two values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees. Moreover, the terms "given range is from the first value to the second value" and "given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values ​​in between.

[0023] In this disclosure, the term "one element surrounding another element" may refer to, in a cross-sectional view, the one element contacting at least one side surface of the other element.

[0024] It should be understood that, according to the embodiments disclosed herein, the depth, thickness, width, or height of each element, or the spacing or distance between elements, can be measured using an optical microscope (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. According to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structural image including the element to be measured, and to measure the depth, thickness, width, or height of each element, or the spacing or distance between elements.

[0025] The manufacturing process of the electronic device disclosed herein can be provided, for example, through a wafer-level package (WLP) or panel-level package (PLP) process, which can be a chip-first or chip-last RDL first process.

[0026] The electronic devices disclosed herein can be applied to high-speed computing modules, power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but are not limited thereto. Electronic devices include, but are not limited to, rollable, bendable, or flexible electronic devices. Display devices can be non-self-emissive or self-emissive display devices. Electronic devices may include, for example, diodes, liquid crystals, light-emitting diodes (LEDs), quantum dots (QDs), fluorescence, phosphorescence, other suitable display media, or combinations thereof. Antenna devices may be liquid crystal type antenna devices or non-liquid crystal type antenna devices. Sensing devices may be sensing devices that sense capacitance, light, heat, or ultrasound, but are not limited thereto. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), micro-LEDs (mini-LEDs), or quantum dot light-emitting diodes (QLEDs (QDLEDs), but are not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but is not limited thereto. Furthermore, the electronic device may be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, and a light source system to support the display device, antenna device, wearable device (e.g., augmented reality or virtual reality), in-vehicle device (e.g., a car windshield), or splicing device. The electronic device may include electronic units, wherein electronic components may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. It should be noted that the electronic device disclosed herein may be various combinations of the above-mentioned devices, but is not limited thereto. The method for fabricating the packaging apparatus disclosed herein can be applied, for example, to wafer-level package (WLP) or panel-level package (PLP) processes, wherein the wafer-level package or panel-level package process may include a chip-first process or a chip-last process, but is not limited thereto.Electronic devices may include, but are not limited to, packaging devices such as High Bandwidth Memory (HBM) packages, System on a Chip (SoC), System in a Package (SiP), Antenna in Package (AiP), Co-packaged Optics (CPO), or various combinations of the above devices.

[0027] Figure 1 This is a schematic flowchart illustrating a method for manufacturing an electronic device according to an embodiment of this disclosure.

[0028] Please refer to Figure 1 According to some embodiments, the electronic device 1a can be formed by performing the following steps, but this disclosure is not limited thereto.

[0029] Step (1): Provide substrate 10.

[0030] The material of substrate 10 may include, for example, a suitable ceramic material. Substrate 10 may include a glass substrate, a silicon-containing material, an optical layer, an acrylic sheet, a semiconductor structure substrate, or a combination thereof or other transparent materials, and possesses a certain degree of stiffness and insulation. That is, the stiffness of substrate 10 may be greater than that of the build-up structure formed thereon (e.g., Figure 4 The rigidity of the added-layer structure 32) shown, for example, the rigidity of the substrate 10, is greater than the rigidity of the insulating layer of the added-layer structure, so that the substrate SB can reduce warping when used to support the added-layer structure, but is not limited thereto. The term "rigidity" as used in this disclosure can be tested using a universal testing machine (UTM). For example, the material of the substrate 10 includes transparent materials, glass, alkali-free glass, and quartz glass, but this disclosure is not limited thereto. According to some embodiments, the substrate 10 is a glass substrate, but this disclosure is not limited thereto.

[0031] In some embodiments, substrate 10 can be formed by stacking a plurality of sub-substrates, wherein the plurality of sub-substrates may be made of the same or different materials, have the same or different coefficients of thermal expansion, have the same or different thicknesses, and have the same or different rigidities. For example, substrate 10 can be formed by heating, pressurizing, bonding, other suitable processes, or combinations thereof on two or more sub-substrates (not shown) with different coefficients of thermal expansion, but this disclosure is not limited thereto.

[0032] Step (2): Form a through hole T through the substrate 10.

[0033] In some embodiments, the via T can be formed by laser modification, drilling, etching, or a combination thereof, but this disclosure is not limited thereto. In other embodiments, sub-substrates with pre-formed vias can be stacked to form a substrate 10 with via T. According to some embodiments, the via T penetrates two opposite surfaces of the substrate 10, that is, the via T penetrates surface 10s1 and surface 10s2 of the substrate 10, and the sidewalls of the via T can be connected to surface 10s1 and surface 10s2, respectively. According to some embodiments, the process of forming the via T further includes forming an opening O in the edge region DS, wherein the edge region DS can be considered as a cutting path and the opening O does not penetrate the substrate 10. Although Figure 1 Only the surface 10s1 of the substrate 10 is shown to have an opening O, but the surface 10s2 of the substrate 10 may also have an opening O.

[0034] It is worth noting that, although Figure 1 This invention illustrates the formation of vias T and openings O by covering a substrate 10 with a mask pattern PR and performing a laser-modified process on the substrate 10, but this disclosure is not limited thereto. In some embodiments, the mask pattern PR can be formed by sequentially performing a suitable coating process, an exposure process, and a development process, but this disclosure is not limited thereto. The mask pattern PR is made of a material that can absorb laser light, for example, that is, the mask pattern PR can serve as a laser-absorbing layer and / or a laser-blocking layer, preventing laser light from penetrating the mask pattern PR. In some embodiments, the transmittance of the mask pattern PR for light with wavelengths from 280 nm to 400 nm is less than or equal to 10%, but is not limited thereto. The thickness T21 of the mask pattern PR can be, for example, greater than or equal to 0.01 μm and less than or equal to 10 μm, but is not limited thereto. The thickness T21 can be the thickness of the mask pattern PR measured in the normal direction (direction Z) of the substrate 10. The material of the mask pattern PR can include suitable organic materials, inorganic materials, or combinations thereof. The material of the mask pattern PR may include silicon, silicon carbide (Si-C), nickel monoxide (NiO), tin dioxide (SnO2), titanium dioxide (TiO2), oxides, polymers, other suitable materials, or combinations thereof, but is not limited thereto. As used in this disclosure, "overlay" means that the mask pattern PR may overlap at least a portion of the substrate 10 in the projection direction or the normal direction (direction Z) of the substrate 10. In other words, the mask pattern PR may directly contact the surface 10s1 of the substrate 10 or may not need to directly contact the surface 10s1 of the substrate 10.

[0035] Step (3): Form the connecting element 20 on the substrate 10.

[0036] In some embodiments, the connecting element 20 may be formed by deposition, chemical plating, electroplating, or a combination thereof, but this disclosure is not limited thereto. In some embodiments, the material of the connecting element 20 may include copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tungsten (W), platinum (Pt), nickel (Ni), or a combination thereof, but this disclosure is not limited thereto. According to some embodiments, the connecting element 20 is conformally formed on the substrate 10 and disposed in a via T. For example, the connecting element 20 may be disposed on at least a portion of the surface of the substrate 10 and in at least a portion of the via T, but this disclosure is not limited thereto.

[0037] In some embodiments, a seed layer (not shown) may be formed on the substrate 10 before the connecting element 20 is formed on the substrate 10. In some embodiments, the seed layer may be formed by performing a suitable deposition process. For example, the seed layer may be formed by performing chemical plating, electroplating, atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or combinations thereof, but this disclosure is not limited thereto. The seed layer may, for example, comprise a stacked multilayer structure, but this disclosure is not limited thereto.

[0038] It is worth noting that, according to some embodiments, a portion of the surface 10s1 and a portion of the surface 10s2 of the substrate 10 are covered by the connecting element 20.

[0039] Step (4): Form a filling material F in the opening O of the dicing zone DS of the substrate 10.

[0040] In some embodiments, the filler material F can be formed by a suitable deposition process. For example, the filler material F can be formed by a coating process, an injection process, or a combination thereof, but this disclosure is not limited thereto. In some embodiments, the filler material F may include organic materials, conductive materials, metallic materials, heat-dissipating materials, or combinations thereof. For example, the filler material F may include a suitable composition of polymers, metals, alloys, graphene, or silicon carbide, but this disclosure is not limited thereto. According to some embodiments, the filler material F fills the opening O. In some embodiments, the filler material F may extend further to the surface 10s3 of the substrate, wherein surface 10s3 is the surface connecting surface 10s1 and surface 10s2. In other embodiments, the filler material F may not extend to the surface 10s3 of the substrate 10. In still other embodiments, the filler material F may be disposed further on the surface 10s2 of the substrate 10, and the filler material F disposed on the surface 10s2 of the substrate 10 may at least partially overlap the filler material F disposed on the surface 10s1 of the substrate 10.

[0041] Step (5): Perform a thinning process to expose the surface 10s1 and surface 10s2 of the substrate 10 covered by the connected element 20, and the surface 10s2 relative to surface 10s1.

[0042] In detail, a portion of the connecting elements 20 located on opposite sides of the substrate 10 can be removed by performing a thinning process. In some embodiments, the thinning process may include a polishing process, a chemical mechanical polishing process, a laser process, an etching process, a plasma process, or a combination thereof, but this disclosure is not limited thereto.

[0043] Step (6): A surface modification process is performed to roughen the surfaces 10s1 and 10s2 of the substrate 10 and the surface of the connecting element 20. In some embodiments, the surfaces 10s1 and 10s2 of the substrate 10, the surface of the connecting element 20, and the sidewall of the through hole T may have a surface roughness Rz between 0.1 μm and 5 μm, for example, satisfying the following condition: 0.1 μm ≤ Rz ≤ 5 μm. The surface roughness of the surfaces 10s1 and 10s2 of the substrate 10 is less than the surface roughness of the surface of the connecting element 20, which can improve the bonding force between the film layers and avoid the risk of glass breakage.

[0044] In some embodiments, the aforementioned rough surface can be formed by a wet etching process, wherein the etching solution can be phosphoric acid, but this disclosure is not limited thereto. According to some embodiments, the roughness of the surface 10s1 of the substrate 10, the surface 10s2 of the substrate 10, and the surface of the connecting element 20 can be 0.1 nm-5 μm, and the roughness of the surface 10s1 of the substrate 10 (or the roughness of the surface 10s2 of the substrate 10) and the roughness of the surface of the connecting element 20 can be different from each other, but this disclosure is not limited thereto.

[0045] In some embodiments, roughness is defined as the roughness of the side surfaces of each substrate 10 observed using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). If the difference between the peaks and valleys of the side surface undulations is 0.15 μm to 1 μm, it can be considered low roughness. The SEM or TEM can observe the surface undulations of the side surfaces of each sub-perforated substrate at the same appropriate magnification, and the undulations can be compared by taking a unit length (e.g., 10 μm). "Appropriate magnification" means that at least one surface can show at least 10 peaks of undulations at this magnification.

[0046] Step (7): Form the added layer structure 30 on both sides of the substrate 10.

[0047] In detail, according to some embodiments, the method of forming the add-on structure 30 may include forming the add-on structure 30 on surfaces 10s1 and 10s2 of the substrate 10, or forming the add-on structure 30 on surfaces 10s1 and 10s2 of the substrate 10 simultaneously. In other words, the add-on structure 30 includes an add-on structure 32 disposed on surface 10s1 of the substrate 10 and an add-on structure 34 disposed on surface 10s2 of the substrate 10. According to some embodiments, the add-on structure 32 is in contact with at least a portion of the rough surface 10s1 of the substrate 10, and the add-on structure 34 is in contact with at least a portion of the rough surface 10s2 of the substrate 10. Alternatively, the add-on structure 32 is in contact with at least a portion of the filler material F.

[0048] According to some embodiments, the add-on structure 30 can be formed by alternately forming multiple insulating layers IL and multiple conductive layers M on surfaces 10s1 and 10s2 of the substrate 10. In some embodiments, the multiple insulating layers IL and multiple conductive layers M can each be formed by suitable deposition processes and patterning processes, and this disclosure is not limited thereto. According to some embodiments, the add-on structure 32 includes multiple insulating layers IL1 and multiple conductive layers M1, and the add-on structure 34 includes multiple insulating layers IL2 and multiple conductive layers M2.

[0049] Specifically, according to some embodiments, the build-up structure 30 may be a rewiring structure used to redistribute lines and / or further increase the fan-out area of ​​the lines. Additionally, different electronic components can be electrically connected to each other via the rewiring structure. For example, multiple electronic components 2, which will be described later, can be electrically connected to each other via the rewiring structure, or the rewiring structure may be a substrate serving as an electrical interface wiring between one connection and another. The purpose of the rewiring structure is to extend the interconnects to a wider spacing or to redistribute the interconnects to another interconnect with a different spacing. In some embodiments, the material of the multilayer insulating layer IL may include Ajinomoto Build-up Film (ABF), polyimide (PI), photosensitive polyimide (PSPI), polybenzoxazole (PBO), epoxy resin, polymer, isoaniline, and silicon dioxide (SiO2). x ), silicon nitride (SiN) xThis disclosure is not limited to any combination thereof. In some embodiments, the material of the multilayer conductive layer M may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), silver (Ag), tantalum (Ta), metal nitrides, other suitable conductive materials, or any combination thereof, and this disclosure is not limited to this. According to some embodiments, after providing the insulating layer and the conductive layer, a surface modification process may be performed to form a rough surface on the surfaces of the insulating layer and the conductive layer, wherein the roughness of the insulating layer is greater than the surface roughness of the substrate 10.

[0050] Step (8): Simultaneously cut the layered structures 30 disposed on opposite sides of the substrate 10.

[0051] In some embodiments, a cutting process can be performed to remove portions of the add-on structure 30 formed on the substrate 10 to form recesses P1 and P2. The cutting process may include laser cutting, rotary cutting, or a combination thereof, but this disclosure is not limited thereto.

[0052] In some embodiments, after removing a portion of the add-on structure 30 formed on the substrate 10, recess P1 exposes a portion of the surface of the filler material F, and recess P2 exposes a portion of the surface 10s2. Specifically, add-on structures 32 and 34 are simultaneously cut on both sides of the substrate 10. In some embodiments, after laser processing on both sides of the substrate 10, grooves R1 and R2 can be formed in the add-on structures 30 located on both sides of the substrate 10, respectively, wherein grooves R1 and R2 at least partially overlap in the normal direction (direction Z) of the substrate 10, and grooves R1 and R2 overlap opening O in the normal direction (direction Z) of the substrate 10. According to some embodiments, the depth d1 of groove R1 is substantially equal to the depth d2 of groove R2, but this disclosure is not limited thereto. With the above design, the risk of substrate 10 cracking can be reduced by placing the filler material F in the opening O and simultaneously cutting the add-on structure 30 at the position corresponding to the opening O.

[0053] Step (9): Cut the substrate 10 in the cutting channel area DS to obtain the electronic device 1a.

[0054] According to some embodiments, the cutting process performed in the dicing zone DS may include laser processing of surfaces 10s1 and 10s2 of the substrate 10 corresponding to the dicing zone DS. In some embodiments, the portion corresponding to the dicing zone DS may be laser-induced treated before the cutting process, but this disclosure is not limited thereto. Furthermore, during the cutting of the substrate 10, a portion of the add-on structure 30 may be removed to expose a portion of surfaces 10s1 and 10s2 of the substrate 10.

[0055] Figure 2 This is a schematic diagram of an intermediate process in the manufacturing method of an electronic device according to an embodiment of this disclosure. It should be noted that... Figure 2 The embodiments can be used Figure 1 The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0056] Please refer to Figure 2 According to some embodiments, before performing the above step (8) (performing laser processing on both sides of the substrate 10), the stress on one side of the surface 10s2 of the substrate 10 is greater than the stress on one side of the surface 10s1 of the substrate 10. This may be because, for example, the proportion of conductive layer M in the added layer structure 34 is greater than the proportion of conductive layer M in the added layer structure 32, but this disclosure is not limited thereto.

[0057] Based on this, after performing step (8) (laser processing on both sides of the substrate 10), grooves R1 and R2 are formed in the add-on structures 30 located on both sides of the substrate 10. Since the metal ratios of add-on structures 32 and 34 are different, the depth d1 of groove R1 is designed to be different from the depth d2 of groove R2. For example, the depth d1 of groove R1 is designed to be less than the depth d2 of groove R2. Through this design, this embodiment can make the stress generated on the opposite sides of the substrate 10 match, thereby reducing the possibility of warping of the electronic device 1a or reducing the risk of substrate 10 cracking.

[0058] In addition, according to some embodiments, after the substrate 10 is cut in the cutting channel area DS, the side surface 10s3 of the substrate 10 may have an arc-shaped profile, such as an outwardly convex arc-shaped profile, but this disclosure is not limited thereto.

[0059] Figure 3 This is a schematic diagram of an intermediate process in a method for manufacturing an electronic device according to another embodiment of this disclosure. It should be noted that... Figure 3 The embodiments can be used Figure 1 and Figure 2 The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0060] Please refer to Figure 3 Similarly, according to some embodiments, before performing the above step (8), the stress on one side of the surface 10s2 of the substrate 10 is greater than the stress on one side of the surface 10s1 of the substrate 10.

[0061] Based on this, after performing step (8) above, since the metal ratios of the added-layer structure 32 and the added-layer structure 34 are different, the width w1 of the groove R1 is designed to be different from the width w2 of the groove R2. For example, the width w1 of the groove R1 is designed to be smaller than the width w2 of the groove R2. Through this design, this embodiment can make the stress generated on the opposite sides of the substrate 10 match, thereby reducing the possibility of warping of the electronic device 1a.

[0062] In addition, according to some embodiments, after the substrate 10 is cut in the cutting channel area DS, the side surface 10s3 of the substrate 10 may have an arc-shaped profile, for example, an inwardly concave arc-shaped profile, but this disclosure is not limited thereto.

[0063] Figure 4 This is a schematic cross-sectional view of an electronic device according to an embodiment of this disclosure. It should be noted that... Figure 4 The embodiments can be used Figure 1 The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0064] Please refer to Figure 4 According to some embodiments, the electronic device 1b may include a substrate 10, a through-hole T, a connecting element 20, and an add-on structure 30.

[0065] According to some embodiments, the substrate 10 is a glass substrate. In some embodiments, the coefficient of thermal expansion of the substrate 10 may be greater than or equal to 3 ppm / ℃ and less than or equal to 15 ppm / ℃, and the light transmittance of the substrate 10 may be greater than or equal to 75%, wherein the light may include white light, UV light, etc., but this disclosure is not limited thereto. In some embodiments, the transmittance of the substrate 10 for light with wavelengths from 280 nanometers (nm) to 400 nm is 75% to 99.9%. In some embodiments, the substrate 10 may include silicon dioxide, boron trioxide, aluminum trioxide, metal oxides, combinations thereof, or other suitable materials, but is not limited thereto. For example, the glass composition forming the glass substrate may include 50 to 90 wt% silicon dioxide (SiO2), 3 to 15 wt% boron trioxide (B2O3), 0.5 to 25 wt% aluminum trioxide (Al2O3), and less than or equal to 20 wt% other metal oxides, such as oxides of alkali metals or alkaline earth metals. This is beneficial for improving the rigidity of the substrate 10, but is not limited to this.

[0066] The through-hole T, for example, penetrates through the substrate 10. Specifically, according to some embodiments, the through-hole T extends from surface 10s1 to surface 10s2 of the substrate 10. In some embodiments, the through-hole T may have a dumbbell-shaped or hourglass-shaped shape, but this disclosure is not limited thereto. Further details regarding the through-hole T can be found in the above embodiments and will not be repeated here.

[0067] The connecting element 20 is disposed, for example, in the through-hole T. According to some embodiments, the connecting element 20 may be disposed on at least a portion of the surface 10s1 and at least a portion of the surface 10s2 of the substrate 10, and fill the through-hole T, but this disclosure is not limited thereto. Additionally, according to some embodiments, a seed layer S may also be formed in the through-hole T, wherein the seed layer S may be disposed on at least a portion of the surface 10s1 and at least a portion of the surface 10s2 of the substrate 10, and disposed in at least a portion of the through-hole T, but this disclosure is not limited thereto. Further details regarding the connecting element 20 and the seed layer S can be found in the above embodiments and will not be repeated here.

[0068] The add-on structure 30 is disposed, for example, on the substrate 10 and electrically connected to the connecting element 20. According to some embodiments, the add-on structure 30 includes add-on structures 32 and 34. Add-on structure 32 is disposed, for example, on the surface 10s1 of the substrate 10 and, for example, at least partially overlaps the via T. In some embodiments, add-on structure 32 includes multiple insulating layers IL1 and multiple conductive layers M1. Add-on structure 34 is disposed, for example, on the surface 10s2 of the substrate 10 and, for example, at least partially overlaps the via T. In some embodiments, add-on structure 34 includes multiple insulating layers IL2 and multiple conductive layers M2, wherein the materials of the multiple insulating layers IL2 and multiple conductive layers M2 may be the same as or similar to the materials of the multiple insulating layers IL1 and multiple conductive layers M1.

[0069] According to some embodiments, add-on structures 32 and 34 are each rewiring structures, which can be used to redistribute lines and / or further increase the fan-out area of ​​the lines. The purpose of setting up the rewiring structure is to extend the connection to a wider spacing or to redistribute the connection to another connection with a different spacing. Based on this, identical or different electronic components 2 can be disposed on and electrically connected to add-on structure 32, and circuit board CB can be disposed on and electrically connected to add-on structure 34, so that electronic components 2 can be electrically connected to circuit board CB through add-on structures 32 and 34.

[0070] For further details regarding the added-layer structure 30, please refer to the above embodiments, and they will not be repeated here.

[0071] According to some embodiments, the electronic device 1b further includes a plurality of electronic components 2, wherein each electronic component 2 may have the same function or different functions. According to some embodiments, the electronic device 1b may be a 2.5D package structure in which a plurality of electronic components 2 are arranged horizontally side by side, but this disclosure is not limited thereto.

[0072] According to some embodiments, electronic device 1b includes two electronic components 2a and 2b. Electronic component 2a may be, for example, a high bandwidth memory (HBM) and is electrically connected to the conductive layer M1 in the build-up structure 32 via a pad PAD and a connection unit CU1. The materials of the pad PAD and the connection unit CU1 may include copper, nickel, tin, silver, gold, gallium, or other suitable materials, and this disclosure is not limited thereto. Electronic component 2b may be, for example, a graphics processing unit (GPU) and is electrically connected to the conductive layer M1 in the build-up structure 32 via the connection unit CU1. However, this disclosure is not limited to the types of these electronic components.

[0073] According to some embodiments, the electronic device 1b also includes an adhesive layer UF1, a circuit board CB, an adhesive layer UF2, and an encapsulation layer PL.

[0074] The adhesive layer UF1 is disposed, for example, between the plurality of electronic components 2 and the build-up structure 32. Specifically, the adhesive layer UF1 can directly contact the active surfaces of the plurality of electronic components 2 and fill the space between two adjacent connecting units CU1. The material of the adhesive layer UF1 may include suitable inorganic or organic materials, but this disclosure is not limited thereto. In some embodiments, the adhesive layer UF1 may include a colloid for fixing the plurality of electronic components 2.

[0075] The circuit board CB can, for example, be used to carry the aforementioned multiple electronic components 2. According to some embodiments, the circuit board CB can be electrically connected to the multiple electronic components 2 via the connection unit CU2 and the layering structure 30.

[0076] Adhesive layer UF2 is disposed, for example, between circuit board CB and add-on structure 34. According to some embodiments, adhesive layer UF2 may fill the space between two adjacent connecting elements CU2. The material of adhesive layer UF2 may be the same as or similar to the material of adhesive layer UF1, and will not be described further here.

[0077] The encapsulation layer PL, for example, surrounds a plurality of electronic components 2. In some embodiments, the encapsulation layer PL may expose the back side of the electronic components 2 to facilitate heat dissipation of the electronic device 1b. The material of the encapsulation layer PL may include epoxy molding compound (EMC), but this disclosure is not limited thereto. According to some embodiments, the add-on structure 32 exposes the rough surface 10s1 of the substrate 10. Therefore, the encapsulation layer PL may contact at least another portion of the rough surface 10s1 of the substrate 10, thereby improving the adhesion between the encapsulation layer PL and the substrate 10.

[0078] Figure 5 This is a flowchart illustrating the manufacturing method of an electronic device according to an embodiment of this disclosure. It should be noted that... Figure 5 The embodiments can be used Figure 1 The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0079] Please refer to Figure 5 According to some embodiments, during step (8) (simultaneously cutting the add-on structure 30 to expose a portion of the substrate 10 surface 10s1 and / or a portion of the substrate 10 surface 10s2), a monitoring device (not shown) can be used to detect whether the substrate 10 warps and / or whether the amount of warpage of the substrate 10 exceeds a predicted value. If so, an alarm device (not shown) can be used to alert the process operator so that the operator can adjust the process parameters used during the cutting process.

[0080] Additionally, after step (8) (simultaneously cutting the add-on structure 30 to expose a portion of the substrate 10 surface 10s1 and / or a portion of the substrate 10 surface 10s2), a detection device (not shown) can be used to detect whether the grooves R1 and / or R2 in the add-on structure 30 are formed as expected. If not, the process parameters used in the cutting process can be adjusted before step (9) (cutting the substrate 10 in the cutting channel area DS to obtain an electronic device).

[0081] Figure 6 This is a schematic cross-sectional view of an electronic device according to another embodiment of this disclosure. It should be noted that... Figure 6 The embodiments can be used Figure 4 The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0082] Please refer to Figure 6According to some embodiments, the electronic device 1c may include a substrate 10, a through-hole T, a connecting element 20, an add-on structure 30, and an interposer INP. Detailed descriptions of the substrate 10, the through-hole T, the connecting element 20, and the add-on structure 30 can be found in the above embodiments, but this disclosure is not limited thereto.

[0083] The interposer layer INP may include, for example, a core layer CL, vias V, an insulating layer IL3, a conductive layer M3, an insulating layer IL4, and a conductive layer M4. The core layer CL may be made of, for example, silicon, glass, or an organic material. In some embodiments, the edges of the core layer CL may have a chamfer C, but this disclosure is not limited thereto. For example, multiple vias V are provided and penetrate the core layer CL. In some embodiments, if the core layer CL is made of silicon, the vias V may be referred to as silicon vias, but this disclosure is not limited thereto. In some embodiments, the vias V may also include a filler material FI, but this disclosure is not limited thereto. The insulating layer IL3 and the conductive layer M3 are disposed, for example, above the core layer CL and located in the Z direction between the core layer CL and the add-on structure 34, wherein the insulating layer IL3 and the conductive layer M3 may be combined to form a redistribution structure so that the conductive layer M2 in the add-on structure 34 can be electrically connected to the vias V in the core layer CL. An insulating layer IL4 and a conductive layer M4 are disposed, for example, below the core layer CL and located between the core layer CL and the circuit board CB in the Z direction. The insulating layer IL4 and the conductive layer M4 can be combined to form a redistribution structure, allowing the circuit board CB to be electrically connected to the through-hole V in the core layer CL via the connection unit CU3. Based on this, according to some embodiments, multiple electronic components 2 can be electrically connected to the circuit board CB via the interposer layer INP.

[0084] According to some embodiments, the interposer layer INP may include an embedded die ED disposed in a recess RE of the core layer CL. The embedded die ED may be electrically connected to a through-hole V in the core layer CL, for example, through a conductive layer M3.

[0085] According to some embodiments, the electronic device 1c may further include a buffer layer BF. The buffer layer BF is disposed, for example, on a substrate 10 and may cover surfaces 10s1, 10s2, and 10s3 of the substrate 10. Therefore, the provision of the buffer layer BF helps reduce the probability of microcracks forming in the substrate 10, but this disclosure is not limited thereto. The buffer layer BF may comprise, for example, a single layer or multiple layers stacked together, and may be formed, for example, using electroplating, chemical electroplating, physical vapor deposition, or other suitable processes. In some embodiments, the toughness of the buffer layer BF may be 0.1 kJ / m². 2 Up to 100kJ / m 2The material of the buffer layer may include, for example, organic or inorganic materials. For instance, the buffer layer BF may include polyimide (PI) resin, parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), oxides, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. For example, the stacking arrangement of the buffer layers BF may be organic-inorganic-organic, organic-organic-organic, organic-organic-inorganic, etc. In some embodiments, at... Figure 6 In the cross-sectional view shown, the thickness of the buffer layer BF can be from 0.01 μm to 10 μm. The aforementioned thickness of the buffer layer BF can refer to the maximum thickness of the buffer layer BF on the surface 10s1 of the substrate 10 along the vertical direction (direction Z), or it can refer to the thickness of the buffer layer BF on the wall of the via T along the horizontal direction (e.g., horizontal direction X or direction Y). In some embodiments, the ratio of the thickness of the buffer layer BF to the diameter of the via T can be from 0.02 to 0.2, but this disclosure is not limited thereto.

[0086] In summary, in the manufacturing methods of electronic devices provided in some embodiments disclosed herein, by simultaneously cutting the add-on structures located on both sides of the substrate, the possibility of technical problems such as warping and / or cracking of the substrate due to stress mismatch can be reduced, thereby improving the yield and / or reliability of the manufactured electronic devices.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an electronic device, characterized in that, include: A substrate is provided, the substrate having opposing first and second surfaces; Forming a through-hole penetrating the substrate; An add-layer structure is formed on the first surface and the second surface of the substrate; as well as Simultaneously, the layered structures disposed on the first surface and the second surface are cut, so that the layered structures respectively form a first groove and a second groove.

2. The method of manufacturing an electronic device according to claim 1, wherein when simultaneously cutting the layered structure disposed on the first surface and the second surface, after cutting to expose a portion of the first surface or the second surface of the substrate, the substrate is cut in a cutting channel area to obtain the electronic device.

3. The method of manufacturing an electronic device according to claim 1, wherein the first groove and the second groove at least partially overlap in the normal direction of the substrate.

4. The method of manufacturing an electronic device according to claim 3, wherein the depth of the first groove is different from the depth of the second groove in the normal direction of the substrate.

5. The method of manufacturing an electronic device according to claim 3, wherein the width of the first groove is different from the width of the second groove in a direction perpendicular to the normal direction of the substrate.

6. The method of manufacturing an electronic device according to claim 2, wherein the cut channel area includes an opening, and the opening includes a filler material.

7. The method of manufacturing an electronic device according to claim 1, wherein connecting elements are formed in the through-holes of the substrate before the added-layer structure is formed on both sides of the substrate.

8. The method for manufacturing an electronic device according to claim 1, wherein during the simultaneous cutting of the add-on structure, it is detected whether the substrate warps and / or whether the amount of warping of the substrate exceeds a predicted value, wherein if the substrate warps and / or the amount of warping of the substrate exceeds the predicted value, the process parameters used in the cutting process of the add-on structure are adjusted.

9. An electronic device, characterized in that, include: substrate; Through-hole, penetrating the substrate; A connecting element is disposed in the through hole; An add-in structure is disposed on both sides of the substrate and electrically connected to the connecting element; Multiple electronic components are electrically connected to the layered structure; as well as Encapsulation layer, surrounding the plurality of electronic components, The surfaces located on both sides of the substrate are rough surfaces, and the added-layer structure exposes at least a portion of the rough surfaces.

10. The electronic device of claim 9, wherein the encapsulation layer contacts at least a portion of the rough surface, and the roughness of the rough surface is between 0.1 micrometers and 5 micrometers.

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