Semiconductor package with suppressed electrical coupling
By introducing a semiconductor package structure consisting of a lead frame, multiple FETs, and a metal clip, and utilizing vertical pin connections to the ground terminal, the electrical coupling problem of DrMOSFETs is solved, resulting in higher electrical performance and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ALPHA & OMEGA SEMICON INT LP
- Filing Date
- 2025-12-11
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional dual-drive metal-oxide-semiconductor field-effect transistors (DrMOSFETs) suffer from electrical coupling problems.
It employs a semiconductor package structure including a lead frame, multiple FETs and metal clips, suppresses electrical coupling by connecting vertical pins to the ground terminal, uses molding to encapsulate key components, and forms the final product through a monomerization process.
It effectively suppresses electrical coupling and improves the electrical performance and reliability of semiconductor packaging.
Smart Images
Figure CN122249065A_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a transistor (FET) and integrated circuit (IC) semiconductor package having a stacked field effect and suppressing electrical coupling, and a method for manufacturing the same. Background Technology
[0002] Traditional dual-drive metal-oxide-semiconductor field-effect transistors (DrMOSFETs) include stacked FETs, which therefore presents an electrical coupling problem.
[0003] The semiconductor package disclosed herein includes a lower metal clip and an upper metal clip, the upper metal clip including two vertical pins connected to a ground terminal to suppress electrical coupling. Summary of the Invention
[0004] The present invention discloses a semiconductor package comprising a lead frame, a first high-voltage side FET, a second high-voltage side FET, a first metal clip, a second metal clip, a first low-voltage side FET, a second low-voltage side FET, a third metal clip, a metal block, an integrated circuit (IC), multiple bonding leads, and a molded package.
[0005] The present invention also discloses a method for manufacturing a semiconductor package, the method comprising the following steps: providing a lead frame; mounting a first high-voltage side FET and a second high-voltage side FET; connecting a first metal clip and a second metal clip; mounting a first low-voltage side FET and a second low-voltage side FET; connecting a third metal clip; connecting an integrated circuit (IC); forming a molded package; and performing a monomerization process. Attached Figure Description
[0006] Figure 1A This represents a top perspective view of a semiconductor package as shown in the examples of this disclosure. Figure 1B This indicates a perspective view taken from below.
[0007] Figure 2 This represents a top perspective view of another semiconductor package in the examples disclosed herein.
[0008] Figure 3 This indicates that molded packaging is not shown in the examples disclosed herein. Figure 1A The image shows a top perspective view of a semiconductor package.
[0009] Figure 4 This indicates that molded packaging is not shown in the examples disclosed herein. Figure 1A The diagram shows an exploded view of the semiconductor package.
[0010] Figure 5 This is a flowchart illustrating the semiconductor packaging manufacturing process in the examples disclosed herein.
[0011] Figure 6AA , 6BA 6CA, 6DA, 6EA, 6EC, 6FA, 6GA, and 6HA represent examples in this disclosure. Figure 5 The diagram shows a top view of the semiconductor packaging manufacturing process. Figure 6AB , 6BB 6CB, 6DB, 6EB, 6ED, 6FB, 6GB, 6HB, and 6I represent their side views. Detailed Implementation
[0012] Figure 1A This represents a top perspective view of the semiconductor package 100 in the examples disclosed herein. Figure 1B This indicates a perspective view taken from below. Figure 3 This indicates that molded packaging is not shown in the examples disclosed herein. Figure 1A Top perspective view of semiconductor package 100 shown; Figure 4 This indicates that molded packaging is not shown in the examples disclosed herein. Figure 1A An exploded view of the semiconductor package 100 shown. The semiconductor package 100 includes... Figure 3 The lead frame 310 shown Figure 4 The first high-voltage side FET 420 shown Figure 4 The second high-voltage side FET 422 shown Figure 4 The first metal clip 440 shown Figure 4 The second metal clip 442 shown Figure 4 The first low-voltage side FET 460 shown Figure 4 The second low-voltage side FET 462 shown Figure 3 The third metal clip 380 shown Figure 1A and Figure 3 The metal block 187 shown Figure 3 IC 390 shown Figure 3 The multiple bonding leads 392 shown, and Figure 1A and Figure 1B The molded package 194 is shown.
[0013] In the examples of this disclosure, semiconductor package 100 is a dual-drive metal-oxide-semiconductor field-effect transistor (DrMOSFET); in other examples of this disclosure, semiconductor package 100 is a dual-phase power stage without IC 390.
[0014] In the examples disclosed herein, the semiconductor package 100 is in the shape of a first cuboid, the first high-voltage side FET 420 and the second high-voltage side FET 422 are in the shape of a second cuboid, the first low-voltage side FET 460 and the second low-voltage side FET 462 are in the shape of a third cuboid, the metal block 187 is in the shape of a fourth cuboid, and the outer contour of the bottom surface of the lead frame 310 is rectangular. As shown in the figure, the first high-voltage side FET 420 and the second high-voltage side FET 422 are formed on two different semiconductor chips; alternatively, the first high-voltage side FET 420 and the second high-voltage side FET 422 can also be formed as common-drain FETs on the same semiconductor chip (not shown in the figure).
[0015] Figure 3 The lead frame 310 shown includes Figure 4 The shown core gasket 412 Figure 4 The common grounding pad 414 shown Figure 4 The first phase node lead 416 shown, and Figure 4 The second phase node lead 418 is shown. In this example, Figure 4 The die pad 412 shown is connected to the power (Vin) terminal. Figure 4 The common grounding pad 414 shown is connected to the grounding (PGND) terminal. As shown, the core pad 412 is generally rectangular, with multiple leads 410 on its first longitudinal side; the common grounding pad 414 is located on the opposite side of the first longitudinal side of the core pad 412 (i.e., the second longitudinal side) and extends to the entire longitudinal length of the core pad 412; the first phase node lead 416 and the second phase node lead 416 are located on the second longitudinal side of the core pad 412 and are separated from the core pad 412 by the common grounding pad 414.
[0016] Figure 4 The first high-voltage side FET 420 shown is mounted on Figure 4 On the core pad 412 shown. Figure 4 The first high-voltage side FET 420 shown has a source electrode 411 and a gate electrode 413 on its front side and a drain electrode 415 on its back side; the drain electrode 415 of the first high-voltage side FET 420 is electrically connected to the die pad 412.
[0017] Figure 4 The second high-voltage side FET 422 shown is mounted on Figure 4 On the core pad 412 shown. Figure 4 The second high-voltage side FET 422 shown has a source electrode 421 and a gate electrode 423 on its front side and a drain electrode 425 on its back side; the drain electrode 425 of the second high-voltage side FET 422 is electrically connected to the die pad 412.
[0018] A first metal clip 440 located on top of the first high-voltage side FET 420 connects the source electrode 411 of the first high-voltage side FET 420 to the first phase node lead 416; a second metal clip 442 located on top of the second high-voltage side FET 422 connects the source electrode 421 of the second high-voltage side FET 422 to the second phase node lead 418.
[0019] The first low-voltage side FET 460 is mounted on the top of the first metal clip 440. The first low-voltage side FET 460 has a source electrode 451 and a gate electrode 453 on its front side and a drain electrode 455 on its back side; the drain electrode 455 of the first low-voltage side FET 460 is electrically connected to the first metal clip 440.
[0020] The second low-voltage side FET 462 is mounted on the top of the second metal clip 442. The second low-voltage side FET 462 has a source electrode 461 and a gate electrode on its front side and a drain electrode 465 on its back side; the drain electrode 465 of the second low-voltage side FET 462 is electrically connected to the second metal clip 442.
[0021] The third metal clip 380 connects the source electrode 451 of the first low-voltage side FET 460 and the source electrode 461 of the second low-voltage side FET 462 to a common ground pad 414. In one example, the IC 390 is mounted on top of the first region of the third metal clip 380; in another example, the package does not include the IC 390.
[0022] In the examples disclosed herein, the third metal clip 380 includes Figure 3 The first vertical pin 331, shown, is connected to the common ground pad 414, and Figure 3 The second vertical pin 333, shown, is connected to the common ground pad 414. Figure 3 The distance 335 between the distal surface of the first vertical pin 331 and the distal surface of the second vertical pin 333 shown is greater than [missing value]. Figure 3 The distance 337 between the distal surface of the first metal clip 440 and the distal surface of the second metal clip 442 is shown.
[0023] The molded package 194 encloses a large portion of the first high-voltage side FET 420, the second high-voltage side FET 422, the first metal clip 440, the second metal clip 442, the first low-voltage side FET 460, the second low-voltage side FET 462, the IC 390, the lead frame 310, and at least a large portion of the third metal clip 380.
[0024] In this disclosed example, the semiconductor package 100 also includes Figure 4 The multiple solder layers 495 shown are encapsulated by the molded package 194.
[0025] In one example, metal block 187 is mounted on third metal clip 380. Figure 1A The top surface 189 of the metal block 187 shown is exposed from the molded package 194. The metal block 187 and the third metal clip 380 may be two separate components joined by solder or other adhesives; or the metal block 187 and the third metal clip 380 may be a single-piece structure (formed simultaneously in a single process step).
[0026] In another example, refer to Figure 2 Semiconductor package 200 without Figure 1A The metal block 187 shown indicates that the top surface of the molded package 294 has no exposed metal surface. This semiconductor package 200 and... Figure 1A The semiconductor package 100 shown has a similar structure, except that it does not include the metal block 187; the molded package 194 completely encloses the third metal clip 380. In yet another example, the semiconductor package 200 does not include the IC 390, in which case the semiconductor package 200 is a two-phase power stage.
[0027] In another example, refer to Figure 6EC and Figure 6ED The third metal clip 680B includes a lower portion 674, an upper portion 678, and a transition portion 676 connecting the lower portion 674 and the upper portion 678. The top surface of the upper portion 678 of the third metal clip 680B protrudes from the molded package 694B. As shown, the lower portion 674 includes a lower metal plate, and the upper portion 678 includes an upper metal plate parallel to the lower metal plate; the transition portion 676 includes a vertical metal plate substantially perpendicular to the lower and upper metal plates. In another example, the lower metal plate and the upper metal plate have the same thickness; in another example, the lower metal plate, the vertical metal plate, and the upper metal plate have the same thickness.
[0028] Figure 5 This is a flowchart illustrating a semiconductor packaging manufacturing process 500 in this disclosure. Process 500 may begin at step 502 and can manufacture multiple semiconductor packages simultaneously. In one example, Figure 6I This demonstrates the simultaneous manufacturing of two semiconductor packages; the number of semiconductor packages manufactured simultaneously can be adjusted according to demand. For simplicity, Figure 6AA-6HB The manufacturing steps of a single semiconductor package are shown only.
[0029] In step 502, refer to Figure 6AA and Figure 6ABA lead frame 610 is provided. The lead frame 610 includes a die pad 612, a common ground pad 614, a first phase node lead 616, and a second phase node lead 618. In this example, the die pad 612 is connected to the power (Vin) terminal, and the common ground pad 614 is connected to the ground (PGND) terminal. Step 504 is performed after step 502.
[0030] In step 504, refer to Figure 6BA and Figure 6BB Install the first high-voltage side FET 620 and the second high-voltage side FET 622. Figure 4 The first high-voltage side FET 620 shown is mounted on the die pad 612, with a source electrode 611 and a gate electrode 613 on its front side and a drain electrode on its back side, and the drain electrode is electrically connected to the die pad 612; the second high-voltage side FET 622 is mounted on the die pad 612, with a source electrode 621 and a gate electrode 623 on its front side and a drain electrode on its back side, and the drain electrode is electrically connected to the die pad 612. Step 504 is followed by step 506.
[0031] In step 506, refer to Figure 6CA and Figure 6CB The first metal clip 640 and the second metal clip 642 are connected. The first metal clip 640 connects the source electrode 611 of the first high-voltage side FET 620 to the first phase node lead 616, and the gate electrode 613 of the first high-voltage side FET 620 is exposed in the first metal clip 640; the second metal clip 642 connects the source electrode 621 of the second high-voltage side FET 622 to the second phase node lead 618, and the gate electrode 623 of the second high-voltage side FET 622 is exposed in the second metal clip 642. Step 508 is executed after step 506.
[0032] In step 508, refer to Figure 6DA and Figure 6DB A first low-voltage side FET 660 and a second low-voltage side FET 662 are mounted. The first low-voltage side FET 660 is mounted on a first metal clip 640, with a source electrode 651 and a gate electrode 653 on its front side and a drain electrode on its back side. The second low-voltage side FET 662 is mounted on a second metal clip 642, with a source electrode 661 and a gate electrode 663 on its front side and a drain electrode on its back side. In this example, the mounting position of the first low-voltage side FET 660 on the first metal clip 640 is horizontally offset from the first high-voltage side FET 620, and the mounting position of the second low-voltage side FET 662 on the second metal clip 642 is horizontally offset from the second high-voltage side FET 622. Step 510 is executed after step 508.
[0033] In step 510, refer to Figure 6EA , Figure 6EB and Figure 6EC The third metal clip 680 is connected. The third metal clip 680 connects the source electrode 451 of the first low-voltage side FET 660 and the source electrode 461 of the second low-voltage side FET 462 to the common ground pad 614, and the gate electrode 653 of the first low-voltage side FET 660 and the gate electrode 663 of the second low-voltage side FET 662 are exposed from the third metal clip 680.
[0034] In the example of this disclosure, the third metal clip 680 includes a first vertical pin 631 and a second vertical pin 633 connected to a common grounding pad 614. Figure 3 The distance 335 between the distal surface of the first vertical pin 331 and the distal surface of the second vertical pin 333 shown is greater than [missing value]. Figure 3 The distance 337 between the distal surface of the first metal clip 440 and the distal surface of the second metal clip 442 is shown.
[0035] In one example, metal block 687 is mounted on third metal clip 680, and its horizontal mounting position overlaps at least a portion of the first low-voltage side FET 660 and the second low-voltage side FET 662; the top surface of metal block 687 extends from... Figure 6HB Exposed in the molded package 694 shown. The metal block 687 and the third metal clip 680 can be two separate components before integration, or the metal block 687 and the third metal clip 680 can be a one-piece molded structure (formed simultaneously in a single process step).
[0036] In another example, refer to Figure 2 Semiconductor package 200 without Figure 1A The metal block 187 shown indicates that the top surface of the molded package 294 has no exposed metal surface. This semiconductor package 200 and... Figure 1A The semiconductor package 100 shown has a similar structure, except that it does not include the metal block 187, and the molded package 194 completely encloses the third metal clip 380. In another example, the semiconductor package 200 does not include the IC 390, in which case the semiconductor package 200 is a two-phase power stage.
[0037] In another example, refer to Figure 6EC and Figure 6ED The third metal clip 680B includes a lower portion 674, a vertical portion 676, and an upper portion 678, with the top surface of the upper portion 678 protruding from the molded package 694B. Step 512 is performed after step 510.
[0038] In step 512, refer to Figure 6FA and Figure 6FB Connect to the optional IC 690. The IC 690 is connected via a solder layer ( Figure 4One of the multiple solder layers shown is mounted on the third metal clip 680. In one example, the horizontal mounting position of IC 690 on the third metal clip 680 overlaps with the first high-voltage side FET 620 and / or the second high-voltage side FET 622. Option steps 514 or 516 can be performed after step 512.
[0039] In step 514, refer to Figure 6GA and Figure 6GB Multiple bonding leads 692 are used to connect the gate electrodes of the high-side FET and the low-side FET to IC 690. Step 514 is followed by step 516.
[0040] In step 516, refer to Figure 6HA and Figure 6HB A molded package 694 is formed. This molded package 694 encloses a first high-voltage side FET 620, a second high-voltage side FET 622, a first metal clip 640, a second metal clip 642, a first low-voltage side FET 660, a second low-voltage side FET 662, an IC 690, a majority portion of the lead frame 610, and at least a majority portion of the third metal clip 680. Step 518 is performed after step 516.
[0041] In step 518, refer to Figure 6I A monomerization process 697 is performed to separate semiconductor package 698 from the adjacent semiconductor package 699. In this example, both semiconductor package 698 and the adjacent semiconductor package 699 are dual-drive metal-oxide-semiconductor field-effect transistors (DrMOSFETs).
[0042] Those skilled in the art will understand that modifications can be made to the embodiments disclosed herein, such as adjusting the number of bonding leads; other modifications may be conceived by those skilled in the art, and all such modifications should be considered within the scope of protection defined by the claims of this invention.
Claims
1. A semiconductor package, comprising: A lead frame, comprising: A core pad, A public grounding mat, A first phase node lead, and A second phase node lead; A first high-voltage-side field-effect transistor (FET) mounted on the die pad, the first high-voltage-side FET comprising: A source electrode and a gate electrode are located on the front side of the first high-voltage side FET, and a drain electrode is located on the back side of the first high-voltage side FET; A second high-voltage side FET mounted on the die pad, the second high-voltage side FET comprising: A source electrode and a gate electrode are located on the front side of the second high-voltage side FET, and a drain electrode is located on the back side of the second high-voltage side FET; A first metal clip that connects the source electrode of the first high-voltage side FET to the first phase node lead; A second metal clip that connects the source electrode of the second high-voltage side FET to the second phase node lead; A first low-voltage side FET is mounted on the first metal clip. The first low-voltage side FET includes a source electrode and a gate electrode located on the front side of the first low-voltage side FET, and a drain electrode located on the back side of the first low-voltage side FET. A second low-voltage side FET is mounted on the second metal clip. The second low-voltage side FET includes a source electrode and a gate electrode located on the front side of the second low-voltage side FET, and a drain electrode located on the back side of the second low-voltage side FET. A third metal clip connecting the source electrode of the first low-voltage side FET and the source electrode of the second low-voltage side FET to the common ground pad; And a molded package that encloses the first high-voltage side FET, the second high-voltage side FET, the first metal clip, the second metal clip, the first low-voltage side FET, the second low-voltage side FET, most of the lead frame, and at least most of the third metal clip.
2. The semiconductor package of claim 1 further includes an integrated circuit (IC) mounted on the third metal clip, wherein the molded package encapsulates the IC.
3. The semiconductor package of claim 2 further includes a metal block mounted on the third metal clip; The top surface of the metal block is exposed from the molded package.
4. The semiconductor package of claim 2, wherein the third metal clip comprises: A lower part; as well as An upper part; The IC is mounted on the lower part of the third metal clip, and the top surface of the upper part of the third metal clip is exposed from the molded package.
5. The semiconductor package of claim 2, wherein the mounting position of the first low-voltage side FET on the first metal clip is horizontally offset from the first high-voltage side FET; and The mounting position of the second low-voltage side FET on the second metal clip is offset horizontally from that of the second high-voltage side FET.
6. The semiconductor package of claim 5, wherein the horizontal mounting position of the IC on the third metal clip overlaps with the first high-voltage side FET or the second high-voltage side FET.
7. The semiconductor package of claim 2, wherein the third metal clip comprises: The first vertical pin connected to the common grounding pad; and Connect to the second vertical pin of the common grounding pad; Wherein, the distance between the distal surface of the first vertical pin and the distal surface of the second vertical pin is greater than the distance between the distal surface of the first metal clip and the distal surface of the second metal clip.
8. The semiconductor package of claim 2, wherein the first high-voltage side FET and the second high-voltage side FET are formed on the same semiconductor chip as common-drain metal-oxide-semiconductor field-effect transistors (MOSFETs).
9. The semiconductor package of claim 1, wherein the mounting position of the first low-voltage side FET on the first metal clip is horizontally offset from the first high-voltage side FET, and the mounting position of the second low-voltage side FET on the second metal clip is horizontally offset from the second high-voltage side FET.
10. The semiconductor package of claim 1, wherein the first high-voltage side FET and the second high-voltage side FET are formed on the same semiconductor chip as common-drain metal-oxide-semiconductor field-effect transistors (MOSFETs).