Semiconductor package with low side field effect transistor chips of different sizes and method of manufacturing the same

Abstract

A semiconductor package includes a lead frame, a high-side chip, a first low-side chip, a second low-side chip, a first metal clip, a second metal clip, an integrated circuit (IC), and a molded package. A manufacturing method includes the steps of: providing a lead frame; mounting a high-side chip, a first low-side chip, and a second low-side chip; mounting a first metal clip and a second metal clip; mounting an integrated circuit; forming a molded package; and performing a dicing process.

Description

Technical Field

[0001] This invention generally relates to a semiconductor package and a method for manufacturing the same. More specifically, this invention relates to a semiconductor package for low-side field-effect transistor (FET) chips of different sizes and a method for manufacturing the same. Background Technology

[0002] U.S. Patent Application Publication No. 2017 / 0047315 by Otremba et al. discloses a semiconductor power converter device comprising a first semiconductor power chip on a first carrier, a second semiconductor power chip on a second carrier, and a third semiconductor control integrated circuit chip located above a contact clip. Figure 1A of this disclosure shows a conventional package layout of a single-phase semiconductor power converter package 100. Each switching node voltage (VSWH) pin 110 of the semiconductor package 100 is electrically connected.

[0003] Figure 1B This is the package layout of semiconductor package 150 in an embodiment of this disclosure. For a two-phase semiconductor power converter package, the VSWH pins are divided into a first group of one or more VSWH pins 160 and a second group of one or more VSWH pins 170. The two-phase semiconductor power converter package includes a first phase for operation under light load conditions to improve light load efficiency, and a second phase for operation under heavy load conditions. Summary of the Invention

[0004] The present invention discloses a semiconductor package comprising a lead frame, a high-side chip, a first low-side chip, a second low-side chip, a first metal clip, a second metal clip, an integrated circuit (IC), and a molded package.

[0005] The present invention also discloses a method for manufacturing a semiconductor package. The method includes the following steps: providing a lead frame; mounting a high-side chip, a first low-side chip, and a second low-side chip; mounting a first metal clip and a second metal clip; mounting an integrated circuit; forming a molded package; and performing a dicing process. Attached Figure Description

[0006] Figure 1A shows the packaging layout of a conventional semiconductor package. Figure 1B This indicates the packaging layout of the semiconductor package in the embodiments of this disclosure.

[0007] Figure 2A This is a top perspective view of the semiconductor package in an embodiment of the present disclosure. Figure 2B This is a bottom-view perspective view of the semiconductor package. Figure 2AA This is a top perspective view of another semiconductor package in this embodiment.

[0008] Figure 3AThis represents a top perspective view of yet another semiconductor package according to an embodiment of the present disclosure. Figure 3B This is an exploded view of the semiconductor package.

[0009] Figure 4 This is a flowchart illustrating the semiconductor packaging manufacturing process in an embodiment of this disclosure.

[0010] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F and Figure 5G This indicates the corresponding embodiment in this disclosure. Figure 4 The semiconductor packaging manufacturing process shown is a semiconductor process. Detailed Implementation

[0011] Figure 1A shows the package layout of a conventional semiconductor package 100. Each VSWH pin 110 of the semiconductor package 100 is electrically connected. Figure 1B This is the package layout of semiconductor package 150 in an embodiment of this disclosure. The VSWH pins are divided into a first group of one or more VSWH pins 160 and a second group of one or more VSWH pins 170 to improve light-load efficiency. Electrical operation includes two phases: a first phase (miniature phase) and a second phase. The first phase has excellent light-load efficiency. The second phase is off when the Forced Continuous On Mode (FCCM) 180 is low and the current is small. In Discontinuous Current Mode (DCM) operation, the second phase remains off until the current limit is reached or FCCM 180 is enabled. When the second phase is off, the offset of the current monitoring output signal (IMON) 190 is improved. In embodiments of this disclosure, the resistance of the first phase is three times that of the second phase. The inductance of the first phase is two to six times that of the second phase.

[0012] Figure 2A This is a top perspective view of the semiconductor package 200 in an embodiment of this disclosure. Figure 2B This is a bottom-view perspective of the semiconductor package. Figure 2AA This is a top-view perspective view of semiconductor package 202. Figure 3A This is a top perspective view of another semiconductor package 300 in an embodiment of this disclosure. Figure 3B This is an exploded view of the semiconductor package. The difference between semiconductor package 300 and semiconductor package 200 is that semiconductor package 300 does not contain... Figure 2AA The metal block 205 in the semiconductor package 200 shown. Figure 3A In the diagram, the molded package 390 is shown in a transparent form. In embodiments of this disclosure, the semiconductor package 200 is cuboid in shape.

[0013] Now refer to Figure 3B The semiconductor package 300 includes a lead frame 310, a high-side chip 320, a first low-side chip 330, a second low-side chip 340, a first metal clip 350, a second metal clip 360, an integrated circuit 370, and a molded package 390. In one embodiment, the semiconductor package 300 is a quad flat no-lead (QFN) package. In another embodiment, the semiconductor package 300 is a driver and metal-oxide-semiconductor field-effect transistor module (DrMOS), wherein the MOSFET is a metal-oxide-semiconductor field-effect transistor. In embodiments of this disclosure, the high-side chip 320 is a cuboid-shaped MOSFET chip. The first low-side chip 330 is a cuboid-shaped MOSFET chip. The second low-side chip 340 is a cuboid-shaped MOSFET chip.

[0014] The lead frame 310 includes a high-side drain pad 311, an optional first high-side gate lead 313, an optional second high-side gate lead 313, a first low-side source pad 312, a first low-side gate lead 314, a second low-side source pad 316, and a second low-side gate lead 318. The first low-side source pad 312 and the second low-side source pad 316 are connected together, and both are arranged side by side with and separate from the high-side drain pad 511.

[0015] In embodiments of this disclosure, the first solder layer 307 is located between the lead frame 310 and the high-side chip 320, the first low-side chip 330, and the second low-side chip 340.

[0016] The high-side chip 320 is mounted on the high-side drain pad 311. The front side of the high-side chip 320 has a first source electrode 322, a first gate electrode 324, a second source electrode 326 electrically isolated from the first source electrode 322, and a second gate electrode 328 electrically isolated from the first gate electrode 324. The back side of the high-side chip 320 has a drain electrode 321.

[0017] The first low-side chip 330 is flipped and mounted on the first low-side source pad 312. The front side of the first low-side chip 330 has a source electrode 332 and a gate electrode 334, and the back side of the first low-side chip 330 has a drain electrode 331. The gate electrode 334 of the first low-side chip 330 is connected to the first low-side gate lead 314 of the lead frame 310.

[0018] The second low-side chip 340 is flipped and mounted on the second low-side source pad 316. The front side of the second low-side chip 340 has a source electrode 342 and a gate electrode 344, and the back side of the second low-side chip 340 has a drain electrode 341. The gate electrode 344 of the second low-side chip 340 is connected to the second low-side gate lead 318 of the lead frame 310.

[0019] In embodiments of this disclosure, the second solder layer 309 is located between the first metal clip 350, the second metal clip 360 and the high-side chip 320, the first low-side chip 330 and the second low-side chip 340.

[0020] A first metal clip 350 connects the first source electrode 322 of the high-side chip 320 to the drain electrode 331 of the first low-side chip 330. A second metal clip 360 connects the second source electrode 326 of the high-side chip 320 to the drain electrode 341 of the second low-side chip 340. An integrated circuit 370 can be mounted in one or both of the first metal clip 350 and the second metal clip 360. In one embodiment of this disclosure, the integrated circuit 370 is mounted in the first metal clip 350. In an embodiment of this disclosure, a third solder layer 319 is located between the integrated circuit 370 and the first metal clip 350 and the second metal clip 360.

[0021] A molded package 390 encapsulates a large portion of the high-side chip 320, a first low-side chip 330, a second low-side chip 340, a first metal clip 350, a second metal clip 360, an integrated circuit 370, and a lead frame 310. "Largest portion" refers to more than 50% of the portion. In embodiments of this disclosure, the bottom surface of the lead frame 310 is exposed from the molded package 390.

[0022] Semiconductor package 300 also includes Figure 3A Multiple bonding wires 380 are shown, which electrically connect the integrated circuit 370 to the high-side chip 320, the first low-side chip 330, the second low-side chip 340, and the lead frame 310. The molded package 390 also encapsulates these bonding wires 380. The first gate electrode 324 and the second gate electrode 328 of the high-side chip 320 are electrically connected to the integrated circuit 370.

[0023] In embodiments of this disclosure, the size of the first low-side chip 330 is smaller than the size of the second low-side chip 340. In one embodiment, the size of the first low-side chip 330 is 30% to 35% of the size of the second low-side chip 340. In another embodiment, the first low-side chip 330 and the second low-side chip 340 have the same thickness. The first low-side chip 330 and the second low-side chip 340 have the same length (e.g., 1.54 mm). The width of the first low-side chip 330 is 30% to 35% of the width of the second low-side chip 340. In one embodiment, the width of the first low-side chip 330 is 0.6 mm, and the width of the second low-side chip 340 is 1.74 mm.

[0024] In embodiments of this disclosure, the first low-side chip 330 and the second low-side chip 340 are aligned along the horizontal direction (X direction).

[0025] In embodiments of this disclosure, Figure 2AA The semiconductor package 200 shown also includes components mounted on... Figure 3B The metal block 205 of the second metal clip 360 shown. Figure 2AA The molded package 290 shown also encapsulates most of the metal block 205 (“most” means more than 50%). The top surface 207 of the metal block 205 is exposed from the molded package 290 to facilitate heat dissipation.

[0026] Figure 4 This is a flowchart illustrating a semiconductor packaging manufacturing process 400 according to an embodiment of the present disclosure. The process 400 may begin at step 402. Multiple semiconductor packages can be manufactured simultaneously. In one embodiment, Figure 5G This indicates that two semiconductor packages are being manufactured simultaneously. The number of semiconductor packages manufactured simultaneously can vary depending on demand. For the sake of simplicity, Figures 5A to 5F A top view showing the process steps involved in manufacturing a single semiconductor package. Figure 5G This represents a top-down 3D view.

[0027] In step 402, now refer to Figure 5AA leadframe 510 is provided. The leadframe 510 includes a generally rectangular high-side drain pad 511, one or more optional high-side gate leads 513, a first low-side source pad 512, a first low-side gate lead 514 adjacent to the first low-side source pad 512, a second low-side source pad 516, and a second low-side gate lead 518 adjacent to the first low-side source pad 512. The first low-side source pad 512 and the second low-side source pad 516 are connected together, both of which are arranged side-by-side with and separate from the high-side drain pad 511. The first low-side gate lead 514 is disposed at a first cut-off portion of the first low-side source pad 512, and the second low-side gate lead 518 is disposed at a second cut-off portion of the second low-side source pad 516. In embodiments of this disclosure, the first low-side gate lead 514 is separated from the high-side drain pad 511 via the first low-side source pad 512, and the second low-side gate lead 518 is separated from the high-side drain pad 511 via the second low-side source pad 516. Alternatively, the first low-side gate lead 514 and / or the second low-side gate lead 518 may be respectively disposed between the high-side drain pad 511 and the first low-side source pad 512 and / or the second low-side source pad 516. Step 404 can be executed after step 402.

[0028] In step 404, now refer to Figure 3B and Figure 5A ,pass Figure 3B The first solder layer 307 shown will Figure 5A The high-side chip 520, the first low-side chip 530, and the second low-side chip 540 shown are mounted on the lead frame 510. The high-side chip 520 is mounted on the high-side drain pad 511. The front side of the high-side chip 520 has... Figure 3B The first source electrode 322, the first gate electrode 324, the second source electrode 326, and the second gate electrode 328 shown are provided on the back side of the high-side chip 520. Figure 3B The drain electrode 321 is shown.

[0029] The first low-side chip 530 is flipped and mounted on the first low-side source pad 512. The front side of the first low-side chip 530 has... Figure 3B The source electrode 332 and gate electrode 334 are shown. The back side of the first low-side chip 530 is provided with... Figure 3B The drain electrode 331 is shown. The gate electrode 334 of the first low-side chip 530 is connected to the first low-side gate lead 514 of the lead frame 510.

[0030] The second low-side chip 540 is flipped and mounted on the second low-side source pad 516. The front side of the second low-side chip 540 has... Figure 3B The source electrode 342 and gate electrode 344 are shown, and the back side of the second low-side chip 540 is provided with Figure 3B The drain electrode 341 is shown. The gate electrode 344 of the second low-side chip 540 is connected to the second low-side gate lead 518 of the lead frame 510.

[0031] In embodiments of this disclosure, the first low-side chip 530 and the second low-side chip 540 are aligned in the vertical direction (X direction). The size of the first low-side chip 530 may be smaller than the size of the second low-side chip 540. In one embodiment, the size of the first low-side chip 530 is 30% to 35% of the size of the second low-side chip 540. In another embodiment, the first low-side chip 530 and the second low-side chip 540 have the same thickness. The first low-side chip 530 and the second low-side chip 540 have the same length (e.g., 1.54 mm). The width of the first low-side chip 530 is 30% to 35% of the width of the second low-side chip 540. In one embodiment, the width of the first low-side chip 530 is 0.6 mm, and the width of the second low-side chip 540 is 1.74 mm. Step 406 can be performed after step 404.

[0032] In step 406, now refer to Figure 3B and Figure 5C ,pass Figure 3B The second solder layer 309 shown is installed. Figure 5C The first metal clip 550 and the second metal clip 560 are shown. The first metal clip 550 holds the high-side chip 520... Figure 3B The first source electrode 322 and the first low-side chip 530 shown Figure 3B The drain electrode 331 shown is electrically connected. The second metal clip 560 connects the high-side chip 520. Figure 3B The second source electrode 326 and the second low-side chip 540 shown Figure 3B The drain electrode 341 shown is electrically connected. Step 408 can be executed after step 406.

[0033] In step 408, now refer to Figure 5D Install integrated circuit 570. As shown in the figure, integrated circuit 570 can be mounted on the first metal clip 550 and the second metal clip 560. Alternatively, integrated circuit 570 can be mounted on either the first metal clip 550 or the second metal clip 560. Figure 2A , Figure 2AA and Figure 2B The semiconductor package shown may include only the high-side chip 520, the first low-side chip 530, and the second low-side chip 540, but not the integrated circuit 570. In this case, the operation described in step 408 can be skipped.

[0034] In embodiments of this disclosure, step 408 further includes attaching the optional metal block 205 shown in FIG. 1A to the second metal clip 560. Option steps 410 or 412 may be performed after step 408.

[0035] In step 410, now refer to Figure 5E Multiple bonding wires 580 are provided. These bonding wires 580 electrically connect the integrated circuit 570 to the high-side chip 520, the first low-side chip 530, the second low-side chip 540, and the lead frame 510. In one embodiment, the high-side chip 520 is connected to the integrated circuit 570 via a direct bonding wire connection. Figure 3B The first gate electrode 324 and the second gate electrode 328 shown are electrically connected to the integrated circuit 570. In another embodiment, a first pair of bonding wires connects the first high-side gate lead to the first gate electrode 324 on the high-side chip 520 and the integrated circuit 570, respectively, and a second pair of bonding wires connects the second high-side gate lead to the second gate electrode 328 on the high-side chip 520 and the integrated circuit 570, respectively. Step 412 can be executed after step 410.

[0036] In step 412, now refer to Figure 5F This forms a molded package 590. The molded package 590 encapsulates a high-side chip 520, a first low-side chip 530, a second low-side chip 540, a first metal clip 550, a second metal clip 560, an integrated circuit 570, multiple bonding wires 580, and a majority (“major” means more than 50%) of the lead frame 310. In embodiments of this disclosure, the bottom surface of the lead frame 510 is exposed from the molded package 590. Figure 2AA As shown, the top surface 207 of the metal block 205 is also exposed from the molded package 290 to facilitate heat dissipation. Step 414 can be performed after step 412.

[0037] In step 414, now refer to Figure 5G A dicing process 597 is performed to separate the semiconductor package 598 from the adjacent semiconductor package 599. In embodiments of this disclosure, both semiconductor package 598 and the adjacent semiconductor package 599 are cuboid in shape. In one embodiment, both semiconductor package 598 and the adjacent semiconductor package 599 are QFN packages. In another embodiment, both semiconductor package 598 and the adjacent semiconductor package 599 are biphase DrMOS.

[0038] Those skilled in the art will understand that modifications can be made to the embodiments disclosed herein. For example, the number of multiple bonding wires 580 can be varied as needed. Other modifications may also occur to those skilled in the art, and all such modifications should be considered to fall within the scope of protection of the invention as defined by the claims.

Claims

1. A semiconductor package, comprising: A lead frame, comprising: A high-side drain pad, A first low-side source pad, A first low-side gate lead, A second low-side source pad, and A second low-side gate lead; A high-side chip, the high-side chip being mounted on the high-side drain pad, the high-side chip comprising: a first source electrode, a first gate electrode, a second source electrode, and a second gate electrode located on the front side of the high-side chip, and A drain electrode located on the back of the high-side chip; A first low-side chip, the first low-side chip being flipped and mounted on a first low-side source pad, the first low-side chip comprising: A source electrode and a gate electrode are located on the front side of the first low-side chip, and a drain electrode is located on the back side of the first low-side chip; A second low-side chip, the second low-side chip being flipped and mounted on a second low-side source pad, the second low-side chip comprising: A source electrode and a gate electrode are located on the front side of the second low-side chip, and a drain electrode is located on the back side of the second low-side chip; A first metal clip connects the first source electrode of the high-side chip to the drain electrode of the first low-side chip. A second metal clip connects the second source electrode of the high-side chip to the drain electrode of the second low-side chip; as well as A molded package encapsulates the high-side chip, the first low-side chip, the second low-side chip, the first metal clip, the second metal clip, the integrated circuit, and most of the lead frame; Wherein, the gate electrode of the first low-side chip is connected to the first low-side gate lead of the lead frame; and The gate electrode of the second low-side chip is connected to the second low-side gate lead of the lead frame.

2. The semiconductor package of claim 1 further includes an integrated circuit (IC) mounted on the first metal clip.

3. The semiconductor package of claim 2 further includes a metal block mounted on the second metal clip, wherein, The molded package also encapsulates most of the metal block; and The top surface of the metal block is exposed from the molded package.

4. The semiconductor package of claim 2 further includes a plurality of bonding wires connecting the integrated circuit to the high-side chip, the first low-side chip, the second low-side chip, and the lead frame. in, The molded package also encapsulates the multiple bonding wires; and The first gate electrode and the second gate electrode of the high-side chip are electrically connected to the integrated circuit.

5. The semiconductor package of claim 2, wherein the size of the first low-side chip is smaller than the size of the second low-side chip.

6. The semiconductor package of claim 5, wherein the size of the first low-side chip is 30% to 35% of the size of the second low-side chip.

7. The semiconductor package of claim 5, wherein the first low-side chip and the second low-side chip have the same thickness; in, The first low-side chip and the second low-side chip have the same length; and The width of the first low-side chip is 30% to 35% of the width of the second low-side chip.

8. The semiconductor package of claim 1, wherein the first low-side chip and the second low-side chip are aligned in a horizontal direction.

9. The semiconductor package of claim 1, wherein the semiconductor package is a quad flat no-lead (QFN) package.

10. The semiconductor package of claim 1, wherein the first low-side source pad is connected to the second low-side source pad.

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