Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor package is disclosed, comprising: a substrate including an insulating layer having a first upper main surface and a second lower main surface opposite to the first upper main surface; a lead frame including a first upper main surface and a second lower main surface opposite to the first upper main surface; a semiconductor transistor die disposed on the first upper main surface of the lead frame; a bonding layer coupling the second lower main surface of the lead frame to the first upper main surface of the insulating layer, wherein the bonding layer has a melting point that is entirely or partially greater than 260°C; and an encapsulation portion covering an internal portion of the lead frame, the semiconductor transistor die, and the insulating layer; wherein the thickness of the bonding layer is in the range of 40 μm to 200 μm, particularly from 100 μm to 200 μm, particularly from 50 μm to 150 μm; or wherein the thickness of the bonding layer is in the range of 1 μm to 50 μm, particularly from 10 μm to 30 μm.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] Semiconductor devices, especially power semiconductor devices, may need to meet stringent electrical performance requirements. For example, such semiconductor devices may need to carry high currents, operate at high voltages, and have low Ro. DS（on） These requirements also apply to connectors that electrically couple different parts of a semiconductor device to each other. In particular, solder joints do not necessarily meet these requirements in every application. Furthermore, another major problem is the ineffective dissipation of excessive heat generated by semiconductor power transistors, with the electrical interconnect layers also contributing significantly to this excessive heat. Improved semiconductor devices and improved methods for manufacturing semiconductor devices can help address these and other problems. Further background information can be found in DE 10 2010 044709 A1, US 2011 / 0074010 A1, US 5767573, and US 2008 / 0230905 A1.

[0003] This disclosure is necessary for these and other reasons. Summary of the Invention

[0004] A first aspect of this disclosure relates to a semiconductor package comprising: a substrate including an insulating layer including a first upper main surface and a second lower main surface opposite to the first upper main surface; a lead frame including a first upper main surface and a second lower main surface opposite to the first upper main surface; a semiconductor transistor die disposed on the first upper main surface of the lead frame; a bonding layer coupling the second lower main surface of the lead frame to the first upper main surface of a ceramic insulating layer, wherein the bonding layer has a melting point that is entirely or partially greater than 260°C; and an encapsulation portion covering an internal portion of the lead frame, the semiconductor transistor die, and the ceramic insulating layer; wherein the thickness of the bonding layer is in the range of 40 μm to 200 μm, particularly in the range of 100 μm to 200 μm, particularly in the range of 50 μm to 150 μm; or wherein the thickness of the bonding layer is in the range of 1 μm to 50 μm, particularly in the range of 10 μm to 30 μm.

[0005] According to the first aspect, the high melting point of the bonding layer of the semiconductor package, greater than 260°C, will allow customers to apply heat sinks with temperatures still below 260°C. Typically, the bonding layer can be a bonding line with a thickness (BLT) ranging from over 20µm to 200µm. Specifically, the BLT can be in the range of over 40µm to 200µm. Within this range and its sub-ranges, Sn-based solder systems incorporating high-melting-point core materials are applied. However, BLTs in the range of 1µm to 50µm are also conceivable. In this case, a sub-range of 10µm–30µm proves advantageous.

[0006] A second aspect of this disclosure relates to a method for manufacturing a semiconductor package, the method comprising: providing a substrate including an insulating layer comprising a first upper main surface and a second lower main surface opposite to the first upper main surface; providing a lead frame including a first upper main surface and a second lower main surface opposite to the first upper main surface; disposing a semiconductor transistor die on the first upper main surface of the lead frame; and applying a bonding layer on one or both of the second lower main surface of the lead frame and the first upper main surface of the insulating layer, wherein the bonding layer is formed from at least one source material having at least one first transition temperature by diffusion bonding or diffusion sintering. After formation, the bonding layer has a second transition temperature higher than the first transition temperature; the lead frame is connected to the substrate by performing melting and subsequent reflow processes; and an encapsulation covering the inner portion of the lead frame, the semiconductor transistor die, and the insulating layer is applied, wherein the thickness of the bonding layer is in the range of 40 μm to 200 μm, particularly in the range of 100 μm to 200 μm, particularly in the range of 50 μm to 150 μm; or wherein the thickness of the bonding layer is in the range of 1 μm to 50 μm, particularly in the range of 10 μm to 30 μm.

[0007] According to an embodiment of the semiconductor package of the first aspect, the bonding layer comprises one or more materials selected from the group consisting of Pb-free materials, SnSb materials, NiSn materials, Sn materials, Cu materials, Ag materials, Ag adhesive materials, or mixed sintering pastes. Soldering systems based on SnSb materials have proven advantageous, but systems based on Cu materials (i.e., Cu alloys) can also be used.

[0008] Specifically, the bonding layer of the semiconductor package of the first aspect may include a diffusion-active layer system or a diffusion-active particle system, wherein the diffusion-active layer system and / or diffusion-active particle system includes sintered particles, metals, or intermetallic compounds. In the context of this disclosure, the term "diffusion-active layer system" may refer to a Sn-Cu-Sn layer system or a solder paste system having a high melting point.

[0009] The bonding layer may specifically include sintering paste, sintering layer or sintering sheet.

[0010] According to the method in the second aspect, the second transition temperature can be higher than 260°C.

[0011] According to an embodiment of the semiconductor packaging in the first aspect, the Pb-free material of the bonding layer, which is one of the above embodiments, does not exclude the possibility that trace amounts of lead may be present, which may inevitably occur during the manufacturing process.

[0012] According to an embodiment of the semiconductor package of the first aspect, the bonding layer is based on or includes a metal. Regarding the method of the second aspect, at least one source metal used to manufacture the bonding layer may include a metal.

[0013] According to an embodiment of the semiconductor package of the first aspect, the bonding layer includes a thickness in the range of 40 μm to 200 μm, particularly in the range of 100 μm to 200 μm, particularly in the range of 50 μm to 150 μm.

[0014] According to an embodiment of the semiconductor package of the first aspect, the bonding layer comprises a material having a thermal conductivity greater than 15 W / mK.

[0015] According to an embodiment of the semiconductor package of the first aspect, the bonding layer includes one or more materials selected from the group consisting of Pb-free materials, CuSn materials, transient liquid phase welding materials, SnSb materials, NiSn materials, Sn materials, Ag materials, Ag adhesive materials, Cu materials, Cu adhesive materials, or mixed sintering pastes.

[0016] According to an embodiment of the semiconductor package of the first aspect, a ceramic insulating layer is the central layer of a substrate, wherein the substrate is one of direct copper bonding (DCB), active metal bonding (AMB), or insulating metal substrate (IMS). Furthermore, the ceramic insulating layer can be a layer composed of sputtered ceramic or directly plated Cu ceramic. In particular, the ceramic insulating layer can be a layer including a metallization layer having a thickness in the range of 1 to 50 µm.

[0017] According to an embodiment of the semiconductor package of the first aspect, the substrate includes a central layer, a first upper metal layer, and a second lower metal layer. As an example, the first upper metal layer has a thickness of 2000 / 1000 / 800 / 300 / 250 / 125 / 75 / 50 / 20 / 10 μm or less, and even as low as 1 μm. The first upper metal layer may be a sputtered seed layer or an organic seed layer. In particular, the thickness of the first upper metal layer can be in the range of 500 µm to 10 µm. More particularly, the thickness of the first upper metal layer can be less than 300 µm, preferably 127 µm, 20 µm, or 10 µm.

[0018] A first top metallization layer with a thickness of 300 µm may be best suited for direct copper bonding substrates, while a first top metallization layer with a thickness of 127 µm may be best suited for active metal brazing substrates (AMB). A thickness of 20 µm may be suitable for direct copper plating substrates (DPC).

[0019] According to an embodiment of the semiconductor package of the first aspect, the substrate includes a single insulating layer having a bottom surface disposed on the outside. On the customer side, a heat sink can be applied directly to the bottom surface of the single ceramic layer. The heat sink can be larger in size compared to the semiconductor package. Alternatively, metal layers can be applied on both sides of the ceramic layer. On the top side, a bonding layer may be required, but not at the system level, especially for high voltage and AMD TSC. Asymmetric designs tend to be curved, thus allowing for the application of thinner metal layers.

[0020] According to an embodiment of the semiconductor packaging of the first aspect, the ceramic insulating layer comprises one or more materials derived from the group consisting of Al2O3, Si3N4, H-AlN, AlN, and diamond. Other insulating layers are also conceivable instead of the ceramic insulating layer. In particular, the insulating layer may be an IMS (isolated metal substrate) or may be made of an organic insulating material. The insulating layer may be a multilayer organic substrate including a thermally conductive layer comprising, for example, epoxy resin, polyimide, or silicone resin, which may be filled with ceramic particles such as Al2O3, AlN, BN, diamond, etc.

[0021] Semiconductor transistor dies can be wide-bandgap semiconductor transistor dies, especially GaN, SiC, or gallium oxide (Ga2O3) transistor dies.

[0022] Furthermore, semiconductor transistor dies can be configured as power semiconductor transistor dies. A power transistor is a switching device rated to accommodate a voltage of at least 20V, and more commonly 100V, 600V, 1200V, 2kV, 3.3kV or higher, and / or rated to accommodate a current of at least 1A, and more commonly 10A, 50A, 100A, 500A, 1000A or higher. Power transistor dies can be part of a multi-chip configuration and / or a multi-die pad configuration.

[0023] The interconnect technologies described in this disclosure include welding, including reflow and vapor phase welding, sintering, particularly Ag and Cu sintering, and pressure and pressureless sintering. Additionally, additional thermal interface materials can be used, such as phase change materials, thermal grease materials, gap pads, gap fillers, thermally conductive adhesives, and graphite pads.

[0024] This disclosure provides an optimal solution for electrical insulation and simultaneously for effectively dissipating excess heat generated by the semiconductor power transistor die when the semiconductor device is operating.

[0025] Embodiments of connecting the lead frame to the substrate according to the second aspect include welding processes, particularly diffusion welding processes.

[0026] Furthermore, an embodiment of the second aspect of the method utilizes diffusion welding or sintering during the manufacturing process of the bonding layer, i.e., manufacturing a material with a melting point higher than that of the starting material through sintering or intermetallic compound formation.

[0027] Further embodiments can be formed based on the semiconductor packaging embodiments of the first aspect. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the embodiments. Other embodiments and many anticipated advantages of the embodiments will be readily appreciated as they become better understood with reference to the following detailed description.

[0029] The elements in the accompanying drawings are not necessarily drawn to scale relative to each other. The same reference numerals indicate corresponding similar parts.

[0030] Figure 1 A cross-sectional view of a semiconductor package including a direct copper bond substrate is shown.

[0031] Figure 2 A cross-sectional view of a semiconductor package including a substrate comprising a single insulating ceramic layer at the bottom of the device is shown.

[0032] Figure 3A and Figure 3B A cross-sectional representation of a semiconductor device is shown, illustrating the different effects of warpage.

[0033] Figure 4A and Figure 4B A cross-sectional representation of a semiconductor device including an additional copper block within the bonding layer is shown.

[0034] Figure 5 A cross-sectional representation of a semiconductor device concentrated in the die attachment layer is shown.

[0035] Figure 6 A flowchart of an embodiment of the method according to the second aspect is shown. Detailed Implementation

[0036] In the following detailed description, directional terms such as "top," "bottom," "left," "right," "upper," "lower," etc., are used with reference to the orientation of the described figures. Because the components of this disclosure can be positioned in many different orientations, the directional terms are used for illustrative purposes only.

[0037] Furthermore, while specific features or aspects of an example may be disclosed only with respect to one of several embodiments, such features or aspects may be combined with one or more other features or aspects of other embodiments, as may be desired and advantageous for any given or particular application, unless otherwise specifically stated or unless technically limited. Moreover, with regard to the use of the terms “comprising,” “having,” “with,” or other variations thereof in the specific embodiments or claims, such terms are intended to be inclusive in a manner similar to the term “comprising.” The terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical or electrical contact or they are not in direct contact with each other; intermediate elements or layers may be provided between elements that are “joined,” “attached,” or “connected.” However, elements that are “joined,” “attached,” or “connected” may also be in direct contact with each other. Furthermore, the term “exemplary” means only as an example, not the best or optimal.

[0038] The semiconductor device described below may include one or more semiconductor dies. As an example, it may include one or more power semiconductor dies. Furthermore, one or more logic integrated circuits may be included in the semiconductor device. The logic integrated circuit may be configured to control other semiconductor dies, such as power semiconductor dies. The logic integrated circuit may be implemented within a logic die.

[0039] Semiconductor dies may have contact pads that allow electrical contact with integrated circuits included in the semiconductor die. The contact pads may include one or more contact pad metal layers of semiconductor material applied to the semiconductor die. The contact pad metal layers may be fabricated to have any desired geometry and any desired material composition. For example, they may include or be made of a material selected from the group consisting of Cu, Ni, NiSn, Au, Ag, Pt, Pd, W, or alloys of one or more of these metals. W (tungsten) is particularly useful in so-called LTTC (low-temperature co-fired ceramic) processes by applying a temperature of about 500°C, and can also be used in HTTC (high-temperature co-fired ceramic) processes with "co-fired ceramic" substrates and multilayer ceramic substrates by applying a temperature of about 1000°C.

[0040] Figure 1 A cross-sectional view of a semiconductor package including a direct copper bond substrate is shown.

[0041] More specifically, such as Figure 1 The semiconductor package 10 shown includes a substrate 11, which may include DCB, AMB, or IMS, and in any case includes an insulating layer 11A, which may be an organic or inorganic insulating layer, particularly a ceramic insulating layer, or even a multilayer insulating material. The insulating layer 11A includes a first upper main surface and a second lower main surface opposite to the first upper main surface. The package 10 also includes: a lead frame 12, which includes a first upper main surface and a second lower main surface opposite to the first upper main surface; a semiconductor transistor die 13 disposed on the first upper main surface of the lead frame 12; a bonding layer 14 that couples the second lower main surface of the lead frame 12 to the first upper main surface of the ceramic insulating layer 11A, wherein the bonding layer 14 has a melting point that is entirely or partially greater than 260°C; and an encapsulation portion 15 that covers the internal portion of the lead frame 12, the semiconductor transistor die 13, and the ceramic insulating layer 11A of the substrate 11.

[0042] It should be noted that, instead of direct copper bonding (DCB), active metal bonding (AMB) or insulating metal substrate (IMS) can also be used, and the aforementioned LTTC or HTTC "co-fired ceramic" substrates can also be used.

[0043] Figure 2 A cross-sectional view of a semiconductor package including a substrate comprising a single ceramic layer at the bottom of the device is shown.

[0044] More specifically, Figure 2 A semiconductor package 20 is shown, comprising: a substrate 21 including a single insulating layer 21, the insulating layer 21 including a first upper main surface and a second lower main surface opposite to the first upper main surface; a lead frame 22 including a first upper main surface and a second lower main surface opposite to the first upper main surface; a semiconductor transistor die 23 disposed on the first upper main surface of the lead frame 22; a bonding layer 24 coupling the second lower main surface of the lead frame 22 to the first upper main surface of the insulating layer 21, wherein the bonding layer 24 has a melting point that is entirely or partially greater than 260°C; and an encapsulation portion 25 covering the internal portion of the lead frame 22, the semiconductor transistor die 23, and the insulating layer 21.

[0045] It should be noted that this disclosure can be applied to different types of packages. One of them is... Figure 1 and Figure 2 The TO247 package is shown and indicated. However, other types of packages are also conceivable. For example, a surface mount device (SMD TSC) with top-side cooling, or a package including both surface mount devices and bottom-side cooling (SMD BSC), where the device can be soldered onto a heatsink. Additionally, power modules, whether single-sided or dual-sided, are conceivable. Furthermore, so-called smart power modules, whether single-sided or dual-sided, including driver dies, are conceivable.

[0046] Figure 3A and Figure 3B A cross-sectional representation of a semiconductor device is shown, illustrating the different effects of warpage.

[0047] Different process results can be observed based on different material parameters.

[0048] In this context, the warpage of the leadframe combined with the semiconductor chip is determined by the die or by the different coefficients of thermal expansion (CTE) of various materials (SiC, Cu). At room temperature, since Cu has a higher CTE than SiC, warpage should always occur, such as... Figure 3A The "crying face" shown. At higher soldering temperatures (~300℃), it becomes almost flat and may even flip towards a "smiling face," for example... Figure 3B As shown. Furthermore, the isolator may also warp due to design and manufacturing processes. Additionally, the interposer may also warp, so warping is possible in both directions.

[0049] Figure 4A and Figure 4B A cross-sectional representation of a semiconductor device including an additional copper block within the bonding layer is shown.

[0050] More specifically, Figure 4A It shows something similar to a combination Figure 1 and Figure 2 The semiconductor package 30 shown and described is a semiconductor package. The only difference is the specific configuration of the bonding layer 34.

[0051] In the current configuration, the bonding layer 34 includes additional copper blocks 34A. The copper blocks 34A are integrated into the bonding layer 34. These copper blocks 34A are a special form of welding material in which, in addition to the actual preform made of SnSb, a so-called high-melting-point Cu metal core is introduced to simplify diffusion welding and the complete formation of the intermetallic phase in Sn. Only a small number of copper blocks are shown in the cross-sectional representation, but in practice, many more can be used. This concept can be implemented using sheets, balls, and wires.

[0052] More specifically, Figure 4B It shows something similar to a combination Figure 4A Semiconductor package 40 is shown and described as semiconductor package 30. The only difference is the specific configuration of the bonding layer 44. In this case, the bonding layer 44 comprises a stack of intermediate Cu layers 44A sandwiched between Sn or SnSb layers 44B on top and bottom of the intermediate Cu layer 44A. In addition to the actual preform made of SnSb, layer 44B is introduced to simplify diffusion bonding and complete formation of the intermetallic phase in Sn.

[0053] Figure 5A cross-sectional representation of a semiconductor device concentrated in the attachment layer is shown.

[0054] More specifically, such as Figure 5 The semiconductor package 50 shown includes: a substrate 11, including DCB, AMB, or IMS; a ceramic insulating layer 11A, the ceramic insulating layer 11A including a first upper main surface and a second lower main surface opposite to the first upper main surface; a lead frame 12, including a first upper main surface and a second lower main surface opposite to the first upper main surface; a semiconductor transistor die 53 disposed on the first upper main surface of the lead frame 12; a bonding layer 54 coupling the second lower main surface of the lead frame 12 to the first upper main surface of the ceramic insulating layer 11A, wherein the bonding layer 54 includes a melting point that is entirely or partially greater than 260°C or greater than 300°C / 400°C / 500°C or even higher; and an encapsulation portion (not shown) covering the internal portion of the lead frame 12, the semiconductor transistor die 53, and the ceramic insulating layer 11 of the substrate 11.

[0055] Figure 5 The semiconductor package 50 also includes a semiconductor die attachment layer 55 for connecting the semiconductor transistor die 53 to the upper surface of the lead frame 12.

[0056] Regarding the semiconductor die 53 and the bonding layer 54, the previously bonded... Figure 1 The semiconductor die 13 and bonding layer 14 of the semiconductor package have the same characteristics as described.

[0057] The semiconductor die attachment layer 55 connects the semiconductor transistor die 53 to the first upper main surface of the lead frame 12 and can be manufactured by a diffusion bonding process.

[0058] In addition, the semiconductor die attachment layer 55 may include a thickness thinner than the bonding layer 54, particularly in the range of 1 μm to 100 μm.

[0059] In addition, the semiconductor die attachment layer 55 may include a melting point that is entirely or partially greater than 260°C, and may particularly include one or more diffusion or sintering bonding layers.

[0060] Figure 6 A flowchart of an embodiment of the method according to the second aspect is shown.

[0061] More specifically, the method 100 for manufacturing a semiconductor package includes: providing a substrate including an insulating layer comprising a first upper main surface and a second lower main surface opposite to the first upper main surface (110); providing a lead frame (120) comprising the first upper main surface and the second lower main surface opposite to the first upper main surface; disposing a semiconductor transistor die (130) on the first upper main surface of the lead frame; applying a bonding layer on one or both of the second lower main surface of the lead frame or the first upper main surface of the insulating layer, wherein the bonding layer is formed by diffusion bonding or diffusion sintering from at least one source material having at least one first transition temperature, wherein after formation, the bonding layer has a second transition temperature higher than the first transition temperature (140); connecting the lead frame to the substrate by performing a melting and subsequent reflow process (150); and applying an encapsulation portion (160) covering the inner portion of the lead frame, the semiconductor transistor die, and the insulating layer.

[0062] While this disclosure has been shown and described with respect to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components or structures (components, devices, circuits, systems, etc.), unless otherwise stated, the terminology used to describe these components (including references to “means”) is intended to correspond to any component or structure that performs the specified function of the described component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of this disclosure shown herein.

Claims

1. A semiconductor package (10; 20), comprising: Substrate (11; 21), the substrate (11; 21) includes an insulating layer (11A; 21), the insulating layer (11A; 21) includes a first upper main surface and a second lower main surface opposite to the first upper main surface; A lead frame (12; 22), the lead frame (12; 22) comprising a first upper main surface and a second lower main surface opposite to the first upper main surface; Semiconductor transistor die (13; 23), the semiconductor transistor die (13; 23) Arranged on the first upper main surface of the lead frame (12; 22); A bonding layer (14; 24) couples the second lower main surface of the lead frame (12; 22) to the first upper main surface of the insulating layer (11A; 21), wherein the bonding layer (14; 24) has a melting point that is entirely or partially greater than 260°C; and Encapsulation portion (15; 25) covers the inner portion of the lead frame (12; 22), the semiconductor transistor die (13; 23), and the insulating layer (11A; 21).

2. The semiconductor package (10; 20) according to claim 1, wherein, The insulating layer (11A) includes a ceramic insulating layer.

3. The semiconductor package (10; 20) according to claim 1 or 2, wherein, The bonding layers (14; 24) are based on metal.

4. The semiconductor package (10; 20) according to any one of the preceding claims, wherein, The bonding layers (14; 24) comprise a material with a thermal conductivity greater than 15 W / mK.

5. The semiconductor package (10) according to any one of the preceding claims, wherein, The bonding layer (14; 24) comprises one or more materials from the group consisting of Pb-free materials, SnSb materials, NiSn materials, CuSn materials, transient liquid phase welding materials, Sn materials, Ag materials, Ag adhesive materials, or mixed sintering pastes, particularly, the mixed sintering paste is a Cu-based sintering paste.

6. The semiconductor package (10) according to any one of the preceding claims, wherein, The insulating layer (11A) is the central layer of the substrate (11), wherein the substrate (11) is one of direct copper bonding (DCB), active metal brazing (AMB) or insulating metal substrate (IMS).

7. The semiconductor package (10) according to claim 6, wherein, The substrate (11) includes a central insulating layer (11A), a first upper metal layer (11B), and a second lower metal layer (11C).

8. The semiconductor package (10) according to claim 6, wherein, The first upper metal layer (11B) has a thickness of less than 500 / 300 / 250 / 125 / 75 / 50 / 20 / 10 μm or even as low as 1 μm. In particular, the first upper metal layer has a thickness of less than 300 μm, preferably 127 μm, 20 μm or 10 μm.

9. The semiconductor package (20) according to any one of the preceding claims, wherein, The substrate (21) includes a single ceramic insulating layer (21) having a bottom surface disposed on the outside.

10. The semiconductor package (10; 20) according to any one of the preceding claims, wherein, The insulating layer (11A; 21) comprises one or more materials from the group consisting of Al2O3, Si3N4, H-AlN and AlN.

11. The semiconductor package (50) according to any one of the preceding claims further comprises: A semiconductor die attachment layer (55) connects the semiconductor transistor die (53) to the first upper main surface of the lead frame (12).

12. The semiconductor package (50) according to claim 11, wherein, The thickness of the semiconductor die attachment layer (55) is thinner than the thickness of the bonding layer (54).

13. The semiconductor package (50) according to claim 11 or 12, wherein, The thickness of the semiconductor die attachment layer (55) is in the range of 1 μm to 100 μm.

14. The semiconductor package (50) according to any one of claims 11 to 13, wherein, The semiconductor die attachment layer (55) includes a melting point that is entirely or partially greater than 260°C.

15. The semiconductor package (50) according to any one of claims 11 to 14, wherein, The semiconductor die attachment layer (55) is manufactured by a diffusion bonding process.

16. A method for manufacturing a semiconductor package (10; 20) of the method (100), the method comprising: A substrate (11; 21) is provided, comprising an insulating layer (11A; 21) including a first upper main surface and a second lower main surface (110) opposite to the first upper main surface. A lead frame (12; 22) (120) is provided, comprising a first upper main surface and a second lower main surface opposite to the first upper main surface; A semiconductor transistor die (13; 23) is disposed on the first upper main surface (130) of the lead frame (12; 22). A bonding layer (14; 24) is applied to one or both of the second lower main surface of the lead frame (12; 22) or the first upper main surface of the insulating layer (11A; 21), wherein the bonding layer (14; 24) is formed from at least one source material having at least one first transition temperature by diffusion welding or diffusion sintering, wherein, after the formation, the bonding layer has a second transition temperature (140) higher than the first transition temperature. The lead frame (12; 22) is connected to the substrate (11; 21) (150) by performing a melting and subsequent reflow process; and An encapsulation portion (15; 25) (160) is applied covering the inner portion of the lead frame (12; 22), the semiconductor transistor die (13; 23), and the insulating layer (11A; 21). The thickness of the bonding layers (14; 24) is in the range of 40 μm to 200 μm, particularly in the range of 100 μm to 200 μm, and particularly in the range of 50 μm to 150 μm; or The thickness of the bonding layers (14; 24) is in the range of 1 μm to 50 μm, particularly in the range of 10 μm to 30 μm.

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