Chip package, power module and manufacturing method

By optimizing the chip packaging structure and utilizing the electrical connection between the redistribution layer and the ceramic substrate, the process flow is simplified, solving the problems of long current paths and large parasitic inductance in traditional packaging, and achieving high integration and high reliability of high-frequency, miniaturized, high-power modules.

CN122249069APending Publication Date: 2026-06-19NIO TECH ANHUI CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
NIO TECH ANHUI CO LTD
Filing Date
2026-04-07
Publication Date
2026-06-19

AI Technical Summary

⚠Technical Problem

Traditional power module packaging suffers from problems such as long current paths, large parasitic inductance, complex module structure, and low integration, making it difficult to meet the development needs of high frequency, miniaturization, and high power.

⚗Method used

The chip packaging structure includes a chip, a ceramic substrate, and a redistribution layer. The back side of the chip is electrically connected to the metal layer on the front side of the ceramic substrate. The first redistribution layer is electrically connected to the ceramic substrate and the gate and source of the chip. The second redistribution layer overlaps with the first redistribution layer and is partially electrically connected to form a pad for connection to external circuits. By combining the encapsulation layer and the opposite redistribution layer, the process flow is simplified, parasitic inductance is reduced, and integration and reliability are improved.

🎯Benefits of technology

It effectively reduces the parasitic inductance of the power module, reduces switching losses, improves power density and reliability, and meets the high power density and high integration requirements of the new generation of modules.

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Abstract

This application provides chip packaging, power modules, and manufacturing methods. The chip package (1) includes a chip (11), a ceramic substrate (12), and a redistribution layer. The redistribution layer includes a first redistribution layer (13) and a second redistribution layer (14). The drain on the back side of the chip (11) is electrically connected to the front metal layer of the ceramic substrate (12). The first redistribution layer (13) is electrically connected to the gate and source of the ceramic substrate (12) and the chip (11), respectively. The second redistribution layer (14) is stacked on top of the first redistribution layer (13) and partially electrically connected. The second redistribution layer (14) forms pads (141) for electrical connection with external circuits. This application simplifies the structure and process complexity of chip packaging through optimized structural design and improves integration and performance.
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