2.5d bridge package structure and 2.5d bridge package process

Abstract

This application provides a 2.5D bridged packaging structure and a 2.5D bridged packaging process, relating to the field of semiconductor packaging technology. The process includes providing an adapter board; the adapter board has a first surface and a second surface disposed opposite to each other; forming a plurality of spaced first trenches on the first surface; forming a first wiring layer within the first trenches; forming second and third trenches on the second surface; forming a second dielectric layer and a second wiring layer within the second trenches, and forming a third dielectric layer and a third wiring layer within the third trenches, with a second metal layer disposed on the surface of the third dielectric layer; mounting a bridge chip; connecting the bridge chip to both the second and first metal layers; forming a heat dissipation trench on the side of the adapter board away from the third wiring layer; and mounting a heat sink in the heat dissipation trench. This process helps alleviate warpage, improves heat dissipation performance, and reduces leakage, short circuits, and overheating caused by parasitic capacitance and other phenomena.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D bridged packaging structure and a 2.5D bridged packaging process. Background Technology

[0002] With the rapid development of the semiconductor industry, chiplet technology, as a new design approach, packages small chips with different functions together. Typically, 2.5D packaging technology is used to package the chips onto a silicon interposer as a multi-chiplet packaging solution. This mainly involves embedding a bridging chip within the interposer, followed by dielectric layer vias and wiring processes to mount other flip chips, thus achieving the interconnect structure. However, the bridging chip requires a flat chip pad structure to meet the requirements of dielectric layer etching and via technology, in order to form a conductive metal pillar structure. As products are used in the transmission paths of ultra-high frequency signals from 100GHz to 300GHz, the longer the transmission path between wiring layers, the greater the transmission loss caused by the phenomenon of current flowing towards the conductive pillars. In addition, the current forms inductive and thermoelectric effects between wiring layers, resulting in parasitic inductance and leakage. This leads to short circuits and overheating between wiring layers. Therefore, it is necessary to shorten the transmission path between active devices (such as RF chips, logic chips, or memory chips) and passive devices (such as components, capacitors, or inductors) in the package, or shorten the transmission paths between active and passive devices and the wiring layers respectively.

[0003] Furthermore, in the existing technology, silicon interposers are used as the insulating layer of the bridging structure. The dielectric constant of silicon material is low, around 11.5εr, which can easily cause inductive and parasitic effects between the bridging wiring layer and the wiring layer in the interposer. This can lead to leakage due to parasitic inductance, resulting in short circuits and overheating between wiring layers. Summary of the Invention

[0004] The purpose of this invention is to provide a 2.5D bridged package structure and a 2.5D bridged package process, which helps to alleviate warping deformation, improve heat dissipation performance, and ensure that the wiring layers on the bridge and the transition parts are independent of each other, reducing leakage, short circuit, overheating and other phenomena caused by parasitic capacitance.

[0005] In a first aspect, the present invention provides a 2.5D bridge package structure, comprising: an adapter portion, a bridge portion, a bridge chip, and a molding compound; The bridging portion and the transition portion are spaced apart. The transition portion is provided with a first metal pillar, a first dielectric layer and a second dielectric layer. The first dielectric layer is provided with a first wiring layer and the second dielectric layer is provided with a second wiring layer. The two ends of the first metal pillar are respectively connected to the first wiring layer and the second wiring layer. The adapter has a third metal layer connected to the first wiring layer on one side and a first metal layer connected to the second wiring layer on the other side; the bridging part has a third wiring layer and a second metal layer connected to the third wiring layer. The bridging chip is connected across the adapter and the bridging portion, and the bridging chip is electrically connected to the first metal layer and the second metal layer respectively. The molding compound covers the bridge chip and the sidewalls of the adapter, and fills the gap between the bridge and the adapter. The bridging portion has a first silicon plate on the side away from the bridging chip, and the first silicon plate has an oxide layer.

[0006] In an optional embodiment, the first silicon plate is provided with heat dissipation grooves.

[0007] In an optional embodiment, the heat dissipation trench is provided with thermally conductive metal.

[0008] In an optional embodiment, the system further includes a substrate, wherein the thermally conductive metal is connected to the substrate; or, the thermally conductive metal is connected to a ground point on the substrate.

[0009] In an optional embodiment, the oxide layer covers the peripheral wall, upper surface, and walls of the heat dissipation trench of the first silicon plate.

[0010] In an optional embodiment, a gap is formed between the first silicon plate and the transition portion to form a channel; or a gap is formed between the oxide layer and the transition portion to form a channel.

[0011] In an optional embodiment, the depth of the channel ends at the plastic seal of the sidewall of the bridge connection.

[0012] In an optional embodiment, a heat sink is also included, which is disposed on the side of the first silicon plate away from the bridge chip.

[0013] In an optional embodiment, the heat sink is provided with heat dissipation channels.

[0014] In an optional embodiment, the first silicon plate is provided with heat dissipation grooves, and the heat dissipation channels are connected to the heat dissipation grooves.

[0015] In an optional embodiment, the heat sink includes an edge portion and a heat dissipation portion, the edge portion being connected to the first dielectric layer, and the heat dissipation portion being attached to the first silicon substrate; the edge portion is provided with through holes.

[0016] In an optional embodiment, the first silicon substrate has a fourth groove on the side away from the bridge chip, the heat sink includes an edge portion and a heat dissipation portion, the edge portion is connected to the first dielectric layer, and the heat dissipation portion is attached to the fourth groove.

[0017] In an optional embodiment, the edge portion is provided with a through hole, and a channel is formed between the first silicon plate and the adapter portion, with the through hole and the channel communicating.

[0018] In an optional embodiment, an oxide layer is formed between the heat sink and the first silicon plate.

[0019] In an optional implementation, a second chip is also included; The first silicon substrate has a fifth groove, and the bridging portion has pads connected to the third wiring layer, the pads being located in the fifth groove; The second chip is disposed in the fifth slot and is electrically connected to the pad.

[0020] In an optional embodiment, the second chip has a transducer region, and the second chip, the bridge portion, the first silicon plate and the heat sink are arranged to form a cavity so that the transducer region can work normally.

[0021] Secondly, the present invention provides a 2.5D bridged packaging process, comprising: An adapter plate is provided; the adapter plate has a first surface and a second surface disposed opposite to each other; A plurality of spaced first grooves are formed on the first surface; A first dielectric layer having a first wiring layer is formed within the first trench. A second groove and a third groove are formed on the second surface; wherein the position of the second groove corresponds to the position of the first groove; A second dielectric layer is formed in the second trench, a second wiring layer is provided in the second dielectric layer, and a first metal layer connected to the second wiring layer is provided on the surface of the second dielectric layer. A third dielectric layer is formed in the third trench, the third dielectric layer is provided with a third wiring layer, and a second metal layer connected to the third wiring layer is provided on the surface of the third dielectric layer; A bridge chip is mounted; the bridge chip is connected to the second metal layer and the first metal layer respectively. The adapter board includes a first silicon plate corresponding to the third dielectric layer; an oxide layer is formed on the side of the first silicon plate away from the bridge chip.

[0022] In an optional embodiment, the method further includes: attaching a heat sink to the first silicon substrate; An oxide layer is formed between the heat sink and the first silicon plate; wherein the edge of the heat sink is connected to the first dielectric layer.

[0023] In an optional embodiment, prior to the step of mounting the heat sink on the first silicon substrate, the method further includes: The first silicon substrate forms a fifth groove that exposes the third dielectric layer; A pad connected to the third wiring layer is formed within the fifth groove. A second chip is mounted into the fifth slot, and the second chip is electrically connected to the pad. The heat sink is attached to the side of the second chip away from the third wiring layer, and an oxide layer is formed between the first silicon substrate and the heat sink.

[0024] In an optional embodiment, prior to the step of mounting the heat sink on the first silicon substrate, the method further includes: An oxide layer is formed on the first silicon substrate; A fifth groove is formed on the first silicon substrate; the fifth groove penetrates the oxide layer and the first silicon substrate and exposes the third dielectric layer; A pad connected to the third wiring layer is formed within the fifth groove. A second chip is mounted into the fifth slot, and the second chip is electrically connected to the pad. The heat sink is attached to the side of the second chip away from the third wiring layer.

[0025] In an optional embodiment, the step of forming an oxide layer between the heat sink and the first silicon plate includes: A silicon dioxide layer is formed between the heat sink and the first silicon plate by high-temperature sintering, followed by high-temperature annealing to complete the welding. Alternatively, the first silicon plate or the heat sink can be subjected to a high-temperature oxidation process to form a silicon dioxide layer, and then the heat sink and the first silicon plate can be welded together using a metal layer or an adhesive compound.

[0026] In an optional implementation, the step of mounting a heat sink on the first silicon substrate includes: The first silicon plate is thinned so that the surface of the first silicon plate is lower than the surface of the first dielectric layer, forming a fourth groove. The heat sink is attached to the fourth slot. A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer is provided with a third metal layer connected to the first wiring layer, the third metal layer protruding from the surface of the fourth dielectric layer; The surface of the heat sink away from the first silicon plate is flush with the surface of the fourth dielectric layer or the surface of the third metal layer.

[0027] In an optional embodiment, prior to the step of forming the second dielectric layer within the second trench, the method further includes: A first metal pillar is formed on the adapter plate; one end of the first metal pillar is connected to the first wiring layer, and the other end protrudes from the bottom of the second groove. In the step of forming a second dielectric layer in the second trench: the second wiring layer is electrically connected to the first metal pillar.

[0028] In an optional implementation, after the step of mounting the bridge chip, the method further includes: A molding compound is formed; the molding compound covers the bridge chip, the sidewalls of the second dielectric layer, and fills the gap between the second dielectric layer and the third dielectric layer.

[0029] The 2.5D bridging package structure and 2.5D bridging package process provided in this invention have the following advantages: The bridging section and the adapter board are set up separately. The wiring layers on the adapter section and the bridging section are set up independently and are not directly connected. This results in shorter transmission paths, lower losses, and higher transmission efficiency. Furthermore, the adapter section and the bridging section are isolated and insulated using a plastic encapsulation, which provides better insulation performance and helps reduce inductive and parasitic effects between the wiring layers. This mitigates leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. Additionally, an oxide layer is formed on the first silicon substrate to help prevent electron migration. Attached Figure Description

[0030] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 One of the process diagrams of the 2.5D bridged packaging process provided in the embodiment of the present invention; Figure 2 A schematic diagram showing the depth of the second and third grooves in the 2.5D bridging packaging process provided in this embodiment of the invention; Figure 3 This is the second schematic diagram of the 2.5D bridged packaging process provided in an embodiment of the present invention; Figure 4The third schematic diagram of the 2.5D bridged packaging process provided in the embodiment of the present invention; Figure 5 Fourth schematic diagram of the 2.5D bridged packaging process provided in the embodiments of the present invention; Figure 6 A schematic diagram of a structure in which thermally conductive metal is filled in part of the heat dissipation trench in the 2.5D bridged packaging process provided in the embodiments of the present invention; Figure 7 A schematic diagram of the process of mounting a heat sink on the first silicon substrate in the 2.5D bridged packaging process provided in the embodiments of the present invention; Figure 8 In the 2.5D bridged packaging process provided in the embodiments of the present invention, the mounted heat sink is formed with through holes in a structural design. Figure 9 A schematic diagram illustrating the formation of a third metal layer and solder balls during the fabrication process of the 2.5D bridged packaging process provided in this embodiment of the invention; Figure 10 A schematic diagram of the process for forming the fifth groove and pad in the 2.5D bridged packaging process provided in the embodiments of the present invention; Figure 11 This is a schematic diagram of the process of mounting a second chip in the 2.5D bridged packaging process provided in an embodiment of the present invention; Figure 12 A schematic diagram of the first structure of the 2.5D bridged package structure provided in the embodiments of the present invention; Figure 13 A schematic diagram of a second structure of the 2.5D bridged package structure provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of a 2.5D bridged package structure connected to a substrate according to an embodiment of the present invention. Figure 15 A schematic diagram of a third structure of the 2.5D bridged package structure provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of the fourth structure of the 2.5D bridged package structure provided in the embodiments of the present invention.

[0032] Icons: 110 - Adapter board; 101 - First surface; 102 - Second surface; 111 - First groove; 112 - First dielectric layer; 113 - First wiring layer; 114 - Third metal layer; 115 - Fourth dielectric layer; 116 - Solder ball; 120 - Adapter section; 121 - Second groove; 122 - First metal pillar; 123 - Second dielectric layer; 124 - Second wiring layer; 125 - First metal layer; 130 - Bridge section; 131 - Third groove; 132 - Third dielectric layer; 133 - Third wiring layer; 134 - Second metal layer; 1 35-Bridge chip; 201-First carrier; 202-Adhesive layer; 203-Cut groove; 141-First chip; 142-Molded body; 151-First silicon substrate; 152-Heat dissipation trench; 153-Silicon dioxide layer; 180-Thermal conductive metal; 160-Heat dissipation plate; 161-Edge portion; 162-Heat dissipation portion; 163-Through hole; 164-Heat dissipation channel; 154-Fourth trench portion; 155-Channel; 156-Fifth trench portion; 157-Pad; 170-Second chip; 171-Transducer region; 172-Cavity; 210-Substrate. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0036] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0037] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0038] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0039] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0040] Please combine Figures 1 to 2 The 2.5D bridging packaging process proposed in this embodiment of the invention generally includes the following steps: S1. Adapter board 110 is provided.

[0041] The adapter board 110 has a first surface 101 and a second surface 102 disposed opposite to each other; the material of the adapter board 110 can be glass, a silicon substrate, or a germanium substrate. In this embodiment, a silicon adapter board can be used. If wafer-level packaging is used, the size of the adapter board 110 can be selected as 6 inches, 8 inches, or 12 inches, etc. If panel-level packaging is used, the size of the adapter board 110 can be selected as 310cm×310cm, 600cm×600cm, 710cm×710cm, etc., and is not limited to the sizes listed above, and can be flexibly designed according to actual needs.

[0042] Figures 2 to 11The diagram shown is a partial schematic of the adapter board 110, which is used to illustrate the schematics of each process.

[0043] S11. A plurality of spaced first grooves 111 are formed on the first surface 101. Optionally, the first grooves 111 can be formed using plasma etching technology, such as dry plasma etching or chemical etching. Dry plasma etching utilizes a plasma gas composed of a mixture of oxygen (O2) and SF6; chemical etching uses one or more chemical agents such as phosphoric acid, acetic acid, hydrogen chloride, or sulfuric acid for etching.

[0044] S12. A first wiring layer 113 is formed in the first groove 111.

[0045] Optionally, a first dielectric layer 112 is formed within the first groove 111. The first dielectric layer 112 is exposed and developed to form a first patterned layer opening. Metal is electroplated into the first patterned layer opening using techniques such as electroplating to form a first wiring layer 113. The number of first wiring layers 113 is not limited; it can be one or more layers. If multiple first wiring layers 113 are designed, they are designed sequentially in stages, and the first dielectric layer 112 is also designed accordingly in multiple layers. It can be understood that the depth of the first groove 111 is the thickness of the first dielectric layer 112, that is, the surface of the first dielectric layer 112 is flush with the first surface 101 of the adapter plate 110. This design allows the first wiring layer 113 to be embedded in the adapter plate 110, avoiding the delamination phenomenon between the first dielectric layer 112 and the first surface 101 of the adapter plate 110 caused by the warping of the adapter plate 110. It is worth noting that placing the first wiring layer 113 inside the first groove 111 can reduce the contact area between the first dielectric layer 112 and the surface of the adapter board 110, thereby reducing the risk of structural delamination.

[0046] S13. A second groove 121 and a third groove 131 are formed on the second surface 102. The position of the second groove 121 corresponds to the position of the first groove 111. The bottom of the second groove 121 is lower than the bottom of the third groove 131. For example, the depth of the second groove 121 is H2, and the depth of the third groove 131 is H3, where H2 is greater than H3. The second groove 121 is distributed along the periphery of the third groove 131. The forming process of the second groove 121 and the third groove 131 is similar to that of the first groove 111, and will not be described in detail here.

[0047] Please combine Figure 3S14. A first metal pillar 122 extending toward the first surface 101 is formed in the second trench 121. The first metal pillar 122 can be formed using a TSV (Through Silicon Via) process. For example, a silicon via can be formed in the second trench 121 of the adapter board 110 using laser drilling or etching, exposing the first wiring layer 113. The first metal pillar 122 is then formed in the silicon via using an electroplating process with a metal plating solution. The first metal pillar 122 is electrically connected to the first wiring layer 113. The end of the first metal pillar 122 away from the first wiring layer 113 is flush with the bottom of the second trench 121.

[0048] S15. A second wiring layer 124 is formed in the second trench 121, and the second wiring layer 124 is electrically connected to the first metal post 122. The method of forming the second wiring layer 124 is similar to the method of forming the first wiring layer 113. The number of second wiring layers 124 can be one or more.

[0049] Optionally, a second dielectric layer 123 is formed in the second groove 121, and a second wiring layer 124 is disposed within the second dielectric layer 123. A first metal layer 125 electrically connected to the second wiring layer 124 is formed on the surface of the second dielectric layer 123. The first metal layer 125 is formed as follows: a first opening is formed on the second dielectric layer 123 exposing the second wiring layer 124, and metal is electroplated in the first opening to form the first metal layer 125 electrically connected to the second wiring layer 124. The first metal layer 125 includes bumps and a solder layer disposed on the surface of the bumps. The material of the solder layer includes, but is not limited to, one or more layers of titanium, titanium-tungsten, and nickel, and the solder layer is beneficial to improving soldering performance. The fabrication of the adapter 120 is completed.

[0050] S16. A third wiring layer 133 is formed in the third trench 131, and the method of forming the third wiring layer 133 is similar to the method of forming the first wiring layer 113. The number of third wiring layers 133 can be one or more. Optionally, a third dielectric layer 132 is formed in the third trench 131, and the third wiring layer 133 is disposed within the third dielectric layer 132. A second metal layer 134 electrically connected to the third wiring layer 133 is formed on the surface of the third dielectric layer 132. The method of forming the second metal layer 134 is similar to the method of forming the first metal layer 125. The fabrication of the bridging portion 130 is completed.

[0051] It is understood that the second wiring layer 124 and the third wiring layer 133 can be designed simultaneously or completed in stages. That is, S15 and S16 can be completed simultaneously or in stages. To improve process efficiency, the third dielectric layer 132 can be spin-coated to form the second dielectric layer 123 at the same time, and the third wiring layer 133 can also be formed simultaneously when the electroplated metal liquid forms the second wiring layer 124. Similarly, the second metal layer 134 and the first metal layer 125 can be formed simultaneously, without specific limitations here.

[0052] Optionally, the surfaces of the first metal layer 125 and the second metal layer 134 are flush. This design ensures a stable mounting structure and reliable electrical connection for the bridge chip 135 when it is mounted on the first metal layer 125 and the second metal layer 134.

[0053] It is worth noting that there is a gap between the second dielectric layer 123 and the third dielectric layer 132, which separates the second wiring layer 124 and the third wiring layer 133 from each other. This gap is subsequently filled by the encapsulant 142, which serves to isolate and protect the wiring layers from leakage, breakdown and other phenomena.

[0054] S2. A first carrier 201 is provided. A liquid adhesive layer 202 is applied to the surface of the first carrier 201 using a spin coater. The layer is then baked and set using a hot plate. The first carrier 201 can be made of materials such as glass, silicon dioxide, or metal. The liquid adhesive layer 202 is made of a thermoplastic material, the material of which can be separated by UV light irradiation. The material of the liquid adhesive layer 202 includes at least one of epoxy resin, polyimide, benzocyclobutene, and other polymer composite materials. The side of the adapter plate 110 having the first wiring layer 113 is attached to the first carrier 201.

[0055] The edge of the adapter plate 110 is cut to form a cutting groove 203. The design of the first carrier 201 is beneficial to improve support and cushioning, avoid the pulling of the wiring layer by the cutting stress, and improve cutting efficiency and cutting quality.

[0056] S3, chip mounting.

[0057] Please combine Figure 4 A bridge chip 135 is mounted, bridging the adapter portion 120 and the bridge portion 130. One end of the bridge chip 135 is flip-chip connected to the first metal layer 125, and the other end is flip-chip connected to the second metal layer 134. The bridge chip 135 is electrically connected to both the first metal layer 125 and the second metal layer 134.

[0058] Optionally, a first chip 141 is mounted on the adapter 120. The first chip 141 can be a flip chip or a standard chip. The first chip 141 is electrically connected to the first metal layer 125.

[0059] S4, Plastic sealing.

[0060] A molding compound 142 is formed using injection molding or liquid printing. The molding compound 142 protects the first chip 141, the bridge chip 135, and the chip's solder structure. The molding compound 142 fills the dicing groove 203, protecting the sidewalls of the adapter board 110 and filling the gap between the adapter portion 120 and the bridge portion 130, i.e., filling the gap between the second dielectric layer 123 and the third dielectric layer 132, thus protecting the sidewalls of the bridge portion 130. The molding compound 142 separates the adapter portion 120 and the bridge portion 130, providing better insulation and reducing inductive and parasitic effects between their wiring layers. This mitigates leakage caused by parasitic inductance, which can lead to short circuits and overheating between wiring layers. The dielectric constant of the molding compound 142 material is higher than that of silicon, further reducing inductive and parasitic effects between wiring layers and lowering the risk of leakage.

[0061] In some embodiments, the molding compound 142 can be replaced by an insulator such as underfill adhesive, which protects the first chip 141, the second chip 170, the bridging chip 135, the sidewalls of the adapter portion 120, the sidewalls of the bridging portion 130, and the chip soldering structure.

[0062] S5. Remove the first carrier 201. Irradiate the back of the first carrier 201 with UV light to separate the first carrier 201 from the packaging structure, exposing the first surface 101 of the adapter plate 110. Flip the product so that the first surface 101 faces upward and the molding compound 142 faces downward. The molding compound 142 provides support for the packaging structure.

[0063] S6. A heat dissipation trench 152 is formed on the side of the adapter board 110 away from the third wiring layer 133. In this embodiment, the heat dissipation trench 152 is formed on the back side of the bridge portion 130.

[0064] Please combine Figure 5 The adapter plate 110 includes a first silicon substrate 151 corresponding to the third dielectric layer 132. The first silicon substrate 151 is located on the back side of the bridging portion 130. Heat dissipation trenches 152 are formed on the first silicon substrate 151. Optionally, the heat dissipation trenches 152 are formed on the adapter plate 110 (first silicon substrate 151) on the back side of the bridging portion 130 using plasma etching technology. For example, they can be formed using dry plasma etching or chemical etching technology. Dry plasma etching utilizes a plasma gas composed of a mixture of oxygen (O2) and SF6; chemical etching uses one or more chemical agents such as phosphoric acid, acetic acid, hydrogen chloride, or sulfuric acid for etching.

[0065] Optionally, after forming the heat dissipation trench 152, a thermally conductive metal 180 is formed in the heat dissipation trench 152 to improve heat dissipation performance. Optionally, before forming the thermally conductive metal 180, an oxide layer, such as a silicon dioxide layer 153, can be formed on the first silicon substrate 151. The silicon dioxide layer 153 can cover the surface of the first silicon substrate 151 and the trench walls of the heat dissipation trench 152.

[0066] Optionally, in the step of forming the thermally conductive metal 180, all heat dissipation trenches 152 can be filled with the thermally conductive metal 180, or only some heat dissipation trenches 152 can be filled with the thermally conductive metal 180, while the remaining heat dissipation trenches 152 retain a cavity structure, such as... Figure 6 As shown.

[0067] Please combine Figure 7 A heat sink 160 is mounted on the first silicon substrate 151. Optionally, the heat sink 160 is made of silicon substrate. First, a high-temperature oxidation welding process is performed, using high-temperature sintering to form a silicon dioxide layer 153 between the silicon substrate and the adapter plate 110, thus completing the welding bonding. Then, a high-temperature annealing process is performed to redistribute and arrange the silicon atoms, completing the welding. Alternatively, the adapter plate 110 or the silicon substrate can first undergo a high-temperature oxidation process to form a silicon dioxide layer 153, then a metal layer or adhesive compound is used for welding, followed by another annealing process to complete the welding.

[0068] Optionally, the side of the first silicon substrate 151 furthest from the third wiring layer 133 can be thinned first, and then the heat dissipation trench 152 can be formed. Of course, the thinning and heat dissipation trench can be formed in one step by etching, which can improve process efficiency.

[0069] Optional, please refer to Figure 8 A second etching process is performed to form through-holes 163 on the heat sink 160. The through-holes 163 extend from the heat sink 160 to the lower molding compound 142, which is the molding compound 142 on the sidewall of the bridging portion 130. The through-holes 163 serve as airflow inlets and outlets, further improving heat dissipation performance. Optionally, the through-holes 163 and the heat dissipation trench 152 are connected. In some embodiments, the through-holes 163 and the heat dissipation trench 152 may not be connected.

[0070] It should be noted that the heat sink 160 includes an edge portion 161 and a heat dissipation portion 162, with the edge portion 161 overlapping the adapter portion 120. Specifically, the edge portion 161 overlaps the first dielectric layer 112. The heat dissipation portion 162 is disposed in the heat dissipation trench 152.

[0071] Optionally, the heat dissipation section 162 is provided with cooling components, including but not limited to coolant or cooling gas, to improve heat dissipation. In this embodiment, the heat dissipation section 162 is provided with cooling components, such as heat dissipation channels 164 or a cooling medium.

[0072] In some embodiments, the thermally conductive metal 180 may be omitted. The heat dissipation grooves 152 on the first silicon substrate 151 and the heat dissipation channels 164 on the heat sink 160 are provided in a one-to-one correspondence, retaining the cavity structure.

[0073] In this embodiment, the adapter plate 110 on the back of the bridge portion 130 has heat dissipation grooves 152. The heat dissipation grooves 152 are arranged horizontally, which helps to improve the heat dissipation performance of the bridge chip 135 area. The horizontal arrangement also increases the stress area on the surface of the adapter plate 110, providing good support and structural reliability. Furthermore, the large heat dissipation area results in good heat dissipation. A silicon dioxide layer 153 is formed between the adapter plate 110 and the silicon substrate. Using the silicon dioxide layer 153 as an insulating layer helps to prevent electron migration in the third wiring layer 133 of the bridge chip 135 area, preventing external or internal electrons from moving between the heat dissipation grooves 152 and damaging the bridge portion 130.

[0074] The silicon substrate is mounted above the heat dissipation trench 152 to provide support and prevent warping and deformation between the adapter plate 110 around the bridge portion 130.

[0075] S7. A third metal layer 114 is formed on the first wiring layer 113.

[0076] Please combine Figure 9 Optionally, a fourth dielectric layer 115 is formed on the first dielectric layer 112. The fourth dielectric layer 115 is exposed and developed to form a second opening. Metal is electroplated into the second opening using techniques such as electroplating to form a third metal layer 114. The structure and formation method of the third metal layer 114 are similar to those of the first metal layer 125. Optionally, in some embodiments, the surface of the fourth dielectric layer 115 is flush with the surface of the heat sink 160 on the side away from the first silicon substrate 151. Or, as... Figure 12 As shown, the surface of the heat sink 160 and the surface of the third metal layer 114 are flush, but this is not specifically limited. If the surface of the silicon substrate and the surface of the third metal layer 114 are flush, this arrangement helps prevent the solder balls 116 from collapsing during soldering, thus preventing bridging between the solder balls 116. Furthermore, the thickness of the silicon substrate helps control the soldering height of the solder balls 116, resulting in a more reliable structure.

[0077] Next, a ball-planting process is performed on the third metal layer 114 to form solder balls 116. Finally, the balls are cut and separated into individual products, completing the manufacturing process.

[0078] Please combine Figure 10In some embodiments, the first silicon substrate 151 is first thinned to form a fourth groove 154. Optionally, the adapter plate 110 on the back side of the molding compound 142 on the sidewall of the bridging portion 130 is completely removed to form a channel 155. An oxide layer is formed on the first silicon substrate 151. A silicon dioxide layer 153 can be formed on the adapter plate 110 using a high-temperature oxidation process. It is understood that the silicon dioxide layer 153 is formed on the surface and sidewalls of the remaining adapter plate 110 on the back side of the bridging portion 130.

[0079] Optionally, the adapter plate 110, on which the silicon dioxide layer 153 is etched, forms a fifth groove 156 that exposes the bridging portion 130. The formation method of the fifth groove 156 is similar to that of the first groove 111, the second groove 121, etc.

[0080] A pad 157 is formed on the surface of the third dielectric layer 132 to connect with the third wiring layer 133. The pad 157 is located within the fifth trench 156.

[0081] Please combine Figure 11 A second chip 170 is mounted in the fifth slot 156. The second chip 170 is a flip chip. The second chip 170 is electrically connected to the pad 157.

[0082] Optionally, the back surface of the second chip 170 is flush with the surface of the silicon dioxide layer 153. Then, a heat sink 160 is attached to the back surface of the second chip 170. The edge 161 of the heat sink 160 overlaps with the adapter 120. Specifically, the edge 161 overlaps with the first dielectric layer 112. The heat sink 162 contacts the back surface of the second chip 170. The heat sink 162 has heat dissipation channels 164. A through-hole 163 is provided on the edge 161, communicating with the channel 155 to further improve heat dissipation performance.

[0083] In other embodiments, a fifth groove 156 can be etched on the adapter plate 110 on the back of the bridging portion 130, and a pad 157 connected to the third wiring layer 133 can be formed in the fifth groove 156, where the second chip 170 is mounted. Then, a high-temperature oxidation welding process is performed, using high-temperature sintering to form a silicon dioxide layer 153 between the silicon substrate and the adapter plate 110 with the fifth groove 156, thereby completing the welding bonding. A high-temperature annealing process is then performed again to redistribute and arrange the silicon atoms, completing the welding. Alternatively, after mounting the second chip 170, the silicon substrate is oxidized at high temperature to form a silicon dioxide layer 153, then welded to the adapter plate 110 with the fifth groove 156, and then annealed again to complete the welding.

[0084] Please combine Figure 12In some embodiments, the second chip 170 may be a surface acoustic wave (SAW) filter chip or other types of chips. The second chip 170 has a transducer region 171, which needs to operate within a cavity 172. That is, during the packaging process, a cavity 172 needs to be formed at the bottom of the second chip 170 to ensure the normal operation of the transducer region 171. In this embodiment, after the silicon substrate is mounted on the adapter plate 110, it forms the cavity 172 structure, which is particularly suitable for mounting the second chip 170 with the transducer region 171 in the fifth slot 156.

[0085] Please combine Figure 13 The 2.5D bridged package structure provided in this embodiment of the invention includes an adapter portion 120, a bridge portion 130, a bridge chip 135, a molding compound 142, a first silicon substrate, and a heat sink 160. The bridge portion 130 and the adapter portion 120 are spaced apart. The adapter portion 120 has a first metal pillar 122, a first wiring layer 113, and a second wiring layer 124. The two ends of the first metal pillar 122 are respectively connected to the first wiring layer 113 and the second wiring layer 124. One side of the adapter portion 120 has a third metal layer 114 connected to the first wiring layer 113, and the other side has a first metal layer 125 connected to the second wiring layer 124. The bridge portion 130 has a third wiring layer 133 and a second metal layer 134 connected to the third wiring layer 133. The bridge chip 135 is connected across the adapter portion 120 and the bridge portion 130. The bridge chip 135 is electrically connected to the first metal layer 125 and the second metal layer 134. The molding compound 142 encapsulates the bridge chip 135 and fills the gap between the bridge portion 130 and the transition portion 120, as well as covering the sidewalls of the transition portion 120. The first silicon substrate 151 has an oxide layer formed thereon, which helps to prevent electron migration.

[0086] The heat sink 160 is located on the side of the bridge section 130 away from the bridge chip 135. The heat sink 160 helps to improve the heat dissipation performance of the bridge section 130.

[0087] Optional, please refer to Figure 5 and Figure 6 The first silicon substrate 151 is provided with heat dissipation trenches 152 to improve heat dissipation performance. An oxide layer covers the peripheral wall, upper surface and trench walls of the first silicon substrate 151, thereby mitigating electron migration.

[0088] Optionally, the heat dissipation trench 152 is provided with thermally conductive metal 180. All heat dissipation trenches 152 can be filled with thermally conductive metal 180, or only some heat dissipation trenches 152 can be filled with thermally conductive metal 180, while the remaining heat dissipation trenches 152 retain a cavity structure.

[0089] Please combine Figure 14Optionally, the packaging structure also includes a substrate 210, with the thermally conductive metal 180 connected to the substrate 210 to improve thermal conductivity. Alternatively, if the thermally conductive metal 180 is connected to a grounding point on the substrate 210, it can provide electrostatic discharge or electromagnetic shielding.

[0090] Optionally, the side of the bridging portion 130 away from the second metal layer 134 is lower than the surface of the transition portion 120 having the third metal layer 114, i.e., a fourth groove 154 is formed on the back side of the bridging portion 130. The heat sink 160 includes an edge portion 161 and a heat dissipation portion 162. The heat dissipation portion 162 is located in the middle of the heat sink 160. A cooling component is provided in the middle of the heat sink 160, the edge portion 161 of the heat sink 160 overlaps with the transition portion 120, and the middle heat dissipation portion 162 is located in the fourth groove 154. Specifically, the edge of the heat sink 160 overlaps with the first dielectric layer 112. The cooling component includes, but is not limited to, coolant or cooling gas, to improve the heat dissipation effect. The heat sink 160 can be made of metal, silicon-based material, or polymer, etc.

[0091] Please combine Figure 13 Optionally, a first silicon plate 151 is provided on the side of the bridging portion 130 away from the second metal layer 134, and a heat sink 160 is mounted on the first silicon plate 151. An oxide layer is provided between the heat sink 160 and the first silicon plate 151. In this embodiment, the heat sink 160 is a silicon plate, and the oxide layer is a silicon dioxide layer 153. The silicon dioxide layer 153 serves as an insulating layer, thereby helping to avoid electron migration in the third wiring layer 133 of the bridging chip 135 region and preventing external or internal electrons from moving between the heat dissipation trenches 152 and breaking down the bridging portion 130. The edge portion 161 of the heat sink 160 is connected to the adapter portion 120, providing support for the adapter portion 120 around the bridging portion 130 and preventing warping deformation between the adapter plates 110 around the bridging portion 130.

[0092] Optionally, the heat sink 160 is provided with heat dissipation channels 164 to improve heat dissipation. The first silicon substrate 151 is provided with horizontally distributed heat dissipation grooves 152, which helps to improve the heat dissipation performance of the bridge chip 135 area. The horizontal arrangement can increase the stress area on the surface of the adapter board 110, providing good support and structural reliability. It also features a large heat dissipation area and good heat dissipation effect.

[0093] Optional, combined Figure 8 The heat dissipation grooves 152 on the first silicon plate 151 and the heat dissipation channels 164 on the heat dissipation plate 160 are set one-to-one, retaining the cavity structure.

[0094] Optional, please refer to Figure 15The edge portion 161 of the heat sink 160 is provided with a through hole 163, which extends to the plastic encapsulation 142 on the side wall of the bridge portion 130 to further improve heat dissipation performance.

[0095] It is understood that there is a gap between the sidewall of the first silicon substrate 151 and the transition portion 120, forming a channel 155. The channel 155 is beneficial for improving heat dissipation performance and acts as a buffer space under the thermal stress expansion of the packaging structure. It can absorb some deformation stress and prevent the components from interfering or being squeezed after structural expansion, thus preventing more internal stress from being generated. If an oxide layer is formed on the surface of the first silicon substrate 151, there is a gap between the oxide layer and the transition portion 120, forming the channel 155.

[0096] Please combine Figure 16 The first silicon substrate 151 has a fifth groove 156 exposing the bridging portion 130. A pad 157 connected to the third wiring layer 133 is provided on the side of the bridging portion 130 away from the second metal layer 134. A second chip 170 is disposed within the fifth groove 156, and the second chip 170 is electrically connected to the pad 157. Optionally, the second chip 170 is a flip-chip. The back surface of the second chip 170 is flush with the surface of the first silicon substrate 151. A heat sink 160 is mounted on the first silicon substrate 151 to dissipate heat from the second chip 170. The heat sink 160 has heat dissipation channels 164 to further improve the cooling effect.

[0097] Optionally, the edge 161 of the heat sink 160 overlaps the adapter 120. The adapter 120 is provided with a first dielectric layer 112, and a first wiring layer 113 is provided within the first dielectric layer 112. A fourth dielectric layer 115 covers the first dielectric layer 112, and the fourth dielectric layer 115 is provided with a third metal layer 114 connected to the first wiring layer 113. The third metal layer 114 protrudes from the fourth dielectric layer 115. The third metal layer 114 is connected to solder balls 116. One side surface of the edge 161 is connected to the surface of the first dielectric layer 112 where the first wiring layer 113 is provided, and the other side surface is flush with the surface of the fourth dielectric layer 115 where the third metal layer 114 is provided.

[0098] Alternatively, in some embodiments, one side surface of the edge portion 161 is connected to the surface of the first dielectric layer 112 where the first wiring layer 113 is provided, and the other side surface is flush with the surface of the third metal layer 114. This helps to prevent the solder balls 116 from collapsing during soldering, thus preventing bridging between solder balls. Furthermore, the thickness of the edge portion 161 of the heat sink 160 helps to control the soldering height of the solder balls 116, resulting in a more reliable structure.

[0099] Please combine Figure 12The second chip 170 has a transducer region 171 on the side near the bridge portion 130. After the heat sink 160 is mounted, the heat sink 160, the first silicon plate 151, and the bridge portion 130 enclose a cavity 172, ensuring that the transducer region 171 can work normally. During the packaging process, no additional process is required to form the cavity 172 structure.

[0100] It is understood that heat dissipation channels 164 are provided on the heat sink 160. In some embodiments, the cavity 172 is connected to the heat dissipation channels 164, which can increase the volume of the cavity 172, thereby improving the filtering effect of the filter chip. Furthermore, a baffle structure is formed between the heat dissipation channels 164. This baffle structure can block noise, effectively filtering out some noise and providing isolation and signal shielding, thereby improving transmission performance and packaging quality.

[0101] Optionally, multiple adapter sections 120 are disposed around the bridging section 130. Each adapter plate 110 has a first surface 101 and a second surface 102 disposed opposite to each other, and a first metal post 122 penetrates through the first surface 101 and the second surface 102. The first surface 101 is provided with a first dielectric layer 112, and a first wiring layer 113 is provided within the first dielectric layer 112. The first wiring layer 113 is connected to the first metal post 122. The end of the first wiring layer 113 away from the first metal post 122 is connected to a third metal layer 114. The number of layers of the first wiring layer 113 can be one or more, which is not specifically limited here.

[0102] The second surface 102 is provided with a second dielectric layer 123, and a second wiring layer 124 connected to the first metal pillar 122 is provided within the second dielectric layer 123. A first metal layer 125 connected to the second wiring layer 124 is provided on the surface of the second dielectric layer 123. The first metal layer 125 protrudes from the surface of the second dielectric layer 123. Optionally, a third chip is mounted on the first metal layer 125 to improve chip integration, enrich the functions of the packaged product, and enhance product performance.

[0103] The bridging portion 130 has a third dielectric layer 132 and a third wiring layer 133 disposed within the third dielectric layer 132. A second metal layer 134 connected to the third wiring layer 133 is provided on the surface of the third dielectric layer 132. The second metal layer 134 protrudes from the surface of the third dielectric layer 132. Optionally, the surfaces of the third dielectric layer 132 and the second dielectric layer 123 are flush, and the surfaces of the first metal layer 125 and the second metal layer 134 are flush, which can ensure that the bridging chip 135 is mounted smoothly, with higher mounting accuracy and more reliable structure.

[0104] Optionally, the first dielectric layer 112, the second dielectric layer 123, the third dielectric layer 132 and the fourth dielectric layer 115 are made of the same material, such as polyimide or benzocyclobutene.

[0105] The 2.5D bridging package structure and 2.5D bridging package process provided in this invention have the following advantages: The bridging section 130 and the adapter board 110 are set separately. The wiring layers on the adapter section 120 and the wiring layers on the bridging section 130 are set independently and are not directly connected. The transmission path of the wiring layers is shorter, the loss is lower, and the transmission efficiency is higher. Furthermore, the adapter section 120 and the bridging section 130 are isolated and insulated by a plastic encapsulation 142, which has better insulation performance. This helps to reduce the inductive effect and parasitic effect between the wiring layers, thereby mitigating the leakage phenomenon caused by parasitic inductance that leads to short circuits and overheating between wiring layers.

[0106] The heat sink 160 improves the heat dissipation performance of the package structure and supports the connected adapter 120, mitigating warpage of the adapter 120. The connection between the heat sink 160 and the bridge portion 130 further reduces warpage of the bridge portion 130, resulting in a more reliable structure and improved product yield. An oxide layer is formed between the heat sink 160 and the first silicon substrate 151, which helps prevent electron migration from the third wiring layer 133 on the bridge portion 130, preventing external or internal electrons from moving between the heat dissipation trenches 152 and damaging the bridge portion 130.

[0107] The wiring layers on the bridging section 130 and the adapter section 120 are set independently. The line width, line spacing, and other parameters of the wiring layers in the two areas can be flexibly designed, and can be the same or different, offering greater flexibility. The wiring precision can also be set differently. For example, the bridging section 130 can be used for more refined, high-precision wiring for high-end products, especially in products with high-frequency or ultra-high-frequency signals. On the other hand, the adapter section 120 can be used for wiring layers with relatively lower precision for other types of products. Due to the different wiring precision, the wiring process difficulty and cost also differ. This partitioned wiring design helps reduce overall cost and process difficulty, and improves process efficiency.

[0108] Furthermore, by setting up a second chip 170, it is beneficial to improve chip integration, make the structure more compact, and be applicable to chips that require the formation of a cavity 172 structure in the packaging process, such as surface acoustic wave filter chips, etc., with a wide range of applications and high flexibility.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A 2.5D bridged package structure, characterized in that, include: Adapter, bridging section, bridging chip, and molding compound; The bridging portion and the transition portion are spaced apart. The transition portion is provided with a first metal pillar, a first dielectric layer and a second dielectric layer. The first dielectric layer is provided with a first wiring layer and the second dielectric layer is provided with a second wiring layer. The two ends of the first metal pillar are respectively connected to the first wiring layer and the second wiring layer. The adapter has a third metal layer connected to the first wiring layer on one side and a first metal layer connected to the second wiring layer on the other side; the bridging part has a third wiring layer and a second metal layer connected to the third wiring layer. The bridging chip is connected across the adapter and the bridging portion, and the bridging chip is electrically connected to the first metal layer and the second metal layer respectively. The molding compound covers the bridge chip and the sidewalls of the adapter, and fills the gap between the bridge and the adapter. The bridging portion has a first silicon plate on the side away from the bridging chip, and the first silicon plate has an oxide layer.

2. The 2.5D bridged package structure according to claim 1, characterized in that, The first silicon plate has heat dissipation grooves.

3. The 2.5D bridged package structure according to claim 2, characterized in that, The heat dissipation trench is filled with thermally conductive metal.

4. The 2.5D bridged package structure according to claim 3, characterized in that, It also includes a substrate, wherein the thermally conductive metal is connected to the substrate; or, the thermally conductive metal is connected to a ground point on the substrate.

5. The 2.5D bridged package structure according to claim 2, characterized in that, The oxide layer covers the peripheral wall, upper surface, and walls of the heat dissipation trench of the first silicon plate.

6. The 2.5D bridged package structure according to claim 1, characterized in that, There is a gap between the first silicon plate and the transition portion, forming a channel; or there is a gap between the oxide layer and the transition portion, forming a channel.

7. The 2.5D bridged package structure according to claim 6, characterized in that, The depth of the channel ends at the plastic seal of the sidewall of the bridge connection.

8. The 2.5D bridged package structure according to claim 1, characterized in that, It also includes a heat sink, which is located on the side of the first silicon plate away from the bridge chip.

9. The 2.5D bridged package structure according to claim 8, characterized in that, The heat sink is provided with heat dissipation channels.

10. The 2.5D bridged package structure according to claim 9, characterized in that, The first silicon plate is provided with heat dissipation grooves, and the heat dissipation channels and the heat dissipation grooves are connected.

11. The 2.5D bridged package structure according to claim 8, characterized in that, The heat sink includes an edge portion and a heat dissipation portion. The edge portion is connected to the first dielectric layer, and the heat dissipation portion is attached to the first silicon substrate. The edge portion is provided with through holes.

12. The 2.5D bridged package structure according to claim 8, characterized in that, The first silicon substrate has a fourth groove on the side away from the bridge chip. The heat sink includes an edge portion and a heat dissipation portion. The edge portion is connected to the first dielectric layer, and the heat dissipation portion is attached to the fourth groove.

13. The 2.5D bridged package structure according to claim 12, characterized in that, The edge portion is provided with a through hole, and a channel is formed between the first silicon plate and the adapter portion, with the through hole and the channel communicating with each other.

14. The 2.5D bridged package structure according to claim 8, characterized in that, An oxide layer is formed between the heat sink and the first silicon plate.

15. The 2.5D bridged package structure according to any one of claims 1 to 14, characterized in that, It also includes a second chip; The first silicon substrate has a fifth groove, and the bridging portion has pads connected to the third wiring layer, the pads being located in the fifth groove; The second chip is disposed in the fifth slot and is electrically connected to the pad.

16. The 2.5D bridged package structure according to claim 15, characterized in that, The second chip has a transducer area, and the second chip, the bridge portion, the first silicon plate and the heat sink form a cavity to enable the transducer area to work normally.

17. A 2.5D bridging packaging process, characterized in that, include: Adapter board provided; The adapter plate has a first surface and a second surface that are disposed opposite to each other; A plurality of spaced first grooves are formed on the first surface; A first dielectric layer having a first wiring layer is formed within the first trench. A second groove and a third groove are formed on the second surface; wherein the position of the second groove corresponds to the position of the first groove; A second dielectric layer is formed in the second trench, a second wiring layer is provided in the second dielectric layer, and a first metal layer connected to the second wiring layer is provided on the surface of the second dielectric layer. A third dielectric layer is formed in the third trench, the third dielectric layer is provided with a third wiring layer, and a second metal layer connected to the third wiring layer is provided on the surface of the third dielectric layer; A bridge chip is mounted; the bridge chip is connected to the second metal layer and the first metal layer respectively. The adapter board includes a first silicon plate corresponding to the third dielectric layer; an oxide layer is formed on the side of the first silicon plate away from the bridge chip.

18. The 2.5D bridging packaging process according to claim 17, characterized in that, Also includes: A heat sink is mounted on the first silicon substrate; An oxide layer is formed between the heat sink and the first silicon plate; wherein the edge of the heat sink is connected to the first dielectric layer.

19. The 2.5D bridging packaging process according to claim 18, characterized in that, Before the step of attaching the heat sink to the first silicon substrate, the method further includes: The first silicon substrate forms a fifth groove that exposes the third dielectric layer; A pad connected to the third wiring layer is formed within the fifth groove. A second chip is mounted into the fifth slot, and the second chip is electrically connected to the pad. The heat sink is attached to the side of the second chip away from the third wiring layer, and an oxide layer is formed between the first silicon substrate and the heat sink.

20. The 2.5D bridging packaging process according to claim 18, characterized in that, Before the step of attaching the heat sink to the first silicon substrate, the method further includes: An oxide layer is formed on the first silicon substrate; A fifth groove is formed on the first silicon substrate; the fifth groove penetrates the oxide layer and the first silicon substrate and exposes the third dielectric layer; A pad connected to the third wiring layer is formed within the fifth groove. A second chip is mounted into the fifth slot, and the second chip is electrically connected to the pad. The heat sink is attached to the side of the second chip away from the third wiring layer.

21. The 2.5D bridging packaging process according to claim 18, characterized in that, The step of forming an oxide layer between the heat sink and the first silicon substrate includes: A silicon dioxide layer is formed between the heat sink and the first silicon plate by high-temperature sintering, followed by high-temperature annealing to complete the welding. Alternatively, the first silicon plate or the heat sink can be subjected to a high-temperature oxidation process to form a silicon dioxide layer, and then the heat sink and the first silicon plate can be welded together using a metal layer or an adhesive compound.

22. The 2.5D bridging packaging process according to claim 18, characterized in that, In the step of attaching a heat sink to the first silicon substrate: The first silicon plate is thinned so that the surface of the first silicon plate is lower than the surface of the first dielectric layer, forming a fourth groove. The heat sink is attached to the fourth slot. A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer is provided with a third metal layer connected to the first wiring layer, the third metal layer protruding from the surface of the fourth dielectric layer; The surface of the heat sink away from the first silicon plate is flush with the surface of the fourth dielectric layer or the surface of the third metal layer.

23. The 2.5D bridging packaging process according to claim 17, characterized in that, Before the step of forming the second dielectric layer in the second trench, the method further includes: A first metal pillar is formed on the adapter plate; one end of the first metal pillar is connected to the first wiring layer, and the other end protrudes from the bottom of the second groove. In the step of forming a second dielectric layer in the second trench: the second wiring layer is electrically connected to the first metal pillar.

24. The 2.5D bridged packaging process according to any one of claims 17 to 23, characterized in that, After the step of mounting the bridge chip, the following steps are also included: A molding compound is formed; the molding compound covers the bridge chip, the sidewalls of the second dielectric layer, and fills the gap between the second dielectric layer and the third dielectric layer.

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