2.5d bridge package structure and 2.5d bridge package method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FOREHOPE SEMICONDUCTOR (NINGBO) CO LTD
- Filing Date
- 2026-05-22
- Publication Date
- 2026-06-19
Smart Images
Figure CN122249071A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D bridged packaging structure and a 2.5D bridged packaging method. Background Technology
[0002] With the rapid development of the semiconductor industry, chiplet technology, as a new design approach, packages small chips with different functions together. Typically, 2.5D packaging technology is used to package the chips onto a silicon interposer as a multi-chiplet packaging solution. This mainly involves embedding a bridging chip within the interposer, followed by dielectric layer vias and wiring processes to mount other flip chips, thus achieving the interconnect structure. However, the bridging chip requires a flat chip pad structure to meet the requirements of dielectric layer etching and via technology, in order to form a conductive metal pillar structure. As products are used in the transmission paths of ultra-high frequency signals from 100GHz to 300GHz, the longer the transmission path between wiring layers, the greater the transmission loss caused by the phenomenon of current flowing towards the conductive pillars. In addition, the current forms inductive and thermoelectric effects between wiring layers, resulting in parasitic inductance and leakage. This leads to short circuits and overheating between wiring layers. Therefore, it is necessary to shorten the transmission path between active devices (such as RF chips, logic chips, or memory chips) and passive devices (such as components, capacitors, or inductors) in the package, or shorten the transmission paths between active and passive devices and the wiring layers respectively.
[0003] Furthermore, in existing technologies, silicon interposers are used as bridging structures. Due to the inconsistency in the thermal expansion coefficients of the wiring layer and the interposer, warping deformation may occur. In severe cases, the wiring layer or chip bump solder joints in the interposer may be stressed and break. Summary of the Invention
[0004] The purpose of this invention is to provide a 2.5D bridged package structure and a 2.5D bridged package method. By designing stress relief pillars, thermal stress can be distributed, and these pillars can serve as priority fracture points under thermal stress conditions. This reduces the risk of wiring layers in the bridge section breaking due to warping deformation, and also avoids breakage at chip bump solder joints due to warping deformation.
[0005] In a first aspect, the present invention provides a 2.5D bridged package structure, comprising: The bridging section includes a first dielectric layer, a first wiring layer, a first metal layer, and a second metal layer. The first wiring layer is disposed within the first dielectric layer, and the first metal layer and the second metal layer are disposed on opposite sides of the first dielectric layer. The first metal layer and the second metal layer are electrically connected to the first wiring layer. The adapter is provided with a second dielectric layer, a second wiring layer and a third metal layer; the second wiring layer is disposed within the second dielectric layer, and the third metal layer and the second wiring layer are electrically connected. A first chip, which connects the bridge portion and the adapter portion, and is electrically connected to the first metal layer and the third metal layer respectively; The second chip is located on the side of the bridge portion away from the first chip, and the second chip is connected to the second metal layer. A stress relief column, wherein the stress relief column is connected to the first dielectric layer; A molding compound, wherein a first gap is formed between the bridging portion and the adapter portion, and the molding compound covers the first chip and the second chip; the first gap is used for integral molding of the molding compound on both sides of the bridging portion.
[0006] In an optional embodiment, the stress relief post is disposed on the side wall of the bridge connection, and / or the stress relief post is disposed on the side of the first dielectric layer where the second metal layer is disposed.
[0007] In an optional embodiment, the stress relief column is disposed on the side wall of the bridge connection, and the height of the stress relief column is less than, equal to or greater than the thickness of the first dielectric layer.
[0008] In an optional embodiment, the sidewall of the bridge connection is provided with one or more stress relief columns, and / or, one or more stress relief columns are provided on the side of the first dielectric layer where the second metal layer is located.
[0009] In an optional embodiment, a first gap is provided between the bridging portion and the transition portion, and a first groove is provided on the side wall of the transition portion, the first groove being in communication with the first gap; The encapsulated body fills the first gap and the first groove.
[0010] In an optional embodiment, the sidewall of the transition portion is provided with stress relief columns.
[0011] In an optional embodiment, the stress relief column is connected to the encapsulated body.
[0012] Secondly, the present invention provides a 2.5D bridged packaging method, comprising: An adapter plate is provided, the adapter plate having a first surface and a second surface disposed opposite to each other; the adapter plate having an adapter region and a bridging region; the adapter region is used to fabricate an adapter part, and the bridging region is used to fabricate a bridging part; A first groove and a second groove are formed on a first surface; the first groove is located in the bridging region, and the second groove is located in the transition region. A first dielectric layer and a first wiring layer are formed within the first groove; A second dielectric layer and a second wiring layer are formed within the second groove; The adapter plate on the back side of the first dielectric layer is removed to form a recessed groove exposing the first dielectric layer, while the adapter plate on the side wall of the first dielectric layer is retained to form a stress relief column; wherein the depth of the first groove is the height of the stress relief column; or, a columnar adapter plate is retained on the back side of the first dielectric layer to form a stress relief column; or, the stress relief column is formed on both the side wall and the back side of the first dielectric layer; wherein, a through first gap is formed between the first dielectric layer and the second dielectric layer, and the first gap communicates with the recessed groove; A second chip is mounted on one side of the first dielectric layer; The first chip is mounted on the other side of the first dielectric layer; The first chip and the second chip are encapsulated in a plastic mold; wherein the encapsulating body flows through the first gap to simultaneously encapsulate the first chip and the second chip on both sides of the first dielectric layer.
[0013] In an optional implementation, in the step of forming the first groove on the first surface: The second groove is formed directly in the bridging region of the first surface; Alternatively, after thinning the bridging region of the first surface, a first groove is formed, and a second groove is formed at the bottom of the first groove.
[0014] In an optional implementation, in the step of forming the first groove on the first surface: A groove is formed on the side of the bridging area near the transition area, and a first column is formed between the groove and the transition area; In the step of removing the adapter plate on the back of the first dielectric layer to form a recessed groove exposing the first dielectric layer: Remove the first column to form a first groove on the sidewall of the transition area; Alternatively, the first column can be retained to form a stress-relieving column.
[0015] In an optional implementation, the first gap and the trench are in communication.
[0016] The 2.5D bridging package structure and method provided by this invention, through the design of stress relief pillars, helps to distribute thermal stress. These pillars can serve as priority fracture points under thermal stress, reducing the risk of wiring layers in the bridging section breaking due to warping deformation, and avoiding breakage at chip bump solder joints due to warping deformation. The bridging section and the transition section are separated, resulting in better electrical insulation, a compact structure, and mitigation of warping deformation issues. Attached Figure Description
[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is one of the process schematic diagrams of the 2.5D bridged packaging method provided in the embodiments of the present invention; Figure 2 This is the second schematic diagram of the manufacturing process of the 2.5D bridging packaging method provided in the embodiment of the present invention; Figure 3 for Figure 2 A magnified view of a portion of point A in the middle; Figure 4 The third schematic diagram of the manufacturing process of the 2.5D bridging packaging method provided in the embodiment of the present invention; Figure 5 for Figure 4 A magnified view of a portion of point B in the middle; Figure 6 Fourth schematic diagram of the manufacturing process of the 2.5D bridged packaging method provided in the embodiments of the present invention; Figure 7 Fifth schematic diagram of the manufacturing process of the 2.5D bridged packaging method provided in the embodiments of the present invention; Figure 8 The sixth schematic diagram of the manufacturing process of the 2.5D bridging packaging method provided in the embodiment of the present invention; Figure 9 One of the process diagrams for forming a second groove directly on the surface of an adapter board in the 2.5D bridging packaging method provided in the embodiments of the present invention; Figure 10 The second schematic diagram of the process of directly forming the second groove on the surface of the adapter board in the 2.5D bridging packaging method provided in the embodiment of the present invention; Figure 11 A schematic diagram of the process of forming stress relief pillars on the back side of the first dielectric layer in the 2.5D bridging packaging method provided in the embodiments of the present invention; Figure 12 A schematic diagram of a first 2.5D bridged package structure provided in an embodiment of the present invention; Figure 13 A schematic diagram of a second 2.5D bridged package structure provided in an embodiment of the present invention; Figure 14 A schematic diagram of a third 2.5D bridged package structure provided in an embodiment of the present invention; Figure 15 A schematic diagram of the fourth 2.5D bridged package structure provided in the embodiments of the present invention; Figure 16 A schematic diagram of the fifth 2.5D bridged package structure provided in the embodiments of the present invention; Figure 17 A schematic diagram of the sixth 2.5D bridged package structure provided in the embodiments of the present invention; Figure 18 A schematic diagram of the seventh 2.5D bridged package structure provided in the embodiments of the present invention; Figure 19 This is a schematic diagram showing the distribution of stress relief pillars in a 2.5D bridging package structure provided in an embodiment of the present invention.
[0019] Icons: 110-Adapter board; 101-First surface; 102-Second surface; 105-First carrier; 1051-Adhesive layer; 106-Second carrier; 107-Third carrier; 111-First groove; 112-Second groove; 113-Second groove; 115-Boss; 120-Bridging part; 121-First dielectric layer; 122-First wiring layer; 123-First metal layer; 124-Second metal layer; 125-Trench; 130-Adapter part; 131-Second 132 - Dielectric layer; 133 - Second wiring layer; 134 - Third metal layer; 135 - Conductive pillar; 141 - First gap; 142 - Third dielectric layer; 143 - Third wiring layer; 144 - Fourth metal layer; 151 - Stress relief pillar; 152 - First pillar; 153 - First groove; 161 - First chip; 162 - Second chip; 163 - Third chip; 164 - Fourth wiring layer; 170 - Molded enclosure; 171 - Cut groove; 173 - Solder ball. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0023] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0024] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0025] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0026] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0027] Please combine Figure 1 The 2.5D bridging packaging method proposed in this embodiment of the invention mainly includes the following steps: S1. An adapter board 110 is provided, having a first surface 101 and a second surface 102 disposed opposite to each other. The material of the adapter board 110 can be glass, a silicon substrate, or a germanium substrate. In this embodiment, a silicon adapter board 110 can be used. If wafer-level packaging is used, the size of the adapter board 110 can be selected as 6 inches, 8 inches, or 12 inches, etc. If panel-level packaging is used, the size of the adapter board 110 can be selected as 310cm×310cm, 600cm×600cm, 710cm×710cm, etc., and is not limited to the sizes listed above; it can be flexibly designed according to actual needs.
[0028] Optionally, S2, a third wiring layer 143 is prepared on the second surface 102 of the adapter plate 110.
[0029] It is understood that the adapter board 110 has a bridging region and an adapter region. The adapter region is used to fabricate the adapter portion 130, and the bridging region is used to fabricate the bridging portion 120. A third groove 141 is formed on the second surface 102 of the adapter board 110. The third groove 141 is formed in the bridging region. The depth of the third groove 141 is less than the thickness of the adapter board 110. The depth of the third groove 141 is determined according to the design requirements of the third wiring layer 143.
[0030] The third groove 141 can be formed using plasma etching technology, such as dry plasma etching or chemical etching. Dry plasma etching utilizes a plasma gas composed of a mixture of oxygen (O2) and SF6; chemical etching uses one or more chemical agents, such as phosphoric acid, acetic acid, hydrogen chloride, or sulfuric acid, for etching.
[0031] Optionally, a third dielectric layer 142 is formed within the third groove 141. The third dielectric layer 142 is exposed and developed to form an opening in the pattern layer. Metal is then electroplated into the opening in the pattern layer using techniques such as electroplating to form a third wiring layer 143. The number of third wiring layers 143 is not limited; it can be one or more layers. If multiple layers of third wiring layers 143 are designed, they are designed sequentially in stages, and the third dielectric layer 142 is also designed in multiple layers accordingly. It can be understood that the depth of the third groove 141 is the overall thickness of the third dielectric layer 142, that is, the surface of the third dielectric layer 142 is flush with the second surface 102 of the adapter plate 110. This design allows the third wiring layer 143 to be embedded in the adapter plate 110, avoiding the delamination phenomenon between the third dielectric layer 142 and the second surface 102 of the adapter plate 110 caused by the warping of the adapter plate 110. It is worth noting that placing the third wiring layer 143 within the third groove 141 reduces the contact area between the third dielectric layer 142 and the surface of the adapter plate 110, thereby reducing the risk of structural delamination. Furthermore, the adapter plate 110, which forms the groove wall of the third groove 141, can protect the sidewalls of the third dielectric layer 142, further reducing the risk of delamination.
[0032] Optionally, the surface of the third dielectric layer 142 is provided with a fourth metal layer 144 that is electrically connected to the third wiring layer 143.
[0033] Please combine Figure 2 and Figure 3 S3. A first carrier 105 is provided, and a flip-over adapter plate 110 is provided. The adapter plate 110 is attached to the first carrier 105 on one side having a third wiring layer 143. The first carrier 105 can be made of materials such as glass, silicon dioxide, or metal. An adhesive layer 1051 is coated on the first carrier 105.
[0034] S4. A first groove 111 and a second groove 112 are formed on the first surface 101; the first groove 111 is located in the bridging region, and the second groove 112 is located in the transition region. A first dielectric layer 121 and a first wiring layer 122 are formed in the first groove 111; a second dielectric layer 131 and a second wiring layer 132 are formed in the second groove 112.
[0035] Optionally, a first groove 111 is formed in the bridging area of the first surface 101, and a second groove 112 is formed in the transition area of the first surface 101. The arrangement of the first groove 111 and the second groove 112 is similar to that of the third groove 141 described above, and is not specifically limited here. Optionally, the depth of the first groove 111 is less than the depth of the second groove 112, that is, the bottom of the first groove 111 is higher than the bottom of the second groove 112. The positions of the second groove 112 and the third groove 141 are correspondingly arranged. The first groove 111 is located between adjacent second grooves 112. Alternatively, the second groove 112 is located on the periphery of the first groove 111.
[0036] Optionally, a groove 125 is formed on the side of the bridging area near the transition area, and a first pillar 152 is formed between the groove 125 and the transition area. The first pillar 152 can be understood as being formed by the wall thickness of the groove wall on the side of the groove 125 near the transition area.
[0037] It should be noted that the appendix Figure 4 To be continued Figure 11 The diagram shown is a partial schematic of the adapter board 110, which is used to illustrate the schematics of each process.
[0038] Please combine Figure 4 and Figure 5S41, Optionally, a conductive post 134 penetrating the adapter plate 110 is formed in the second groove 112. One end of the conductive post 134 is electrically connected to the third wiring layer 143, and the other end is flush with the bottom of the second groove 112. The conductive post 134 can be formed by using a TSV through-hole process and then filling the through-hole with metal. It can be understood that the height of the conductive post 134 is the vertical distance between the bottom of the second groove 112 and the bottom of the third groove 141.
[0039] S42. A first dielectric layer 121 is formed in the first groove 111, and a first wiring layer 122 is fabricated. Optionally, the surface of the first dielectric layer 121 is provided with a first metal layer 123 that is electrically connected to the first wiring layer 122.
[0040] A second wiring layer 132 electrically connected to the conductive post 134 is formed in the second groove 112. Optionally, a third metal layer 133 electrically connected to the second wiring layer 132 is provided on the surface of the second dielectric layer 131.
[0041] The second wiring layer 132 and the first wiring layer 122 can be fabricated simultaneously or in stages; no specific limitation is made here. In this embodiment, the surfaces of the first dielectric layer 121 and the second dielectric layer 131 are flush. In some embodiments, the fabrication order of the first wiring layer 122 and the second wiring layer 132 is not limited. The fabrication processes of the first wiring layer 122 and the second wiring layer 132 can be found in the aforementioned fabrication process of the third wiring layer 143, and will not be repeated here.
[0042] Optionally, a second groove 113 can be formed at the bottom of the first groove 111, in which a first dielectric layer 121 and a first wiring layer 122 are formed. In this way, the sidewalls of the first dielectric layer 121 are covered by the groove walls of the second groove 113, protecting both the first dielectric layer 121 and the first wiring layer 122. Furthermore, the material of the transition plate 110 on the sidewall of the first dielectric layer 121 can be retained in the structure as a stress-relieving pillar 151, serving to distribute and release stress on the transition plate 110, thus preventing problems such as warping or breakage of the first wiring layer 122 within the first dielectric layer 121 due to stress.
[0043] Optionally, the first dielectric layer 121 and the second dielectric layer 131 can be spaced apart from each other, such as completely or partially separated, thus forming a first gap 135 between the first dielectric layer 121 and the second dielectric layer 131. The first gap 135 has a buffering effect, providing more deformation space when subjected to thermal stress during the manufacturing process, avoiding problems such as delamination or breakage of wiring layers or chip bump solder joints caused by stress. Optionally, the first gap 135 and the trench 125 are connected.
[0044] Please combine Figure 6Remove the first carrier 105 and attach the second carrier 106 to the side of the adapter plate 110 away from the first wiring layer 122. The second carrier 106 is placed downwards, and the side of the adapter plate 110 with the third dielectric layer 142 is placed upwards.
[0045] S5. Remove the adapter plate 110 on the back side of the first dielectric layer 121 to form a recessed groove exposing the first dielectric layer 121, and retain the adapter plate 110 on the sidewall of the first dielectric layer 121 to form a stress relief post 151. The depth of the second groove 113 is the height of the stress relief post 151. In some embodiments, the first groove 111 can be omitted, and the second groove 113 can be formed directly on the adapter plate 110, forming the first dielectric layer 121 and the first wiring layer 122. Thus, the groove wall of the second groove 113 serves as the stress relief post 151 at the periphery of the first dielectric layer 121. Optionally, the stress relief post 151 is flush with the surface of the first dielectric layer 121 near the third dielectric layer 142.
[0046] Alternatively, the bridging region of the first surface 101 can be thinned to form the first groove 111; and the second groove 113 can be formed in the thinned bridging region, that is, the second groove 113 is formed at the bottom of the first groove 111.
[0047] The adapter plate 110 on the back side of the first dielectric layer 121 can be removed by etching to expose the first dielectric layer 121. The etching method is similar to that used to form the third groove 141. It can be understood that in this etching step, the material of the adapter plate 110 retained after etching serves as a stress relief pillar 151. The cross-sectional shape, number, and position of the stress relief pillars 151 can be controlled by adjusting the etching parameters. For example, the stress relief pillars 151 can be located on the sidewall of the first dielectric layer 121, and their height can be less than, equal to, or greater than the thickness of the first dielectric layer 121. The stress relief pillars 151 can be located on the surface of the first dielectric layer 121 near the third wiring layer 143, i.e., retaining the columnar adapter plate 110 on the back side of the first dielectric layer 121 to form the stress relief pillars 151; their height can be flexibly designed according to actual needs. Alternatively, stress relief pillars 151 can be formed on both the sidewall and the back side of the first dielectric layer 121, without specific limitations.
[0048] It is understandable that in the step of removing the adapter plate 110 on the back of the first groove 111 to expose the first dielectric layer 121, the wall thickness at the groove 125, i.e., the first pillar 152, can be retained as a stress relief pillar 151, as shown in the figure. Alternatively, the first pillar 152 can be etched away, which can form a first groove 153 on the outer wall of the third dielectric layer 142, increasing the groove space, and forming a stepped structure on the outer wall of the second dielectric layer 131, which can improve the fluidity and filling properties of the subsequent encapsulant 170, and improve the bonding force between the dielectric layer and the encapsulant 170.
[0049] S6. Attach the second chip 162 to one side of the first dielectric layer 121; attach the first chip 161 to the other side of the first dielectric layer 121.
[0050] Optionally, a second metal layer 124 is formed on the side of the first dielectric layer 121 near the third dielectric layer 142, and the second metal layer 124 is electrically connected to the first wiring layer 122. A second chip 162 is mounted on the side of the first dielectric layer 121 where the second metal layer 124 is formed. The second chip 162 is electrically connected to the second metal layer 124. The second chip 162 can be a flip chip or a regular chip, and there is no specific limitation here. The number and type of the second chips 162 are not limited and can be flexibly designed.
[0051] Please combine Figure 7 Remove the second carrier 106, flip the product, and mount the side of the adapter board 110 with the third wiring layer 143 onto the third carrier 107. Mount a first chip 161 on the side of the adapter board 110 with the third wiring layer 143. The first chip 161 bridges the first dielectric layer 121 and the second dielectric layer 131, and is electrically connected to the first metal layer 123 and the second metal layer 124, respectively. It is understood that the first chip 161 can be a flip-chip or a regular-mount chip; no specific limitation is made here. The number and type of the first chips 161 are not limited and can be flexibly designed.
[0052] Optionally, a third chip 163 is mounted on the second dielectric layer 131. The third chip 163 is connected to the third metal layer 133 to improve chip integration.
[0053] Optionally, a cutting groove 171 is formed on the edge of the cut adapter plate 110, exposing the sidewalls of the second dielectric layer 131 and the third dielectric layer 142. The cutting groove 171 is subsequently filled with a molding compound 170 to protect the sidewalls of the adapter portion 130.
[0054] Please combine Figure 8 S7, plastic sealing.
[0055] Optionally, after the step of mounting the first chip 161 on the other side of the first dielectric layer 121, the process further includes: molding the first chip 161 and the second chip 162. The molding compound 170 flows through the first gap 135 and the trench 125 to simultaneously encapsulate the first chip 161 and the second chip 162 on both sides of the first dielectric layer 121. In this embodiment, since the first gap 135 and the trench 125 are connected, the molding compound 170 can flow through the first gap 135 and the trench 125, thereby achieving double-sided molding. That is, in the same molding process, the first chip 161 and the second chip 162 on both sides of the first dielectric layer 121 are simultaneously molded. This configuration allows the molding compounds 170 on both sides to be formed in one step, resulting in a more reliable structure and reducing the risk of structural delamination. Furthermore, it simplifies the process, reduces the number of molding and baking processes for the molding compound 170, and improves problems such as thermal stress shrinkage and warping deformation of the molding compound 170.
[0056] The third carrier 107 is removed, and solder balls 173 are formed on the fourth metal layer 144. Finally, the product is cut and separated to form a single product. During the cutting process, the encapsulation 170 on the outside of the second dielectric layer 131 and the third dielectric layer 142 can be retained, thus protecting the second dielectric layer 131 and the third dielectric layer 142. Alternatively, the encapsulation 170 on the outside of the second dielectric layer 131 and the third dielectric layer 142 can be cut and removed to further reduce the product volume.
[0057] Combination Figure 9 and Figure 10 This is a process diagram showing the direct formation of the second groove 113 in the bridging area of the first surface 101.
[0058] In step S4, a third groove 141 is formed in the transition area of the first surface 101, and a second groove 113 is directly formed in the bridging area of the first surface 101. The bottom of the third groove 141 is lower than the bottom of the second groove 113. A boss 115 is formed on one side of the groove wall of the second groove 113; optionally, the height of the boss 115 is the thickness of the first dielectric layer 121. The groove wall on the other side of the second groove 113 is removed to form a groove 125. The boss 115 also serves to prevent adhesive overflow.
[0059] After fabricating the second wiring layer 132 and the first wiring layer 122, the product is flipped over, and the adapter plate 110 of the bridging area of the second surface 102 is removed. During the removal of the adapter plate 110, the boss 115 structure is retained. In this embodiment, the surface of the boss 115 is flush with the surface of the first dielectric layer 121. Furthermore, the remaining adapter plate 110 in the bridging area is removed so that the trench 125 extends through the thickness direction of the adapter plate 110. Subsequent processes are similar to those in the aforementioned embodiments and will not be described again here.
[0060] It should be noted that the third wiring layer 143 can be formed before the first wiring layer 122 and the second wiring layer 132, or the third wiring layer 143 can be formed after the first wiring layer 122 and the second wiring layer 132 are formed. No specific limitation is made here.
[0061] Combination Figure 11 In some embodiments, a first groove 111 and a second groove 112 are first formed on the first surface 101 of the adapter plate 110. A first dielectric layer 121 and a first wiring layer 122 are formed in the first groove 111, and a second dielectric layer 131 and a second wiring layer 132 are formed in the second groove 112. The adapter plate 110 is flipped over, and a third groove 141 is formed on the second surface 102. The bridging area of the adapter plate 110 on the second surface 102 is removed to expose the first dielectric layer 121. When removing the adapter plate 110, a stress relief post 151 is formed on the side surface of the first dielectric layer 121 near the third groove 141. Optionally, the adapter plate 110 on the sidewall of the first dielectric layer 121 is etched away, so that a first gap 135 is formed between the first dielectric layer 121 and the second dielectric layer 131. The through first gap 135 communicates with the recessed groove to facilitate the subsequent one-time double-sided molding of the encapsulant 170.
[0062] Combination Figure 12 This invention also provides a 2.5D bridge package structure, including a bridge portion 120, a transition portion 130, a first chip 161, and stress relief pillars 151. The bridge portion 120 has a first dielectric layer 121, a first wiring layer 122, a first metal layer 123, and a second metal layer 124. The first wiring layer 122 is disposed within the first dielectric layer 121, and the first metal layer 123 and the second metal layer 124 are disposed on opposite sides of the first dielectric layer 121, respectively, and are electrically connected to the first wiring layer 122. The transition portion 130 has a second dielectric layer 131, a second wiring layer 132, and a third metal layer 133. The second wiring layer 132 is disposed within the second dielectric layer 131, and the third metal layer 133 is electrically connected to the second wiring layer 132. The first chip 161 bridges the bridge portion 120 and the transition portion 130, and is electrically connected to both the first metal layer 123 and the third metal layer 133. Stress relief post 151 is connected to the first dielectric layer 121. Stress relief post 151 helps to distribute thermal stress and can serve as a priority fracture point under thermal stress, reducing the risk of wiring layers in the bridging portion 120 breaking due to warping deformation, and preventing breakage at the chip bump solder joints due to warping deformation. The bridging portion 120 and the transition portion 130 are separately arranged, resulting in better electrical insulation, a more compact structure, and mitigation of warping deformation problems.
[0063] Optionally, the stress relief post 151 is disposed on the side wall of the bridging portion 120, or the stress relief post 151 is disposed on the side surface of the first dielectric layer 121 where the second metal layer 124 is provided, such as... Figure 13 As shown. Alternatively, stress relief columns 151 may be provided on the side wall of the bridge connection 120 and the side surface of the first dielectric layer 121 where the second metal layer 124 is provided.
[0064] It is understood that stress relief columns 151 are provided on the side wall of the bridge connection portion 120, and the height of the stress relief column 151 is less than, equal to, or greater than the thickness of the first dielectric layer 121. The height, cross-section, and number of stress relief columns 151 can be flexibly designed according to actual needs. One or more stress relief columns 151 are provided on the side wall of the bridge connection portion 120, and / or one or more stress relief columns 151 are provided on the side of the first dielectric layer 121 where the second metal layer 124 is located.
[0065] Optionally, a first gap 135 is provided between the bridging portion 120 and the transition portion 130, and a first groove 153 is provided on the side wall of the transition portion 130, the first groove 153 communicating with the first gap 135. The encapsulant 170 fills the first gap 135 and the first groove 153. The first groove 153 is provided to improve the filling properties and flowability of the encapsulant 170, as well as to improve the adhesion between the encapsulant 170 and the dielectric layer.
[0066] The side wall of the adapter 130 is provided with stress relief post 151. It can be understood that the side wall of the adapter 130 does not form the first groove 153. The material of the adapter plate 110 retained at the location of the first groove 153 forms the stress relief post 151, which helps to prevent the wiring layer from warping, deforming, or even breaking.
[0067] Optionally, the adapter 130 includes an adapter plate 110 and conductive posts 134 penetrating the adapter plate 110. A second dielectric layer 131 is provided on one side of the adapter plate 110, a second wiring layer 132 is provided within the second dielectric layer 131, and a third metal layer 133 electrically connected to the second wiring layer 132 is provided on the surface of the second dielectric layer 131. A third dielectric layer 142 is provided on the other side of the adapter plate 110, a third wiring layer 143 is provided within the third dielectric layer 142, and a fourth metal layer 144 electrically connected to the third wiring layer 143 is provided on the surface of the third dielectric layer 142. The fourth metal layer 144 is used to connect solder balls 173.
[0068] Optionally, a second chip 162 is also included. The second chip 162 is disposed on the side of the bridging portion 120 where the second metal layer 124 is located, and the second chip 162 is connected to the second metal layer 124. The bridging portion 120 realizes the interconnection of the first chip 161 and the second chip 162. The type and quantity of the first chip 161 and the second chip 162 are not limited.
[0069] In this embodiment, the sidewall of the first dielectric layer 121 is provided with stress relief posts 151 whose height is less than the thickness of the first dielectric layer 121. The stress relief posts 151 on the sidewall of the transition portion 130 help prevent the wiring layer or the bump solder joint from warping, deforming or breaking due to stress.
[0070] Optionally, a third chip 163 is also included. The third chip 163 is mounted on the adapter 130 and connected to the third metal layer 133, which helps to improve the chip integration.
[0071] Combination Figure 14 In some embodiments, the sidewall of the adapter 130 is provided with a first groove 153, and a first gap 135 is formed between the first dielectric layer 121 and the second dielectric layer 131. The first groove 153 and the first gap 135 are in communication, and the encapsulant 170 fills the first groove 153 and the first gap 135. The encapsulant 170 covers the sidewall of the adapter 130.
[0072] Combination Figure 15 In some embodiments, the sidewall of the adapter 130 does not have a molding compound 170, and the molding compound 170 covers the first chip 161, the second chip 162 and the third chip 163.
[0073] Optionally, in some embodiments, the surface of the molding compound 170 is flush with the surface of the first chip 161, which helps to improve heat dissipation performance.
[0074] Combination Figure 16 In some embodiments, the height of the stress relief column 151 on the sidewall of the first dielectric layer 121 is equal to the thickness of the first dielectric layer 121.
[0075] Combination Figure 17 In some embodiments, the second chip 162 may be a silicon bridge chip, and a fourth wiring layer 164 is provided on the back side of the silicon bridge chip. The fourth wiring layer 164 is electrically connected to the silicon bridge chip, and the fourth wiring layer 164 is electrically connected to the third chip.
[0076] It should be noted that silicon bridge chips can form integrated circuit (IC) packages. An IC package includes a package substrate and one or more IC chips or other electronic modules mounted on the package substrate to provide electrical connections to the IC chips. For example, the IC chip in an IC package can be a system-on-a-chip (SoC). The IC chip is electrically coupled to other IC chips and / or other components within the IC package via metal lines electrically coupled to the package substrate. The IC chip can also be electrically coupled to other circuits outside the IC package via electrical connections of external metal interconnects. For example, one or more embedded capacitors can provide decoupling capacitance for the power distribution network (PDN) within the IC package to reduce current resistance (IR) drop. Furthermore, the active wiring layer of the embedded capacitor is disposed between the IC chip and the package substrate to minimize the distance between the embedded capacitor and the IC chip. This reduces parasitic inductance in the power distribution lines between the embedded capacitor and the IC chip, thereby reducing IR drop in the PDN and also helping to reduce PDN noise. In some embodiments, the number and type of silicon bridge chips are not limited.
[0077] Optional, please refer to Figure 18 In some embodiments, the height of the stress relief column 151 on the sidewall of the first dielectric layer 121 is greater than the thickness of the first dielectric layer 121.
[0078] Combination Figure 19 It can be understood that the bridging portion 120 is surrounded by multiple transition portions 130. A first chip 161 is connected between each transition portion 130 and the bridging portion 120. Stress relief pillars 151 can be located on any one or more sides of the bridging portion 120. Here, "one side or multiple sides" can be understood as the sidewall of the bridging portion 120, or the sidewall of the transition portion 130, or the edge of the surface of the bridging portion 120 where the second metal layer 124 is located, or at one or more of the aforementioned locations. The stress relief pillars 151 can be arranged in a continuous block shape, such as a retaining wall, or in a multi-point columnar arrangement, i.e., in a discontinuous state. Their number, cross-sectional shape, or distribution position can be flexibly designed and are not specifically limited. Figure 19 Optionally, stress relief columns 151 are provided on three sides of the bridge connection 120, wherein the stress relief columns 151 on two side walls are in a disconnected state, and the stress relief columns 151 on one side wall are in a continuous state, without being specifically limited here.
[0079] The 2.5D bridging package structure and method provided in this invention, through the design of stress relief pillars 151, facilitates the distribution of thermal stress. These pillars can act as priority fracture points under thermal stress, reducing the risk of wiring layer breakage due to warping deformation in the bridging portion 120 and preventing breakage at chip bump solder joints due to warping deformation. The separate arrangement of the bridging portion 120 and the transition portion 130 provides better electrical insulation and a more compact structure, mitigating warping deformation. The flexible design of the cross-sectional shape, number, and distribution of the stress relief pillars 151 facilitates stress release during the thermal process, preventing warping, deformation, or breakage of the wiring layer or bump solder joints. The use of a double-sided molding compound 170 in a single molding process simplifies the process, ensures structural reliability, and improves packaging efficiency and product yield.
[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.
Claims
1. A 2.5D bridged package structure, characterized in that, include: The bridging section includes a first dielectric layer, a first wiring layer, a first metal layer, and a second metal layer. The first wiring layer is disposed within the first dielectric layer, and the first metal layer and the second metal layer are disposed on opposite sides of the first dielectric layer. The first metal layer and the second metal layer are electrically connected to the first wiring layer. The adapter is provided with a second dielectric layer, a second wiring layer and a third metal layer; the second wiring layer is disposed within the second dielectric layer, and the third metal layer and the second wiring layer are electrically connected. A first chip, which connects the bridge portion and the adapter portion, and is electrically connected to the first metal layer and the third metal layer respectively; The second chip is located on the side of the bridge portion away from the first chip, and the second chip is connected to the second metal layer. A stress relief column, wherein the stress relief column is connected to the first dielectric layer; A molding compound is provided, wherein a first gap is formed between the bridging portion and the transition portion, and the molding compound covers the first chip and the second chip; the first gap is used to allow the molding compound on both sides of the bridging portion to be integrally formed.
2. The 2.5D bridged package structure according to claim 1, characterized in that, The stress relief column is disposed on the side wall of the bridge connection, and / or the stress relief column is disposed on the side of the first dielectric layer where the second metal layer is disposed.
3. The 2.5D bridged package structure according to claim 1, characterized in that, The stress relief column is disposed on the side wall of the bridge connection, and the height of the stress relief column is less than, equal to or greater than the thickness of the first dielectric layer.
4. The 2.5D bridged package structure according to claim 1, characterized in that, The sidewall of the bridge connection is provided with one or more stress relief columns, and / or, one or more stress relief columns are provided on the side of the first dielectric layer where the second metal layer is located.
5. The 2.5D bridged package structure according to claim 1, characterized in that, There is a first gap between the bridge part and the transition part, and the side wall of the transition part is provided with a first groove, which communicates with the first gap; The encapsulated body fills the first gap and the first groove.
6. The 2.5D bridged package structure according to claim 1, characterized in that, The sidewall of the transition section is provided with stress relief columns.
7. The 2.5D bridged package structure according to any one of claims 1-6, characterized in that, The stress relief column is connected to the encapsulation body.
8. A 2.5D bridging packaging method, characterized in that, include: An adapter plate is provided, the adapter plate having a first surface and a second surface disposed opposite to each other; the adapter plate has an adapter area and a bridging area; The transition area is used to fabricate the transition part, and the bridging area is used to fabricate the bridging part; A first groove and a second groove are formed on the first surface; the first groove is located in the bridging region, and the second groove is located in the transition region. A first dielectric layer and a first wiring layer are formed within the first groove; A second dielectric layer and a second wiring layer are formed within the second groove; The adapter plate on the back side of the first dielectric layer is removed to form a recessed groove exposing the first dielectric layer, while the adapter plate on the side wall of the first dielectric layer is retained to form a stress relief column; wherein the depth of the first groove is the height of the stress relief column; or, a columnar adapter plate is retained on the back side of the first dielectric layer to form a stress relief column; or, the stress relief column is formed on both the side wall and the back side of the first dielectric layer; wherein, a through first gap is formed between the first dielectric layer and the second dielectric layer, and the first gap communicates with the recessed groove; A second chip is mounted on one side of the first dielectric layer; The first chip is mounted on the other side of the first dielectric layer; The first chip and the second chip are encapsulated in a plastic mold; wherein the encapsulating body flows through the first gap to simultaneously encapsulate the first chip and the second chip on both sides of the first dielectric layer.
9. The 2.5D bridging packaging method according to claim 8, characterized in that, In the step of forming the first groove on the first surface: The second groove is formed directly in the bridging region of the first surface; Alternatively, after thinning the bridging region of the first surface, the first groove is formed; and the second groove is formed at the bottom of the first groove.
10. The 2.5D bridging packaging method according to claim 9, characterized in that, In the step of forming the first groove on the first surface: A groove is formed on the side of the bridging area near the transition area, and a first column is formed between the groove and the transition area; In the step of removing the adapter plate on the back of the first dielectric layer to form a recessed groove exposing the first dielectric layer: Remove the first column to form a first groove on the sidewall of the transition area; Alternatively, the first column can be retained to form a stress-relieving column.
11. The 2.5D bridging packaging method according to claim 10, characterized in that, The first gap and the groove are connected.