High-density interconnect structures and methods based on glass substrates and any layer of pspl

Abstract

This invention discloses an arbitrary-layer high-density interconnect structure and method based on a glass substrate and PSPI. The structure includes: a glass core plate having multiple through-glass vias (TGVs); and a layered structure disposed on a first and a second surface of the glass core plate. The layered structure employs at least one photosensitive polyimide (PSPI) dielectric layer, with micropores and conductive patterns formed in each PSPI dielectric layer. The conductive patterns are interconnected through the micropores and the through-glass vias to form a high-density arbitrary-layer interconnect structure.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an arbitrary-layer high-density interconnect structure and method based on a glass substrate and PSPI. Background Technology

[0002] As integrated circuits evolve towards higher performance, higher density, and higher frequency, advanced packaging technology has become crucial for improving system performance. Traditional organic substrates (such as FR-4 and BT resin) are gradually facing bottlenecks in addressing next-generation high-performance computing, artificial intelligence chips, and radio frequency modules due to their large coefficient of thermal expansion, high high-frequency loss, and poor dimensional stability.

[0003] Glass substrates are considered ideal candidate materials for next-generation advanced packaging due to their excellent intrinsic properties, such as a thermal expansion coefficient matching that of silicon, excellent high-frequency electrical performance, ultra-high dimensional stability, flat surface, and potential low cost. However, significant technical challenges remain in applying glass substrates to high-density interconnects. Interconnect density bottleneck: Current glass substrate technology mainly focuses on achieving double-sided interconnects (i.e., 2+0 structure) through glass vias (TGV). This simple double-sided board structure greatly limits its wiring capabilities and cannot meet the needs of multi-chip, high I / O quantity packages for complex power, ground, and signal networks.

[0004] Process integration challenge: There is a lack of a mature and efficient process integration solution specifically designed for the characteristics of glass substrates that can seamlessly integrate high aspect ratio TGV with high density fine line layering technology.

[0005] Therefore, there is an urgent need in this field for an innovative method that can overcome the limitations of glass substrates in terms of the number of layers and enable high-density, high-reliability arbitrary layer stacking interconnection on them. Summary of the Invention

[0006] In view of this, the main objective of the present invention is to provide an arbitrary layer high-density interconnect structure and method based on a glass substrate and PSPI.

[0007] To achieve the above objectives, the technical solution of the present invention is implemented as follows: A high-density interconnect structure with arbitrary layers based on a glass substrate and PSPI, comprising: A glass core plate having multiple glass through-holes (TGV). The added-layer structure is respectively disposed on the first and second surfaces of the glass core plate; The added-layer structure employs at least one photosensitive polyimide (PSPI) dielectric layer, with micropores and conductive patterns formed in each PSPI dielectric layer; The conductive pattern is interconnected between the micropores and the glass via layers to form a high-density arbitrary layer interconnect structure.

[0008] Preferably, the micropores in the PSPI dielectric layer are formed by photolithography, and copper is electroplated inside the micropores to form vertical interconnects.

[0009] Preferably, the number of PSPI dielectric layers on the first and second surfaces is asymmetrical.

[0010] Preferably, the surfaces of the first and second surfaces, as well as the inner wall of the glass through-hole, have roughened surfaces that have undergone chemical roughening treatment.

[0011] Preferably, the aspect ratio of the glass through-hole is greater than 5:1.

[0012] Preferably, the inner wall of the glass through-hole is provided with an adhesion layer, a copper seed layer, and an electroplated copper filler layer in sequence.

[0013] A method for fabricating an arbitrary-layer high-density interconnect structure based on a glass substrate and PSPI as described above, the method comprising: Fabrication of a glass core plate with through-glass vias (TGV); A layering process is performed sequentially on the first side of the glass core plate to form multiple PSPI dielectric layers and conductive patterns. The glass core plate is flipped over, and a layering process is performed sequentially on the second side of the glass core plate to form multiple PSPI dielectric layers and conductive patterns. After all the added-layer structures are completed, laser ablation is performed to open windows, expose the pads, and prepare the solder bumps.

[0014] Preferably, the preparation of the glass core plate with through-glass vias (TGV) further includes: roughening the first surface, the second surface and the inner wall surface of the glass core plate and the through-glass via by chemically etching the glass core plate with fluoride.

[0015] Preferably, the layer-addition process is performed sequentially on the first surface of the glass core plate to form multiple PSPI dielectric layers and conductive patterns, specifically including: A photosensitive polyimide (PSPI) layer is coated on the first surface of the glass core plate as a first dielectric layer; The first dielectric layer is exposed and developed to simultaneously form grooves for micropores and conductive patterns. By chemically plating copper and patterned electroplating copper, a first layer of conductive pattern is formed in the groove of the conductive pattern and the micropores are filled at the same time to form a vertical interconnect.

[0016] Preferably, the glass core plate is flipped over, and a layering process is performed sequentially on the second side of the glass core plate to form multiple PSPI dielectric layers and conductive patterns, specifically including: coating a layer of photosensitive polyimide (PSPI) on the second side of the glass core plate as the first dielectric layer; The first dielectric layer is exposed and developed to simultaneously form grooves for micropores and conductive patterns. By chemically plating copper and patterned electroplating copper, a first layer of conductive pattern is formed in the groove of the conductive pattern and the micropores are filled at the same time to form a vertical interconnect.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: Using a glass core board with extremely high dimensional stability as a rigid core, the problem of thermal expansion and contraction of organic substrates is fundamentally avoided, thus providing a stable reference platform for multi-layer high-precision wiring. At the same time, since the added layer uses a PSPI dielectric layer that can be patterned by photolithography, it is possible to create micro-holes and fine lines with a precision far exceeding that of traditional lamination processes, thus achieving extremely high wiring density. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and, together with their descriptions, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings: Figure 1 This is a schematic diagram illustrating the completion of a double-sided layered structure in an arbitrary-layer high-density interconnect structure based on a glass substrate and PSPI, as provided in an embodiment of the present invention. Figure 2 This invention provides a schematic diagram of a glass via (TGV) in an arbitrary-layer high-density interconnect structure based on a glass substrate and PSPI. Figure 3 This is a schematic diagram of the completion of a single-sided layer addition structure in an arbitrary-layer high-density interconnect structure based on a glass substrate and PSPI, as provided in an embodiment of the present invention. Figure 4 This image shows a physical effect of the glass substrate process in an arbitrary-layer high-density interconnect structure based on a glass substrate and PSPI, as provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] In the accompanying drawings of this embodiment, the same or similar reference numerals correspond to the same or similar components. In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the accompanying drawings are only for illustrative purposes and should not be construed as limiting this patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0021] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes that element.

[0022] This invention provides an arbitrary-layer high-density interconnect structure based on a glass substrate and PSPI, such as... Figure 1 As shown, it includes: Glass core plate 1, wherein the glass core plate 1 has a plurality of glass through holes 11 (TGV). The layered structure 2 is respectively disposed on the first and second surfaces of the glass core plate 1; The added-layer structure 2 employs at least one photosensitive polyimide (PSPI) dielectric layer 21, and each PSPI dielectric layer 21 has micropores and conductive patterns formed therein; The conductive pattern is interconnected between the micropores and the glass vias 11 to form a high-density arbitrary layer interconnect structure.

[0023] This invention uses a glass core plate 1 with extremely high dimensional stability as a rigid core, which fundamentally avoids the problem of thermal expansion and contraction of organic substrates, thus providing a stable reference platform for multilayer high-precision wiring; at the same time, since the layer-addition structure 2 uses a PSPI dielectric layer 21 that can be patterned by photolithography, it is possible to fabricate micro-holes and fine lines with a precision far exceeding that of traditional lamination processes, thus achieving extremely high wiring density. In addition, since the PSPI dielectric layer 21 itself has the characteristics of low dielectric constant (Dk) and low loss factor, it provides an excellent channel environment for high-speed signal transmission, meeting the stringent requirements of AI / HPC chips for low latency and high bandwidth. Finally, since the glass core board 1 provides sufficient rigid support, the number of PSPI dielectric layers 21 on both sides can be designed asymmetrically.

[0024] In summary, this structure successfully combines the stability of the glass core board 1 with the high precision and performance of the PSPI process, achieving a breakthrough in "arbitrary layer interconnection" on the glass core board 1.

[0025] In some embodiments, the micropores in the PSPI dielectric layer 21 are formed by photolithography, and copper is electroplated inside the micropores to form vertical interconnects.

[0026] In some embodiments, the number of PSPI dielectric layers 21 on the first and second surfaces is asymmetrical.

[0027] In some embodiments, the surfaces of the first and second surfaces and the inner wall of the glass through-hole 11 have roughened surfaces that have undergone chemical roughening treatment.

[0028] In some embodiments, the aspect ratio of the glass through-hole 11 is greater than 5:1.

[0029] In some embodiments, the inner wall of the glass through-hole 11 is sequentially provided with an adhesion layer, a copper seed layer, and an electroplated copper filler layer.

[0030] This invention also discloses a method for fabricating an arbitrary-layer high-density interconnect structure based on a glass substrate and PSPI, the method comprising: S1. Prepare a glass core plate 1 with glass through-holes 11 (TGV); Specifically, S1.1: Substrate preparation: The glass substrate is precisely cut, ground and polished to achieve the target thickness (e.g. 100um) and the required surface roughness.

[0031] Because the glass core board 1 itself has extremely high planar dimensional stability and its coefficient of thermal expansion matches that of the silicon chip, it can effectively suppress its deformation during processing, thereby providing a reliable reference for multi-layer high-precision wiring. For example, alkali-free glass such as CorningEagleXG or AF32 can be selected.

[0032] S1.2: Ultrafast laser drilling: Using a femtosecond or picosecond laser system, high-precision drilling is performed according to the designed through-hole layout.

[0033] By optimizing the laser wavelength (e.g., 355nm), pulse energy, repetition frequency, and scanning strategy, blind holes or through holes with smooth walls, no microcracks, and a depth-to-width ratio greater than 5:1 are fabricated.

[0034] For example, the aspect ratio of the glass through-hole 11 is preferably 5:1, and the typical aperture value is 30-50μm.

[0035] S1.3: TGV metallization: a) Chemical roughening of the glass core plate 1: The first surface, the second surface and the hole wall surface of the glass core plate 1 and the glass through hole 11 are roughened by chemical etching of the glass with fluoride, so as to increase the roughness of the plate surface and the hole wall and overcome the separation problem caused by the smooth hole wall.

[0036] The surface roughness (Ra value) after chemical roughening is generally recommended to be controlled within the range of 0.1–0.3 μm, which can effectively increase surface roughness while avoiding excessive corrosion that could affect structural strength. Specific parameters need to be determined experimentally based on the glass type (such as soda-lime glass or borosilicate glass) and the etching solution composition (such as the HF / HCl mixing ratio).

[0037] To enhance adhesion while avoiding excessive corrosion that could affect structural strength, an acidic solution containing fluorides (such as HF or BHF) was used to chemically etch the first and second surfaces of the glass core plate 1 and the walls of the glass through-holes 11 (TGV). The concentration and temperature of the HF solution were precisely controlled to directly regulate the etching rate and surface uniformity, ensuring that the surface roughness (Ra value) after chemical roughening remained stable within the range of 0.1–0.3 μm. This effectively increased the roughness of the plate surface and the hole walls, enhancing the adhesion of the metal layer.

[0038] Secondly, in terms of environmental parameter control, the etching temperature is stabilized at 20–40℃, and temperature fluctuations must be strictly controlled within ±1℃ to avoid pattern deformation caused by uneven reaction rates. At the same time, the etching time must be accurate to the second according to the standards of industrial electronic products. Through precise control of time, metal layer separation due to insufficient etching or loss of structural strength due to excessive etching is avoided, ensuring that the substrate and the inner wall of the hole obtain ideal microstructure.

[0039] Finally, after roughening is completed, necessary post-processing is carried out. CO2 supercritical drying technology can be used to repair the roughened surface, aiming to repair microcracks that may be caused by chemical etching, further improve the overall quality and mechanical strength of the glass surface, and provide a solid interface foundation for subsequent metallization steps such as deposition of adhesion layer, copper seed layer and electroplating of solid copper.

[0040] b) Seed layer deposition: First, an adhesion layer is deposited on the borehole wall and the first and second surfaces by magnetron sputtering, followed by the deposition of a copper seed layer.

[0041] To ensure uniform coverage of the pore walls, bias sputtering or ionization physical vapor deposition techniques are used.

[0042] For example, the adhesion layer is made of Ti or Cr and has a thickness of about 50-100 nm; the copper seed layer has a thickness of about 200-500 nm.

[0043] c) Electroplating filling: Using the sputtered copper seed layer as the cathode, an acidic copper sulfate electroplating solution is used with additives to completely fill the holes from the bottom up with copper without any voids through a pulse or DC electroplating process.

[0044] For example, the additive may be an inhibitor, an accelerator, and / or a leveling agent.

[0045] S1.4: Surface planarization: Chemical mechanical polishing (CMP) process is used to remove excess copper and seed layer from the surface of glass core board 1, so that the copper pads are flush with the glass surface, forming a smooth and flat double-sided interconnect core board.

[0046] S2. A layering process is performed sequentially on the first side of the glass core plate 1 to form a multilayer PSPI dielectric layer 21 and conductive pattern. Specifically, the first layer is added on the first side by coating PSPI on the first side of the glass core plate 1, forming micro-holes (MVIA) and conductive patterns by photolithography (exposure and development), and forming the first layer of added circuitry by chemical copper plating. This design bypasses the commonly used lamination layering process in PCB manufacturing. Compared to traditional PCB lamination, where the thinnest PP layer is 50µm and the Dk is generally above 3.0, the PSPI dielectric layer 21, through optimized process parameters, allows for thickness control that can be adjusted according to the product's linewidth and microvia size, achieving a minimum thickness of less than 5µm and a Dk of around 2.5-2.8. This design can be used for higher-speed AIPCB requirements, ensuring stable expansion and contraction of the glass core board 1 and perfectly solving the expansion and contraction problem of traditional PCBs.

[0047] Furthermore, the first side is added to the Nth layer, and the above steps are repeated. New PSPI is coated on the previous PSPI dielectric layer 21, photolithography and metallization are performed to achieve multi-layer stacking of the first side.

[0048] Compared to traditional PCB lamination processes, where the number of pressure tests for PP is limited by material properties, PSPI can be stacked an unlimited number of times.

[0049] S3. Flip the glass core plate 1 and perform a layering process on the second side of the glass core plate 1 to form a multilayer PSPI dielectric layer 21 and conductive pattern. Specifically, the second layer is first added on the second side. PSPI is coated on the second side of the glass core board 1. The rotation speed and acceleration are optimized according to the structure of the second side (such as the distribution of TGV vias) to ensure the uniformity of PSPI at the orifices and edges, avoiding local over-thickness or under-thinness. Stepped temperature rise (e.g., 80℃→120℃→150℃) is used to reduce internal stress and improve interlayer adhesion. The exposure energy is adjusted according to the PSPI thickness and the light transmittance of the glass substrate to avoid overexposure leading to pattern distortion or underexposure leading to incomplete development. An alkaline developer (such as TMAH) is used and the concentration and temperature are controlled to ensure steep sidewalls of microvias and lines, reducing undercutting. Plasma activation or chemical roughening (such as dilute hydrofluoric acid treatment) is used to improve the surface roughness of PSPI and enhance the adhesion of the chemical copper layer. The ratio of copper sulfate, sulfuric acid and additives is optimized to ensure that the chemical copper layer is uniform and dense, reducing voids and cracks. Photolithography (exposure and development) forms microvias (MVIA) and conductive patterns, and chemical copper plating forms the first layer of added circuitry. This embodiment implements the following refined control over the exposure and development processes: 1. Exposing process details When performing patterned exposure of the PSPI dielectric layer, this invention employs multi-dimensional optimization measures to improve imaging quality: Compensation for imaging errors: Local corrections are made to the imaging characteristics of different areas of the glass substrate by adjusting correction parameters such as M, MR, and R to compensate for the systematic errors of the imaging system.

[0050] Optimize energy distribution: Based on the photosensitive characteristics of the selected PSPI photoresist, multiple wavelength light sources (such as ArF, i-line, etc.) are used for combined exposure to precisely optimize the energy distribution, thereby significantly improving the fidelity of micro-holes and fine line patterns.

[0051] Real-time alignment correction: Using a dynamic alignment system, the positional deviation between the existing pattern at the bottom layer and the current mask is detected in real time, and the alignment parameters are dynamically adjusted accordingly to ensure that the interlayer alignment accuracy meets the requirements of high-density interconnection.

[0052] Improving photoresist stability: After exposure, the temperature and time of the photoresist baking (PEB) are precisely adjusted according to the physicochemical properties of the photoresist to enhance the structural stability of the photoresist and reduce linewidth fluctuations caused by the standing wave effect.

[0053] 2. Development process details To ensure the clarity of high aspect ratio micro-vias and fine line grooves, the following precision control methods were employed during the development process: Fine-tuning of the formula: The concentration and temperature of the developer (such as TMAH solution) are flexibly adjusted according to the type of photoresist and the aspect ratio of the target structure, and the dilution ratio is strictly controlled.

[0054] Segmented development control: For high aspect ratio structures, segmented or intermittent development processes are used to effectively prevent the collapse of the sidewalls of microstructures and ensure that there is no photoresist residue at the bottom of the hole and the bottom of the tank.

[0055] Optimize edge roughness: After development, post-baking process is used to improve the etching resistance of the photoresist; at the same time, the surfactant ratio in the developer is optimized to reduce line edge roughness (LER) and improve wiring quality.

[0056] Real-time monitoring and closed-loop feedback: Combined with an automated optical inspection (AOI) system, the development quality is monitored in real time. Once a development defect is detected, the data is immediately fed back to the exposure or development unit for parameter compensation and adjustment.

[0057] This design bypasses the commonly used lamination layering process in PCB manufacturing. Compared to traditional PCB lamination, where the thinnest PP layer is 50µm and the depth-to-weight (Dk) is generally above 3.0, the PSPI dielectric layer, through optimized process parameters, allows for thickness control that can be adjusted according to the product's linewidth and microvia size, achieving a minimum thickness of less than 5µm and a Dk of around 2.5-2.8. This design can be used for higher-speed AIPCB applications, ensuring stable expansion and contraction of the glass core board 1 and perfectly solving the expansion and contraction problems of traditional PCBs.

[0058] Furthermore, the second side is added for the Nth time, and the above steps are repeated. New PSPI is coated on the previous PSPI dielectric layer 21, and then photolithography and metallization are performed to achieve multi-layer stacking on the second side.

[0059] Compared to traditional PCB lamination processes, which generally require double-sided symmetry to avoid board warping and affecting SMT processes, the PSPI process eliminates the need for symmetrical design on both sides.

[0060] S4. After all the added-layer structures 2 are completed, laser ablation is performed to open windows, expose the pads, and prepare the welding bumps.

[0061] Specifically, after all the layers are added, a laser is used to ablate windows on the top PSPI dielectric layer 21 to expose the underlying pads, and then solder bumps (such as solder balls) are prepared. The solder balls can be directly assembled with ICs / BGAs.

[0062] This invention replaces the traditional high-temperature and high-pressure lamination process with a PSPI coating-photolithography-electroplating process that does not require high pressure. This not only simplifies the process steps, but more importantly, it eliminates the internal stress and board warping problems caused by the mismatch between high pressure and material CTE from the source. At the same time, since this method completes all the layering on one side of the glass core plate 1 first, and then flips it to perform layering on the other side, the process stress on each side is applied independently and is ultimately constrained by the rigid glass substrate. Therefore, it can perfectly support asymmetric stacked design and break through the constraints of traditional symmetric design. Furthermore, since the thickness of PSPI can be precisely controlled through spin coating parameters, it is possible to achieve ultra-thin dielectric layers of sub-10 micrometers (or even <5μm), which is unattainable by traditional PP materials, directly resulting in higher interconnect density and better high-frequency performance.

[0063] In summary, this invention provides a reliable manufacturing path for achieving high-yield, high-density glass-based arbitrary layer interconnects through the innovative combination of a low-stress, high-precision layer-addition process and a high-stability substrate.

[0064] Example 1 This embodiment provides a method for fabricating an arbitrary-layer interconnect glass substrate for high-end AI chip packaging, specifically including the following steps: S1: Fabrication of a glass core plate with TGV 1 S1.1: Substrate preparation and laser drilling Corning Eagle XG alkali-free glass with a thickness of 100μm was selected as the substrate.

[0065] First, using a picosecond ultraviolet laser (wavelength 355nm), holes were drilled on a glass substrate according to a predetermined layout to create blind holes with a diameter of 40μm and an aspect ratio of approximately 10:1. The laser parameters were optimized to ensure smooth hole walls and no microcracks.

[0066] S1.2: TGV metallization a) Chemical roughening: The drilled glass substrate is immersed in a dilute hydrofluoric acid solution for brief etching, which chemically roughens the inner wall of the hole and the surface of the board, significantly increasing the surface roughness to enhance the adhesion of the metal layer.

[0067] b) Seed layer deposition: The roughened substrate is placed in a magnetron sputtering apparatus. First, a titanium (Ti) layer with a thickness of about 80 nm is deposited as an adhesion layer, and then a copper (Cu) layer with a thickness of about 500 nm is deposited on it as a seed layer.

[0068] c) Electroplating to fill the holes: An electroplating process is used to completely fill the TGV vias with solid copper using an acidic copper sulfate electroplating solution, forming a reliable vertical interconnect structure.

[0069] S2: First layer added to the first side S2.1: PSPI Coating: On the first side of the glass core board after TGV metallization, a layer of photosensitive polyimide (PSPI) liquid is coated by spin coating. By controlling the rotation speed and solid content, the thickness of the cured PSPI dielectric layer 21 is approximately 8 μm.

[0070] S2.2: Photolithography Patterning: The coated PSPI is pre-baked (soft bake), and then exposed to ultraviolet light using a photomask designed with microvias (MVIAs) and circuit patterns. After exposure, development is performed to form microvias (MVIAs) with a diameter of approximately 15 μm and circuit pattern grooves with a linewidth / spacing of 10 μm / 10 μm in a single step.

[0071] S2.3: Forming Circuits and Interconnects: First, chemical copper plating is performed to form a thin layer of chemical copper on the patterned PSPI surface and within the grooves. Then, patterned electroplating copper is performed to fill the circuit grooves and microvias, forming the first layer of conductive circuits and vertical interconnects. Finally, the surface chemical copper layer is removed (flash etching) to make the circuit flush with the dielectric layer surface or maintain an appropriate protrusion.

[0072] S3: Multiple layers added to the first surface On the first side of the substrate after the first layering is completed, step S2 (i.e., S2.1 to S2.3) is repeated twice. For example, the second layering prepares a 7 μm thick PSPI layer and finer lines; the third layering prepares a 6 μm thick PSPI layer. Thus, a total of 3 layers of PSPI dielectric layers and 3 layers of conductive lines are constructed on the first side of the glass core board.

[0073] S4: Flip and Add Second Layer Flip the substrate 180 degrees and fix it with a special clamp to ensure that the substrate is flat. Repeat the layering process of steps S2 and S3 on the second side of the glass core plate.

[0074] Depending on the wiring requirements, the second side can be constructed as a 3-layer structure symmetrical to the first side, or an asymmetrical 2-layer structure.

[0075] In this embodiment, two PSPI dielectric layers and conductive lines were constructed on the second side, successfully achieving asymmetric stacking, and the substrate had no visible warping.

[0076] S5: Laser windowing and bump fabrication a) Laser windowing: After all the add-on structures are completed, a CO2 laser is used to selectively ablate the outermost PSPI dielectric layer to create a window and expose the top copper pads.

[0077] b) Ball placement: Solder paste is printed on exposed pads and then formed into solder balls through a reflow soldering process, which serve as bumps for soldering to external chips (such as AI processors).

[0078] like Figure 4 The image shown is a side view of the actual glass substrate, clearly displaying the structure of the TGV vias, PSPI dielectric layer, conductive lines, and solder ball bumps. 1. TGV through-hole process data Aperture and aspect ratio: Aperture 40μm, aspect ratio 10:1, hole wall roughness (Ra) ≤0.2μm.

[0079] Metallization adhesion: 80nm titanium adhesion layer, 500nm copper seed layer, and electroplated copper filling density ≥99.9%.

[0080] 2. Data on the added-floor structure PSPI dielectric layer thickness: 8μm for the first time, 7μm for the second time, and 6μm for the third time, with a thickness deviation of ±0.5μm.

[0081] Circuit pattern accuracy: line width / line spacing 10μm / 10μm, micro-hole diameter 15μm, position deviation ±1μm.

[0082] 3. Laser windowing and bulb planting data Window opening size deviation: ±3μm, edge roughness (Ra) ≤0.3μm.

[0083] Solder ball diameter deviation: ±5μm, soldering strength ≥50MPa, void ratio <5%.

[0084] III. Verification of Process Effect TGV through-holes: The smoothness of the hole walls was observed by SEM, and the filling density was detected by X-ray.

[0085] Add-layer structure: The accuracy of the circuit pattern is observed by optical microscope or SEM, and the thickness is measured by step gauge.

[0086] Laser windowing and ball placement: The quality of the window edge is observed using an optical microscope or SEM, and the internal void ratio of the solder ball is detected by X-ray.

[0087] The above data and physical images can fully verify the effectiveness of the process.

[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A high density interconnect structure based on glass substrate and PSPI arbitrary layer, characterized in that, include: A glass core plate having multiple glass through-holes (TGV). The added-layer structure is respectively disposed on the first and second surfaces of the glass core plate; The added-layer structure employs at least one photosensitive polyimide (PSPI) dielectric layer, with micropores and conductive patterns formed in each PSPI dielectric layer; The conductive pattern is interconnected between the micropores and the glass via layers to form a high-density arbitrary layer interconnect structure.

2. The glass substrate and PSPI-based any layer high density interconnect structure of claim 1, wherein, The micropores in the PSPI dielectric layer are formed by photolithography, and copper is electroplated inside the micropores to form vertical interconnects.

3. The glass substrate and PSPI-based any layer high density interconnect structure of claim 1, wherein, The number of PSPI dielectric layers on the first and second surfaces is asymmetrical.

4. The glass substrate and PSPI-based any layer high density interconnect structure of claim 1, wherein, The surfaces of the first and second surfaces, as well as the inner wall of the glass through-hole, have roughened surfaces that have undergone chemical roughening treatment.

5. The glass substrate and PSPI-based any layer high density interconnect structure of claim 1, wherein, The aspect ratio of the glass through-hole is greater than 5:

1.

6. The glass substrate and PSPI-based any layer high density interconnect structure of claim 1 or 5, wherein, The inner wall of the glass through-hole is sequentially provided with an adhesion layer, a copper seed layer, and an electroplated copper filler layer.

7. A method of fabricating a high-density interconnect structure based on a glass substrate and any layer of PSPI according to any one of claims 1-6, characterized in that, The method includes: Fabrication of a glass core plate with through-glass vias (TGV); A layering process is performed sequentially on the first side of the glass core plate to form multiple PSPI dielectric layers and conductive patterns. The glass core plate is flipped over, and a layering process is performed sequentially on the second side of the glass core plate to form multiple PSPI dielectric layers and conductive patterns. After all the added-layer structures are completed, laser ablation is performed to open windows, expose the pads, and prepare the solder bumps.

8. The method of claim 7, wherein the method further comprises: The preparation of the glass core plate with glass through-hole (TGV) further includes: roughening the first surface, the second surface and the inner wall surface of the glass core plate and the glass through-hole by chemical etching with fluoride.

9. The method of claim 7, wherein the method further comprises: The process of sequentially performing a layer-addition process on the first surface of the glass core plate to form multiple PSPI dielectric layers and conductive patterns specifically includes: A photosensitive polyimide (PSPI) layer is coated on the first surface of the glass core plate as a first dielectric layer; The first dielectric layer is exposed and developed to simultaneously form grooves for micropores and conductive patterns. By chemically plating copper and patterned electroplating copper, a first layer of conductive pattern is formed in the groove of the conductive pattern and the micropores are filled at the same time to form a vertical interconnect.

10. The method of making a glass substrate and PSPI-based any layer high density interconnect structure of claim 7, wherein, The step of flipping the glass core plate and performing a layering process on the second side of the glass core plate to form multiple PSPI dielectric layers and conductive patterns specifically includes: coating a layer of photosensitive polyimide (PSPI) on the second side of the glass core plate as the first dielectric layer. The first dielectric layer is exposed and developed to simultaneously form grooves for micropores and conductive patterns. By chemically plating copper and patterned electroplating copper, a first layer of conductive pattern is formed in the groove of the conductive pattern and the micropores are filled at the same time to form a vertical interconnect.

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