A packaging board and a packaging structure

Abstract

This invention provides a packaging carrier and packaging structure, wherein the packaging carrier includes a thermal insulation structure, and a core layer, a building block layer, and a solder mask layer stacked sequentially; wherein a redistribution layer in the building block layer extends to the surface of the building block layer away from the core layer and is electrically connected to a first pad and a second pad in the solder mask layer; the solder mask layer includes a first region and a second region disposed adjacent to each other; in the first region, the first pad is used for electrical connection with a first chip, and in the second region, the second pad is used for electrical connection with a second chip; the thermal insulation structure is located between the first region and the second region, and a portion of the thermal insulation structure is filled in a groove disposed through the solder mask layer; the orthographic projection of the thermal insulation structure on the core layer does not overlap with the orthographic projection of the redistribution layer on the core layer.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and in particular to a packaging carrier and packaging structure. Background Technology

[0002] With the continuous improvement of chip integration, multi-chip heterogeneous integrated packaging technology has become one of the core technologies to meet the needs of high-performance chips. Among them, glass packaging substrates are widely used in multi-chip packaging systems due to their advantages such as good dimensional stability, high flatness, high wiring density, and low signal loss.

[0003] In 2D packaging systems using glass-based substrates, multiple functional chips are packaged on the same building block plane. The heat generated by high-power logic chips is far greater than that generated by temperature-sensitive memory chips, and this heat is laterally conducted to adjacent chips within the same layer. For 2.5D packaging structures with embedded interconnect silicon bridges, the heat is also transferred vertically to other chips in the upper and lower layers. Inter-chip thermal crosstalk affects the normal operation of various functional chips, significantly reducing chip performance and reliability. Suppressing thermal crosstalk has become an urgent technical problem to be solved. Summary of the Invention

[0004] This invention provides a packaging carrier and packaging structure for effectively suppressing thermal crosstalk.

[0005] In a first aspect, embodiments of the present invention provide a packaging carrier board, comprising: Thermal insulation structure, and a core layer, a structural layer and a weld barrier layer stacked in sequence; The redistribution layer in the building layer extends to the surface of the building layer away from the core layer and is electrically connected to the first pad and the second pad in the solder mask layer, respectively. The solder mask layer includes a first region and a second region disposed adjacent to each other. In the first region, the first pad is used to electrically connect to a first chip, and in the second region, the second pad is used to electrically connect to a second chip. The heat insulation structure is located between the first region and the second region, and a portion of the heat insulation structure is filled in a groove that penetrates the solder resist layer; the orthographic projection of the heat insulation structure on the core layer does not overlap with the orthographic projection of the redistribution layer on the core layer.

[0006] In one possible implementation, the building layer further includes an add-on dielectric layer, the redistribution layer being disposed through the add-on dielectric layer; the groove also extends along the add-on dielectric layer toward a side away from the solder mask layer.

[0007] In one possible implementation, an embedded interconnect silicon bridge is further included in the add-on dielectric layer, the embedded interconnect silicon bridge being located between the first region and the second region and electrically connected to the redistribution layer; the thermal insulation structure is located on the side of the embedded interconnect silicon bridge away from the core layer and completely covers the embedded interconnect silicon bridge.

[0008] In one possible implementation, the thermal insulation structure includes a first portion extending along a first direction, and the extension length of the first portion along the first direction is greater than the maximum extension length of the corresponding sides of the first region and the second region; the orthographic projections of the first region and the second region on the core layer do not overlap with the orthographic projection of the first portion on the core layer, and the first direction is a direction perpendicular to the center line of the first region and the second region.

[0009] In one possible implementation, the thermal insulation structure further includes a second portion located on the side of the first portion closer to the core layer, the second portion being connected to the first portion and extending along a second direction, the second direction being a direction parallel to the center line of the first region and the second region; the orthographic projection of the first portion on the core layer overlaps with the orthographic projection of the second portion on the core layer, and the extension length of the first portion along the second direction is less than the extension length of the second portion along the second direction; the extension length of the first portion along the first direction is greater than the extension length of the second portion along the first direction.

[0010] In one possible implementation, the orthographic projection of the first region onto the core layer overlaps with the orthographic projection of the second part onto the core layer; the orthographic projection of the second region onto the core layer overlaps with the orthographic projection of the second part onto the core layer.

[0011] In one possible implementation, a plurality of first through holes are provided at intervals along the thickness direction of the thermal insulation structure.

[0012] In one possible implementation, each first via is either a blind via or a through via.

[0013] In one possible implementation, the material of the thermal insulation structure is at least one of porous polyimide, silicon-based aerogel, carbon-based aerogel, and titanium-based aerogel.

[0014] In one possible implementation, it further includes a plurality of second vias formed along the thickness direction of the core layer, each second via being filled with a conductive material; the packaging substrate also includes another wiring layer located on the side of the core layer away from the redistribution layer; the conductive material is electrically connected to the redistribution layer and the other wiring layer respectively; the orthographic projections of the conductive material and the other wiring layer on the core layer do not overlap with the orthographic projections of the thermal insulation structure on the core layer.

[0015] Secondly, embodiments of the present invention also provide a packaging structure, including: Packaging carrier as described in any of the above; The first chip is electrically connected to the first pad on the packaging substrate; The second chip is electrically connected to the second pad on the packaging substrate.

[0016] In one possible implementation, the first chip is a high-power chip, and the second chip is a temperature-sensitive chip.

[0017] In one possible implementation, the high-power chip is one of a logic chip, a power management chip, or a high-bandwidth memory controller; and the temperature-sensitive chip is one of a clock chip, a memory chip, or a radio frequency chip.

[0018] The beneficial effects of this invention are as follows: This invention provides a packaging carrier and packaging structure. The packaging carrier includes a heat insulation structure and a core layer, a building block layer, and a solder mask layer stacked sequentially. A redistribution layer in the building block layer extends to the surface of the building block layer away from the core layer and is electrically connected to a first pad and a second pad in the solder mask layer. The solder mask layer includes a first region and a second region disposed adjacent to each other. In the first region, the first pad is used for electrical connection with a first chip, and in the second region, the second pad is used for electrical connection with a second chip. This provides a guarantee for the subsequent electrical connection between the packaging carrier and the required chip.

[0019] Furthermore, the thermal insulation structure is located between the first and second regions, and a portion of the thermal insulation structure fills a groove that penetrates the solder mask layer; the orthographic projection of the thermal insulation structure onto the core layer does not overlap with the orthographic projection of the redistribution layer onto the core layer. In this way, without affecting the chips required for electrical connections on the packaging substrate, the thermal insulation structure effectively prevents thermal crosstalk between chips, thereby improving the performance of the packaging substrate. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a packaging structure based on a glass encapsulation substrate in related technologies; Figure 2This is a schematic diagram of a heterogeneous integrated packaging system that uses embedded interconnect silicon bridges in related technologies. Figure 3 This is a top view schematic diagram of one type of packaging carrier provided in an embodiment of the present invention; Figure 4 For along Figure 3 A schematic diagram of one type of cross-sectional structure in the direction shown in MM; Figure 5 This is a top view schematic diagram of one type of packaging carrier provided in an embodiment of the present invention; Figure 6 For along Figure 5 A schematic diagram of one type of cross-sectional structure in the direction shown in the middle NN; Figure 7 This is a top view schematic diagram of one type of packaging carrier provided in an embodiment of the present invention; Figure 8 For along Figure 7 A schematic diagram of one type of cross-sectional structure in the direction shown in the middle OO; Figure 9 for Figure 7 A top view schematic diagram of one type of thermal insulation structure; Figure 10 For preparation Figure 4 The diagram shows one of the process flow diagrams for the packaging substrate. Figure 11 This is a schematic diagram of one type of packaging structure provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of one type of packaging structure provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of one type of packaging structure provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0024] In related technologies, such as Figure 1 The diagram shows a packaging structure based on a glass-based substrate. In this structure, the high-density interconnect structure easily forms in-plane heat conduction paths, exacerbating thermal crosstalk between chips. In particular, when using... Figure 2 When the embedded multi-die interconnect bridge (EMIB) is used in a heterogeneous integrated packaging system, the silicon bridge itself has high thermal conductivity, and the thermal coupling between chips and silicon bridges, and between chips, is tighter, making thermal crosstalk problems more prominent.

[0025] Therefore, embodiments of the present invention provide a packaging carrier and packaging structure for effectively suppressing thermal crosstalk.

[0026] Combination Figure 3 and Figure 4 As shown, where, Figure 3 This is a top view schematic diagram of one of the packaging carrier boards provided in an embodiment of the present invention. Figure 4 For along Figure 3 A schematic diagram of one cross-sectional structure along the direction shown in the diagram; specifically, the packaging substrate includes: The thermal insulation structure 10, and the core layer 20, the structural layer 30 and the weld resistance layer 40 are stacked in sequence; The redistribution layer 31 in the building layer 30 extends to the surface of the building layer 30 away from the core layer 20 and is electrically connected to the first pad 50 and the second pad 60 in the solder mask layer 40, respectively. The solder mask layer 40 includes a first region A and a second region B disposed adjacent to each other. In the first region A, the first pad 50 is used to electrically connect to a first chip, and in the second region B, the second pad 60 is used to electrically connect to a second chip. The heat insulation structure 10 is located between the first region A and the second region B, and a portion of the heat insulation structure 10 is filled in the groove 70 that penetrates the solder resist layer 40; the orthographic projection of the heat insulation structure 10 on the core layer 20 does not overlap with the orthographic projection of the redistribution layer 31 on the core layer 20.

[0027] In specific implementation, the encapsulation carrier provided in this embodiment of the invention includes a heat insulation structure 10, and a core layer 20, a building layer 30, and a solder resist layer 40 stacked sequentially. For example, the core layer 20 is made of glass, and correspondingly, the encapsulation carrier is a glass encapsulation carrier. The redistribution layer 31 (RDL) in the building layer 30 extends to the surface of the building layer 30 away from the core layer 20 and is electrically connected to the first pad 50 and the second pad 60 in the solder resist layer 40, respectively. For example, the solder resist layer 40 can be a liquid photosensitive ink, a thermosetting ink, etc. For example, the solder resist layer 40 can also be a dry film solder resist, whose main material system can be an epoxy resin system, an acrylate system, a polyimide system, and a benzocyclobutene (BCB) system. In actual preparation, photoinitiators, curing agents, inorganic fillers, and additives can be combined to form a composite solder resist material system according to process requirements. Of course, the material for preparing the solder resist layer 40 can also be selected according to actual application needs, and is not limited here. For example, the first pad 50 can be one, or two or more, without limitation. Similarly, the second pad 60 can be one, or two or more, without limitation. For example, the thickness of the solder mask layer 40 ranges from 15μm to 30μm. This effectively protects the redistribution layer 31. In practical applications, windows can be opened in the chip mounting area corresponding to the solder mask layer 40 to expose the underlying pads. This provides protection for subsequent packaging substrate and related chip mounting.

[0028] Furthermore, the solder mask layer 40 includes a first region A and a second region B disposed adjacent to each other; wherein the first region A and the second region B are spaced apart from each other. In the first region A, a first pad 50 is used for electrical connection with the first chip; in the second region B, a second pad 60 is used for electrical connection with the second chip. Accordingly, the first region A is the area of ​​the package carrier board for mounting the first chip; the second region B is the area of ​​the package carrier board for mounting the second chip. For example, the first chip is a high-power chip. For example, the high-power chip is one of a logic chip, a power management chip, or a high-bandwidth memory controller. Of course, the specific type of the first chip can also be selected according to the actual application requirements. For example, the second chip is a temperature-sensitive chip. This temperature-sensitive chip is extremely susceptible to temperature effects. For example, the temperature-sensitive chip is one of a clock chip, a memory chip, or an RF chip. Of course, the specific type of the second chip can also be selected according to the actual application requirements. In practical applications, if a high-power chip and a temperature-sensitive chip are placed next to each other, the high-power chip is very likely to generate a lot of heat during operation. If the heat is not dissipated in time, it can easily affect the adjacent temperature-sensitive chip, causing thermal crosstalk and affecting the performance of the package structure.

[0029] Furthermore, the heat insulation structure 10 is located between the first region A and the second region B, and a portion of the heat insulation structure 10 fills the groove 70 that penetrates the solder resist layer 40; for example, the thermal conductivity of the heat insulation structure 10 ranges from 0.02 W / (m·K) to 0.05 W / (m·K). This effectively isolates heat from the first and second chips, avoiding thermal crosstalk between the chips, improving the performance of the packaging substrate, and ensuring the mechanical strength of the packaging substrate at the corresponding groove 70. In addition, the orthographic projection of the heat insulation structure 10 onto the core layer 20 does not overlap with the orthographic projection of the redistribution layer 31 onto the core layer 20. This ensures both the heat insulation performance of the packaging substrate and the electrical connection between the packaging substrate and the chip.

[0030] In this embodiment of the invention, the building layer 30 further includes an augmentation dielectric layer 32, and the redistribution layer 31 is disposed through the augmentation dielectric layer 32; the groove 70 is also disposed along the augmentation dielectric layer 32, on the side away from the solder resist layer 40.

[0031] In the specific implementation process, it is still combined with Figure 4As shown, the structural layer 30 also includes an additive dielectric layer 32, through which the redistribution layer 31 is disposed. For example, the material of the additive dielectric layer 32 can be BT resin, ABF resin, etc. For example, when the material of the additive dielectric layer 32 is ABF resin, the thermal conductivity of the additive dielectric layer 32 is greater than 0.2 W / (m·K). Thus, in this embodiment of the invention, the heat insulation structure 10 disposed in the groove 70 provides better heat insulation compared to not having the groove 70 or not having the heat insulation structure 10. Of course, in practical applications, the material of the additive dielectric layer 32 can be selected as needed, and is not limited here. In the actual preparation process, a multilayer lamination process can be used to form an additive dielectric layer 32 composed of multiple patterned redistribution layers 31 and multiple additive materials on the core layer 20. That is, the additive preparation is carried out by alternating layers of redistribution layer 31 and layer of additive material. The specific preparation process can be implemented with reference to relevant technologies, and will not be detailed here. For example, the thickness of each redistribution layer 31 can range from 10 μm to 20 μm, and the thickness of each add-on material layer can range from 20 μm to 40 μm. For example, the number of add-on dielectric layers 32 can range from 3 to 10, and is not limited here.

[0032] Furthermore, the redistribution layer 31 extends through the build-up dielectric layer 32, thereby ensuring the electrical connection between the corresponding chip and the package substrate. In one exemplary embodiment, the groove 70 also extends along the build-up dielectric layer 32 towards the side away from the solder mask layer 40. This improves the heat insulation effect of the heat insulation structure 10. Still in conjunction with... Figure 4 In the exemplary embodiment shown, the groove 70 penetrates not only the solder mask layer 40 but also the add-on dielectric layer 32. Exemplarily, the thickness of the add-on dielectric layer 32 ranges from 100 μm to 600 μm. Of course, the specific thickness of the add-on dielectric layer 32 can be set according to actual application needs, and is not limited here.

[0033] In this embodiment of the invention, the packaging substrate further includes an embedded interconnect silicon bridge 80 located in the add-on dielectric layer 32. The embedded interconnect silicon bridge 80 is located between the first region A and the second region B and is electrically connected to the redistribution layer 31. The thermal insulation structure 10 is located on the side of the embedded interconnect silicon bridge 80 away from the core layer 20 and completely covers the embedded interconnect silicon bridge 80.

[0034] In one exemplary embodiment, combined with Figure 5 and Figure 6 As shown, where, Figure 5 This is a top view schematic diagram of one type of packaging carrier board structure. Figure 6 For along Figure 5The diagram shows one possible cross-sectional structure along the NN direction. Specifically, the package substrate also includes an embedded interconnect silicon bridge 80 (EMIB) located in the build-up dielectric layer 32; the embedded interconnect silicon bridge 80 is located between the first region A and the second region B, and is electrically connected to the redistribution layer 31. In this way, the embedded interconnect silicon bridge 80 ensures high bandwidth and high density interconnection. Furthermore, the thermal insulation structure 10 is located on the side of the embedded interconnect silicon bridge 80 away from the core layer 20, and completely covers the embedded interconnect silicon bridge 80. In this way, while ensuring high bandwidth and high density interconnection, it also isolates heat from the related chips to a certain extent, as well as heat from the embedded interconnect silicon bridge 80, thereby effectively avoiding thermal crosstalk.

[0035] In this embodiment of the invention, the heat insulation structure 10 can be set in the following ways, but is not limited to these ways.

[0036] In one exemplary embodiment, the heat insulation structure 10 includes a first portion 11 extending along a first direction, and the extension length of the first portion 11 along the first direction is greater than the maximum extension length of the corresponding side of the first region A and the second region B; the orthographic projections of the first region A and the second region B on the core layer 20 do not overlap with the orthographic projections of the first portion 11 on the core layer 20, and the first direction is a direction perpendicular to the center line of the first region A and the second region B.

[0037] Still combined Figure 4 and Figure 6In the exemplary embodiment shown, the heat insulation structure 10 includes a first portion 11 extending along a first direction, which is perpendicular to the center line of the first region A and the second region B, as indicated by arrow X in the figure. The extension length of the first portion 11 along the first direction is greater than the maximum extension length of the corresponding side of the first region A and the second region B. Let L represent the extension length of the first portion 11 along the first direction, L1 represent the extension length of the corresponding side of the first region A, and L2 represent the extension length of the corresponding side of the second region B, satisfying the following formula: L > L1, and L > L2. For example, the extension length of the first portion 11 along the first direction extends by 0.5mm to 2mm compared to the maximum extension length of the corresponding side of the first region A and the second region B. This effectively isolates heat from the first region A and the second region B, ensuring effective prevention of thermal crosstalk between chips. For example, along the second direction, the distance between the edge of the first portion 11 and the edge of the first region A on the same side is greater than 100 μm, and the distance between the edge of the first portion 11 and the edge of the second region B on the same side is greater than 100 μm. In this way, the influence of the heat insulation structure 10 of the set region on the redistribution layer 31 of the corresponding region is avoided, and the electrical connection between the subsequent packaging substrate and the chip is guaranteed.

[0038] Furthermore, the orthographic projections of the first region A and the second region B onto the core layer 20 do not overlap with the orthographic projection of the first part 11 onto the core layer 20. In this way, while ensuring the heat insulation effect of the heat insulation structure 10, the influence of the heat insulation structure 10 on the redistribution layer 31 for electrical connection between the relevant regions and the chip is effectively avoided, thus improving the performance of the packaging substrate.

[0039] In one exemplary embodiment, the heat insulation structure 10 further includes a second portion 12 located on the side of the first portion 11 near the core layer 20. The second portion 12 is connected to the first portion 11 and extends along a second direction, which is a direction parallel to the center line of the first region A and the second region B. The orthographic projection of the first portion 11 on the core layer 20 overlaps with the orthographic projection of the second portion 12 on the core layer 20. The extension length of the first portion 11 along the second direction is less than the extension length of the second portion 12 along the second direction. The extension length of the first portion 11 along the first direction is greater than the extension length of the second portion 12 along the first direction.

[0040] Still combined Figure 5 and Figure 6As shown, the thermal insulation structure 10 also includes a second part 12 located on the side of the first part 11 near the core layer 20. The second part 12 is connected to the first part 11 and extends along a second direction. The second part 12 is parallel to the center line of the first region A and the second region B, as shown by arrow Y in the figure. Exemplarily, the first part 11 and the second part 12 are integrally formed. Furthermore, the orthographic projection of the first part 11 onto the core layer 20 overlaps with the orthographic projection of the second part 12 onto the core layer 20, and the extension length of the first part 11 along the second direction is less than the extension length of the second part 12 along the second direction. Exemplarily, W1 represents the extension length of the first part 11 along the second direction, and W2 represents the extension length of the second part 12 along the second direction, with the relationship satisfying the formula: W1 < W2. Moreover, the extension length of the first part 11 along the first direction is greater than the extension length of the second part 12 along the first direction. For example, L represents the extension length of the first portion 11 along the first direction, and D represents the extension length of the second portion 12 along the first direction. The relationship between the two satisfies the formula: L > D. In this way, while taking into account the wiring space on the surface of the package substrate, heat from the first chip and the second chip is effectively isolated, avoiding thermal crosstalk between the first chip and the embedded interconnect silicon bridge 80, as well as thermal crosstalk between the second chip and the embedded interconnect silicon bridge 80, thereby improving the performance of the package substrate.

[0041] In one exemplary embodiment, the extension length of the first portion 11 along the first direction can be set to be equal to the extension length of the second portion 12 along the second direction, provided that W1 < W2. This improves the heat insulation effect of the heat insulation structure 10. Unless otherwise specified, "equal to" here can mean approximately equal or roughly equal, and is not limited herein.

[0042] In this embodiment of the invention, the orthographic projection of the first region A onto the core layer 20 overlaps with the orthographic projection of the second part 12 onto the core layer 20; the orthographic projection of the second region B onto the core layer 20 overlaps with the orthographic projection of the second part 12 onto the core layer 20.

[0043] Still combined Figure 5 and Figure 6As shown, the orthographic projection of the first region A onto the core layer 20 overlaps with the orthographic projection of the second part 12 onto the core layer 20. In this way, the second part 12 in the heat insulation structure 10 effectively prevents thermal crosstalk between the first chip and the embedded interconnect silicon bridge 80. Furthermore, the orthographic projection of the second region B onto the core layer 20 overlaps with the orthographic projection of the second part 12 onto the core layer 20. In this way, the second part 12 in the heat insulation structure 10 effectively prevents thermal crosstalk between the second chip and the embedded interconnect silicon bridge 80.

[0044] In this embodiment of the invention, a plurality of first through holes H1 are provided at intervals along the thickness direction of the heat insulation structure 10.

[0045] Combination Figures 7 to 9 As shown, where, Figure 7 This is a top view schematic diagram of one type of packaging carrier board structure. Figure 8 For along Figure 7 A schematic diagram of one type of cross-sectional structure in the direction shown in the diagram. Figure 9 for Figure 7 This is a top view schematic diagram of one type of thermal insulation structure 10. Specifically, a plurality of first through holes H1 are spaced apart along the thickness direction of the thermal insulation structure 10. For example, the plurality of first through holes H1 can be two, three, or more, without limitation. Each first through hole H1 can be a blind hole or a through hole. For example, the plurality of first through holes H1 can be uniformly arranged or non-uniformly arranged, without limitation. For example, the diameter of each first through hole H1 ranges from 8μm to 30μm. Of course, the arrangement of the plurality of first through holes H1 and the specific diameter of each first through hole H1 can be set according to actual application needs, without limitation. It should be noted that the more first through holes H1 arranged per unit area, the better the thermal insulation effect of the thermal insulation structure 10.

[0046] In this embodiment of the invention, the material of the heat insulation structure 10 is at least one of porous polyimide, silicon-based aerogel, carbon-based aerogel, and titanium-based aerogel.

[0047] In specific implementation, the material of the thermal insulation structure 10 can be at least one of porous polyimide, silicon-based aerogel, carbon-based aerogel, and titanium-based aerogel. For example, at least one material can be used, or it can be two or more, without limitation. For example, representative materials of the aerogel system can be one or more of SiO2: aerogel, TiO2: aerogel, carbon nanotube aerogel, and RF phenolic-resorcinol resin aerogel. For example, it can also be a SiO2-TiO2: composite aerogel. This ensures the low thermal conductivity of the thermal insulation structure 10, thereby improving the thermal insulation effect of the thermal insulation structure 10 and avoiding thermal crosstalk. Of course, the specific material of the thermal insulation structure 10 can be selected according to the actual application needs, which will not be detailed here.

[0048] It should be noted that in a non-convection environment, i.e., a static state, the thermal conductivity of air is 0.026 W / (m·K); under conditions of thermal convection, the thermal conductivity of air increases. In specific implementations, if only the groove 70 is created without filling it with the thermal insulation structure 10, the effective thermal conductivity range of the encapsulation air groove corresponding to the groove 70 is 0.05 W / (m·K) to 0.1 W / (m·K). In practical applications, although the thermal conductivity of air is low in a static state, a pure gas layer is not only prone to thermal convection, but the design of the encapsulation air groove also has poor resistance to deformation of the bridge area. In this embodiment of the invention, the thermal insulation structure 10 not only has a low thermal conductivity, but also a relatively stable thermal conductivity; furthermore, compared with the encapsulation air groove, the solid porous structure within the thermal insulation structure 10 can not only effectively suppress gas convection, but also has strong resistance to deformation. In this way, the encapsulation carrier plate has high mechanical strength and reliability.

[0049] In this embodiment of the invention, the packaging carrier further includes a plurality of second vias H2 formed along the thickness direction of the core layer 20, and each second via H2 is filled with a conductive material 90; the packaging carrier further includes another wiring layer 91 located on the side of the core layer 20 away from the redistribution layer 31; the conductive material 90 is electrically connected to the redistribution layer 31 and the other wiring layer 91 respectively; the orthographic projections of the conductive material 90 and the other wiring layer 91 on the core layer 20 do not overlap with the orthographic projections of the heat insulation structure 10 on the core layer 20.

[0050] Still combined Figure 4 , Figure 6 as well as Figure 8As shown, the packaging substrate also includes a plurality of second vias H2 formed along the thickness direction of the core layer 20. Exemplarily, the plurality of second vias H2 can be two, or three or more, without limitation. Furthermore, each second via H2 is filled with a conductive material 90. Exemplarily, the conductive material 90 can be a conductive metal such as copper or silver. Exemplarily, the diameter of each second via H2 ranges from 50 μm to 70 μm. Of course, the specific material of the conductive material 90 and the specific diameter of the second via H2 can be selected according to the actual application, without limitation.

[0051] Furthermore, the package substrate also includes another wiring layer 91 located on the side of the core layer 20 away from the redistribution layer 31. Exemplarily, the other wiring layer 91 and the redistribution layer 31 can be arranged symmetrically with respect to the core layer 20, or they can be arranged asymmetrically. Additionally, the addition of another wiring layer 91 can be implemented with reference to related technologies, which will not be detailed here. Furthermore, the conductive material 90 is electrically connected to both the redistribution layer 31 and the other wiring layer 91; this provides a guarantee for the electrical connection between the package substrate and the printed circuit board (PCB). Moreover, the orthographic projections of the conductive material 90 and the other wiring layer 91 onto the core layer 20 do not overlap with the orthographic projections of the thermal insulation structure 10 onto the core layer 20.

[0052] In embodiments of the present invention, the following methods can be employed: Figure 10 The process flow diagram shown is used to prepare Figure 4 The packaging substrate is shown. First, the glass core layer 20 is laser-modified; then, through-glass vias (TGVs) are prepared using an acidic or alkaline etching solution, wherein the TGV via is the second via H2; then, the TGV vias are filled by filling the TGV vias with conductive material 90; then, a patterned redistribution layer 31 is set, while reserving an area for preparing the thermal insulation structure 10; then, symmetrical addition layers are applied to the upper and lower sides of the core layer 20 for solder mask encapsulation; for example, the number of addition layers is 3 to 10 layers. Then, a patternable material such as photoresist is used as a sacrificial layer 92 and spin-coated at the chip mounting location; grooves 70 for embedding the thermal insulation structure 10 are formed on the packaging substrate by exposure and laser etching; then, a low thermal conductivity material is filled into the grooves 70 and cured by dispensing, potting, etc.; then, the sacrificial layer 92 is removed to complete the embedding of the thermal insulation structure 10.

[0053] It should be noted that the thermal insulation structure 10, prepared using low thermal conductivity resin materials such as porous polyimide, porous epoxy resin, and porous styrene-cyclobutene, has a relatively lower thermal insulation effect compared to thermal insulation materials prepared using composite materials with multiple embedded first through-holes H1, or those made using silicon-based aerogel, carbon-based aerogel, or titanium-based aerogel. However, composite materials require more processing steps and have higher requirements for processing capabilities and yield.

[0054] In the embodiments of the present invention, during the preparation Figure 8 The process of preparing the encapsulation substrate shown is the same as that of preparing the substrate. Figure 4 The main difference lies in the steps involved. After filling the groove 70 with a low thermal conductivity material, multiple first vias H1 can be fabricated along the thickness direction of the thermal insulation structure 10 using methods such as laser etching, photolithography pre-patterning, and plasma etching. In this way, the introduction of multiple first vias H1 significantly reduces the thermal conductivity of the thermal insulation structure 10, thereby improving the heat insulation effect of the encapsulation substrate. Furthermore, since this method allows for the fabrication of multiple first vias H1 on a solid resin substrate, compared to simply setting the groove 70 without filling it with a low thermal conductivity material, it ensures the mechanical strength of the encapsulation substrate.

[0055] In the embodiments of the present invention, during the preparation Figure 6 In the process of creating the packaging substrate, a space for embedding an EMIB can be formed on the packaging substrate by means of laser etching or mechanical processing. The bottom of the space exposes an RDL interconnect area that matches the pads at the end of the EMIB. Then, the EMIB is embedded in the space and interconnected with the RDL, fanning out to the pins of the first and second chips to achieve high-density interconnection of multiple chips at the same level. After the EMIB embedding and interconnection are completed, a sacrificial layer 92 is formed on the side of the EMIB away from the core layer 20 and at the edge to define a structure corresponding to the first part 11 of the thermal insulation structure 10, and a second part 12 of the thermal insulation structure 10 is formed, thereby forming the desired thermal insulation structure 10. In this exemplary embodiment, the orthographic projection of the EMIB on the core layer 20 falls completely within the region of the orthographic projection of the thermal insulation structure 10 on the core layer 20. Moreover, the thermal insulation structure 10 is continuously arranged along the thickness direction, thereby effectively suppressing thermal crosstalk in the second direction. Furthermore, in this exemplary embodiment, the thickness of the thermal insulation structure 10 ranges from 100 μm to 600 μm. This creates a continuous thermal isolation boundary between the first region A and the second region B, thus avoiding thermal crosstalk and improving the performance of the packaging substrate. In practical applications, if the first chip is a high-power chip and the second chip is a temperature-sensitive chip, it can effectively reduce the risk of the temperature-sensitive chip being affected by the heat from adjacent high-power chips and EMIB, thereby improving the thermal zoning controllability and operational reliability of the packaging substrate in multi-chip packaging systems.

[0056] It should be noted that, in addition to the structures mentioned above, the packaging carrier provided in this embodiment of the invention also includes another solder mask layer 93 located on the side of another wiring layer 91 away from the core layer 20, and a third solder joint located on the side of the other solder mask layer 93 away from the core layer 20; for example, the third solder joint 96 is used to electrically connect the packaging carrier to the PCB. Of course, other structures can be provided according to actual application needs, which will not be described in detail here.

[0057] Based on the same inventive concept, such as Figure 11 , Figure 12 , Figure 13 As shown, this embodiment of the invention also provides a packaging structure, including: Encapsulation carrier 100 as described in any of the above items; The first chip 200 is electrically connected to the first pad 50 of the packaging substrate 100; The second chip 300 is electrically connected to the second pad 60 of the packaging substrate 100.

[0058] For example, the first chip 200 is electrically connected to the first pad 50 of the package carrier 100 via a first solder joint 94 located on the side of the solder mask layer 40 away from the core layer 20; the second chip 300 is electrically connected to the second pad 60 of the package carrier 100 via a second solder joint 95 located on the side of the solder mask layer 40 away from the core layer 20. For example, the first solder joint 94 can be one, or two or more, without limitation. For example, the second solder joint 95 can be one, or two or more, without limitation.

[0059] In this embodiment of the invention, the first chip 200 is a high-power chip, and the second chip 300 is a temperature-sensitive chip.

[0060] In this embodiment of the invention, the high-power chip is one of a logic chip, a power management chip, and a high-bandwidth memory controller; the temperature-sensitive chip is one of a clock chip, a memory chip, and a radio frequency chip.

[0061] Since the principle behind this packaging structure for solving the problem is similar to that of the aforementioned packaging substrate, the implementation of this packaging structure can be found in the implementation of the aforementioned packaging substrate, and the repetitive parts will not be repeated.

[0062] This invention provides a packaging substrate and packaging structure. The packaging substrate includes a heat insulation structure 10, and a core layer 20, a building layer 30, and a solder mask layer 40 stacked sequentially. The redistribution layer 31 in the building layer 30 extends to the surface of the building layer 30 away from the core layer 20 and is electrically connected to a first pad 50 and a second pad 60 in the solder mask layer 40, respectively. The solder mask layer 40 includes a first region A and a second region B arranged adjacent to each other. In the first region A, the first pad 50 is used for electrical connection with a first chip, and in the second region B, the second pad 60 is used for electrical connection with a second chip. In this way, the electrical connection between the packaging substrate and the required chip is guaranteed.

[0063] Furthermore, the heat insulation structure 10 is located between the first region A and the second region B, and a portion of the heat insulation structure 10 fills the groove 70 provided through the solder mask layer 40; the orthographic projection of the heat insulation structure 10 on the core layer 20 does not overlap with the orthographic projection of the redistribution layer 31 on the core layer 20. In this way, without affecting the chips required for electrical connection of the packaging substrate, the heat insulation structure 10 effectively prevents thermal crosstalk between chips, thereby improving the performance of the packaging substrate.

[0064] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0065] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A package substrate, characterized by, include: Thermal insulation structure, and a core layer, a structural layer and a weld barrier layer stacked in sequence; The redistribution layer in the building layer extends to the surface of the building layer away from the core layer and is electrically connected to the first pad and the second pad in the solder mask layer, respectively. The solder mask layer includes a first region and a second region disposed adjacent to each other. In the first region, the first pad is used to electrically connect to a first chip, and in the second region, the second pad is used to electrically connect to a second chip. The heat insulation structure is located between the first region and the second region, and a portion of the heat insulation structure is filled in a groove that penetrates the solder resist layer; the orthographic projection of the heat insulation structure on the core layer does not overlap with the orthographic projection of the redistribution layer on the core layer.

2. The package board according to claim 1, wherein The building layer also includes an add-on dielectric layer, and the redistribution layer is disposed through the add-on dielectric layer; the groove also extends along the add-on dielectric layer to the side away from the solder resist layer.

3. The packaging carrier board as described in claim 2, characterized in that, It also includes an embedded interconnect silicon bridge located in the add-on dielectric layer, the embedded interconnect silicon bridge being located between the first region and the second region and electrically connected to the redistribution layer; the thermal insulation structure is located on the side of the embedded interconnect silicon bridge away from the core layer and completely covers the embedded interconnect silicon bridge.

4. The packaging carrier board according to any one of claims 1-3, characterized in that, The heat insulation structure includes a first portion extending along a first direction, and the extension length of the first portion along the first direction is greater than the maximum extension length of the corresponding side of the first region and the second region. The orthographic projections of the first region and the second region onto the core layer do not overlap with the orthographic projection of the first part onto the core layer, and the first direction is a direction perpendicular to the center line of the first region and the second region.

5. The packaging carrier board as described in claim 4, characterized in that, The heat insulation structure further includes a second part located on the side of the first part closer to the core layer. The second part is connected to the first part and extends along a second direction, which is a direction parallel to the center line of the first region and the second region. The orthographic projection of the first part on the core layer overlaps with the orthographic projection of the second part on the core layer, and the extension length of the first part along the second direction is less than the extension length of the second part along the second direction. The length of the first portion extending along the first direction is greater than the length of the second portion extending along the first direction.

6. The packaging carrier board as described in claim 5, characterized in that, The orthographic projection of the first region onto the core layer overlaps with the orthographic projection of the second part onto the core layer; The orthographic projection of the second region onto the core layer overlaps with the orthographic projection of the second part onto the core layer.

7. The packaging carrier board according to any one of claims 1-3, 5, and 6, characterized in that, Multiple first through holes are provided at intervals along the thickness direction of the heat insulation structure.

8. The packaging carrier as described in claim 7, characterized in that, Each first via is either a blind via or a through via.

9. The packaging carrier board according to any one of claims 1-3, 5, 6, and 8, characterized in that, The material of the thermal insulation structure is at least one of porous polyimide, silicon-based aerogel, carbon-based aerogel, and titanium-based aerogel.

10. The packaging carrier board according to any one of claims 1-3, 5, 6, and 8, characterized in that, It also includes a plurality of second vias formed along the thickness direction of the core layer, each of which is filled with a conductive material; the packaging substrate also includes another wiring layer located on the side of the core layer away from the redistribution layer; the conductive material is electrically connected to the redistribution layer and the other wiring layer respectively; the orthographic projections of the conductive material and the other wiring layer on the core layer do not overlap with the orthographic projections of the thermal insulation structure on the core layer.

11. A packaging structure, characterized in that, include: The packaging carrier as described in any one of claims 1-10; The first chip is electrically connected to the first pad on the packaging substrate; The second chip is electrically connected to the second pad on the packaging substrate.

12. The packaging structure as described in claim 11, characterized in that, The first chip is a high-power chip, and the second chip is a temperature-sensitive chip.

13. The packaging structure as described in claim 12, characterized in that, The high-power chip is one of a logic chip, a power management chip, or a high-bandwidth memory controller; the temperature-sensitive chip is one of a clock chip, a memory chip, or a radio frequency chip.

Images