Semiconductor device and method of manufacturing the same

Abstract

This application provides a semiconductor device and its fabrication method. The semiconductor device includes a first semiconductor structure, which includes a first wafer and at least one compensation layer. The first wafer includes a first interconnect layer, and the compensation layer is located on one side of the first interconnect layer. The compensation layer is a patterned film layer, and the stress direction of the compensation layer is opposite to the stress direction of the corresponding region of the first wafer and the compensation layer. The semiconductor device and its fabrication method provided in this application can improve warpage and increase the reliability and yield of bonding.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Hybrid bonding technology holds immense potential in 3D stacked memory and high-end logic applications, and is one of the most important methods for achieving heterogeneous integration, such as silicon photonics. Currently, the process node of the top die is becoming increasingly advanced, with an increase in the number of metal layers or wiring density, and multi-stacked top dies are emerging. When the thickness of the top die is reduced to a certain value, individual top dies are prone to warping. Consequently, the surface morphology of individual top dies becomes irregular, which affects the reliability and yield of bonding. Summary of the Invention

[0003] In view of this, this application provides a semiconductor device and a method for fabricating the same, which can control the surface morphology of the first bonding contact layer of the first semiconductor structure, thereby improving the reliability and yield of bonding.

[0004] To solve the above problems, the technical solution provided in this application is as follows:

[0005] In a first aspect, embodiments of this application provide a semiconductor device, including a first semiconductor structure, the first semiconductor structure including: a first wafer including a first interconnect layer; and at least one compensation layer located on one side of the first interconnect layer; wherein the compensation layer is a patterned film layer, and the stress direction of the compensation layer is opposite to the stress direction of the corresponding region of the first wafer and the compensation layer.

[0006] Secondly, this application also provides a method for fabricating a semiconductor device, the method comprising: forming an initial semiconductor structure having an initial wafer, the initial wafer including a first interconnect layer; and forming at least one compensation layer on one side of the first interconnect layer; wherein the compensation layer is a patterned film layer, and the stress direction of the compensation layer is opposite to the stress direction of the corresponding region of the first wafer and the compensation layer.

[0007] The semiconductor device and its fabrication method provided in this application include a first semiconductor structure, comprising a first wafer and at least one compensation layer. The first wafer includes a first interconnect layer. The compensation layer is located on one side of the first interconnect layer and is a patterned film layer. The stress direction of the compensation layer is opposite to the stress direction of the corresponding region of the first wafer and the compensation layer. By adding a patterned compensation layer with a stress direction opposite to the stress direction of the corresponding region of the first wafer and the compensation layer at the location of stress non-uniformity in the first wafer of the first semiconductor structure, stress compensation is performed at the location of stress non-uniformity in the first wafer, thereby uniformizing the stress of the first wafer of the first semiconductor structure. This achieves control over the first wafer of the first semiconductor structure, thereby improving warpage and increasing the reliability and yield of bonding. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a semiconductor device provided in some embodiments of this application.

[0010] Figure 2 This is a schematic diagram of a semiconductor device provided for other embodiments of this application.

[0011] Figure 3 This is a schematic diagram of a semiconductor device provided in some embodiments of this application.

[0012] Figure 4 This is a schematic diagram of a semiconductor device provided for some embodiments of this application.

[0013] Figure 5A The final surface topography of the semiconductor device without the added compensation layer.

[0014] Figure 5B A surface topography diagram of the compensation layer of the semiconductor device provided in this application.

[0015] Figure 5C A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this application.

[0016] Figure 5D-5E The flowcharts show two methods for preparing compensation layers provided in some embodiments of this application.

[0017] Figure 6AA cross-sectional view of an initial semiconductor structure provided for some embodiments of this application.

[0018] Figure 6B In order to be in Figure 6A A cross-sectional view of the initial semiconductor structure after the first initial dielectric layer has been formed.

[0019] Figure 6C To be Figure 6B The first initial dielectric layer is patterned to obtain a cross-sectional view after the first sub-dielectric layer.

[0020] Figure 6D and 6E They are respectively in Figure 6C The cross-sectional view shown is taken after the initial compensation layer is formed on the first sub-dielectric layer.

[0021] Figure 6F and 6G Remove respectively Figure 6D and 6E The image shows a portion of the initial compensation layer, and a cross-sectional view of the compensation layer.

[0022] Figure 6H In order to be in Figure 6A The cross-sectional view shown is taken after the first sub-dielectric layer has been formed on the initial semiconductor structure.

[0023] Figure 6I In order to be in Figure 6H The cross-sectional view shown is taken after the initial compensation layer is formed on the first sub-dielectric layer.

[0024] Figure 6J To be Figure 6I The initial compensation layer shown is patterned to form a cross-sectional view after the compensation layer.

[0025] Figure 6K In order to be in Figure 6J The cross-sectional view shown is taken after the second initial dielectric layer is formed on the compensation layer.

[0026] Figure 6L To be Figure 6K The second initial dielectric layer is patterned to obtain a cross-sectional view after the second sub-dielectric layer.

[0027] Figures 7A-7C They are respectively in Figure 6F , Figure 6G and Figure 6L The cross-sectional view of the structure shown after the second dielectric layer has been formed on one side.

[0028] Figure 8 In order to be in Figure 7A The cross-sectional view shown is taken after bonding vias and bonding contact layers have been formed within or on the dielectric insulating layer.

[0029] Figure 9 In order to be in Figure 8 The cross-sectional view of the second intermediate semiconductor structure after the carrier is formed on one side.

[0030] Figure 10 To flip Figure 9 The second intermediate semiconductor structure is shown in a cross-sectional view after removing part of the first initial wafer.

[0031] Figure 11 This is a schematic diagram of a memory system provided for some embodiments of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] In the description of this application, it should be understood that the directional terms used in this invention, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the invention, and not for limiting the invention. In the drawings, structurally similar units are represented by the same reference numerals. In the drawings, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thickness of each component shown in the drawings are arbitrarily shown, but the invention is not limited thereto. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly and specifically defined.

[0034] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0035] Please refer to Figure 1This application provides a semiconductor device 100, which includes a first semiconductor structure 110. The first semiconductor structure 110 includes a first wafer 1101 and at least one compensation layer 22. The compensation layer 22 is located on one side of the first wafer 1101 and is a patterned film layer. The first wafer 1101 includes a first interconnect layer 30, and the stress direction of the compensation layer 22 is opposite to the stress direction of the corresponding region of the first wafer 1101 and the compensation layer 22.

[0036] In some embodiments of this application, the first semiconductor structure 110 may include chips of different sizes and types. These chips may be various types of memory devices, such as phase-change memory devices, 3D NAND memory devices, etc., and this application does not impose any limitations on them.

[0037] In some embodiments of this application, the first semiconductor structure 110 may include a single chip or die, or may be a stack of multiple dies or chips, or may be a stack of other semiconductor elements.

[0038] In a stacked network of dies, the top die, when its thickness is reduced to a certain value, can experience irregular warping due to uneven distribution of the device layer, dielectric layer, and metal layer of the first wafer 1101. However, this embodiment addresses this by adding a patterned compensation layer 22 at locations of stress unevenness on the first wafer 1101 of the first semiconductor structure 110. This compensation layer 22 has a stress direction opposite to that of the corresponding region of the compensation layer 22 on the first wafer 1101. The compensation layer 22 compensates for the stress unevenness at these locations, thereby balancing the stress on the first wafer 1101 of the first semiconductor structure 110, controlling the first semiconductor structure 110, reducing warping, and improving bonding reliability and yield.

[0039] In some embodiments of this application, the first semiconductor structure 110 further includes an insulating dielectric layer 21, which is located on one side of the first interconnect layer 30, and a compensation layer 22 is located within the insulating dielectric layer 21.

[0040] The insulating dielectric layer 21 is used to protect the compensation layer 22, and the absolute value of the stress in the compensation layer 22 is greater than that in the insulating dielectric layer 21. In this way, it can better contribute to different warp bow values. The compensation layer 22 contributes more to the warp bow value of the first wafer 1101 and has greater internal stress, thereby flattening the warp value of the entire first wafer 1101.

[0041] In some embodiments of this application, the insulating dielectric layer 21 is made of silicon nitride (Si).x N y ), silicon dioxide (Si) x O y Insulating materials such as silicon oxynitride (SiON).

[0042] In some embodiments of this application, the first wafer 1101 further includes a first device layer 10, and a first interconnect layer 30 is located on the first device layer 10. The insulating dielectric layer 21 includes a first dielectric layer 211 and a second dielectric layer 212. The first dielectric layer 211 is located on the side of the first interconnect layer 30 away from the device layer 10. The compensation layer 22 is located within the first dielectric layer 211. The second dielectric layer 212 is located on the side of the first dielectric layer 211 away from the first interconnect layer 30 and covers the compensation layer 22.

[0043] In some embodiments of this application, the materials of the first dielectric layer 211 and the second dielectric layer 212 include (Si) x N y ), silicon dioxide (Si) x O y It is an insulating material selected from at least one of silicon oxynitride (SiON). The materials of the first dielectric layer 211 and the second dielectric layer 212 may be the same or different.

[0044] In some embodiments of this application, the first dielectric layer 211 includes a plurality of grooves 2112, and the compensation layer 22 is located within the plurality of grooves 2112 and connected to the first dielectric layer 211 forming the inner wall of the grooves 2112. The second dielectric layer 212 is connected to the first dielectric layer 211 and to the compensation layer 22.

[0045] In some embodiments of this application, the side of the first dielectric layer 211 away from the first interconnect layer 30 is flush with the side of the compensation layer 22 away from the first interconnect layer 30.

[0046] In some embodiments of this application, the material of the compensation layer 22 includes an insulating medium. The compensation layer 22 includes a dielectric film layer 221, which is in direct contact with the insulating dielectric layer 21 (e.g., the first dielectric layer 211 and the second dielectric layer 212).

[0047] In some embodiments of this application, the material of the compensation layer 22 includes (Si) x N y ), silicon dioxide (Si) x O y Insulating materials include silicon oxynitride (SiON), silicon oxide doped with fluorine and carbon (SiFCO), and silicon nitride doped with carbon.

[0048] In some embodiments of this application, the insulating dielectric layer 21 and the compensation layer 22 are made of different materials, so that the absolute value of the stress in the compensation layer 22 can be greater than the absolute value of the stress in the insulating dielectric layer 21, which can better contribute different warp values ​​and thus flatten the warp value of the entire first wafer 1101.

[0049] In some embodiments of this application, the first interconnect layer 30 is located between the first device layer 10 and the first dielectric layer 211 and is stacked with the first device layer 10 in the first direction Z. The first interconnect layer 30 includes an interconnect conductive layer 31 and an interconnect dielectric layer 32. The interconnect conductive layer 31 and the interconnect dielectric layer 32 are respectively located on one side of the first wafer 1101. The interconnect conductive layer 31 is also located within the interconnect dielectric layer 32 and is electrically connected to the first wafer 1101. The interconnect dielectric layer 32 is used to protect the interconnect conductive layer 31.

[0050] In some embodiments of this application, the interconnect dielectric layer 32 is made of silicon nitride (Si). x N y ), silicon dioxide (Si) x O y Insulating materials such as silicon oxynitride, silicon oxide doped with fluorine and carbon, and silicon nitride doped with carbon.

[0051] Among them, there are other metals between the first device layer 10 and the interconnect conductive layer 31, and the metals are filled with many dielectric layers of different materials, not only silicon nitride and silicon oxide.

[0052] The first semiconductor structure 110 also includes a plurality of bonding vias 23 extending along a first direction Z, one end of each bonding via 23 being connected to an interconnect conductive layer 31. The orthographic projection of the compensation layer 22 onto the first interconnect layer 30 falls on at least one side of the orthographic projection of at least some of the bonding vias 23 onto the first interconnect layer 30. That is, not all bonding vias 23 have a compensation layer 22 on one side; the position of the compensation layer 22 is selected according to the need for stress compensation.

[0053] In order to ensure the consistency of etching, the compensation layer 22 and the bonding via 23 do not overlap in the first direction Z. That is, the orthogonal projections of the compensation layer 22 and the bonding via 23 on the first interconnect layer 30 do not overlap. This can both achieve stress compensation for the first bonding contact layer 24 and not affect the formation of the subsequent bonding via 23.

[0054] In some embodiments of this application, the first semiconductor structure 110 further includes a first bonding contact layer 24, which is located within the insulating dielectric layer 21 and on the side away from the first interconnect layer 30. A plurality of bonding vias 23 connect the first bonding contact layer 24 and the interconnect conductive layer 31.

[0055] In some embodiments of this application, the first bonding contact layer 24 is located within the second dielectric layer 212 and is away from the first dielectric layer 211.

[0056] The first bonding contact layer 24 includes a plurality of bonding pads, which are connected to the bonding vias 23.

[0057] In this design, the compensation layer 22 is disposed within the insulating dielectric layer 21, and the first bonding contact layer 24 is formed on the side of the insulating dielectric layer 21 away from the first interconnect layer 30. This achieves stress compensation for the first bonding contact layer 24 without affecting the subsequent formation of the first bonding contact layer 24.

[0058] In some embodiments of this application, the thickness of the first semiconductor structure 110 in the first direction Z is 10 micrometers to 300 micrometers. Preferably, the thickness of the first semiconductor structure 110 in the first direction Z is 10 micrometers to 50 micrometers. Generally, when the thickness of the first semiconductor structure 110 in the first direction Z is 10 micrometers to 100 micrometers, during the fabrication of the first semiconductor structure 110, the first wafer 1101 of the first semiconductor structure 110 is prone to warping irregular changes due to stress imbalance. Warping easily leads to irregular changes in the morphology of the first wafer 1101, resulting in uneven bonding interfaces, and the bonding equipment cannot compensate for the irregular warping value of a single chip. In this application, the compensation layer 22 can compensate for the stress on the first wafer 1101, thereby balancing the stress on the first wafer 1101, reducing warping, and improving the bonding reliability and bonding yield of the first semiconductor structure 110 and other semiconductor structures. The compensation layer 41 can actually be used in any scenario where it is necessary to adjust the irregular warping of the by-die.

[0059] Please see Figure 2 This application also provides a semiconductor device 200, which has a basically the same structure as the semiconductor device 100, except that the compensation layer 41 of the semiconductor device 200 has a different structure than the compensation layer 22 of the semiconductor device 100.

[0060] In some embodiments of this application, the material of the compensation layer 41 includes metal.

[0061] In some embodiments of this application, the material of the compensation layer 41 includes at least one of the following metals: Ti (titanium), Ta (tantalum), W (tungsten), TiW (titanium tungstenide), metal nitrides (e.g., WN (tungsten nitride), tungsten nitride, TaN (tantalum nitride), TiN (titanium nitride), Cu, Ni, Au, and Al.

[0062] Of course, in other embodiments, the compensation layer may also include a metal oxide.

[0063] Please continue reading. Figure 1 In some embodiments of this application, if the material selected for the compensation layer 41 does not have a risk of migration, the compensation layer 41 includes a metal layer 223, which is in direct contact with the insulating dielectric layer 21 (e.g., the first dielectric layer 211 and the second dielectric layer 212).

[0064] Please continue reading. Figure 2 In some embodiments of this application, if the material used for the compensation layer 41 has a migration risk, the compensation layer 41 includes a metal layer 223 and a barrier layer 222. The barrier layer 222 is located between the first dielectric layer 211 and the metal layer 223, and is in direct contact with the insulating dielectric layer 21 (e.g., the first dielectric layer 211). The metal layer 223 is located on the side of the barrier layer 222 away from the first dielectric layer 211 and is in contact with the second dielectric layer 212. The barrier layer 222 is used to block particle migration from the metal layer 223.

[0065] In some embodiments of this application, when the metal layer 223 is made of W (tungsten), the barrier layer 222 is made of TiN (titanium nitride) and Ti (titanium), with Ti serving as an adhesion layer. If the material selected for the compensation layer 41 has a migration risk, the specific materials of the metal layer 223 and the barrier layer 222 can be selected according to the actual situation, and will not be described in detail here.

[0066] In some embodiments of this application, when the compensation layer 41 is made of metal, the first semiconductor structure 110 further includes a third dielectric layer 25, which is located between the first dielectric layer 211 and the second dielectric layer 212 and covers the compensation layer 22. The third dielectric layer 25 is used to protect the metal layer 223 and acts as a barrier layer to prevent particles from the metal layer from diffusing into the dielectric layer.

[0067] In some embodiments of this application, the material of the third dielectric layer 25 may include silicon nitride, etc.

[0068] Please see Figure 3 This application also provides a semiconductor device 300, which has a structure that is basically the same as that of semiconductor device 100. The difference is that the compensation layer 42 of semiconductor device 300 is not made of the same material as the compensation layer 22 of semiconductor device 100, and the structure of the first dielectric layer 311 of semiconductor device 300 is not exactly the same as the structure of the first dielectric layer 211 of semiconductor device 100.

[0069] In some embodiments of this application, the first dielectric layer 311 of the semiconductor device 300 includes a first sub-dielectric layer 2113 and a second sub-dielectric layer 2115. The first sub-dielectric layer 2113 is located on the side of the first interconnect layer 30 away from the first wafer 1101. The compensation layer 42 is located on the side of the first sub-dielectric layer 2113 away from the first interconnect layer 30. The second sub-dielectric layer 2115 is located on the side of the first sub-dielectric layer 2113 away from the first interconnect layer 30 and at least partially covers the compensation layer 42. The second dielectric layer 212 is located on the side of the second sub-dielectric layer 2115 away from the first sub-dielectric layer 2113 and is in contact with the compensation layer 42. That is, the second dielectric layer 212 covers the compensation layer 42 from the side perpendicular to the first direction Z.

[0070] In some embodiments of this application, the side of the second sub-dielectric layer 2115 away from the first sub-dielectric layer 2113 is flush with the side of the compensation layer 42 away from the first sub-dielectric layer 2113.

[0071] Please see Figure 4 This application also provides a semiconductor device 400, which has a structure that is basically the same as that of semiconductor device 100, except that semiconductor device 400 further includes a second semiconductor structure 120, which is bonded to the first semiconductor structure 110 in the first direction Z.

[0072] In some embodiments of this application, the second semiconductor structure 120 has a second wafer 51 and a second bonding contact layer 53. The second wafer 51 includes a second device layer 511 and a second interconnect layer 512 connected to the device layer 511. The second interconnect layer 512 is located on one side of the second device layer 511 and connected to it. The second bonding contact layer 53 is located on the side of the second interconnect layer 512 away from the second device layer 511 and connected to the interconnect conductive layer of the second interconnect layer 512. The second bonding contact layer 53 is bonded to a first bonding contact layer 24. A portion of the second bonding contact layer 53 or the first bonding contact layer 24 can be dummy contacts, which are not connected to the interconnect conductive layer of the first interconnect layer 30 or the second interconnect layer 512.

[0073] In some embodiments of this application, the bonding method between the second semiconductor structure 120 and the first semiconductor structure 110 is a fusion bonding process, a hybrid bonding process, etc. The hybrid bonding process can be a chip-to-wafer (W2W) or die-to-wafer (D2W) process, etc.

[0074] In some embodiments of this application, the second wafer 51 may include logic circuitry, that is, the second wafer 51 may be a logic wafer.

[0075] In some embodiments of this application, the specific type of the second semiconductor structure 120 is not further limited and can be determined according to the actual application.

[0076] This application also provides a method for fabricating a semiconductor device, comprising: forming an initial semiconductor structure having an initial wafer, the initial wafer including a first interconnect layer; and forming at least one compensation layer on one side of the first interconnect layer; wherein the compensation layer is a patterned film layer, and the stress direction of the compensation layer is opposite to the stress direction of the first wafer.

[0077] In this embodiment, a compensation layer is added at the location of stress non-uniformity (preset compensation region) of the first wafer of the first semiconductor structure. The stress direction is opposite to the stress direction of the region corresponding to the compensation layer 22 of the first wafer. The compensation layer compensates for the stress non-uniformity of the first wafer, so as to balance the stress of the first wafer of the first semiconductor structure, reduce warpage, and improve bonding reliability and bonding yield.

[0078] The fabrication method of semiconductor devices will be explained in detail below with reference to the accompanying drawings.

[0079] Please see Figures 5C-10 as well as Figures 1-4 This application provides a method for fabricating a semiconductor device, the method comprising:

[0080] Please see Figure 5C and Figure 6A Step S1: Form an initial semiconductor structure 101 having an initial wafer 1011, the initial wafer 1011 including a first interconnect layer 30.

[0081] It should be noted that the initial wafer 1011 is an unthinned wafer. The initial wafer 1011 is made of silicon and may also include a device layer 10 and a substrate (not shown). The first interconnect layer 30 is located on one side of the first device layer 10.

[0082] The first interconnect layer 30 includes an interconnect conductive layer 31 and an interconnect dielectric layer 32 connected to the initial wafer 1011. The interconnect conductive layer 31 and the interconnect dielectric layer 32 are respectively located on one side of the initial wafer 1011. The interconnect conductive layer 31 is also located within the interconnect dielectric layer 32 and is electrically connected to the initial wafer 1011. The interconnect dielectric layer 32 is used to protect the interconnect conductive layer 31. The interconnect conductive layer 31 is the top metal layer of the initial wafer 1011. The number of interconnect conductive layers 31 can be one or more. If it is multiple, it is formed by stacking multiple interconnect conductive layers 31. Correspondingly, the interconnect dielectric layer 32 can also be multiple.

[0083] Please see Figure 5C and Figure 6F , 6GIn step S2, at least one compensation layer 22 / 41 / 42 is formed on one side of the first interconnect layer 30, wherein the compensation layer 22 / 41 / 42 is a patterned film layer and the stress direction of the compensation layer 22 / 41 / 42 is opposite to the stress direction of the initial wafer 1011.

[0084] Please see Figures 6B-6F Before step S2, step S20 is also included: forming a first dielectric layer 211 on one side of the first interconnect layer 30.

[0085] Please see Figure 5C and Figures 7A-7C After step S2, step S3 is also included: forming a second dielectric layer 212 on the side of the first dielectric layer 211 away from the initial wafer 1011, and such that the compensation layers 22 / 41 / 42 are located within the insulating dielectric layer 21 formed by the first dielectric layer 211 and the second dielectric layer 212.

[0086] The absolute stress value of the compensation layer 22 / 41 / 42 is greater than the absolute stress value of the insulating dielectric layer 21 (i.e., the second sub-dielectric layer 2115). In some embodiments of this application, the material of the compensation layer 22 / 41 / 42 is different from that of the insulating dielectric layer 21.

[0087] The final surface morphology of a semiconductor device without a compensation layer can be obtained by direct measurement or by using bow value simulation software such as Comsol. Based on the final surface morphology, it can be determined where warping occurs and stress compensation is required. The area requiring stress compensation is the preset compensation area.

[0088] Please refer to some embodiments of this application. Figures 5A-5B , Figure 5A The final surface topography image of a semiconductor device without an added compensation layer (e.g., a single die). Figure 5B This is a graphical representation of the surface topography of the corresponding compensation layer, where the horizontal axis represents the wafer radius and the vertical axis represents the bow height.

[0089] Depend on Figure 5A It can be seen that the bow value of the first wafer in the first region V1 without the added compensation layer has two upward peaks and one downward trough, while the bow value of the first wafer in the second region V2 has two downward troughs and one upward peak. From... Figure 5BIt can be seen that the bow value of the first wafer in the third region V3 of the compensation layer has two downward troughs and one upward peak, while the bow value of the first wafer in the fourth region V4 has two upward peaks and one downward trough. Specifically, the two upward peaks and one downward trough of the bow value of the first wafer in the first region V1 without the compensation layer correspond to the two downward troughs and one upward peak of the bow value of the first wafer in the third region V3 of the compensation layer, and their bow values ​​are similar. Similarly, the two downward troughs and one upward peak of the bow value of the first wafer in the second region V2 without the compensation layer correspond to the two upward peaks and one downward trough of the bow value of the first wafer in the fourth region V4 of the compensation layer, and their bow values ​​are similar. The same configuration applies to other regions, and will not be described in detail here.

[0090] In other words, the stress direction of the compensation layer 22 / 41 / 42 is opposite to the stress direction of the corresponding region of the first wafer 1101 and the compensation layer 22. The surface morphology of the patterned compensation layer 22 / 41 / 42 can complement the final surface morphology of the first wafer of the semiconductor device without the added compensation layer, thereby controlling the overall surface morphology of the first wafer of the semiconductor device. This method can not only improve the irregular warpage value introduced by design (e.g., by-shot / by-die) when the semiconductor device is bonded to other devices, but can also be used in other scenarios where irregular warpage value needs to be improved.

[0091] Please see Figure 5C and Figure 8 In some embodiments of this application, the preparation method further includes: step S4, forming a bonding via 23 in a preset area of ​​the insulating dielectric layer 21, with one end of the bonding via 23 connected to the interconnect conductive layer 31; step S5, forming a first bonding contact layer 24 on the side of the insulating dielectric layer 21 away from the first interconnect layer 30 to obtain an intermediate semiconductor structure 102, with the first bonding contact layer 24 connected to a plurality of bonding vias 23 respectively.

[0092] The orthographic projection of the compensation layers 22 / 41 / 42 onto the first interconnect layer 30 falls on at least one side of the orthographic projection of at least a portion of the bonded vias 23 onto the first interconnect layer 30. To ensure etching consistency, the compensation layers 22 and the bonded vias 23 do not overlap in the first direction Z; that is, the orthographic projections of the compensation layers 22 and the bonded vias 23 onto the first interconnect layer 30 do not overlap.

[0093] The bonding contact layer 24 and the bonding via 23 are generally formed by a dual damascene process, which typically involves the following steps: photolithography-etching-photolithography-etching-PVD-electroplating-CMP process, etc. PVD stands for Physical Vapor Deposition, and CMP stands for Chemical Mechanical Polishing.

[0094] Please refer to it again. Figure 5C and Figure 9 and Figure 10 In some embodiments of this application, the preparation method further includes: step S6, forming a carrier 220 on one side of the intermediate semiconductor structure 102 having a first bonding contact layer 24; flipping the intermediate semiconductor structure 102 having the carrier 220; removing a portion of the initial wafer 1011 to obtain a thinned first wafer 1101; and removing the carrier 220 to obtain the first semiconductor structure 110.

[0095] In some embodiments of this application, the carrier 220 can be a glass substrate, silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Another carrier with a border and an ultraviolet film (UV film) is added to the first wafer 1101 of the entire first semiconductor structure 110 to temporarily store the first semiconductor structure 110.

[0096] The carrier 220 is temporarily bonded to the first bonding contact layer 24 of the intermediate semiconductor structure 102, or other bonding processes are used. Specifically, the temporary bonding process can involve forming bonding adhesive on one side of the first bonding contact layer 24 of the intermediate semiconductor structure 102 and attaching the bonding adhesive to the carrier 220; or the bonding adhesive can be directly formed on the carrier 220. Generally, different bonding adhesives can be applied to the first bonding contact layer 24 and the carrier 220 respectively in the temporary bonding process. The purpose of the temporary bonding is to thin the initial wafer 1011, thereby enabling the initial wafer 1011 to reach a target thickness (e.g., 10 μm to 300 μm), and thinning the initial wafer 1011 facilitates dicing.

[0097] Specifically, the thinned wafer is placed on another carrier, such as an iron ring with a UV film. The carrier 220 is then removed by debonding (temporary bonding between the intermediate semiconductor structure 102 and the carrier 220) using laser or mechanical methods.

[0098] After the "removal of carrier 220" step in step S6, the process further includes: dividing the entire chip into independent small chips by mechanical cutting, laser cutting, plasma cutting, etc. on the iron ring with UV film, and cleaning and activating the obtained small chips to form the first semiconductor structure 110.

[0099] Please refer to it again. Figure 4 In some embodiments of this application, the preparation method further includes: step S7, bonding the first semiconductor structure 110 to the second semiconductor structure 120.

[0100] In some embodiments of this application, the first semiconductor structure 110 and the second semiconductor structure 120 are D2W hybrid bonded (HB) to form an electrical connection.

[0101] In some embodiments of this application, the compensation layer 22 / 41 / 42 is made of metal, insulating medium, or metal oxide.

[0102] Please refer to it again. Figure 5D and Figure 6A-6G In some embodiments of this application, when the material of the compensation layer 22 / 41 is metal or an insulating medium, step S2 includes: Please refer to Figure 6B Step S11: A first initial dielectric layer 2111 is formed on the first interconnect layer 30 of the initial semiconductor structure 101; please refer to... Figure 6C Step S12, patterning the first initial dielectric layer 2111 to obtain the first dielectric layer 211, the first dielectric layer 211 including patterned grooves 2112; please refer to Figure 6D and 6E In step S13, an initial compensation layer 230 is formed on the surface of the first dielectric layer 211 away from the first interconnect layer 30 and in the groove 2112; and please refer to Figure 6F and 6G In step S14, the initial compensation layer 230 outside the groove 2112 is removed to obtain the compensation layer 22 / 41.

[0103] In step S12, the first initial dielectric layer 2111 can be patterned by processes such as photolithography to obtain the first dielectric layer 211. When patterning the first initial dielectric layer 2111 by processes such as photolithography, a patterned photoresist layer is generally formed on the first initial dielectric layer 2111 first, and then the first initial dielectric layer 2111 is patterned by processes such as dry etching or wet etching.

[0104] In step S14, the initial compensation layer 230 outside the groove 2112 can be removed by processes such as mechanical grinding to obtain the compensation layer 22 / 41. Specifically, a grinding process with a high selectivity is first selected to remove the initial compensation layer 230 outside the groove 2112, and then a grinding process with a low selectivity for the initial compensation layer 230 / first dielectric layer 211 is selected for planarization. In order not to affect the formation of the bonding via 23, the position of the groove 2112 should avoid the position used to form the bonding via 23.

[0105] Please see Figure 5E and Figure 6H-6L In some embodiments of this application, when the material of the compensation layer 42 is metal or an insulating medium, step S1 includes: Please refer to Figure 6H In step S110, a first sub-dielectric layer 2113 is formed on the first interconnect layer 30 of the initial semiconductor structure 101; please refer to Figure 6I and 6J In step S120, an initial compensation layer 230 is formed and patterned on the side of the first sub-dielectric layer 2113 away from the first interconnect layer 30 to obtain compensation layer 42; please refer to Figure 6K In step S130, a second initial dielectric layer 2114 is formed on the side of the first sub-dielectric layer 2113 away from the first interconnect layer 30, such that the second initial dielectric layer 2114 covers the compensation layer 42; and please refer to Figure 6L In step S140, a portion of the second initial dielectric layer 2114 is removed to obtain the second sub-dielectric layer 2115, and the compensation layer 42 is exposed from the second sub-dielectric layer 2115. The first sub-dielectric layer 2113 and the second sub-dielectric layer 2115 constitute the first dielectric layer 311.

[0106] The first sub-dielectric layer 2113, the initial compensation layer 230, and the second initial dielectric layer 2114 can be formed through processes such as deposition.

[0107] In step S120, the initial compensation layer 230 is patterned using processes such as photolithography. When patterning the initial compensation layer 230 using photolithography, a patterned photoresist layer is typically formed on the initial compensation layer 230 first, and then the initial compensation layer 230 is patterned using processes such as dry etching or wet etching. If the reflectivity of the initial compensation layer 230 is high, an anti-reflection layer can also be formed between the photoresist layer and the initial compensation layer 230.

[0108] In step S140, part of the second initial dielectric layer 2114 is removed by processes such as mechanical grinding to obtain the second sub-dielectric layer 2115.

[0109] Please see Figure 6F and Figure 7AIn some embodiments of this application, the material of the compensation layer 22 includes an insulating medium, and the compensation layer 22 includes a dielectric film layer 221, which is in direct contact with the insulating dielectric layer 21 (e.g., the first dielectric layer 211 and the second dielectric layer 212).

[0110] Please refer to it again. Figure 6G In some embodiments of this application, the material of the compensation layer 41 includes metal. The step of "forming at least one compensation layer on one side of the first interconnect layer 30" in step S2 includes: forming a patterned barrier layer 222 in a preset compensation area of ​​the first dielectric layer 211; and forming a metal layer 223 on the side of the barrier layer 222 away from the first dielectric layer 211; the metal layer 223 and the barrier layer 222 may be formed simultaneously or sequentially.

[0111] Please see Figure 7B In some embodiments of this application, the material of the compensation layer 41 includes metal. Before step S3, the method further includes the step of forming a third dielectric layer 25 on the side of the first dielectric layer 211 away from the first interconnect layer 30. The third dielectric layer 25 is located between the first dielectric layer 211 and the second dielectric layer 212 and covers the compensation layer 41.

[0112] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0113] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, comprising a first semiconductor structure, characterized in that, The first semiconductor structure includes: The first wafer includes a first interconnect layer; and At least one compensation layer is located on one side of the first interconnect layer; The compensation layer is a patterned film layer, and the stress direction of the compensation layer is opposite to the stress direction of the corresponding region of the first wafer and the compensation layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The first semiconductor structure further includes an insulating dielectric layer located on one side of the first interconnect layer, and the compensation layer located within the insulating dielectric layer.

3. The semiconductor device as described in claim 2, characterized in that, The absolute stress value of the compensation layer is greater than the absolute stress value of the insulating dielectric layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The first interconnect layer includes an interconnect conductive layer; The first semiconductor structure further includes a plurality of bonding vias, one end of which is connected to the interconnect conductive layer; Wherein, the orthographic projection of the compensation layer on the first interconnect layer falls on at least one side of the orthographic projection of at least a portion of the bonding vias on the first interconnect layer, and the compensation layer and the bonding vias do not overlap in a first direction.

5. The semiconductor device as claimed in claim 4, characterized in that, The first semiconductor structure further includes a first bonding contact layer, one end of the bonding via is connected to the interconnect conductive layer, and the other end is connected to the first bonding contact layer.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The material of the compensation layer includes at least one of insulating media, metals, and metal compounds.

7. The semiconductor device as claimed in claim 6, characterized in that, The compensation layer is made of at least one of silicon oxide, silicon nitride, silicon oxynitride, fluorine- and carbon-doped silicon oxide, carbon-doped silicon nitride, Ti, Ta, W, TiW, TaN, TiN, WN, Cu, Ni, Au, and Al.

8. The semiconductor device as claimed in claim 2, characterized in that, The insulating dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on one side of the first interconnect layer, the compensation layer is located inside the first dielectric layer, and the second dielectric layer is located on the side of the first dielectric layer away from the first interconnect layer and covers the compensation layer.

9. The semiconductor device as claimed in claim 8, characterized in that, The first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. The first sub-dielectric layer is located on one side of the first interconnect layer. The compensation layer is located on the side of the first sub-dielectric layer away from the first interconnect layer. The second sub-dielectric layer is located on the side of the first sub-dielectric layer away from the first interconnect layer and at least partially covers the compensation layer. The second dielectric layer is located on the side of the second sub-dielectric layer away from the first sub-dielectric layer and is in contact with the compensation layer.

10. The semiconductor device as claimed in claim 6, characterized in that, The compensation layer includes a dielectric film layer located within a first dielectric layer, with a portion of the dielectric film layer in contact with the first dielectric layer and another portion in contact with a second dielectric layer.

11. The semiconductor device as claimed in claim 8, characterized in that, The compensation layer includes a metal layer; The first bonding contact layer further includes a third dielectric layer, which is located between the first dielectric layer and the second dielectric layer and covers the compensation layer.

12. The semiconductor device as claimed in claim 11, characterized in that, The compensation layer further includes a barrier layer located between the insulating dielectric layer and the metal layer.

13. The semiconductor device according to any one of claims 1-5 and 8-9, characterized in that, It also includes a second semiconductor structure, which is bonded to the first semiconductor structure.

14. A method for fabricating a semiconductor device, characterized in that, include: An initial semiconductor structure is formed having an initial wafer, the initial wafer including a first interconnect layer; and At least one compensation layer is formed on one side of the first interconnect layer; The compensation layer is a patterned film layer, and the stress direction of the compensation layer is opposite to the stress direction of the corresponding region of the first wafer and the compensation layer.

15. The method for fabricating a semiconductor device as described in claim 14, characterized in that, Before the step of "forming at least one compensation layer on one side of the first interconnect layer", the method further includes: forming a first dielectric layer on one side of the first interconnect layer; After forming at least one compensation layer on one side of the first interconnect layer, the method further includes forming a second dielectric layer on the side of the first dielectric layer away from the initial wafer, such that the compensation layer is located within an insulating dielectric layer formed by the first dielectric layer and the second dielectric layer.

16. The method for fabricating a semiconductor device as described in claim 15, characterized in that, The absolute stress value of the compensation layer is greater than the absolute stress value of the insulating dielectric layer.

17. The method for fabricating a semiconductor device as described in claim 15, characterized in that, The compensation layer is made of at least one of metal, insulating medium, and metal compound; The step of forming at least one compensation layer on one side of the first interconnect layer includes: A first initial dielectric layer is formed on the first interconnect layer; The first initial dielectric layer is patterned to obtain a first dielectric layer; the first dielectric layer includes patterned grooves; An initial compensation layer is formed on the surface of the first dielectric layer away from the first interconnect layer and within the groove; and Remove the initial compensation layer outside the groove to obtain the compensation layer.

18. The method for fabricating a semiconductor device as described in claim 15, characterized in that, The compensation layer is made of at least one of metal, insulating medium, and metal compound; The step of forming at least one compensation layer on one side of the first interconnect layer includes: A first sub-dielectric layer is formed on the first interconnect layer; An initial compensation layer is formed on the side of the first sub-dielectric layer away from the first interconnect layer, and the initial compensation layer is patterned to obtain a compensation layer; A second initial dielectric layer is formed on the side of the first sub-dielectric layer away from the first interconnect layer, such that the second initial dielectric layer covers the compensation layer; and A portion of the second initial dielectric layer is removed to obtain a second sub-dielectric layer, and the compensation layer is exposed from the second sub-dielectric layer; the first sub-dielectric layer and the second sub-dielectric layer constitute the first dielectric layer.

19. The method for fabricating a semiconductor device as described in claim 17 or 18, characterized in that, The compensation layer is made of metal, and before the step of "forming a second dielectric layer on the side of the first dielectric layer away from the first interconnect layer", the method further includes: A third dielectric layer is formed on the side of the first dielectric layer away from the first interconnect layer; The third dielectric layer is located between the first dielectric layer and the second dielectric layer and covers the compensation layer.

20. The method for fabricating a semiconductor device as described in claim 17 or 18, characterized in that, The compensation layer is made of metal, and the step "forming a patterned compensation layer in the preset compensation area of ​​the first dielectric layer" includes: A patterned barrier layer is formed in a predetermined compensation area of ​​the first dielectric layer; and A metal layer is formed on the side of the barrier layer away from the first dielectric layer; The metal layer and the barrier layer can be formed simultaneously or sequentially.

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