Modules and apparatuses

Abstract

This invention relates to modules and devices. The width Dc of the intermediate portion defined by a first semiconductor element and a second semiconductor element is less than the sum of the thickness Ta and the thickness Tb of the lower portion, and the distance Da from at least a portion of the outline of the projection of the first semiconductor element onto the mounting surface to at least a portion of the outer edge of the board bonding surface is less than the width Dc, the board bonding surface being the bonding surface of an adhesive to a wiring board.

Description

Technical Field

[0001] The technology disclosed herein relates to a module comprising a wiring board, semiconductor elements, and an adhesive. Background Technology

[0002] Japanese Patent Application Publication No. 2007-134540 discloses a semiconductor device in which a plurality of semiconductor elements are mounted on a circuit board with their bump surfaces facing down, and the gap between the underside of the semiconductor elements and the topside of the circuit board is filled with an underfill resin.

[0003] In this technical field, the mechanical properties of the module have become a problem. Summary of the Invention

[0004] This disclosure relates to providing modules with excellent mechanical properties.

[0005] A module according to one aspect of this disclosure includes a wiring board having a mounting surface, a first semiconductor element, a second semiconductor element, and an adhesive. The first and second semiconductor elements are electrically connected to the wiring board, overlap the wiring board in a first direction perpendicular to the mounting surface, and are arranged side-by-side along the mounting surface in a second direction. The adhesive is bonded to the wiring board, the first semiconductor element, and the second semiconductor element on the mounting surface. The adhesive includes a first portion located between the wiring board and the first semiconductor element in the first direction, a second portion located between the wiring board and the second semiconductor element in the first direction, and a third portion located between the first and second semiconductor elements in the second direction. The width Dc of the third portion defined by the first and second semiconductor elements in the second direction is less than the sum of the thickness Ta of the first portion in the first direction and the thickness Tb of the second portion in the first direction. The distance Da from at least a portion of a first profile projected from the first semiconductor element on the mounting surface in the first direction to at least a portion of the outer edge of a board-joining surface is less than the width Dc, the board-joining surface being the bonding surface of the adhesive to the wiring board.

[0006] The features of this disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings. The following description of the embodiments is given by way of example. Attached Figure Description

[0007] Figure 1A This is a top view of a module according to a first embodiment of the present disclosure.

[0008] Figure 1B It is along Figure 1A The cross-sectional view of the module cut by line IB-IB in the diagram.

[0009] Figure 2A It is an enlarged view of the cross-section of the module, including the middle section.

[0010] Figure 2B It is an enlarged view of the cross-section of the module, including the end portion.

[0011] Figure 3A This is a top view of the module according to the second embodiment.

[0012] Figure 3B It is along Figure 3A The diagram shows a cross-sectional view of the module cut by line IIIB-IIIB.

[0013] Figure 4A This is a top view of the module according to the third embodiment.

[0014] Figure 4B It is along Figure 4A The diagram shows a cross-sectional view of the module taken by line IVB-IVB.

[0015] Figure 5A This is a top view of the module according to the fourth embodiment.

[0016] Figure 5B It is along Figure 5A The diagram shown is a cross-sectional view of the module captured by line VB-VB.

[0017] Figure 6A and Figure 6B The cross-sectional view of the module according to the fifth embodiment shows its manufacturing process.

[0018] Figure 6C This is a cross-sectional view of the module according to the sixth embodiment.

[0019] Figure 7A This is a diagram illustrating the modules according to the seventh embodiment.

[0020] Figure 7B This is a diagram illustrating the following steps of injecting adhesive into a semiconductor device.

[0021] Figure 7C This is a diagram showing the state of the adhesive after it has been cured by heating.

[0022] Figure 7D This diagram shows the state after the masking tape has been removed following the curing of the adhesive.

[0023] Figure 8 This is a diagram illustrating a camera system according to the eighth embodiment.

[0024] Figure 9This is a diagram showing the module according to the reference pattern, illustrating the warping caused by the expansion of the adhesive. Detailed Implementation

[0025] Embodiments will now be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used for elements common to multiple figures. Therefore, common structures are described with reference to multiple figures, and repeated descriptions of elements indicated by the same reference numerals are appropriately omitted.

[0026] Reference Figure 1A and Figure 1B as well as Figure 2A and Figure 2B A first embodiment of this disclosure is described. Figure 1A and Figure 1B Relevant parts of the module according to the first embodiment are shown. Figure 1A This is a top view of module 400. Figure 1B It is along Figure 1A The cross-sectional view of module 400 is taken from line IB-IB.

[0027] Module 400 includes a wiring board 1, a semiconductor element 10 (first semiconductor element), a semiconductor element 20 (second semiconductor element), and an adhesive 30.

[0028] The wiring board 1 has a mounting surface 2. The wiring board 1 also has an opposite surface 3 opposite to the mounting surface 2 and an end surface 4 connecting the mounting surface 2 and the opposite surface 3. The opposite surface 3 can also be used as a mounting surface, which will be described later.

[0029] Semiconductor element 10 is electrically connected to wiring board 1 and overlaps with wiring board 1 in the Z direction perpendicular to mounting surface 2. Semiconductor element 20 is electrically connected to wiring board 1 and overlaps with wiring board 1 in the Z direction perpendicular to mounting surface 2. Semiconductor elements 10 and 20 are arranged side by side along mounting surface 2 in the X direction.

[0030] exist Figure 1A In the diagram, the outline 100 of the projection of semiconductor element 10 in the Z direction onto the plane including the mounting surface 2 is indicated by a thick line, and the outline 200 of the projection of semiconductor element 20 in the Z direction onto the plane including the mounting surface 2 is indicated by a thick line.

[0031] Electrical connections between the semiconductor element 10 and the wiring board 1 are made using multiple conductive members 14. The multiple conductive members 14 may be conductive balls or conductive bumps disposed between the semiconductor element 10 and the wiring board 1. The multiple conductive members 14 may be metal bumps, solder balls, conductive resin, or combinations thereof. This structure is not limited to having multiple conductive members 14 disposed between the semiconductor element 10 and the wiring board 1; alternatively, wires may be used as conductive members 14 to form an electrical connection between the semiconductor element 10 and the wiring board 1 outside the area between them. In this case, the multiple conductive members 14, acting as wires, are wired and bonded to the semiconductor element 10 and the wiring board 1.

[0032] Electrical connections between the semiconductor element 20 and the wiring board 1 are made using multiple conductive members 24. The multiple conductive members 24 may be conductive balls or conductive bumps disposed between the semiconductor element 20 and the wiring board 1. The multiple conductive members 24 may be metal bumps, solder balls, conductive resin, or combinations thereof. This structure is not limited to having multiple conductive members 24 disposed between the semiconductor element 20 and the wiring board 1; alternatively, wires may be used as conductive members 24 to form an electrical connection between the semiconductor element 20 and the wiring board 1 outside the area between them. In this case, the multiple conductive members 24, acting as wires, are wired and bonded to the semiconductor element 20 and the wiring board 1.

[0033] Adhesive 30 bonds the wiring board 1, semiconductor element 10, and semiconductor element 20 to the mounting surface 2. Adhesive 30 is formed by drying to solidify the liquid adhesive and / or by polymerization to cure the adhesive. Adhesive 30 is typically made of resin and acts as a reinforcing material, sealant, or underfill material.

[0034] Figure 1A The outline 300 is shown as the projection of the adhesive 30 in the Z direction onto a plane including the mounting surface 2. The area enclosed by the outline 300 is shaded; however, the adhesive 30 is not necessarily present in the entire area enclosed by the outline 300. Typically, the adhesive 30 is not present in the portions within the outline 300 where the conductive members 14 and 24 are located.

[0035] like Figure 1B As shown, the adhesive 30 has a lower portion 31, a lower portion 32, and a middle portion 33. The lower portion 31 is located between the wiring board 1 and the semiconductor element 10 in the Z direction. The lower portion 32 is located between the wiring board 1 and the semiconductor element 20 in the Z direction. The middle portion 33 is located between the semiconductor element 10 and the semiconductor element 20 in the X direction. The adhesive 30 also has an end portion 36 forming a contour 300 near the semiconductor element 10 and an end portion 37 forming a contour 300 near the semiconductor element 20. The middle portion 33 and the ends 36 and 37 are also... Figure 1A As shown in the image.

[0036] Ends 36 and 37 are exposed to a void space. The void space is typically a gaseous space such as air, but may alternatively be a vacuum or a space filled with liquid. By exposing ends 36 and 37 to the void space, the mechanical properties of module 400 can be controlled by the shape of ends 36 and 37.

[0037] Reference Figure 9 This embodiment describes the problem it aims to solve. Based on... Figure 9 In the reference model of module 401 shown, semiconductor elements 10 and 20 are mounted above wiring board 1, and adhesive 30 is provided. Shrinkage may occur when the liquid adhesive used to form adhesive 30 solidifies and / or cures. When adhesive 30 experiences temperature changes during the manufacture or use of module 401, it may expand or shrink according to its coefficient of thermal expansion. In particular, when the volume of the middle portion 33 and the ends 36 and 37 of adhesive 30 is large, such expansion or shrinkage of adhesive 30 may cause deformation of wiring board 1, such as warping (W). Figure 9 The diagram illustrates warping (W) caused by the expansion of adhesive 30, and warping in the opposite direction that may occur when adhesive 30 contracts. This deformation can have undesirable effects during manufacturing or use. Specifically, such deformation can cause a reduction in the yield, reliability, performance, and lifespan of module 401. For example, such effects may include a decrease in the reliability of the connection between wiring board 1 and semiconductor elements 10 and 20, or damage to semiconductor elements 10 and 20. Furthermore, this deformation may also affect the connection status between components (not shown) in module 401 and wiring board 1 or semiconductor elements 10 and 20.

[0038] Therefore, this embodiment suppresses deformation of the wiring board 1 by reducing the volume of the middle portion 33 and the ends 36 and 37, thereby providing a module with excellent mechanical properties. Preferred options for reducing the volume of the middle portion 33 and the ends 36 and 37 will be described below.

[0039] Figure 2A It is an enlarged view of the cross-sectional view of module 400, including the middle part 33. Figure 2B This is an enlarged view of the cross-sectional view of module 400, including the portion at end 36 or 37. For simplicity, refer to... Figure 2B The components associated with semiconductor element 10 and the components associated with semiconductor element 20 will be described similarly. Figure 2BIn the figures, elements associated with semiconductor element 10 (e.g., end 36 of the portion forming contour 300 near semiconductor element 10) are indicated by reference numerals without parentheses. Elements associated with semiconductor element 20 (e.g., end 37 of the portion forming contour 300 near semiconductor element 20) are indicated by reference numerals with parentheses.

[0040] Semiconductor element 10 has a lower surface 101 facing the wiring board 1, an upper surface 102 opposite to the lower surface 101, and a side surface 103 facing the semiconductor element 20.

[0041] Semiconductor element 20 has a lower surface 201 facing the wiring board 1, an upper surface 202 opposite to the lower surface 201, and a side surface 203 facing the semiconductor element 10.

[0042] The adhesive 30 has a bonding surface 301 for bonding to the semiconductor element 10. The bonding surface 301 has a bonding region of the adhesive 30 for bonding to the lower surface 101 of the semiconductor element 10 and a bonding region of the adhesive 30 for bonding to the side surface 103 of the semiconductor element 10. The end of the bonding surface 301 near the side surface 103 is an inner end 313. (As in...) Figure 2A In the example, the inner end 313 can be located on the side facing 103, but can alternatively be located on the top 102.

[0043] The adhesive 30 has a bonding surface 302 for bonding to the semiconductor element 20. The bonding surface 302 has a bonding region of the adhesive 30 for bonding to the lower surface 201 of the semiconductor element 20 and a bonding region of the adhesive 30 for bonding to the side surface 203 of the semiconductor element 20. The end of the bonding surface 302 near the side surface 203 is an inner end 323. (As in...) Figure 2A In the example, the inner end 323 can be located on the side facing 203, but can alternatively be located on the top 202.

[0044] The middle portion 33 of the adhesive 30 has a top surface 34 opposite to the wiring board 1. Typically, the top surface 34 is concave.

[0045] The adhesive 30 has a relay portion 35 located in the Z direction between the intermediate portion 33 and the wiring board 1. The relay portion 35 is not located between the semiconductor element 10 and the semiconductor element 20 in the X direction, and is not located between the semiconductor element 10 and the wiring board 1 or between the semiconductor element 20 and the wiring board 1 in the Z direction. The intermediate portion 33 and the lower portion 31 are continuous with each other via the relay portion 35. The intermediate portion 33 and the lower portion 32 are continuous with each other via the relay portion 35.

[0046] The adhesive 30 has a bonding surface 303 that bonds to the wiring board 1. The bonding surface 303 has a lower portion 31 and 32, a relay portion 35, and ends 36 and 37 of the adhesive 30.

[0047] like Figure 2B As shown, semiconductor element 10 has a non-facing side 104 that does not face semiconductor element 20. Of the four sides of semiconductor element 10, the non-facing side 104 can be any of the three sides other than the facing side 103, but is generally the side opposite to the facing side 103.

[0048] like Figure 2B As shown, semiconductor element 20 has a non-facing side 204 that does not face semiconductor element 10. Of the four sides of semiconductor element 20, the non-facing side 204 can be any of the three sides other than the facing side 203, but is typically the side opposite to the facing side 203.

[0049] In other words, typically, facing sides 103 and 203 are located between non-facing sides 104 and 204 in the X direction.

[0050] The end of the mating surface 301 near the non-facing side 104 is the outer end 312. (As in...) Figure 2B In the example, the outer end 312 may be located on the non-facing side 104 or the bottom 101, but may alternatively be located on the top 102. When the outer end 312 is located on the non-facing side 104, the bonding surface 301 has an area of ​​adhesive 30 bonded to the non-facing side 104 of the semiconductor element 10. In some embodiments, the adhesive 30 is not bonded to at least a portion of the top 102.

[0051] The end of the mating surface 302 near the non-facing side 204 is the outer end 322. (As in...) Figure 2B In the example, the outer end 322 may be located on the non-facing side 204 or the bottom 201, but may alternatively be located on the top 202. When the outer end 322 is located on the non-facing side 204, the bonding surface 302 has a region of adhesive 30 bonded to the non-facing side 204 of the semiconductor element 20. In some embodiments, the adhesive 30 is not bonded to at least a portion of the top 202. The outer end 312 is a portion of the end 36 and is exposed to the space. The outer end 322 is a portion of the end 37 and is exposed to the void space.

[0052] The edge of the mating surface 303 near the non-facing side 104 is the outer edge 311. The edge of the mating surface 303 near the non-facing side 204 is the outer edge 321. The outer edge 311 is a portion of the end 36 and is exposed to the void space. The outer edge 321 is a portion of the end 37 and is exposed to the void space.

[0053] The portion of the adhesive 30 exposed in the gap space, specifically the connecting outer edge 311 and outer end 312, forms the end face of end 36. The portion of the adhesive 30 exposed in the gap space, specifically the connecting outer edge 321 and outer end 322, forms the end face of end 37. The surface of the adhesive 30 exposed in the gap space may include the upper surface 34 of the intermediate portion 33; however, in some embodiments, the upper surface 34 need not be exposed in the gap space.

[0054] Figure 2A and Figure 2B A portion of the outline 100 of the semiconductor element 10 projected in the Z direction onto a plane including the mounting surface 2 is shown (a portion of the outline 100 or 200 in a certain cross section). Figure 2A The inner ends 313 and 323 shown are also in a specific cross section, and are part of the inner ends 313 and 323. Figure 2B The outer ends 312 and 322 shown are also portions of the outer ends 312 and 322 in a specific cross section. Figure 2B The outer edges 311 and 321 shown are also portions of the outer edges 311 and 321 in a specific cross section.

[0055] Figure 2A The width Dc of the intermediate portion 33 defined by semiconductor element 10 and semiconductor element 20 in the X direction is shown. The width Dc of the intermediate portion 33 corresponds to the spacing between semiconductor element 10 and semiconductor element 20 in the X direction. More specifically, the width Dc of the intermediate portion 33 corresponds to the distance between the facing side 103 of semiconductor element 10 facing semiconductor element 20 and the facing side 203 of semiconductor element 20 facing semiconductor element 10.

[0056] Figure 2A and Figure 2B The thickness Ta of the lower part 31 in the Z direction and the thickness Tb of the lower part 32 in the Z direction are shown.

[0057] Figure 2A and Figure 2B The thickness Tc of semiconductor element 10 in the Z direction and the thickness Td of semiconductor element 20 in the Z direction are shown. The thicknesses Tc and Td can be, for example, 100 μm or more, 300 μm or more, 500 μm or more, 5 mm or less, 3 mm or less, 2 mm or less, or 1 mm or less.

[0058] Figure 2A and Figure 2B The thickness Te of the wiring board 1 in the Z direction is shown. The thickness Te is, for example, 100 μm or more, 300 μm or more, 500 μm or more, 5 mm or less, 3 mm or less, 2 mm or less, or 1 mm or less.

[0059] exist Figure 2A In the diagram, the distance from the mating surface 303 to the inner end 313 in the Z direction is shown as the height Hc. Figure 2A In the figure, the distance from the bonding surface 303 to the inner end 323 in the Z direction is shown as the height Hd. The height Hc can be defined as the distance in the Z direction from the bonding surface to the point where the middle portion 33 of the adhesive 30 meets the edge of the semiconductor element 10 (or semiconductor element 20).

[0060] exist Figure 2A In the diagram, the distance from mounting surface 2 to the top 102 in the Z direction is shown as height He. Figure 2A In the figure, the distance from the mounting surface 2 to the top 202 in the Z direction is shown as the height Hf.

[0061] exist Figure 2B In the figure, the distance from the mating surface 303 to the outer end 312 in the Z direction is shown as the height Ha. Figure 2B In the figure, the distance from the mating surface 303 to the outer end 322 in the Z direction is shown as the height Hb.

[0062] exist Figure 2B The diagram shows the distance Da from the portion of profile 100 corresponding to the non-facing side 104 to the outer edge 311. Figure 2B The figure shows the distance Db from the portion of the profile 200 corresponding to the non-facing side 204 to the outer edge 321.

[0063] exist Figure 2B The diagram shows a range Roa extending outward from the portion of profile 100 corresponding to the non-facing side 104 up to a distance Oa. Figure 2B The diagram shows a range Ria extending inward from the portion of profile 100 corresponding to the non-facing side 104 up to a distance Ia. The sum of range Roa and range Ria is shown as range Ra. Figure 2B The diagram shows a range Rob extending outward from the portion of contour 200 corresponding to the non-facing side 204 up to a distance of Ob. Figure 2B The diagram shows the range Rib extending inward from the portion of contour 200 corresponding to the non-facing side 204 up to a distance Ib. The sum of range Rob and range Rib is shown as range Rb.

[0064] exist Figure 2B The diagram shows the straight-line distance La from the outer end 312 to the outer edge 311. Figure 2B The figure shows the straight-line distance Lb from the outer end 322 to the outer edge 321.

[0065] exist Figure 2BThe diagram shows the distance Ea from the portion of profile 100 corresponding to the non-facing side 104 to the end face 4. Figure 2B The figure shows the distance Eb from the portion of profile 200 corresponding to the non-facing side 204 to the end face 4.

[0066] exist Figure 2B The image shows a position located at a distance Ga outward from the portion of profile 100 corresponding to the non-facing side 104. Figure 2B The diagram shows the location at a distance Gb from the portion of profile 200 corresponding to the non-facing side 204. Distances Ga and Gb can be 5 mm or less, 3 mm or less, 2 mm or less, or 1 mm or less. Distance Ga can be equal to or greater than height He, or less than height He. Distance Gb can be equal to or greater than height Hf, or less than height Hf.

[0067] The characteristic of this embodiment is that the width Dc is small. For example, the width Dc is less than the sum of the thicknesses Ta and Tb (Dc < (Ta + Tb)). The lower portions 31 and 32 are formed as the liquid adhesive penetrates through capillary action. In other words, the thicknesses Ta and Tb allow capillary action to occur. The gap between semiconductor element 10 and semiconductor element 20 is set such that the width Dc satisfies Dc < (Ta + Tb). This allows the intermediate portion 33 between semiconductor element 10 and semiconductor element 20 to be formed by the liquid adhesive through capillary action between semiconductor element 10 and semiconductor element 20. The liquid surface of the adhesive formed at this time forms a concave meniscus, which results in the upper portion 34 being concave.

[0068] The width Dc can be, for example, 1 mm or less, 500 μm or less, 300 μm or less, 250 μm or less, 200 μm or less, or 150 μm or less. The width Dc can also be, for example, 10 μm or more, 20 μm or more, or 50 μm or more. The thicknesses Ta and Tb can be, for example, 500 μm or less, 250 μm or less, 150 μm or less, 100 μm or less, or 75 μm or less. The thicknesses Ta and Tb can also be, for example, 10 μm or more, 20 μm or more, or 50 μm or more.

[0069] The outer edge 311 can be located within the range Ra. Figure 2BIn the example shown, the outer edge 311 is within the range Roa, but may alternatively be within the range Ria. When the outer edge 311 is within the range Roa, the non-facing side 104 overlaps with the bonding surface 303 where the adhesive 30 is bonded to the wiring board 1 in the Z direction. When the outer edge 311 is within the range Ria, at least a part of the portion of the contour 100 corresponding to the non-facing side 104 does not overlap with the bonding surface 303 where the adhesive 30 is bonded to the wiring board 1 in the Z direction.

[0070] The distance Oa for defining the range Roa may be less than the distance Dc (Oa < Dc). The distance Ia for defining the range Ria may be less than the distance Dc (Ia < Dc). In other words, the distance Da from the portion of the contour 100 corresponding to the non-facing side 104 to the outer edge 311 may be less than the width Dc (Da < Dc).

[0071] The outer edge 321 may be within the range Rb. In Figure 2B In the example shown, the outer edge 321 is within the range Rob, but may alternatively be within the range Rib.

[0072] When the outer edge 321 is within the range Rob, the non-facing side 204 overlaps with the bonding surface 303 where the adhesive 30 is bonded to the wiring board 1 in the Z direction. When the outer edge 321 is within the range Rib, at least a part of the portion of the contour 200 corresponding to the non-facing side 204 does not overlap with the bonding surface 303 where the adhesive 30 is to be bonded to the wiring board 1 in the Z direction.

[0073] The distance Ob for defining the range Rob may be less than the distance Dc (Ob < Dc). The distance Ib for defining the range Rib may be less than the distance Dc (Ib < Dc). In other words, the distance Db from the portion of the contour 200 corresponding to the non-facing side 204 to the outer edge 321 may be less than the width Dc (Db < Dc).

[0074] The distances Da and Db may be, for example, less than 1,000 μm, less than 500 μm, less than 300 μm, less than 250 μm, less than 200 μm, less than 150 μm, equal to or greater than 20 μm, or equal to or greater than 50 μm.

[0075] The height Ha may be less than the height Hc (Ha < Hc). The height Hb may be less than the height Hd (Hb < Hd).

[0076] The height Hc may be equal to or less than the height He (Hc ≤ He). The height Hd may be equal to or less than the height Hf (Hd ≤ Hf).

[0077] The length of the joint surface between the adhesive 30 and the non-facing side 104 in the Z direction may be small. The length of the joint surface between the adhesive 30 and the non-facing side 104 in the Z direction can be expressed as the difference between the height Ha and the thickness Ta. The difference between the height Ha and the thickness Ta can be less than the thickness Tc ((Ha - Ta) < Tc). The difference between the height Ha and the thickness Ta can be less than the width Dc ((Ha - Ta) < Dc). The difference between the height Ha and the thickness Ta can be less than the thickness Ta ((Ha - Ta) < Ta).

[0078] The length of the joint surface between the adhesive 30 and the non-facing side 204 in the Z direction may be small. The length of the joint surface between the adhesive 30 and the non-facing side 204 in the Z direction can be expressed as the difference between the height Hb and the thickness Tb. The difference between the height Hb and the thickness Tb can be less than the thickness Td ((Hb - Tb) < Td). The difference between the height Hb and the thickness Tb can be less than the width Dc ((Hb - Tb) < Dc). The difference between the height Hb and the thickness Tb can be less than the thickness Tb ((Hb - Tb) < Tb).

[0079] The height Ha can be less than the width Dc (Ha < Dc). The height Hb can be less than the width Dc (Hb < Dc).

[0080] The straight-line distance La can be less than times the width Dc (La < ×Dc).

[0081] The straight-line distance Lb can be less than times the width Dc (Lb < ×Dc). This is based on the fact that when the lengths of two adjacent sides of a right-angled isosceles triangle are set to Ha (Hb) = Dc and Da (Db) = Dc, the length of the hypotenuse of the right-angled isosceles triangle is expressed as ×Dc. The straight-line distances La and Lb can be less than the width Dc.

[0082] In the Figure 2B example, the distances Ea and Eb are greater than the width Dc (Ea > Dc, Eb > Dc). In this case, the warping tendency of the wiring board 1 tends to be large. Therefore, the advantageous effects of this embodiment are more significant. To reduce the warping of the wiring board 1, the distances Ea and Eb can be less than the width Dc (Ea < Dc, Eb < Dc).

[0083] In Figure 2BIn the example where the thickness Te is less than the thicknesses Tc and Td (Te < Tc, Te < Td), the wiring board 1 tends to warp. Therefore, the advantageous effects of this embodiment are more significant. To reduce the warping of the wiring board 1, the thickness Te can be greater than the thicknesses Tc and Td (Te > Tc, Te > Td).

[0084] The wiring board 1 will be described. The wiring board 1 includes a base material and a wiring material. When the wiring board 1 is a printed wiring board, the base material is a resin base material such as glass epoxy resin, and the wiring material is a printed line or through-hole made of copper or a similar material. The base material of the wiring board 1 is not limited to a resin base material and can also be a ceramic base material, a silicon base material, a glass base material (glass core), or a metal base material. An insulating layer and a wiring layer can be formed on such a base material, and through-holes can be formed in the base material to constitute the wiring board 1. The wiring board 1 can be a mother board or an interposer. When the wiring board 1 is an interposer, the opposite surface 3 of the wiring board 1 can be connected to the mother board. The wiring board 1 used as an interposer can be a silicon interposer or a glass interposer. The silicon interposer can have through-silicon vias (TSVs). The glass interposer can have through-glass vias (TGVs).

[0085] The semiconductor elements 10 and 20 will be described. Figure 1B The semiconductor element 10 (20) shown is a packaged semiconductor element. The semiconductor element 10 (20) includes a semiconductor layer 11 (21), a support substrate 12 (22) that supports the semiconductor layer 11 (21), and a sealing resin 13 (23) that encapsulates the semiconductor layer 11 (21). Electrodes and wirings are provided on the support substrate 12 (22). The semiconductor layer 11 (21) is electrically connected to the support substrate 12 (22) by wire bonding or flip-chip bonding. The thickness of the sealing resin 13 (23) on the semiconductor layer 11 is about 100 μm to 1 mm. In this case, the distance between the upper surface 102 (202) and the semiconductor layer 11 (21) can be about 100 μm to 1 mm. The semiconductor layer 11 and the semiconductor layer 21 can be formed of a Group-IV semiconductor or a compound semiconductor. The semiconductor layer 11 and the semiconductor layer 21 can be formed of a single-crystal semiconductor or a polycrystalline semiconductor. Typical semiconductor layers 11 and 21 are single-crystalline silicon layers.

[0086] The outer edge of the bonding surface 303 can be located within the preferred range Ra or Rb. For example, 25% or more, preferably 50% or more, more preferably 75% or more, and still more preferably 90% or more of the portion of the contour 100 corresponding to a non-facing surface is located within the range Ra or Rb.

[0087] In Figure 1A and Figure 1BIn the example, a total of two semiconductor elements 10 and 20 are arranged facing each other via a central portion 33 in one row in the X direction and two columns in the Y direction; however, this disclosure is not limited thereto. Alternatively, a total of M×N semiconductor elements can be arranged facing each other via a central portion in M ​​(M≥1) rows in the X direction and N (N>1) columns in the Y direction. In this case, one of the two opposing semiconductor elements in the M×N semiconductor elements can be considered as semiconductor element 10, and the other can be considered as semiconductor element 20.

[0088] For example, a total of four semiconductor elements in two rows and two columns can be arranged to face each other via the central portion 33. In this case, two of the four sides of each semiconductor element can be used as facing surfaces to other semiconductor elements, and the remaining two sides can be used as non-facing surfaces. In this case, 50% or less of the contour of each semiconductor element can be used as a non-facing surface. Therefore, the outer edge of the bonding surface 303 can be located within a preferred range Ra or Rb, for example, 12.5% ​​or more, preferably 25% or more, more preferably 37.5% or more, and even more specifically 45% or more of the contour of each semiconductor element is located within the range Ra or Rb.

[0089] For example, a total of nine semiconductor elements can be arranged in three rows and three columns, facing each other via the central portion 33. In this case, the semiconductor elements located in the second row and second column do not have a non-facing surface. The four semiconductor elements located in the first row and second column, the second row and first column, the second row and third column, and the third row and second column can each have three of their four sides used as facing surfaces, and the remaining side used as a non-facing surface relative to the other semiconductor elements. The four semiconductor elements located in the first row and first column, the first row and third column, the third row and first column, and the third row and third column can each have two of their four sides used as facing surfaces, and the remaining two sides used as non-facing surfaces.

[0090] Reference Figure 3A and Figure 3B A second embodiment of this disclosure is described. Aspects not described in the second embodiment may be the same as those in other embodiments.

[0091] Figure 3A This is a top view of module 400. Figure 3B It is along Figure 3A The diagram shows a cross-sectional view of module 400 taken by line IIIB-IIIB.

[0092] Semiconductor element 10 (20) may include semiconductor layer 11 (21), connection structure 15 (25) formed on the front side of semiconductor layer 11 (21), and insulating film 16 (26) formed on the back side of semiconductor layer 11 (21). Semiconductor layer 11 (21) is similar to the semiconductor layer in the first embodiment. Connection structure 15 (25) includes an insulator such as an interlayer insulating film and a conductor such as wiring or electrode. Insulating film 16 (26) acts as a protective film and includes an inorganic insulating layer and / or an organic insulating layer. The inorganic insulating layer may contain the native oxide of semiconductor layer 11 (21). Top surface 102 (202) of semiconductor element 10 (20) may be formed of insulating film 16 (26). The thickness of insulating film 16 (26) on semiconductor layer 11 (21) is about 1 nm to 100 μm. In this case, the distance between top surface 102 (202) and semiconductor layer 11 (21) may be 100 μm or less. The insulating film 16 (26) can be omitted. In this case, the top 102 (202) of the semiconductor element 10 (20) can be formed by the semiconductor layer 11 (21).

[0093] The second embodiment employs a configuration where Te is greater than each of Tc and Td (Te>Tc, Te>Td). The second embodiment employs a configuration where Ea is greater than Dc (Ea>Dc) for the three non-facing sides 104, and a configuration where Eb is greater than Dc (Eb>Dc) for the three non-facing sides 204. Forty percent or more (80% or more in this example) of the outer edge 311 lies within range Roa, and 40% or more (80% or more in this example) of the outer edge 321 lies within range Rob.

[0094] Multiple electronic components 40 are mounted on the mounting surface 2 of the wiring board 1. Electronic components 40 include electronic components 41, 42, 43, and 44. Electronic components 40 are passive components and are typically chip components. Electronic components 40 include resistors, capacitors, and inductors. Electronic components 40 are used to ensure the proper operation of semiconductor elements 10 and 20, and examples of them include terminating resistors, bypass capacitors, and ferrite beads. Some of the electronic components 40 may be arranged in a manner different from a reference. Figure 2BThe position at the described distance Ga (Gb) is closer to the semiconductor elements 10 (20). In the present embodiment, compared with the amount of the adhesive 30 located at the position corresponding to the distance Ga (Gb), the amount of the adhesive 30 located closer to the semiconductor elements 10 (20) can be reduced, which reduces the limitation of the arrangement of the electronic components 40 due to the adhesive 30 and enables high-density mounting of the electronic components 40. In addition, since the distance between the electronic components 40 and the semiconductor elements 10 and 20 can be reduced, the impedance between the electronic components 40 and the semiconductor elements 10 and 20 can be reduced, thereby contributing to improving the operation of the semiconductor elements 10 and 20.

[0095] Reference will be made to Figure 4A and Figure 4B to describe the third embodiment of the present disclosure. Aspects not described for the third embodiment may be the same as those of other embodiments.

[0096] Figure 4A is a top view of the module 400. Figure 4B is along Figure 4A a cross-sectional view of the module 400 taken along the line IVB-IVB shown.

[0097] The third embodiment employs a configuration in which Te is less than each of Tc and Td (Te < Tc, Te < Td). The third embodiment employs a configuration in which Ea is less than Dc (Ea < Dc) for three non-facing sides 104 and a configuration in which Eb is less than Dc (Eb < Dc) for three non-facing sides 204. Forty percent or more (80% or more in this example) of the outer edge 311 is located within the range Roa, and 40% or more (80% or more in this example) of the outer edge 321 is located within the range Rob.

[0098] Reference will be made to Figure 5A and Figure 5B to describe the fourth embodiment of the present disclosure. Aspects not described for the fourth embodiment may be the same as those of other embodiments.

[0099] Figure 5A is a top view of the module 400. Figure 5B is along Figure 5A a cross-sectional view of the module 400 taken along the line VB-VB shown.

[0100] The fourth embodiment adopts a configuration in which Te is less than each of Tc and Td (Te < Tc, Te < Td). For the three non-facing sides 104, the fourth embodiment adopts a configuration in which Ea is less than Dc (Ea < Dc), and for the three non-facing sides 204, the fourth embodiment adopts a configuration in which Eb is less than Dc (Eb < Dc). Forty percent or more (in this example, 80% or more) of the outer edge 311 is located within the range Ria, and 40% or more (in this example, 80% or more) of the outer edge 321 is located within the range Rib.

[0101] Reference will be made Figure 6A to Figure 6B describe the fifth embodiment of the present disclosure. Aspects not described for the fifth embodiment may be the same as those of other embodiments.

[0102] Figure 6A and Figure 6B are cross-sectional views of the module 400 according to the fifth embodiment, showing its manufacturing process.

[0103] As Figure 6A shown, a plurality of connection members 5 are provided on the opposite surface 3 of the wiring board 1. The circuit board 6 is arranged on the side of the wiring board 1 opposite to the mounting surface 2. The electronic component 50 is mounted on the mounting surface 8 of the circuit board 6. The electronic component 50 may be a semiconductor element or a passive element. For example, the semiconductor elements 10 and 20 may be memories, and the electronic component 50 may be a processor.

[0104] As Figure 6B shown, the wiring board 1 and the circuit board 6 are electrically connected by a plurality of connection members 5. According to this embodiment, since the warping of the wiring board 1 is suppressed, the electrical connection between the circuit board 6 and the wiring board 1 through the plurality of connection members 5 can be ensured with high reliability. Specifically, the open circuit failure or short circuit failure of the connection member 5 caused by the warping of the wiring board 1 is suppressed.

[0105] The electronic component 50 arranged between the wiring board 1 and the circuit board 6 may be mounted on the opposite surface 3 of the wiring board 1 instead of the mounting surface 8 of the circuit board 6. Figure 6A and Figure 6BA ball grid array (BGA) is shown as an example of the connecting member 5; however, a pin grid array (PGA), a land grid array (LGA), or a combination thereof can be used alternatively. When the circuit board 6 is a motherboard with PGA sockets, an LGA-type central processing unit (CPU) including a wiring board 1 can be mounted on the circuit board 6, wherein the wiring board 1 has an LGA on the opposite side 3, opposite to the semiconductor elements 10 and 20 used as the processor. Alternatively, the configuration disclosed in Japanese Patent Application Laid-Open No. 2024-127762 or 2023-80425 can also be used to connect the wiring board 1 and the circuit board 6.

[0106] Reference Figure 6C A sixth embodiment of this disclosure is described. Aspects not described in the sixth embodiment may be the same as those in other embodiments.

[0107] Figure 6C This is a cross-sectional view of module 400 according to the sixth embodiment.

[0108] Module 400 includes a plate-like member 60 disposed on the side of wiring board 1 opposite to semiconductor elements 10 and 20. The distance between the plate-like member 60 and semiconductor elements 10 may be less than the thickness Tc, and more preferably, less than the thickness Ta. The distance between the plate-like member 60 and semiconductor elements 20 may be less than the thickness Td, and more preferably, less than the thickness Tb. The plate-like member 60 is fixed to wiring board 1 by a fixing member 61. The spacing between the plate-like member 60 and semiconductor elements 10 and 20 may be a gap; however, as Figure 6CAs shown, an intermediate member 62 may be provided. The plate-like member 60 has at least one of thermal, electrical, optical, and mechanical functions. Examples of a plate-like member 60 with a thermal function include a heat sink. In this case, the intermediate member 62 may be thermal paste or a thermal sheet. Examples of a plate-like member 60 with an electrical function include an electromagnetic shield. Examples of a plate-like member 60 with an optical function include a filter and an optical cover. The intermediate member 62 for a plate-like member 60 with an optical function may be a light-transmitting bonding material. The intermediate member 62 may contact the upper surface 34 of the intermediate portion 33. In any plate-like member 60, according to this embodiment, warping of the wiring board 1 is suppressed, thereby enabling proper positional control of the semiconductor elements 10 and 20 relative to the plate-like member 60 and allowing the function of the plate-like member 60 to be fully presented. For example, when the plate-like member 60 is a heat sink, warping of the wiring board 1 may cause gaps between the semiconductor elements 10 and 20 and the plate-like member 60, thereby reducing heat conduction therebetween. By suppressing the warping of the wiring board 1, the upper surface 102 of semiconductor element 10 and the upper surface 202 of semiconductor element 20 can be substantially coplanar with each other, thereby reducing the gap between semiconductor elements 10 and 20 and plate member 60 and improving the thermal conduction therebetween. When plate member 60 has optical functions, misalignment of the optical path between plate member 60 and semiconductor elements 10 and 20 can be reduced.

[0109] Reference Figures 7A to 7D A seventh embodiment of this disclosure is described. Aspects not described in the seventh embodiment may be the same as those in other embodiments.

[0110] Figures 7A to 7D A method for manufacturing module 400 is shown.

[0111] like Figure 7A As shown, semiconductor elements 10 and 20 are mounted on wiring board 1 with a spacing Gc. Masking tapes 391 and 392, used to prevent adhesive 30 from adhering, are attached to the sides of semiconductor elements 10 and 20 and the surface of wiring board 1. Masking tapes 391 and 392 have high oil repellency. Masking tapes 391 and 392 can be made of fluoroplastic films such as polytetrafluoroethylene (PTFE) or perfluoroalkoxyalkane (PFA). The distance Ga between semiconductor elements 10 and 20 and the masking tape 392 attached to wiring board 1 is less than the spacing Gc between semiconductor elements 10 and 20. The distance Gb between the end of masking tape 391 and the surface of wiring board 1 is less than the spacing Gc between semiconductor elements 10 and 20.

[0112] Figure 7BThis diagram illustrates the steps of injecting adhesive 390 into the underside of semiconductor elements 10 and 20. Adhesive 390 is a thermosetting resin referred to as an underfill. When adhesive 390, contained in syringe 380, is applied between semiconductor elements 10 and 20 and wiring board 1, specifically to the periphery of the ends of semiconductor elements 10 and 20, adhesive 390 flows under semiconductor elements 10 and 20 by capillary action, thereby forming adhesive portions 310 and 320. Adhesive 390 also flows by capillary action to the gap between semiconductor elements 10 and 20, thereby forming adhesive portion 330. As adhesive 390 flows under the underside of semiconductor elements 10 and 20 to cover the entire underside, adhesive 390 seeps out to an edge different from the edge where adhesive 390 was applied, thereby allowing confirmation that adhesive 390 has flowed under the entire underside. At this time, due to the oil-repellent properties of the masking tape 391, adhesive 390 adhered to the masking tape 391 is repelled and flows out. Therefore, the contact length of the adhesive 390 that contacts the sides of the semiconductor elements 10 and 20 is equal to or less than the area exposed from the shielding strip 391, i.e., the distance Gb between the end of the shielding strip 391 and the surface of the wiring board 1.

[0113] Figure 7C This diagram shows the state of the adhesive 390 after it has been cured by heating. Due to the oil-repellent properties of the shielding tape 392, the adhesive 390 that has flowed out of the area where the semiconductor elements 10 and 20 are mounted and has been dispersed on the shielding tape 392 forms droplets, thereby forming residue 393, which then cures in this state. Therefore, the contact length of the adhesive 390 attached to the wiring board 1 is equal to or less than the distance Ga between the semiconductor elements 10 and 20 and the shielding tape 392.

[0114] Figure 7D This diagram shows the state after the adhesive 390 has cured and the masking strips 391 and 392 have been removed. The granular resin formed by the cured droplet residue 393 can be removed simultaneously with the removal of the masking strips 391 and 392. The length of the adhesive 390 in contact with the wiring board 1 outside the electronic component mounting area is set to be equal to or less than the distance Ga between the semiconductor elements 10 and 20 and the masking strip 392, that is, less than the spacing Gc between the semiconductor elements 10 and 20.

[0115] The method for controlling the shape of ends 36 and 37 is not limited to using the shielding tapes 391 and 392 as described above. For example, excess adhesive can be wiped off. The portion with excess adhesive can be separated by cutting the wiring board 1 or by other methods.

[0116] Reference Figure 8 The eighth embodiment of this disclosure is described. Aspects not described in the eighth embodiment may be the same as those in other embodiments.

[0117] The module 400 of this embodiment can be used in various devices or systems in the form of various electronic modules. Figure 8 A camera system 1000 is shown, comprising an electronic device 800 (camera body) and an optical device 900 (interchangeable lens). The electronic device 800 includes a module 600 (image capture module), a module 400 (processing module), and a module 830 (display module). Module 600 is electrically connected to module 400. Module 830 is electrically connected to module 400. For example, the electronic device 800 includes a flexible wiring member 500 connecting module 400 and module 600. For example, the electronic device 800 includes a flexible wiring member 700 connecting module 400 and module 830.

[0118] Module 600 includes an image sensor 610 and a wiring board 620 on which the image sensor 610 is mounted. Module 400 includes a circuit board 6, a wiring board 1, and semiconductor elements 10 and 20. Module 830 includes a display element such as a liquid crystal display (LCD) or an organic light-emitting diode (OLED).

[0119] Circuit board 6 has a control element 70 mounted thereon. Video signals acquired by image sensor 610 are transmitted to flexible wiring member 500 and processed by module 400. The display element of module 830 displays an image corresponding to the video signal. Control element 70 controls these operations.

[0120] Electronic device 800 includes mounting member 890. Mounting member 890 has optical device 900 mounted thereon. Optical device 900 includes lens optical system 910 and lens barrel 920 for housing lens optical system 910.

[0121] Here, the electronic device is exemplified as a camera system of a video device; however, the module of this embodiment can be applied to various types of devices. For example, the electronic device including the module can be an information device such as a smartphone or personal computer, or a communication device such as a modem or router. Alternatively, the module can be used in office equipment or printing equipment such as printers, copiers, or scanners; medical devices such as X-ray imaging equipment or endoscopes; industrial equipment such as robots or semiconductor manufacturing equipment; or transportation equipment such as vehicles, aircraft, or ships.

[0122] In this embodiment, the semiconductor elements 10 and 20 in module 400 can have various functions, and the functions of semiconductor elements 10 and 20 can be the same or different.

[0123] Examples of semiconductor elements 10 and 20 include memory (storage element), processor (computing element), sensor (detection element), and display (display element). Other examples of semiconductor elements 10 and 20 include communication elements, control elements, and power supply elements.

[0124] Examples of memory (storage elements) include Dynamic Random Access Memory (DRAM) and Flash Memory. Examples of processors (computing elements) include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Digital Signal Processors (DSPs), and Image Signal Processors (ISPs). Examples of sensors (detection elements) include Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, Single-Photon Avalanche Diode (SPAD) sensors, and Microelectromechanical Systems (MEMS) sensors. Examples of display elements include Liquid Crystal Displays (LCDs) and Organic Electroluminescent (EL) Displays.

[0125] Modules of multiple semiconductor components mounted on a single printed circuit board can be incorporated into various types of electronic devices. For example, there are semiconductor mounting structures called Package On Package (PoP), where semiconductor packages such as memory devices and application-specific integrated circuits (ASICs) are vertically stacked. In a PoP, the ASIC is typically provided in the lower semiconductor package, and the memory device is typically provided in the upper semiconductor package. In some types of PoP, multiple semiconductor packages to be mounted in the upper section are mounted on a single printed circuit board to form a module, and are subsequently stacked on top of the lower semiconductor package. Therefore, by forming multiple modules, multiple semiconductor packages can be mounted in the upper section, thereby enhancing the performance of the PoP.

[0126] A chiplet is a semiconductor module in which multiple semiconductor chips are mounted on a single printed circuit board. Chipslets are semiconductor modules formed by individually manufacturing semiconductor chips (such as CPUs or memory devices) with different processing nodes and mounting them on a single printed circuit board. By individually manufacturing multiple semiconductor chips, defect-free products can be selected and mounted on the printed circuit board, thereby increasing the yield of semiconductor packages. Similarly, in some types of optical sensor modules, multiple semiconductor elements are mounted on a single printed circuit board to function as a single sensor module. By manufacturing small semiconductor elements, selecting defect-free semiconductor elements, and forming the module using the selected semiconductor elements, sensor modules with large light-receiving areas can be manufactured without using large optical sensors with low yields.

[0127] Next, the structure for connecting semiconductor components and the printed circuit board when semiconductor components, such as semiconductor packages, semiconductor chips, or semiconductor devices, are mounted on the printed circuit board will be described. The semiconductor package used on the upper segment of the PoP is a ball grid array (BGA) type semiconductor package with a small mounting area, and is connected to the printed circuit board via solder balls located below the BGA. In the semiconductor chips used in the die, multiple semiconductor chips are mounted close together, making wiring connections unusable; therefore, they are mounted on the printed circuit board via bumps or copper pillars flip chips.

[0128] In optical sensors, similar to chip wafers, sensor chips are flip-chip mounted to be installed close to each other. This semiconductor module mounting structure typically employs a resin called an underfill, which is injected and cured between the semiconductor element and the printed circuit board to enhance the connection and ensure connection reliability. Compared to methods that seal the entire semiconductor element with molding resin, this reinforced structure (such as an underfill) where only the gap between the semiconductor element and the printed circuit board is sealed with resin has the following advantages: heat dissipation components, such as heat sinks, can be directly attached to the semiconductor element, thus promoting thermal management. Furthermore, in the sensor module, the light-receiving surface is not sealed with resin, thereby ensuring optical properties.

[0129] In the reinforcement step using an underfill, liquid resin is applied near the semiconductor components on a printed circuit board. The applied resin flows between the semiconductor components and the printed circuit board via capillary action, flowing over the entire underside of the semiconductor components, with excess resin flowing out of the area where the semiconductor components are mounted and spreading on the printed circuit board and the sides of the semiconductor components. After the resin has flowed over the entire underside of the semiconductor components, the entire module is heated in an oven or other heater to cure the resin, thus completing the reinforcement step. However, excess resin, i.e., resin on the printed circuit board outside the semiconductor component mounting area, also cures. The excess resin cured outside the semiconductor component mounting area expands or contracts due to changes in ambient temperature, thus affecting the thermal deformation of the entire module.

[0130] For example, when a module mounted on the upper section of the PoP warps significantly, bonding failure is more likely to occur at the intermediate solder joint portion during the process of stacking the module on the lower semiconductor package. When a die-type semiconductor module warps significantly, bonding failure is more likely to occur at the solder joint portion during the process of mounting the die onto the motherboard.

[0131] In an optical sensor module, the parallelism between the faces of semiconductor sensors arranged in multiple rows may deviate, leading to degradation of the optical sensor's characteristics. According to this embodiment, during the process of mounting the module on a printed circuit board, mounting failures due to thermal deformation can be suppressed. Furthermore, degradation of the optical sensor module's characteristics due to thermal deformation can also be suppressed.

[0132] In response to the above problems, this embodiment provides a structure configured to suppress thermal deformation of a module in which multiple semiconductor elements are mounted on a printed circuit board and the spacing between the semiconductor elements and the printed circuit board is sealed with resin.

[0133] According to this embodiment, thermal deformation of the module can be reduced by making the length of the resin in contact with the printed circuit board outside the semiconductor element mounting area smaller than the spacing between the semiconductor elements.

[0134] Thermal deformation of the module can be further reduced by making the length of the resin in contact with the sides of the semiconductor elements smaller than the spacing between the semiconductor elements. When the spacing between the semiconductor elements is 200 μm or less, the effect of suppressing thermal deformation can be further enhanced.

[0135] This effect allows for the suppression of mounting failures due to thermal deformation during the process of mounting the module on the printed circuit board. It also suppresses the degradation of the optical sensor module's characteristics due to thermal deformation.

[0136] The above embodiments can be appropriately modified without departing from the spirit of this disclosure. For example, two or more embodiments can be combined. Furthermore, certain elements of at least one embodiment can be deleted or replaced. New elements can be added to at least one embodiment.

[0137] It should be noted that the disclosure of this specification includes not only what is explicitly described herein, but also everything that can be understood from this specification and the accompanying drawings. Furthermore, the disclosure of this specification includes supplements to the various concepts described herein. In other words, when this specification describes, for example, "A is B," even if the case of "A is not B" is omitted, this specification is considered to disclose the case of "A is not B," because the premise is that the case of "A is not B" is inherently considered when describing "A is B."

[0138] Regarding the specific numerical ranges illustrated in this specification, the description "e to f" (where e and f are numbers) means "equal to or greater than e" and / or "equal to or less than f". When specific numerical ranges such as "i to j" and "m to n" (where i, j, m, and n are numbers) are described together, the combination of the lower and upper limits is not limited to pairs of i and j or m and n. For example, the lower and upper limits of the corresponding ranges can be combined in various ways. In other words, when the ranges "i to j" and "m to n" are described together, the range can be considered as "i to n" or "m to j" as long as no narrowing occurs. Furthermore, "equal to or greater than e" means e itself or a value greater than e (i.e., exceeding e), and a value greater than e can be used instead of e. Similarly, "equal to or less than f" means f itself or a value less than f (i.e., less than f), and a value less than f can be used instead of f. Example

[0139] Reference Figure 4A and Figure 4B An example of a module 400 according to a third embodiment is described. The mounting surface 2 of the wiring board 1 has a long side of 38 mm and a short side of 18 mm. The thickness Te of the wiring board 1 is 1 mm. Semiconductor elements 10 and 20 each have a profile with a long side of 14 mm and a short side of 8 mm, and have thicknesses Tc and Td of 2 mm, respectively. Semiconductor elements 10 and 20 are arranged with a spacing of 100 μm such that their short sides face each other. The distances Ea and Eb are each 5 mm. The adhesive 30 has thicknesses Ta and Tb of 80 μm, a width Dc of 100 μm, a distance Da and Db of 50 μm, a height Ha and Hb of 100 μm, and heights Hc and Hf of approximately 2 mm. This module exhibits reduced warpage of the wiring board 1 and has good mechanical properties.

[0140] The present disclosure provides a module with excellent mechanical properties.

[0141] While this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. A module comprising: A wiring board having a mounting surface; A first semiconductor element and a second semiconductor element are electrically connected to the wiring board, overlap the wiring board in a first direction perpendicular to the mounting surface, and are arranged side by side along the mounting surface in a second direction. as well as An adhesive, which bonds the wiring board, the first semiconductor element, and the second semiconductor element to the mounting surface. The adhesive comprises a first portion located between the wiring board and the first semiconductor element in the first direction, a second portion located between the wiring board and the second semiconductor element in the first direction, and a third portion located between the first semiconductor element and the second semiconductor element in the second direction. Wherein, the width Dc of the third portion defined by the first semiconductor element and the second semiconductor element in the second direction is less than the sum of the thickness Ta of the first portion in the first direction and the thickness Tb of the second portion in the first direction, and Wherein, the distance Da from at least a portion of the first profile of the first semiconductor element projected on the mounting surface in the first direction to at least a portion of the outer edge of the board bonding surface is less than the width Dc, and the board bonding surface is the bonding surface of the adhesive to the wiring board.

2. The module according to claim 1, wherein, The height Ha is less than the height Hc, wherein the height Ha is a distance in the first direction from at least a portion of the outer end of the bonding surface of the adhesive to the first semiconductor element. The height Hc is the distance in the first direction from at least a portion of the plate bonding surface to the inner end of the bonding surface of the adhesive to the first semiconductor element.

3. The module according to claim 1, in, The first semiconductor element has a first facing surface facing the mounting surface and a first opposite surface opposite to the first facing surface, and Wherein, the height Hc is equal to or less than the height He, wherein the height Hc is the distance in the first direction from at least a portion of the inner end of the bonding surface of the adhesive to the first semiconductor element, and The height He is the distance from the plate mating surface to the first opposite surface in the first direction.

4. The module according to claim 1, wherein, The straight-line distance La from at least a portion of the end of the first bonding surface of the first semiconductor element to at least a portion of the outer edge of the board bonding surface is less than the width Dc. times.

5. The module according to claim 1, wherein, The difference between the height Ha and the thickness Ta is less than the width Dc, wherein the height Ha is the distance in the first direction from the plate bonding surface to at least a portion of the outer end of the first bonding surface of the adhesive bonded to the first semiconductor element.

6. The module according to claim 1, wherein, The height Ha is less than the width Dc, wherein the height Ha is the distance in the first direction from the plate bonding surface to at least a portion of the outer end of the first bonding surface of the adhesive to the first semiconductor element.

7. The module according to claim 1, wherein, The difference between the height Ha and the thickness Ta is less than the thickness Ta, wherein the height Ha is the distance in the first direction from the plate bonding surface to at least a portion of the outer end of the first bonding surface of the adhesive bonded to the first semiconductor element.

8. The module according to claim 1, wherein, The distance Ea from at least a portion of the first contour to at least a portion of the end face of the wiring board is less than the width Dc.

9. The module according to claim 1, wherein, The thickness of the wiring board in the first direction is less than the thickness of the first semiconductor element and the second semiconductor element in the first direction.

10. The module according to claim 1, wherein, The surface of the third part opposite to the mounting surface is concave.

11. The module according to claim 1, wherein, The distance Db from at least a portion of the second profile of the second semiconductor element projected onto the mounting surface in the first direction to at least a portion of the outer edge of the board bonding surface, which serves as the bonding surface of the adhesive to the wiring board, is less than the width Dc.

12. The module according to claim 1, in, The height Hb is less than the height Hd, wherein the height Hb is a distance in the first direction from at least a portion of the outer end of the bonding surface of the adhesive to the second semiconductor element. The height Hd is the distance in the first direction from at least a portion of the plate bonding surface to the inner end of the bonding surface of the adhesive to the second semiconductor element.

13. The module according to claim 1, in, The second semiconductor element has a second facing surface facing the mounting surface and a second opposite surface opposite to the second facing surface, and Wherein, the height Hd is equal to or less than the height Hf, wherein the height Hd is at least a portion of the distance in the first direction from the plate bonding surface to the inner end of the bonding surface of the adhesive to the second semiconductor element, and The height Hf is the distance from the plate mating surface to the second opposite surface in the first direction.

14. The module according to claim 1, wherein, The straight-line distance Lb from at least a portion of the end of the second bonding surface of the second semiconductor element to at least a portion of the outer edge of the board bonding surface is less than the width Dc. times.

15. The module according to claim 1, wherein, At least one of the following conditions must be met: The width Dc is equal to or less than 200 μm; The thickness Ta and the thickness Tb are equal to or less than 100 μm; and The distance Da is equal to or less than 100 μm.

16. The module according to any one of claims 1 to 15, in, The first semiconductor element has a first facing surface facing the mounting surface and a first opposite surface opposite to the first facing surface. The second semiconductor element has a second facing surface facing the mounting surface and a second opposite surface opposite to the second facing surface. The adhesive is not bonded to at least a portion of the first opposite surface and at least a portion of the second opposite surface.

17. The module according to claim 16, wherein, At least one of the following conditions must be met: The first opposite side is formed by a first semiconductor layer included in the first semiconductor element, and the second opposite side is formed by a second semiconductor layer included in the second semiconductor element; The first opposite surface is formed by a first insulating film covering the first semiconductor layer included in the first semiconductor element, and the distance between the first opposite surface and the first semiconductor layer is equal to or less than 100 μm; as well as The second opposite surface is formed by a second insulating film covering the second semiconductor layer included in the second semiconductor element, and the distance between the second opposite surface and the second semiconductor layer is equal to or less than 100 μm.

18. The module according to any one of claims 1 to 15, further comprising: Electronic components, which are mounted on the mounting surface, Wherein, the distance from the first semiconductor element to the electronic component is equal to or less than 2 mm.

19. The module according to any one of claims 1 to 15, wherein, The first semiconductor element and the second semiconductor element are any one of a memory, a processor, a sensor, and a display.

20. The module according to any one of claims 1 to 15, further comprising: A circuit board located on the side of the wiring board opposite to the mounting surface. The wiring board and the circuit board are electrically connected to each other.

21. The module of claim 20, further comprising electronic components between the wiring board and the circuit board.

22. The module according to any one of claims 1 to 15, further comprising: A plate-like member is arranged on the side of the first semiconductor element and the second semiconductor element opposite to the wiring board. Wherein, the distance between the plate-shaped member and the first semiconductor element is less than the thickness Tc of the first semiconductor element, and Wherein, the distance between the plate-shaped member and the second semiconductor element is less than the thickness Td of the second semiconductor element.

23. A device comprising a first module and a second module, in, The first module is the module according to any one of claims 1 to 22; and The second module is electrically connected to the first module.

24. The device according to claim 23, further comprising a flexible wiring component connecting the first module and the second module.

25. The device according to claim 23, wherein, The device is any one of video equipment, printing equipment, medical equipment, and industrial equipment.

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