Via glass through hole with multi-layer organic / inorganic liner for integrated circuit device package
By lining the through-glass vias in the glass substrate with a multilayer material stack, the stress problem between the glass substrate and the conductive features is alleviated, thereby improving the mechanical stability and yield of IC device packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INTEL CORP
- Filing Date
- 2025-11-17
- Publication Date
- 2026-06-19
AI Technical Summary
During IC packaging, high stress between the glass substrate and conductive features can lead to mechanical failures and reduce packaging yield. Existing technologies are unable to effectively alleviate packaging warpage problems.
Through-glass vias (TGVs) with multi-layered material stacking linings, including inorganic and organic material layers, are formed on the glass surface using processes such as chemical vapor deposition and atomic layer deposition to buffer internal stress and reduce warping.
It effectively alleviates the stress problem between the glass substrate and the conductive features, and improves the mechanical stability and yield of IC device packaging.
Smart Images

Figure CN122249077A_ABST