Packaging substrate with components included in cavity of glass core

Abstract

A packaging substrate having components included in a cavity of a glass core is disclosed. An example device includes: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening and between the electronic component and a sidewall of the opening; and a through-glass via comprising a conductive material extending through the glass layer.

Description

Background Technology

[0001] Integrated circuit (IC) chips and / or semiconductor dies are typically connected to larger circuit boards (such as motherboards and other types of printed circuit boards) via a packaging substrate. As the size of IC chips and / or dies decreases and interconnect density increases, alternatives to traditional substrate layers are being developed to provide stable transmission of high-frequency data signals and / or increased power delivery between different circuits. One option being pursued is to implement a packaging substrate with a glass core. Attached Figure Description

[0002] Figure 1 An example integrated circuit (IC) package constructed in accordance with the teachings disclosed herein is shown.

[0003] Figure 2A It shows that it can be used Figure 1 An example glass core assembly implemented within an example packaging substrate.

[0004] Figure 2B It corresponds to Figure 2A The enlarged view of the dashed box shown illustrates an example structure of the outer surface of an example through-glass via (TGV) relative to the inner surface of the associated through-hole.

[0005] Figure 2C It corresponds to Figure 2A The enlarged view of the dashed box shown represents another example structure of the outer surface of another example TGV relative to the inner surface of the associated through hole.

[0006] Figure 2D yes Figure 2A Another example TGV top cross-sectional view is shown.

[0007] Figure 2E yes Figure 2A Another example TGV top cross-sectional view is shown.

[0008] Figure 3A It shows that it can be used Figure 1 Another example of a glass core assembly implemented within an example packaging substrate.

[0009] Figure 3B It corresponds to Figure 3A The enlarged view of the dashed box shown represents an example structure of the outer surface of an example through-glass via (TGV) relative to the inner surface of the associated through-hole.

[0010] Figure 3C It corresponds to Figure 3A The enlarged view of the dashed box shown represents another example structure of the outer surface of another example TGV relative to the inner surface of the associated through hole.

[0011] Figure 3D yes Figure 3A Another example TGV top cross-sectional view is shown.

[0012] Figure 3E yes Figure 3A Another example TGV top cross-sectional view is shown.

[0013] Figure 4-18 Manufacturing process is shown Figure 2A and / or Figure 3A Different stages in the example manufacturing process of an example glass core assembly.

[0014] Figure 19 It shows that it can be used Figure 1 Another example of a glass core assembly implemented within an example packaging substrate.

[0015] Figure 20 It shows that it can be used Figure 1 Another example of a glass core assembly implemented within an example packaging substrate.

[0016] Figure 21-27 Manufacturing process is shown Figure 19 and / or Figure 20 Different stages in the example manufacturing process of an example glass core assembly.

[0017] Figure 28 It shows that it can be used Figure 1 Another example of a glass core assembly implemented within an example packaging substrate.

[0018] Figure 29 It shows that it can be used Figure 1 Another example of a glass core assembly implemented within an example packaging substrate.

[0019] Figures 30-36 Manufacturing process is shown Figure 19 and / or Figure 20 Different stages in the example manufacturing process of an example glass core assembly.

[0020] Figure 37 It shows that it can be used Figure 1 Another example of a glass core assembly implemented within an example packaging substrate.

[0021] Figure 38 It shows that it can be used Figure 1 Another example of a glass core assembly implemented within an example packaging substrate.

[0022] Figures 39-44 Manufacturing process is shown Figure 37 and / or Figure 38 Different stages in the example manufacturing process of an example glass core assembly.

[0023] Figure 45 This demonstrates how processing can be carried out according to the teachings disclosed herein to produce... Figure 2A , Figure 3A , Figure 19 , Figure 20 , Figure 28 , Figure 29 , Figure 37 and / or Figure 38 Example glass panels for any example glass core assembly.

[0024] Figure 46 This demonstrates the inclusion of [the example framework]. Figure 45 Example glass panel, example reconstructed panel.

[0025] Figure 47A , Figure 47B , Figure 48 and Figure 49 It means that manufacturing can be done Figure 1 The example IC package 100 is implemented Figure 2A , Figure 3A , Figure 19 , Figure 20 , Figure 28 , Figure 29 , Figure 37 and / or Figure 38 The flowchart shows an example method for any of the example glass core components.

[0026] Figure 50 It is a top view of a wafer that includes a die that may be included in an IC package constructed in accordance with the teachings disclosed herein.

[0027] Figure 51 It is a cross-sectional side view of an IC device that can be included in an IC package constructed in accordance with the teachings disclosed herein.

[0028] Figure 52 It may include a cross-sectional side view of an IC device assembly that may be constructed in accordance with the teachings disclosed herein.

[0029] Figure 53 It may include a block diagram of an example electrical device that can be constructed in accordance with the teachings disclosed herein using an IC package.

[0030] Generally, the same reference numerals will be used throughout the accompanying drawings and written description to refer to the same or similar parts. The drawings are not necessarily drawn to scale. Instead, the thickness of layers or regions may be enlarged in the drawings. Although the drawings show layers and regions with clearly defined lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, mixed, and / or irregular. Detailed Implementation

[0031] Figure 1 An example integrated circuit (IC) package 100 constructed according to the teachings disclosed herein is shown. In the illustrated example, the IC package 100 is electrically coupled to an underlying substrate 102 via an array of contacts 104 on a package mounting surface 106 (e.g., bottom surface, outer surface). In some examples, the substrate 102 may be implemented as a printed circuit board (PCB) or a package substrate (e.g., the IC package 100 is part of another larger package). In the illustrated example, the contacts 104 are represented as pads or connection pads. However, in some examples, in addition to or in place of the pads or connection pads shown, the IC package 100 may include balls, leads, and / or any other type of contacts to enable the IC package 100 to be electrically coupled to the substrate 102. In this example, the package 100 includes two semiconductor dies 108, 110 (e.g., silicon dies), sometimes also referred to as chips or chiplets, which are mounted to a package substrate 112 and surrounded by a package cover 114 (e.g., a molding compound, an integrated heat sink (IHS)). Therefore, the packaging substrate 112 is an example device for supporting the semiconductor die. In some examples, the packaging cover 114 is omitted, thereby exposing or exposing the semiconductor dies 108, 110.

[0032] Although Figure 1 The example IC package 100 includes two dies 108 and 110, but in other examples, the IC package 100 may have only one die or more than two dies. In some examples, one of the dies 108 and 110 (or a single die) is embedded in a package substrate 112. Dies 108 and 110 can provide any suitable type of functionality (e.g., data processing, memory storage, etc.). In some examples, one or both of dies 108 and 110 are implemented by a die package comprising a plurality of dies arranged in a stacked manner. For example, die 110 may include a stack of dynamic random access memory (DRAM) dies arranged on top of a memory controller die to form a memory die stack.

[0033] As shown in the example, each of dies 108 and 110 is electrically and mechanically coupled to the package substrate 112 via an array of corresponding interconnects 116. Figure 1In this diagram, interconnects are shown as bumps. In some examples, interconnect 116 may include solder joints, microbumps, combinations of metal (e.g., copper) pillars and solder, etc. In other examples, interconnect 116 may include direct bonding or "hybrid bonding" metal interconnects. In other examples, interconnect 116 may be any other type of electrical connection (e.g., ball, pin, pad, pillar, wire bond, etc.) other than or in lieu of the bumps shown. The electrical connection between dies 108, 110 and package substrate 112 (e.g., interconnect 116) is sometimes referred to as a first-level interconnect. In contrast, the electrical connection between IC package 100 and substrate 102 (e.g., contact 104) is sometimes referred to as a second-level interconnect. In some examples, one or both of dies 108, 110 may be stacked on top of one or more other dies and / or interposers. In such examples, dies 108, 110 are coupled to the underlying die and / or interposer via a first set of first-level interconnects, and the underlying die and / or interposer may be connected to the package substrate 112 via a separate set of first-level interconnects associated with the underlying die and / or interposer. Thus, as used herein, a first-level interconnect refers to an interconnect (e.g., ball, bump, pin, pad, wire bond, etc.) between the die and the package substrate or between the die and the underlying die and / or interposer.

[0034] like Figure 1As shown, the interconnect 116 in the first-level interconnect includes two different types of bumps corresponding to core bumps 118 and bridging bumps 120. As used herein, core bump 118 is a bump on dies 108, 110 through which electrical signals are transmitted between dies 108, 110 and components outside the IC package 100. More specifically, as shown in the example, when dies 108, 110 are mounted to the package substrate 112, core bump 118 is physically connected to and electrically coupled to contact pads 122 on the die mounting surface 124 (e.g., upper surface, top surface, etc.) of the package substrate 112. The contact pads 122 on the die mounting surface 124 of the package substrate 112 are electrically coupled via internal interconnects 126 within the package substrate 112 to contacts 104 on the package mounting surface 106 (e.g., bottom, outer surface) (e.g., the surface opposite to the die mounting surface 124) of the package substrate 112. As a result, a continuous electrical signal path exists between the core bumps 118 of dies 108 and 110 and the contacts 104 mounted to the substrate 102, passing through the contact pads 122 and interconnects 126 disposed therebetween. As shown, the package mounting surface 106 and the die mounting surface 124 define opposing outer surfaces of the package substrate 112. While both surfaces are outer surfaces of the package substrate, the die mounting surface 124 is sometimes referred to herein as an inner surface or internal surface relative to the entire IC package 100. In contrast, in this example, the package mounting surface 106 is an outer surface or external surface of the IC package 100.

[0035] As used herein, bridging bump 120 is a bump on dies 108 and 110 through which electrical signals are transmitted between different dies within the IC package 100. Therefore, as shown in the example, bridging bump 120 of the first die 108 is electrically coupled to bridging bump 120 of the second die 110 via interconnect bridge 128 (e.g., silicon-based interconnect bridge, interconnect die, embedded interconnect bridge (EMIB) embedded in the package substrate 112). Figure 1 As shown, the core bump 118 is typically larger than the bridging bump 120. In some examples, the interconnect bridge 128 and the associated bridging bump 120 are omitted.

[0036] In some examples, underfill material 130 is disposed around the first-level interconnect 116 and / or between the first-level interconnects 116 (e.g., around the core bump 118 and / or the bridging bump 120 and / or between the core bump 118 and / or the bridging bump 120) between the dies 108, 110 and the package substrate 112. In the example shown, only the first die 108 is associated with underfill material 130. However, in other examples, both dies 108 and 110 are associated with underfill material 130. In other examples, underfill material 130 is omitted. In some examples, the molding compound for the package cap 114 is used as the underfill material around the first-level interconnects 116.

[0037] In some examples, IC package 100 includes additional passive components, such as surface mount resistors, capacitors and / or inductors disposed on package mounting surface 106 and / or die mounting surface 124 of package substrate 112.

[0038] exist Figure 1 In the example IC package 100, the substrate 112 includes a glass core 132 (e.g., a glass substrate, glass layer, etc.) between two separate build-up layers or regions 134, 136 (e.g., a first build-up region 134 and a second build-up region 136, also referred to herein as a redistribution layer or region). In some examples, the glass core 132 includes at least one of the following: aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, and / or fused silica. In some examples, the glass core 132 includes one or more additives, including: alumina (Al2O3), boron trioxide (B2O3), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), tin oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and / or zinc (Zn). In some examples, the glass core 132 includes silicon and oxygen. In some examples, the glass core 132 comprises one or more of silicon, oxygen and / or aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium and / or zinc. In some examples, the glass core 132 comprises at least 23% by weight silicon and at least 26% by weight oxygen. In some examples, the glass core is a glass layer comprising silicon, oxygen, and aluminum. In some examples, the glass core 132 comprises at least 23% by weight silicon, at least 26% by weight oxygen, and at least 5% by weight aluminum.

[0039] In some examples, glass core 132 is an amorphous solid glass layer. In some examples, glass core 132 is a glass layer that does not include organic binders or organic materials. In some examples, glass core 132 is a solid glass layer having a rectangular shape in a plan view. In some examples, glass core 132, as a glass substrate, comprises at least one glass layer and does not include epoxy resin or glass fibers (e.g., does not include an epoxy resin-based prepreg layer with glass cloth). In some examples, core 132 corresponds to a monolithic glass extending the entire height / thickness of the core. In other examples, glass core 132 can be silicon, a dielectric material, and / or any other material.

[0040] In some examples, the glass core 132 has a rectangular shape, which, in a plan view, extends substantially together with the layers above and / or below the core. In some examples, the thickness of the glass core 132 ranges from about 50 micrometers (μm) to about 1.4 millimeters (mm). In some examples, the glass core 132 may be a multilayer glass substrate (e.g., a coreless substrate) where the thickness of the glass layers ranges from about 25 μm to about 50 μm. In some examples, the glass core 132 may have dimensions of about 10 mm on one side to about 250 mm on the other side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some examples, the glass core 132 corresponds to a rectangular prism volume where segments (e.g., vias) are removed and filled with other materials (e.g., metals). Glass cores are preferred over epoxy-based cores because glass is harder and therefore provides greater mechanical support or strength to the encapsulation substrate. Therefore, the glass core 132 is an example device for reinforcing an encapsulation substrate.

[0041] The first and second accumulation regions 134 and 136 are in Figure 1 The diagram is represented as a mass / block, where internal interconnects 126 extend in straight lines through stacked regions 134, 136 (and glass core 132). However, for clarity and explanation purposes, a simplified representation has been provided. Figure 1 In practice, the interconnects are not necessarily straight. More specifically, in some examples, stacked regions 134, 136 are defined by alternating layers of dielectric material and conductive material (e.g., a metal such as copper). The conductive (metallic) layer serves as the basis for the internal interconnects 126, which are simplified in form as... Figure 1 The straight lines shown are representative. In some examples, the metal layers are patterned to define electrical wiring or conductive traces that are electrically coupled between different metal layers via conductive (e.g., metal) vias extending through the intervening dielectric layer. Furthermore, electrical wiring or traces on either side of the glass core 132 can be electrically coupled via through-glass vias (TGVs) (e.g., copper-plated vias) extending through the glass core 132.

[0042] Using glass as the starting core material (e.g., Figure 1 The glass core 132 offers mechanical, electrical, and design flexibility advantages over conventional organic core materials such as epoxy-based prepregs. Specifically, the glass core is superior to epoxy-based cores because glass is harder, thus providing greater mechanical support or strength to the encapsulation substrate. Therefore, the glass core 132 is an example device for reinforcing the encapsulation substrate 112. In addition to the mechanical benefits, the glass core offers other advantages, including higher plated via (PTH) density, lower signal loss, and lower overall thickness variation. However, the glass core also presents challenges due to the brittle (e.g., brittle) nature of glass, the potential for defects to develop into cracks propagating through the glass, and related limitations in the methods available for manufacturing and / or processing the glass core.

[0043] For example, cavities, holes, and / or openings can be mechanically drilled into epoxy-based organic cores, but such processes are unsuitable for glass cores. As an alternative, cavities, holes, and / or openings are created in the glass layer via a laser-induced etching (LIDE) process. Specifically, in the LIDE process, a laser is focused on specific areas of a glass sheet (e.g., glass core 132) to alter the chemical properties of the glass core 132 at those areas. This change in chemical properties increases the etching sensitivity of the glass core 132 at the laser-exposed areas, allowing these areas to be removed during subsequent etching processes. This etching process exposes the entire glass core 132 to the etching solution. This presents challenges when different cavities, holes, and / or openings are to be added to the glass core 132 at different times. For example, the glass associated with a first opening established during a first LIDE process may be negatively affected by exposure to the etching solution associated with a second (subsequent) LIDE process performed to create a second (subsequent) opening. Furthermore, repeated exposure to the etching solution may affect other portions or features of the glass core 132, regardless of whether the glass associated with the first opening is affected. Such a problem does not exist in many known manufacturing processes for cores based on organic materials, because the first opening can be produced by a first machining process (e.g., drilling), and the second opening can be added at any later point in time by a second machining process without affecting the first opening or other areas of the core.

[0044] The examples disclosed herein are based on process flows in which multiple different types of cavities, holes, and / or openings are created in a glass core during a single LIDE process to overcome one or more of the challenges described above. More specifically, in some examples, the different types of openings include through-holes for TGVs associated with interconnect 126 and at least one larger cavity 138 having sufficient dimensions to accommodate some other electronic components 140 disposed therein. Electronic components 140 can be any suitable electronic component, such as a coaxial magnetic inductor circuit (CMIL), a deep trench capacitor (DTC), another semiconductor device (e.g., a semiconductor die), etc. Figure 1 In the example shown, electronic component 140 is entirely contained within cavity 138. However, in some examples, at least some of electronic components 140 extend beyond cavity 138. In some examples, more than one electronic component 140 (whether of the same or different type) may be located within a given cavity 138 (e.g., in the X, Y, and / or Z directions). Additionally or alternatively, glass core 132 may include more than one cavity 138, wherein each such cavity includes one or more electronic components 140. Fabricating vias for TGV in glass core 132 simultaneously (e.g., concurrently) with the larger cavity 138 avoids the problems associated with multiple etching processes that negatively impact glass core 132 (e.g., the structural integrity of glass core 132 and / or one or more structural features of glass core 132).

[0045] Furthermore, the examples disclosed herein ensure that features and / or structures to be provided in different types of openings can be manufactured without affecting each other. For example, in some examples, after creating the through-hole and cavity 138, the cavity 138 is then filled with a dielectric material before the through-hole is filled with a conductive material (e.g., a metal, such as copper) to define the TGV. By first filling the cavity 138 with a dielectric material, the plating process of adding conductive material to generate the TGV does not result in any conductive material entering the cavity 138. Additionally, in some examples, methods unsuitable for glass can be used to process the dielectric material within the cavity. For example, a machining (e.g., drilling) process can be performed in a manner similar to known processes involving cores based on organic materials to remove portions of the dielectric material in order to make room for the electronic components 140.

[0046] Figure 2A It shows that it can be used Figure 1 An example glass core assembly 200 is implemented within an example packaging substrate 112. In the example shown in FIG2, the glass core assembly 200 includes a glass core 202, which may correspond to the above-described bonding... Figure 1 The glass core 132 is described. Therefore, the above is combined with... Figure 1The description of glass core 132 is similarly applicable to glass core 202 of Figure 2. For example... Figure 2A As shown, the glass core 202 includes a plurality of through-glass vias (TGVs) 204 defined by a first conductive material 206, which substantially fills the associated vias 208 (e.g., holes, cavities, openings, etc.) extending through the glass core 202. As used herein, “substantially filled” or “substantially filled” means filled to at least 95%. In some examples, the first conductive material 206 includes any suitable metal, such as copper. In some examples, the TGVs 204 of FIG2 correspond to the extensions through the internal interconnects 126. Figure 1 The portion of the packaging substrate 112.

[0047] As shown in the example, the glass core 202 includes components corresponding to... Figure 1 Cavity 138 and cavity 210. Therefore, as Figure 2A As shown, electronic component 212 (corresponding to Figure 1 Electronic component 212 (140) is disposed within cavity 210. In this example, electronic component 212 is a coaxial magnetic inductor circuit (CMIL). For illustrative purposes, electronic component 212 will be referred to as CMIL 212 hereinafter. Nevertheless, one or more additional and / or other types of electronic components may be used. As shown, example CMIL 212 extends through glass core assembly 200, including a first buffer layer 214 and a second buffer layer 216 (e.g., adhesive layer, dielectric layer) extending through corresponding first surfaces 218 and second surfaces 220 of glass core 202. Thus, in this example, CMIL 212 extends through and beyond cavity 210 (e.g., above and / or below first surfaces 218 and second surfaces 220). In some examples, buffer layers 214, 216 are made of dielectric material. More specifically, in some examples, buffer layers 214, 216 comprise organic laminated dielectrics (e.g., epoxy-based stacked dielectrics).

[0048] exist Figure 2A In the example shown, CMIL 212 includes a first portion 222 and a second portion 224 defined by two plated through-holes within a dielectric material 226 within a cavity 210. More specifically, as Figure 2A As shown, dielectric material 226 substantially fills the gaps within cavity 210 not occupied by the structure of CMIL 212. In some examples, dielectric material 226 fills the space between CMIL 212 and the sidewalls 227 of cavity 210 (e.g., inward-facing surfaces, walls, etc.) to separate CMIL 212 from glass core 202. Furthermore, in some such examples, dielectric material 226 fills the space between different portions 222, 224 of CMIL 212.

[0049] In the illustrated example, each of the first portion 222 and the second portion 224 of the CMIL 212 includes a non-magnetic plug 228 (e.g., a non-magnetic core) defining a central region of each portion 222, 224, which is surrounded by a second conductive material 230, which itself is surrounded by a magnetic material 232 (e.g., a magnetic liner). That is, in some examples, the magnetic material 232 defines the magnetic exterior of each portion 222, 224 of the CMIL 212, while the conductive material 230 defines the conductive core of each portion 222, 224 of the CMIL 212. In some examples, the portions of the non-magnetic plug 228, the conductive material 230, and the magnetic material 232 of the CMIL 212 have a generally cylindrical shape. In some examples, the non-magnetic plug 228 comprises a dielectric material (e.g., epoxy resin). In some examples, the non-magnetic plug 228 is omitted, and the central region of each portion 222, 224 is filled with a solid block of the second conductive material 230. That is, in some examples, the second conductive material 230 extends continuously across the space inside the magnetic material 232. In some examples, the second conductive material 230 comprises the same metal (e.g., copper) as the first conductive material 206 in TGV 204. In other examples, the second conductive material 230 may comprise any other suitable conductive material (e.g., metal). In some examples, the magnetic material 232 comprises any suitable material having magnetic properties (e.g., iron, iron-containing alloys (e.g., silicon steel), ferrite materials (e.g., nickel-zinc ferrite (e.g., Ni...)). a Zn (1-a) Fe2O4), manganese ferrite (e.g., Mn) a Zn （1-a） Fe2O4), cobalt ferrites (e.g., CoFe2O4, CoO·Fe2O3), and other ferromagnetic particles or elements.

[0050] exist Figure 2A In the example shown, the first portion 222 and the second portion 224 of the CMIL 212 are each covered by a corresponding conductive pad 234 (e.g., a contact pad). In some examples, the conductive pad 234 comprises the same material as a second conductive material 230 (e.g., copper) extending along the axial length of the two portions 222\224 of the CMIL 212. In some examples, the conductive pad 234 associated with portions 222, 224 of the CMIL 212 is in the same metal layer as an additional conductive pad 235 electrically coupled to the TGV 204.

[0051] exist Figure 2AIn this context, the first buffer layer 214 and the second buffer layer 216 are represented as materials different from the dielectric material 226 that fills the gaps(s) surrounding the cavity 210 of the CMIL 212. More specifically, as described above, in some examples, the first buffer layer 214 and the second buffer layer 216 comprise an organic laminated dielectric (e.g., an epoxy-based stacked dielectric), while the dielectric material 226 comprises a liquid-dispensable dielectric. In other examples, the first buffer layer 214 and the second buffer layer 216 comprise the same material as the dielectric material 226 within the cavity 210.

[0052] As described above, in this example, the first buffer layer 214 and the second buffer layer 216 are located on opposite first surfaces 218 and 229 of the glass core 202. Therefore, in this example, the first buffer layer 214 and the second buffer layer 216 define the first outer surface 236 and the second outer surface 238 of the entire glass core assembly 200. However, in some examples, Figure 2A The first buffer layer 214 and the second buffer layer 216 shown may be omitted and / or correspond to the stacking area on either side of the glass core assembly 200 (e.g., Figure 1 The first layer of the stacked regions 134, 136). In such an example, the first and second surfaces of the glass core 202 define the first outer surface 236 and the second outer surface 238 of the entire glass core assembly 200.

[0053] Figure 2B It corresponds to Figure 2A The enlarged view of the dashed box 240 shown represents an example structure in which the outer surface 242 (e.g., the outward-facing surface) of the first conductive material 206 of the TGV 204 is defined relative to the inner surface 244 (e.g., the inward-facing surface, wall, sidewall, etc.) of the through hole 208. Figure 2C It corresponds to Figure 2A The enlarged view of the dashed box 240 shown represents another example structure of the outer surface 242 of the first conductive material 206 facing the inner surface 244 of the through hole 208. Figure 2BIn some examples, multiple open spaces 246 (e.g., gaps, voids, etc.) are defined between facing surfaces 242, 244. That is, the open space 246 separates at least a portion of the outer surface 242 of the conductive material 206 and the inner surface 244 of the through-hole 208. In some examples, the open space 246 is empty and / or has no solid material. In some cases, the open space 246 is defined by notches, cracks, and / or defects in one or both of the facing surfaces 242, 244 of the TGV 204 and the glass core 202. Additionally or alternatively, in some examples, the facing surfaces 242, 244 may be relatively smooth (e.g., substantially free of notches, gaps, and / or defects), but slightly spaced to define a single gap and / or open space 246 therebetween. Figure 2B Compared to the shorter open space 246 shown, this gap and / or open space 246 can be relatively long, such as Figure 2C As shown in the example. In other examples, the gaps and / or open spaces 246 can be any other size.

[0054] The dimensions of the multiple open spaces 246 between the glass core 202 and the TGV 204 can vary. For example, in some examples, the open spaces have a longitudinal axis 250 radially (e.g., perpendicular to) the through-hole 208. Figure 2A The width 248, measured in the direction shown (e.g., the longitudinal axis of TGV204), can be as high as about 250 nanometers (nm), but is sometimes significantly smaller (e.g., about 200 nm or less, about 150 nm or less, about 100 nm or less, about 50 nm or less, about 25 nm or less, etc.). In contrast, as Figure 2B As shown, example open space 246 has a length 252 measured in a direction parallel to longitudinal axis 250, which can be significantly greater than width 248 (e.g., at least twice, at least three times, at least five times, at least ten times, etc., the width 248). In some examples, the length 252 of a given open space 246 extends a perceptible distance over the full length of via 208 or TGV 204 (e.g., at least 5%, at least 10%, at least 25%, at least 50%, at least 75%, at least 90%, etc.). In some examples, a single open space 246 can extend the entire length of via 208. In other examples, multiple open spaces 246 exist (which may or may not be connected).

[0055] In some examples, the open spaces 246 not only extend longitudinally, partially and / or entirely, along the length of the through-hole 208, but also extend circumferentially, partially and / or entirely, along the inner surface 244 of the through-hole 208 (e.g., along the periphery of the cross-section of the first conductive material 206), such as... Figure 2D and Figure 2E shown. Specifically, Figure 2D yes Figure 2A The example TGV 204 shown (e.g., with) Figure 2B The same TGV 204, and Figure 2C Top view cross section of the same TGV 204 or different TGV. Figure 2E yes Figure 2A Another example shown is the TGV 204 (e.g., with...). Figure 2B The same TGV 204, and Figure 2C Top view cross section of the same TGV 204 or different TGV. Figure 2D Examples and Figure 2E The difference in the examples is that, Figure 2D Multiple open spaces 246 extending in different circumferential lengths around TGV 204 are shown, while Figure 2E A single open space 246 extending the entire circumference of TGV 204 is shown. More than one open space 246 may be in the same circumferential plane. Thus, as shown, the open spaces 246 may extend around TGV 204 by any suitable circumferential distance (e.g., at least 5%, at least 10%, at least 25%, at least 50%, at least 75%, at least 90%, etc.). While one or more open spaces 246 may exist between the conductive material 206 of TGV 204 and the inner surface 244 (e.g., sidewall) of the associated via 208, in some examples, the dielectric material 226 in cavity 210 directly contacts (e.g., abuts) the sidewall 227 of cavity 210 in various locations and / or in most areas.

[0056] In some examples, open spaces 246 are created by plating a first conductive material 206 within the via 208 to produce a TGV 204. Known TGVs are typically fabricated by first depositing a seed layer on the surface of a glass core (e.g., along the inner surface of the via 208) using an electroless plating process. Subsequently, a bulk of the first conductive material 206 is deposited onto the seed layer using an electrolytic plating process, where the seed layer acts as an electrode. The implementation of the seed layer promotes relatively strong adhesion between the conductive material and the inner wall of the plated via. In contrast to this known method, in some examples, a bottom-up plating process is used to deposit the TGV 204 without a seed layer. That is, the conductive material is positioned at the base or bottom of the via 208 to act as an electrode in the electrolytic plating process by which the first conductive material 206 is deposited until it has accumulated along the entire length (or substantially the entire length, e.g., at least 90%) of the via 208.

[0057] Since there is no seed layer along the walls of the through-hole 208 (e.g., inner surface 244) in such an example, the conductive material to which the first conductive material 206 is plated is the substrate beneath the electrode, and portions of the first conductive material 206 are gradually deposited thereon during the plating process. As a result, no strong adhesion is generated between the first conductive material 206 and the glass core 202, leading to one or more open spaces 246 as described above. The lack of adhesion between the first conductive material 206 and the glass core 202, and between them and the associated open spaces 246, is advantageous because it reduces stress caused by the mismatch of the coefficients of thermal expansion (CTE) of the two different materials. That is, the open spaces 246 can provide some space for the first conductive material 206 to expand and / or contract radially without significantly affecting the glass core 202. Furthermore, the relatively low adhesion and the associated open spaces 246 allow the first conductive material 206 to expand longitudinally, allowing longitudinal displacement of the material relative to the glass core 202 without generating undue stress on the glass core 202. As a result, the examples disclosed herein reduce the stress in glass core 202, thereby reducing the occurrence of cracks and / or other failures known to occur in known glass core applications.

[0058] Figure 3A It shows that it can be used Figure 1 Another example glass core assembly 300 is implemented within the example encapsulation substrate 112. Figure 3A Example glass core assembly 300 and Figure 2A The example glass core assembly 200 is substantially the same, except as described below and / or otherwise becomes clear from the context. Therefore, Figure 3A The shown with Figure 2ACorresponding or similar features are identified by the same reference numerals. Furthermore, the above text, in conjunction with... Figure 2A The description of this type of feature is relative to Figure 3A The corresponding features in the example are similarly applicable. Specifically, the example glass core assembly 300 includes a glass core 202 and a cavity 210, the glass core 202 including a TGV 204 extending through the glass core 202, and a CMIL 212 disposed within the cavity 210.

[0059] Figure 3A Examples and Figure 2A The difference in the example is the inclusion of a thin-film dielectric 302 (e.g., a dielectric layer) coated on the outer surface of the glass core 202. That is, as... Figure 3A As shown, the thin-film dielectric 302 extends along the opposing first surface 218 and second surface 220 of the glass core 202 and along the sidewalls of the through-hole 208 and the cavity 210. In some examples, the thin-film dielectric 302 comprises the same dielectric material used in the first buffer layer 214 and the second buffer layer 216 and / or the same dielectric material used in the dielectric material 226 filling the cavity 210. In other examples, the thin-film dielectric 302 differs from the materials used in the first buffer layer 214 and the second buffer layer 216, and differs from the dielectric material 226 filling the cavity 210. More specifically, in some examples, the thin-film dielectric 302 comprises at least one of silicon nitride, silicon oxide, silicon carbide, carbon-doped oxide (CDO), polyimide, parylene, and / or any other suitable dielectric material. In some examples, the thin-film dielectric 302 is referred to as a repair layer because it “repairs” the underlying glass by filling notches, cracks, and / or fissures on the surface of the glass core, thereby reducing its negative impact.

[0060] Figure 3B and Figure 3C It corresponds to Figure 3A The enlarged view of the dashed box 304 shown represents different example structures of the outer surface 242 of the first conductive material 206 facing the inner surface 244 of the through hole 208. Figure 3E And Figure 3F is Figure 3A Top cross-sectional views of different examples of TGV 204 shown. Figure 3B-3E and Figure 2B-2E They are essentially the same, except as described below and / or otherwise become clear from the context. More specifically, Figure 3B-3EA thin-film dielectric 302 is shown coated (e.g., in contact with, adjacent to) the inner surface of the through-hole 208 of the glass core 202. As shown, in these examples, there are still multiple open spaces 246 between the inner surface 244 of the through-hole 208 and the outer surface 242 of the first conductive material 206 (e.g., TGV 204). However, in these examples, the thin-film dielectric 302 is located between the glass core 202 and the multiple open spaces 246. Although there may be multiple open spaces 246 between the conductive material 206 of TGV 204 and the associated inner surface 244 of the through-hole 208, in some examples, the dielectric material 226 in the cavity 210 directly contacts (e.g., adjacent to) the thin-film dielectric 302 adjacent to the sidewall 227 of the cavity 210.

[0061] Figure 4-18 Manufacturing process is shown Figure 2A Example glass core assembly 200 and / or Figure 3A Different stages in the example manufacturing process of the example glass core assembly 300. Figure 4 This refers to the glass panel 400 corresponding to the initial state of the glass core 202. In some examples, the glass panel 400 is manufactured to a thickness corresponding to the final thickness of the glass core 202. However, in some examples, the glass panel 400 is initially slightly larger than the final thickness of the glass core 202 to allow for the removal of a certain amount of glass during subsequent polishing or planarization processes, as discussed further below.

[0062] Figure 5 This refers to a manufacturing stage following the exposure of the glass core 202 to a laser as part of a laser-induced deep etching (LIDE) process. The laser is focused on a defined region 502 of the glass core 202 to alter the optical and / or chemical properties of the glass core 202 at those regions 502. Figure 6 This indicates a manufacturing stage following the chemical etching process, which is used to remove... Figure 4The material in the modified region 502 of the glass core 202 is used to define a through-hole 208 for the TGV 204 and a cavity 210 associated with the location of the CMIL 212. In this example, both the through-hole 208 and the cavity 210 have a cross-sectional profile that generally corresponds to an hourglass shape, wherein the width (e.g., diameter) of the opening is narrower near the midpoint of the opening between the opposing first surface 218 and second surface 220 of the glass core 202. In other examples, one or more of the through-hole 208 and / or the cavity 210 may have different cross-sectional shapes. For example, in some examples, one or more of the through-hole 208 and / or the cavity 210 may have a generally conical or tapered shape, wherein the width (e.g., diameter) is minimum at one of the two surfaces 218, 220 of the glass core 202 and maximum at the opposing surfaces 218, 220. In other examples, the width (e.g., diameter) of one or more of the through-holes 208 and / or cavities 210 is substantially consistent along the entire length of the opening between the opposing surfaces 218, 220 of the glass core 202.

[0063] like Figure 6 As shown, the through-hole 208 has a first width 602 that is smaller than the second width 604 of the cavity 210. In some examples, the second width 604 is significantly larger than the first width 602 (e.g., at least twice, at least three times, at least five times, at least ten times, etc.). Despite the difference in width, the through-hole 208 and the cavity 210 have the same height 606 (e.g., length) defined by the thickness of the glass core (e.g., the distance between the first surface 218 and the second surface 220). Therefore, in the example shown, the through-hole 208 has a first aspect ratio that is greater than the second aspect ratio of the cavity.

[0064] In some examples, Figure 6 After the stage indicated in the middle (and in Figure 7 The previous manufacturing process involved depositing a thin-film dielectric 302 onto all external (e.g., exposed) surfaces of the glass core 202, as described above. Figures 3A-3E The discussion focuses on the following. In some such examples, conformal coating processes (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.) are used to deposit the thin film dielectric 302. In other examples, directional deposition processes (e.g., physical vapor deposition (PVD), etc.) are used to deposit the thin film dielectric 302.

[0065] Figure 7 This indicates the manufacturing stage after the glass core 202 is attached to the conductive carrier 702. In this example, the conductive carrier includes a conductive layer 704 (e.g., a copper layer) and a release layer 706 (e.g., an adhesive dielectric layer). Figure 8This indicates the manufacturing stage after the cavity 210 in the glass core 202 has been filled with dielectric material 226. In some examples, the dielectric material 226 is dispensed into the opening as a liquid or paste (e.g., a liquid dispensable dielectric) and subsequently cured. In some examples, any excess dielectric material 226 extending beyond the first surface 218 of the glass core 202 is removed by polishing (e.g., a chemical mechanical planarization (CMP) process). In some examples, this polishing process slightly thins the glass core 202.

[0066] Figure 9 This indicates the manufacturing stage after a mask 902 is applied (e.g., via photolithography) to cover the components except for the through-hole 208 of the glass core. Furthermore, Figure 9 The manufacturing stage indicated is after an etching process (e.g., plasma etching, dry etching) to remove the portion of the release layer 706 exposed within the vias 208 of the glass core 202, thereby exposing the underlying conductive layer 704. The mask 902 protects the dielectric material 226 during the etching process.

[0067] Figure 10 This indicates the manufacturing stage after the mask 902 is removed (e.g., stripped) and a conductive material 206 (e.g., copper) is subsequently plated within the via 208 to define a TGV 204 extending through the glass core 202. In this example, the TGV 204 is plated from the exposed portion of the conductive layer 704 (e.g., bottom-up plating). Therefore, in this example, no seed layer is deposited along the walls of the via 208 prior to the plating process. However, in other examples, a seed layer may be used to facilitate the plating of the TGV 204. Figure 10 The manufacturing stage indicated in the diagram also follows a subsequent polishing process (e.g., CMP process) to remove excess copper extending over the first surface 218 of the glass core 202. Therefore, in some examples, the outer surfaces (e.g., ends) of both the dielectric material 226 and the TGV 204 are substantially flush with and / or substantially parallel to the first surface 218. As used herein, the two surfaces are substantially flush when there is an offset of no more than 100 nm between them. Furthermore, as used herein, the two surfaces are substantially parallel when they are within 3 degrees of precise parallelism.

[0068] Figure 11 This indicates the manufacturing stage after the removal of the conductive carrier 702, which includes both the conductive layer 704 and the release layer 706. In some examples, the second surface 220 of the glass core 202 undergoes a polishing process (e.g., a CMP process) to make both the dielectric material 226 and the TGV 204 substantially flush with the second surface 220. In some examples, the component also undergoes a cleaning process to remove any residual material.

[0069] Figure 12This indicates the manufacturing stage following the application (e.g., lamination) of the first buffer layer 214 and the second buffer layer 216 on the respective first surface 218 and second surface 220 of the glass core 202 and on the outer surface of the dielectric material 226 within the cavity 210. Figure 12 This also describes the result of adding a conductive via 1202 through buffer layers 214, 216 to electrically couple the underlying TGV 204 to the outer layer 1204 of conductive material. More specifically, holes (e.g., vias) are drilled through buffer layers 214, 216 to expose the ends of the TGV 204, and then the holes are filled to define the material of the conductive via 1206 and create the outer layer 1204 of conductive material. In some examples, the outer layer 1204 of conductive material is used as a bonding as described above. Figure 2A The foundation for the subsequent development of the conductive pad 235 of the TGV 204 discussed.

[0070] Figure 13 This indicates the manufacturing stage after drilling 1302 through the outer layer 1204 of the conductive material, the buffer layers 214 and 216, and the dielectric material 226. Therefore, Figure 13 The hole 1302 extends through the cavity 210 within the glass core 202 and the outer layer 1204 of the conductive material. In this example, the hole 1302 defines... Figure 2A The outer extent of the first portion 222 and the second portion 224 of the CMIL 212 shown. Unlike the through-holes 208 and cavities 210 in the glass core 202 produced by the LIDE process, holes 1302 can be directly machined (e.g., drilled) through the dielectric material 226. Thus, in some examples, the hole 1302 is a circular hole with straight (e.g., substantially parallel along the entire length of the circular hole 1302) opposing sidewalls. In contrast, as shown in the example shown, the sidewalls of the cavity 210 are not straight (e.g., not parallel along the entire length of the cavity wall).

[0071] Figure 14 This indicates the manufacturing stage after the hole 1302 has been filled with the magnetic material 232 used in CMIL 212. In some examples, the magnetic material 232 is deposited within the hole 1302 as a subsequently cured paste or resin. Afterward, grinding and / or polishing processes (e.g., CMP processes) can be applied to both sides of the component to remove excess material.

[0072] Figure 15 This indicates the manufacturing stage after drilling an internal through-hole 1402 through different parts of the magnetic material 232.

[0073] Figure 16This refers to the manufacturing stage following the deposition (e.g., electroplating) of conductive material 230 onto the walls of the internal via 1402 (e.g., the inner wall of magnetic material 232) plated with conductive material 230. In some examples, this is achieved through a bottom-up plating process. In other examples, this is achieved by direct plating onto magnetic material 232 and / or a seed layer on magnetic material 232. Figure 16 As shown, the remaining central region of the internal through-hole 1402 (the interior of the conductive material 230) is filled with a non-magnetic plug 228. In some examples, the non-magnetic plug 228 is deposited as a subsequently cured paste or resin within the central region of the conductive material 230. Subsequently, grinding and / or polishing processes (e.g., CMP processes) can be applied to both sides of the component to remove excess material.

[0074] Figure 17 This indicates that additional conductive material 1702 is deposited (e.g., plated) onto... Figure 12 The manufacturing stages following the addition of conductive material to the outer layer 1204 at the stage indicated in the diagram. (e.g., ...) Figure 17 As shown, the additional conductive material 1702 extends across CMIL 212.

[0075] Figure 18 This indicates the manufacturing stage following the selective removal (e.g., via photolithography) of portions of the attached conductive material 1702 (and the outer layer 1204 of the previously deposited conductive material) to provide conductive pads 235 associated with TGV 204 and conductive pads 234 covering the ends of the first portion 222 and the second portion 224 of CMIL 212. Figure 18 The structure of the example glass core assembly shown corresponds to Figure 2A The example glass core assembly 200 shown illustrates the structure of the glass core assembly and thus represents the completion of the manufacturing process.

[0076] Figure 19 It shows that it can be used Figure 1 Another example glass core assembly 1900 is implemented within the example packaging substrate 112. Figure 19 Example glass core assembly 1900 and Figures 2A-2E The example glass core assembly 200 is substantially the same, except as described below and / or otherwise becomes clear from the context. Therefore, Figure 19 The shown with Figures 2A-2E (and related) Figure 4-18 Features that are identical or similar to those in the figures are identified by the same reference numerals. Furthermore, the above combinations... Figures 2A-2E (and related) Figure 4-18 The descriptions of these features are similarly applicable to... Figure 19 The corresponding features in.

[0077] Figure 19 Examples and Figure 2A The difference lies in the construction of the example CMIL 1902 (e.g., an electronic component) embedded within the cavity 210 in the glass core 202. Specifically, in Figure 2A In the CMIL 212, the central regions of the two portions 222, 224 are defined by non-magnetic plugs 228. In contrast, in Figure 19 In the example shown, there are no non-magnetic plugs in the first portion 1904 and the second portion 1906 of CMIL 1902. Instead, the central regions of the two portions 1904 and 1906 are defined by a conductive material 230 (e.g., copper) that fills the entire space inside the magnetic material 232. That is, the conductive material 230 in the first portion 1904 and the second portion 1906 is a solid block that extends continuously from the inner surface of the magnetic material 232 to the center (e.g., the central axis) of the longitudinal length of the portions 1904 and 1906. In other words, in Figure 19 In the example shown, each part 1904, 1906 includes a solid metal core with a cross section that extends continuously across the metal core.

[0078] Figure 19 Examples relative to Figure 2A Another difference between the examples is the thickness of the magnetic material 232. That is, as shown in the example, the magnetic material 232 is... Figure 19 The example shown is more than in Figure 2A The example shown is thicker. In other examples (based on...) Figure 2A or Figure 19 The thickness of the magnetic material 232 may differ from the thickness shown. Additionally, in Figure 19 In the example shown, the upper and lower ends of the magnetic material 232 extend together with the dielectric material 226 within the cavity 210. That is, in this example, the ends (e.g., outer surfaces) of the magnetic material 232 (and the dielectric material 226) are substantially flush with the opposing first surface 218 and second surface 220 (e.g., outer surfaces) of the glass core 202. This differs from... Figure 2A In the example, the magnetic material extends beyond the opposing surfaces of the dielectric material 226 and the glass core 202.

[0079] Figure 20 It shows that it can be used Figure 1 Another example glass core assembly 2000 is implemented within the example encapsulation substrate 112. Figure 20 Example glass core assembly 2000 and Figure 19 The example glass core assembly 1900 is substantially the same, except as described below and / or as otherwise made clear from the context. Therefore, Figure 20 The shown and Figure 19Corresponding or similar features are identified by the same reference numerals. Furthermore, the above text, in conjunction with... Figure 19 The description of this type of feature is relative to Figure 20 The corresponding features in the text are similarly applicable.

[0080] Figure 20 Examples and Figure 19 The difference in the examples is the inclusion of a thin-film dielectric 2002 (e.g., a dielectric layer) coated on the outer surface of the glass core 202. In some examples, the thin-film dielectric 2002 is... Figure 3A The thin-film dielectric 302 is basically the same. Therefore, the above combination Figure 3A The thin-film dielectric 302 described (and associated) Figure 3B-3E The description of ) is similarly applicable to Figure 20 Thin film dielectric 2002.

[0081] manufacture Figure 19 and Figure 20 The process for example glass core components 1900 and 2000 can follow the above combination. Figure 2A and Figure 3A The example glass core assemblies 200 and 300 discussed are made of Figure 4-8 The different manufacturing stages are described in detail as identical or similar processes. However, in Figure 8 Following the manufacturing stage shown, subsequent processes may diverge. Figure 21-27 Manufacturing process is shown Figure 19 and Figure 20 Examples of different stages in the subsequent process flow of glass core components 1900 and 2000.

[0082] Figure 21 This indicates the manufacturing stage after a mask 2102 is applied (e.g., via photolithography) to cover the components (including the through-holes 208 and dielectric material 226 within the cavity 210 of the glass core 202). Furthermore, Figure 9 The manufacturing stage indicated is after drilling a hole 2104 through the mask 2102 and the dielectric material 226. In this example, the hole 2104 defines... Figure 19 The outer extent of the first portion 1904 and the second portion 1906 of CMIL 1902 is shown. Therefore, in this example, hole 2104 is... Figure 13 The hole 1302 provided in the middle is equivalent. Therefore, for Figure 13 The description of hole 1302 is similarly applicable to Figure 21 Hole 2104.

[0083] Figure 22This indicates the manufacturing stage after the via 2104 is filled with the magnetic material 232 used in CMIL 212. In some examples, the magnetic material 232 is deposited within the via 1302 as a subsequently cured paste or resin. Afterward, grinding and / or polishing processes (e.g., CMP processes) can be applied to both sides of the assembly to remove excess material. In some examples, grinding and / or polishing processes are also used to remove the mask 2102, such as... Figure 22 As shown. Alternatively, in some examples, the mask 2102 can be removed by peeling, and then subsequent polishing and / or grinding processes can be performed to remove any residue and ensure that the outer surface of the magnetic material 232 is substantially flush with the first surface 218 of the glass core 202.

[0084] Figure 23 This indicates the manufacturing stage after drilling an internal through-hole 2302 through different parts of the magnetic material 232.

[0085] Figure 24 This indicates a manufacturing stage following the application of another mask 2402 (e.g., via photolithography) to cover components other than the through-holes 208 in the glass core 202 and the internal through-holes 2302 in the magnetic material 232. Furthermore, Figure 9 The manufacturing stage described is after an etching process (e.g., plasma etching, dry etching) to remove the portion of the release layer 706 exposed within the vias 208, 2302, thereby exposing the underlying conductive layer 704. Similar to the above combination... Figure 9 As described, mask 2402 protects dielectric material 226 during the etching process.

[0086] Figure 25 This refers to the manufacturing stage after the mask 2402 is removed (e.g., stripped) and conductive materials 206, 230 (e.g., copper) are subsequently plated within vias 208, 2302 to define the central regions of different portions 1904, 1906 extending through the glass core 202 and defining CMIL 1902. In this example, vias 208, 2302 are plated from the exposed portions of conductive layer 704 (e.g., bottom-up plating). Therefore, in this example, no seed layer is deposited along the walls of vias 208, 2302 prior to the plating process. Thus, an open space 246 (e.g., gap, void, etc.) can be located between the conductive material 206 of TGV 204 and the sidewalls (e.g., inner surface 244) of via 208, as described above. Figure 2B-2EAs discussed above, since the internal via 2302 and via 208 are plated simultaneously during the same bottom-up plating process (e.g., without a seed layer), similar open spaces 246 (e.g., gaps, voids, etc.) can be located between the conductive material 230 in the internal via 2302 and the sidewalls of the internal via 2302. In other examples, a seed layer may be used to facilitate the plating of vias 208 and 2302.

[0087] Figure 25 The manufacturing stage indicated in the text also follows a subsequent polishing process (e.g., CMP process) to remove excess copper extending above the first surface 218 of the glass core 202. Therefore, in some examples, both the dielectric material 226 and TGV 204 are substantially flush with the first surface 218. Furthermore, Figure 25 This indicates the manufacturing stage following the application (e.g., lamination) of the first buffer layer 214 on the first surface 218 of the glass core 202, the outer surface of the trans-dielectric material 226, and the upper end of the CMIL 1902.

[0088] Figure 26 This indicates the manufacturing stage after the removal of the conductive carrier 702, which includes both the conductive layer 704 and the release layer 706. In some examples, the second surface 220 of the glass core 202 undergoes a polishing process (e.g., CMP process) to make both the dielectric material 226 and TGV 204 substantially flush with the second surface 220. In some examples, the component also undergoes a cleaning process to remove any residual material. Furthermore, Figure 26 This indicates the manufacturing stage following the application (e.g., lamination) of a second buffer layer 216 on the second surface 220 of the glass core 202, the outer surface of the trans-dielectric material 226, and the lower end of the CMIL 1902.

[0089] Figure 27 This indicates the result of adding conductive pads 235 to the buffer layers 214 and 216 of the TGV 204 and electrically coupling the TGV 204 to the conductive pads 235 using conductive vias 2702 extending through the buffer layers 214 and 216. Furthermore, Figure 27 This indicates that conductive pads 234 are added to the buffer layers 214, 216 of the CMIL 1902, and conductive material 230 in the CMIL 1902 is electrically coupled to the conductive pads 234 using conductive vias 2704 extending through the buffer layers 214, 216. More specifically, in some examples, openings (e.g., vias) are provided (e.g., drilled) through the buffer layers and subsequently filled (e.g., via plating) to define the conductive vias 2702, wherein the positions of the conductive pads 234, 235 are defined by a photolithography process. Figure 27 The structure of the example glass core assembly shown corresponds to Figure 19The structure of the example glass core assembly 1900 is shown, and thus represents the completion of the manufacturing process.

[0090] Figure 28 It shows that it can be used Figure 1 Another example glass core assembly 2800 is implemented within the example encapsulation substrate 112. Figure 28 Example glass core assembly 2800 and Figure 19 The example glass core assembly 1900 is substantially the same, except as described below and / or otherwise becomes clear from the context. Therefore, Figure 28 The shown and Figure 19 Corresponding or similar features are identified by the same reference numerals. Furthermore, the above text, in conjunction with... Figure 19 The description of this type of feature is relative to Figure 28 The corresponding features in the text are similarly applicable.

[0091] Figure 28 Examples and Figure 19 The difference lies in the construction of the example CMIL 2802 (e.g., an electronic component) embedded within the cavity 210 in the glass core 202. Specifically, in Figure 19 In CMIL 1902, the two separate portions 1904 and 1908 are defined by two separate regions of magnetic material 232. That is, in Figure 19 In the example shown, different regions of the magnetic material 232 are separated by a portion of the dielectric material 226. In contrast, in Figure 20 In the example shown, the magnetic material 232 associated with the first portion 2804 and the second portion 2806 of CMIL 2802 is defined by a continuous block of magnetic material 232. In other words, in Figure 28 In the example shown, the first portion 2804 of CMIL 2802 includes a first portion of conductive material 230 and a first portion of magnetic material 232 surrounding the first portion of conductive material, wherein the first portion of magnetic material 232 is a continuous extension of the second portion of magnetic material 232 associated with the second portion 2806 of CMIL 2802.

[0092] Figure 29 It shows that it can be used Figure 1 Another example glass core assembly 2900 is implemented within the example encapsulation substrate 112. Figure 29 Example glass core assembly 2900 and Figure 28 The example glass core assembly 2800 is substantially the same, except as described below and / or otherwise becomes clear from the context. Therefore, Figure 29 The shown and Figure 28 Corresponding or similar features are identified by the same reference numerals. Furthermore, the above text, in conjunction with... Figure 28 The description of this type of feature is relative to Figure 29 The corresponding features in the text are similarly applicable.

[0093] Figure 29 Examples and Figure 28 The difference in the examples is the inclusion of a thin-film dielectric 2902 (e.g., a dielectric layer) coated on the outer surface of the glass core 202. In some examples, the thin-film dielectric 2902 is... Figure 3A The thin-film dielectric 302 is basically the same. Therefore, the above combined with Figure 20 The description of the thin film dielectric 2002 is relative to Figure 29 The thin-film dielectric 2902 is similarly applicable.

[0094] manufacture Figure 28 and Figure 29 The process for example glass core modules 2800 and 2900 can follow the above combination. Figure 19 and Figure 20 The example glass core assemblies 1900 and 2000 describe the same or similar processes in detail at different manufacturing stages. Figures 30-36 Manufacturing process is shown Figure 28 and Figure 29 The example glass core components 2800 and 2900 are shown at different stages of the manufacturing process. It can be seen that... Figures 30-36 They usually correspond to Figure 21-26 Therefore, the same reference numerals are used to refer to the same or similar features, and the above are combined. Figure 21-26 The details provided in the description are similarly applicable to Figures 30-36 .

[0095] Figure 21-27 The process flow shown in the middle is the same as Figures 30-36 The main differences between the example process flows shown in the text occur in... Figure 30 The manufacturing stage indicated in the text (usually corresponding to...) Figure 21 Specifically, such as Figure 21 As shown, two separate holes 2104 are created (e.g., by machining, drilling, etc.) within the cavity 210 of the glass core 202, passing through the mask 2102 and the dielectric material 226. In contrast, in Figure 30 In this example, a single (larger) hole 3002 is created (e.g., by machining, drilling, etc.) through a mask 2102 and dielectric material 226 within a cavity 210 of the glass core 202. Figure 30 Hole 3002 in the middle corresponds to Figure 21 The combined area of ​​the two holes 2104 plus the area between the two holes 2104. In other examples, in Figure 30 The hole 3002 produced in the indicated manufacturing stage may be larger or smaller than the hole shown.

[0096] Depend on Figures 31-36 The manufacturing stage indicated usually corresponds to the combination above. Figure 22-27 The main difference in the described manufacturing stages lies in Figure 31 The single hole 3002 produced in the middle, instead of the above combination Figure 21 The two individual holes 2104 are discussed. Therefore, Figure 31 This indicates the manufacturing stage after the magnetic material 232 used in CMIL 212 is filled into a single hole 3002 and the mask 2102 is subsequently removed, similar to the stage described above. Figure 22 As described in [the text]. Figure 32 This indicates the manufacturing stage after drilling the inner through-hole 2302 through the magnetic material 232, similar to the above-mentioned combination. Figure 23 As described. However, it is not through different parts of the magnetic material 232 that a through hole 2302 is drilled (as described). Figure 23 Instead of the shown, the magnetic material 232 of the same (single) block is drilled through the hole 2302 through the same (single) hole 3002. Figure 33 This indicates the manufacturing stage following the application of another mask 2402 and a subsequent etching process to remove portions of the release layer 706, similar to the combination above. Figure 24 As described. Figure 34 This indicates the manufacturing stage following the removal of mask 2402, subsequent plating of conductive material 206 within vias 208 and 2302, and application of the first buffer layer 214, similar to the above-described combination. Figure 25 As described. Figure 35 This indicates the manufacturing stage after the removal of the conductive carrier 702 and the subsequent application of the second buffer layer 216, similar to the bonding described above. Figure 26 As described. Finally. Figure 36 This indicates the result of adding conductive pads 234 and 235 and associated vias 2702 and 2704, similar to the combination above. Figure 27 As described. Figure 36 The structure of the example glass core assembly shown corresponds to Figure 28 The structure of the example glass core assembly 2800 is shown, and thus represents the completion of the manufacturing process.

[0097] Figure 37 It shows that it can be used Figure 1 Another example glass core assembly 3700 is implemented within the example packaging substrate 112. Figure 37 Example glass core assembly 3700 and Figures 2A-2E The example glass core assembly 200 is substantially the same, except as described below and / or otherwise becomes clear from the context. Therefore, Figure 37 The shown with Figures 2A-2E (and related) Figure 4-18 Features that are identical or similar to those in the figures are identified by the same reference numerals. Furthermore, the above combinations... Figures 2A-2E (and related) Figure 4-18 The descriptions of these features are similarly applicable to... Figure 37 The corresponding features in.

[0098] Figure 37 Examples and Figure 2A The difference in the examples lies in the type of electronic components embedded within the cavity 210 in the glass core 202. Specifically, in Figure 2A In the example, CMIL 212 is embedded within cavity 210. In contrast, in... Figure 37 In the example shown, capacitor 3702 (e.g., a deep trench capacitor) is embedded within cavity 210. In this example, capacitor 3702 is a deep trench capacitor implemented on a semiconductor (e.g., silicon) substrate. That is, in this example, capacitor 3702 is a semiconductor die (e.g., similar to...). Figure 1 Semiconductor dies 108 and 110).

[0099] In some examples, capacitor 3702 includes a first surface 3704 (e.g., an upper surface) and a second surface 3706 (e.g., a lower surface) opposite the first surface 3704 to define the thickness of capacitor 3702. In some examples, such as Figure 37 As shown, the thickness of capacitor 3702 is less than the thickness of glass core 202. In other examples, the thickness of capacitor 3702 is approximately equal to the thickness of glass core 202.

[0100] like Figure 37 As shown in the illustrated example, capacitor 3702 is encapsulated in dielectric material 226 (e.g., covered or surrounded by dielectric material 226). Therefore, in some examples, dielectric material 226 separates capacitor 3702 from the sidewall 227 of the cavity 210 of glass core 202. In some examples, at least one of the first surface 3704 or the second surface 3706 of capacitor 3702 (in both illustrated examples) is embedded or recessed relative to the adjacent outer surfaces 218, 220 of glass core 202. In such examples, the embedded surfaces 3704, 3706 are covered by dielectric material 226. That is, as shown in the illustrated example, dielectric material 226 separates capacitor 3702 from buffer layers 214, 216. In other examples, at least one of the first surface or the second surface of capacitor 3702 is substantially flush with the adjacent outer surfaces 218, 220 of glass core 202. In some such examples, the associated buffer layers 214, 216 may be in direct contact with the surfaces 3704, 3706 of the capacitor 3702.

[0101] In this example, capacitor 3702 includes two contact pads 3708 on a first surface 3704, which are electrically coupled to conductive pads 3710 on the first buffer layer 214 via conductive vias extending through the first buffer layer 214. In this example, the contact pads 3708 protrude outward from the first surface 3704 of capacitor 3702, causing the first surface 3704 to be recessed or embedded relative to the outer surface 218 of glass core 202. In other examples, the contact pads 3708 of capacitor 3702 may be embedded within and flush with the first surface 3704 of capacitor 3702.

[0102] Figure 38 It shows that it can be used Figure 1 Another example glass core assembly 3800 is implemented within the example encapsulation substrate 112. Figure 38 Example glass core assembly 3800 and Figure 37 The example glass core assembly 3700 is substantially the same, except as described below and / or otherwise becomes clear from the context. Therefore, Figure 38 The shown and Figure 37 Corresponding or similar features are identified by the same reference numerals. Furthermore, the above text, in conjunction with... Figure 37 The description of this type of feature is relative to Figure 38 The corresponding features in the text are similarly applicable.

[0103] Figure 38 Examples and Figure 37 The difference in the examples is the inclusion of a thin-film dielectric 3802 (e.g., a dielectric layer) coated on the outer surface of the glass core 382. In some examples, the thin-film dielectric 3802 is... Figure 3A The thin-film dielectric 302 is basically the same. Therefore, the above combination Figure 3A The thin-film dielectric 302 described (and associated) Figure 3B-3E The description of ) is similarly applicable to Figure 38 Thin film dielectric 3802.

[0104] manufacture Figure 37 and Figure 38 The process for example glass core modules 3700 and 3800 can follow the above combination. Figure 2A and Figure 3A The example glass core components 380 and 300 discussed are made of Figure 4-7 The different manufacturing stages are described in detail as identical or similar processes. However, in Figure 7 After the manufacturing stage indicated in the text, subsequent processes may diverge. Figures 39-44 Manufacturing process is shown Figure 37 and Figure 38Examples of different stages in the subsequent process flow of glass core components 3700 and 3800.

[0105] Figure 39 This indicates the manufacturing stage after the capacitor 3702 is placed onto the conductive carrier 702 within the cavity 210 of the glass core 202. In some examples, the capacitor 3702 is placed upside down (e.g., the first (upper) surface 3704 faces downward toward the conductive carrier 702). In some such examples, the glass core 202 is also upside down (e.g., the first surface 218 faces downward toward the conductive carrier 702). In other examples, the capacitor 3702 is placed with its face up in the cavity 210.

[0106] Figures 40-43 The manufacturing stage indicated in the middle usually corresponds to the combination above. Figure 8-11 The described process flow, except for the presence of capacitor 3702 within the cavity, therefore, the above is aimed at... Figure 8-11 The provided description is similar to Figures 40-43 The manufacturing stages referred to herein, except as described below and / or otherwise become clear from the context. Specifically, Figure 40 This indicates the manufacturing stage after the cavity 210 in the glass core 202 is filled with dielectric material 226, similar to the above-described bonding process. Figure 8 As described. In this example, dielectric material 226 is distributed around capacitor 3702, which is already positioned within cavity 210. Thus, dielectric material 226 surrounds (e.g., encapsulates, covers, etc.) capacitor 3702. Figure 41 This indicates the manufacturing stage following the application of mask 902 and subsequent etching process to remove portions of release layer 706, similar to the combination above. Figure 9 As described. Figure 42 This indicates the manufacturing stage after removing the mask 902 and subsequently plating the conductive material 206 within the through-hole 208 to define the TGV 204, similar to the combination above. Figure 10 As described. Figure 43 This indicates the manufacturing stage after the removal of the conductive carrier 702, similar to the bonding process described above. Figure 11 As described.

[0107] Figure 44 This indicates the manufacturing stage following the application (e.g., lamination) of the first buffer layer 214 and the second buffer layer 216 on the respective outer surfaces 218, 220 of the glass core 202 and the outer surface of the dielectric material 226 within the transcavity 210. Figure 44This also represents the result of adding conductive vias 1202 through buffer layers 214, 216 to electrically couple the underlying TGV 204 to the corresponding conductive pad 235 and to electrically couple the contact pad 3708 of capacitor 3702 to the corresponding conductive pad 3710. The outer layer 1204 is made of conductive material. More specifically, holes (e.g., vias) are drilled through buffer layers 214, 216 to expose the ends of the TGV 204 and the contact pad 3708 of capacitor 3702. The holes are then filled with material to define the conductive vias 1206 and to create the conductive pads 235, 3710. Figure 44 It also indicates that the entire component is inverted or flipped so that capacitor 3702 is facing upwards. Figure 44 The structure of the example glass core assembly shown corresponds to Figure 37 The example glass core assembly 3700 shown illustrates the structure and thus represents the completion of the manufacturing process.

[0108] The foregoing examples of glass core assemblies 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 teach or suggest different features. Although each of the example glass core assemblies 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 disclosed above has certain features, it should be understood that a particular feature of an example need not be used exclusively with that example. Rather, any feature depicted above and / or in the figures may be combined with any example, in addition to or in lieu of any other feature of those examples. Features of one example are not mutually exclusive with features of another example. Rather, the scope of this disclosure covers any combination of any features. Thus, for example, as... Figure 2A , Figure 3A , Figure 19 , Figure 20 , Figure 28 and Figure 29 The two or more different CMIL structures shown can be implemented within the same glass core (e.g., within the same cavity or different cavities within the glass core). Furthermore, Figure 37 and Figure 38 Capacitor 3702 can be used with Figure 2A , Figure 3A , Figure 19 , Figure 20 , Figure 28 and Figure 29 Any CMIL structure is implemented in the same glass core (e.g., in the same or different cavities within the glass core).

[0109] Figure 45 An example glass panel 4500 is shown, which can be processed according to the teachings disclosed herein for production. Figure 2A , Figure 3A , Figure 19 , Figure 20 , Figure 28 , Figure 29 , Figure 37 and Figure 38 Any example glass core assembly 200, 300, 1900, 2000, 2800, 2900, 3700, 3800. In the example shown, glass panel 4500 is defined corresponding to a specific encapsulation substrate (e.g., Figure 1 A specific glass core (e.g., of the encapsulation substrate 112) Figure 1 Individual active regions 4502, 4504, 4506, and 4508 associated with the glass core 132. That is, during subsequent manufacturing stages, Figure 45 The example glass panel 4500 will be cut or divided into four separate pieces to serve as the base for four separate encapsulation substrates. The area outside the active regions 4502, 4504, 4506, and 4508 is referred to as the restricted area (KOZ) 4510.

[0110] like Figure 45 As shown, the KOZ 4510 of the glass panel 4500 includes one or more machining holes 4512. The machining holes facilitate the manipulation and / or positioning of the glass panel 4500 and / or facilitate the alignment of manufacturing tools relative to the glass panel 4500 during various stages of manufacturing. That is, in some examples, the machining holes 4512 serve as reference marks for alignment purposes. Although four machining holes 4512 are shown in the KOZ 4510, a different number of machining holes 4512 may be implemented in other examples. In some examples, the machining holes 4512 are omitted. Furthermore, while machining holes 4512 are most commonly implemented in the KOZ 4510 (so as not to occupy space within the active regions 4502, 4504, 4506, 4508), in some examples, one or more additional machining holes 4514 are included in one or more of the active regions 4502, 4504, 4506, 4508. In this example, an additional machined hole 4514 is included in one of the active regions (e.g., the first active region 4502). In other examples, more than one (e.g., all) of the active regions 4502, 4504, 4506, and 4508 include one or more machined holes 4514. In other examples, none of the active regions 4502, 4504, 4506, and 4508 include a machined hole 4514.

[0111] In some examples, machined holes 4512 and 4514 are manufactured during the same manufacturing process used to produce through-holes 208 for TGV 204 and cavity 210 to accommodate electronic components (e.g., one or more of CMIL 212, 1902, 2802, and / or capacitor 3702, etc.). That is, in some examples, the above is combined... Figure 5 and Figure 6 Holes 4512 and 4514 are manufactured during the LIDE process discussed. Figure 45 In the example shown, through hole 208 and cavity 210 are not shown for simplicity. Furthermore, machined holes 4512 and 4514 are typically much larger than through hole 208 and can be much larger than cavity 210.

[0112] Since the processed holes 4512 and 4514 are formed simultaneously with the through-hole 208 and the cavity 210, in examples including thin-film dielectrics 302, 2002, 2902, and 3802, the inner walls of the processed holes 4512 and 4514 are lined or coated with thin-film dielectrics 302, 2002, 2902, and 3802. However, because the processed holes 4512 and 4514 are relatively large compared to other openings in the glass panel 4500 (e.g., through-hole 208 and cavity 210), the processed holes 4512 and 4514 will not be filled with conductive material 206 (as described above) during the bottom-up plating process to form TGV 204. Figure 9 and 10 (As discussed above). That is, even after the plating process that produces TGV 204, the machined holes 4512 and 4514 will remain empty. Therefore, in some examples, the machined holes 4512 and 4514 are filled with a different material applied during a later manufacturing process. More specifically, in some examples, the machined holes 4512 and 4514 will be filled with magnetic material 232. As discussed above... Figure 14 In some examples, the magnetic material 232 is deposited as a paste or resin that subsequently cures. More specifically, in some examples, the magnetic material 232 is applied as a paste to the entire surface of the glass panel 4500, resulting in the machined holes 4512, 4514 being filled with the magnetic material 232, such as... Figure 46 As shown.

[0113] Figure 46 This illustrates the inclusion of within example frame 4602. Figure 45 Example glass panel 4500 and example reconstructed panel 4600. Example frame 4602 enables compatibility with manufacturing tools specifically designed for organic cores rather than glass cores. That is, example frame 4602 enables the glass panel 4500 to be processed using manufacturing techniques typically designed for organic cores, while protecting the glass panel 4500 from damage. Figure 46As shown, the machined holes 4512 and 4514 are filled with magnetic material 232, which also extends around the outer periphery of the glass panel 4500. In some examples, different materials extend along the outer periphery of the glass panel 4500, where the magnetic material 232 still fills the machined holes 4512 and 4514. Therefore, the presence of magnetic material 232 within the machined holes 4512 and 4514 is part of the development... Figure 5 The glass panel 4500 follows the instructions of the example manufacturing process disclosed herein.

[0114] Figure 47A-49 It means that manufacturing can be done Figure 1 The example IC package 100 is implemented Figure 2A , Figure 3A , Figure 19 , Figure 20 , Figure 28 , 29 Flowcharts of example methods for any of the example glass core assemblies 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800. In some examples, Figure 47A-49 Some or all of the operations outlined in the example methods are performed automatically by a manufacturing device programmed to perform the operations. That is, in some examples, the example methods or portions thereof may be implemented and / or controlled by one or more processor circuits based on data from sensors and / or user input instructions. Although the references... Figure 47A-49 The flowcharts described herein illustrate an example manufacturing method, but many other methods may be used alternatively. For example, the execution order of the boxes may be changed, and / or some of the described boxes may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, in some examples, additional processing operations may be performed before, between, and / or after any of the boxes represented in the illustrated examples.

[0115] The example process begins at frame 4702, where an opening is added through a glass core (e.g., glass core 202). In some examples, glass core 202 at this manufacturing stage is a glass panel (such as...) Figure 45 This is part of an example glass panel 4500. In some examples, the openings added to the glass core 202 include a through-hole 208 for a TGV 204, a cavity 210 for accommodating electronic components, and / or machined holes 4512, 4514. In some examples, this is achieved through the combination of the above... Figure 5 and Figure 6 The LIDE process discussed is used to add openings.

[0116] At box 4704, the example process involves determining whether to add a thin-film dielectric layer. If so, the process proceeds to box 4706, where the exposed surfaces of the glass core are coated with a thin-film dielectric (e.g., thin-film dielectrics 302, 2002, 2902, 3802). The process then proceeds to box 4708. If no thin-film dielectric layer is added (as determined at box 4704), the process proceeds directly to box 4708.

[0117] At box 4708, the example process involves attaching a glass core to a conductive carrier (e.g., as described above in conjunction with...). Figure 7 The conductive carrier 702 under discussion. At block 4710, the example process involves determining whether at least one opening includes at least one semiconductor device (e.g., capacitor 3702 and / or any other suitable semiconductor device). If so, the process proceeds to block 4712, where a semiconductor device is placed within the opening (e.g., capacitor 3702 is placed together with cavity 210, as described above). Figure 39 (As discussed). The process then proceeds to box 4714. If no semiconductor device (as defined at box 4710) is included, the process proceeds directly to box 4714.

[0118] At box 4714, the example process involves depositing a dielectric material (e.g., dielectric material 226) into an opening (e.g., cavity 210) including a semiconductor device and / or any other opening (e.g., other cavity 210) to include at least one CMIL (e.g., at least one of CMIL 212, 1902, 2802).

[0119] At box 4716, the example process involves determining whether at least one CMIL will include a conductive material (e.g., conductive material 230) deposited simultaneously (e.g., concurrently) with the conductive material (e.g., conductive material 206) deposited for TGV 204. If so, the process proceeds to box 4706, where the CMIL structure is fabricated to be plated simultaneously with TGV 204. (See below for details.) Figure 48 Further details regarding the implementation of box 4718 are provided. The process then proceeds to box 4720. If no CMIL includes conductive material deposited simultaneously with the conductive material of the TGV (as determined at box 4716), the process proceeds directly to box 4720.

[0120] At box 4720, the example process involves applying a mask that exposes the opening to be plated (e.g., in conjunction with the above). Figure 9 , Figure 24 , Figure 33 , Figure 41(Either of the masks 902 and 2402 discussed). In some examples, these openings include through-holes 208 for the TGV 204, while the cavity 210 is covered, as in combination. Figure 9 and 41 As shown and described. In some examples, the opening also includes an internal through-hole 2302 within a magnetic material 232 inside the cavity 210, such as in combination Figure 23 and Figure 32 As shown and described. Thereafter, the process proceeds to... Figure 47B Box 4722 is shown at the top.

[0121] At box 4722, the example process involves depositing conductive material into the exposed opening. In the example where only the via 208 for TGV204 is exposed, the conductive material corresponds to the combination as described above. Figure 10 and Figure 42 The conductive material 206 is discussed. In the example where the internal through-hole 2302 within the magnetic material 232 is also exposed, the conductive material corresponds to both conductive material 206 and conductive material 230 within CMIL 1902 and 2802, as described above. Figure 25 and Figure 34 The subject of discussion.

[0122] At box 4724, the example process involves removing masks 902 and 2402 from glass core 202. At box 4726, the example process involves removing conductive carrier 702 from glass core 202. At box 4728, the example process involves depositing a buffer layer (e.g., buffer layers 214, 216) onto the outer surfaces 218 and 220 of glass core 202. In some examples, a first buffer layer 214 (e.g., ...) may be added before removing conductive carrier 702. Figure 25 and Figure 26 or Figure 34 and Figure 35 (As shown in the image). In other examples, the conductive carrier 702 is removed before adding buffer layers 214, 216 (as shown in the image). Figure 11 and Figure 12 or Figure 43 and Figure 44 (As shown).

[0123] At box 4730, the example process involves adding a conductive via through buffer layers 214, 216 (e.g., in conjunction with the above). Figure 12 , Figure 27 , Figure 36 , Figure 44 The conductive vias 1202, 2702, and 2704 are discussed. In some examples, the conductive vias are connected to the contact pads 3708 below the TGV 204, the copper core below the CMIL, and / or the capacitor 3702.

[0124] At block 4732, the example process involves determining whether at least one CMIL will include a conductive material (e.g., conductive material 230) deposited separately from TGV 204. If so, the process proceeds to block 4734, where the CMIL is fabricated using the conductive material deposited separately from TGV 204. In some examples, a separate plating of the CMIL is employed to enable the inclusion of a non-magnetic plug (e.g., non-magnetic plug 228). (The following is in conjunction with...) Figure 49 Further details regarding the implementation of box 4734 are provided. The process then proceeds to box 4736. If no CMIL includes conductive material deposited separately from the TGV (as determined at box 4732), the process proceeds directly to box 4736.

[0125] At box 4736, the example process involves adding conductive pads to electrically couple to a conductive via (added at box 4730) and / or covering the end of the CMIL (as in combination). Figure 17 and Figure 18 (As described). After that, Figure 47A and Figure 47B The example process has ended.

[0126] Figure 48 It means to realize Figure 47A The flowchart for the example process in box 4718. The example process begins in box 4802, where a mask is applied (e.g., in conjunction with the above). Figure 21 and Figure 30 The mask 2102 is described to cover the opening (e.g., through-hole 208) of the TGV 204. At frame 4804, the example process involves drilling a hole through a dielectric material extending through the opening in the glass core 202. In some examples, the hole is also drilled through the mask 2102. In some examples, multiple holes are drilled (e.g., Figure 21 Hole 2104) is used to define different portions of a given CMIL (e.g., different portions 1904 and 1906 of CMIL 1902). In other examples, a single hole is drilled (e.g., Figure 30 Hole 3002) to define the area of ​​all parts of a given CMIL (e.g., the two parts 2804, 2806 of CMIL 2802).

[0127] At box 4806, the example process involves using magnetic materials (e.g., as described above in conjunction with...). Figure 22 and Figure 31 The magnetic material 232 described herein fills the holes. As described above, in some examples, the magnetic material 232 is added as a paste covering the entire underlying component. Therefore, in some examples, the magnetic material 232 also fills the machined holes 4512, 4514. The magnetic material 232 within the machined holes 4512, 4514 is not used for any purpose, but is a result of the manufacturing process disclosed herein.

[0128] At frame 4808, the example process involves removing mask 2102 from glass core 202. At frame 4810, the example process involves drilling an internal through-hole through magnetic material 232 (e.g., as described above). Figure 23 and Figure 32 The aforementioned internal through hole 2302). Thereafter, Figure 48 The example process ends and returns to complete. Figure 47A and Figure 47B Example process.

[0129] Figure 49 It means to realize Figure 47B The flowchart for the example process in box 4734 is shown. The example process begins in box 4902, where an outer layer of conductive material is added above buffer layers 214, 216 (e.g., bonded to the top). Figure 12 The outer layer 1204 of the conductive material is described. At box 4904, the example process involves drilling a hole through the dielectric material extending through an opening in the glass core 202. In some examples, the hole is also drilled through the outer layer 1204 of the conductive material and the buffer layers 214, 216. In some examples, multiple holes are drilled (e.g., Figure 13 Hole 1302 is drilled to define different portions of a given CMIL (e.g., different portions 222, 224 of CMIL 212). In other examples, a single hole is drilled to define an area for all portions of a given CMIL (e.g., similar to the combination above). Figure 28-36 (As described in CMIL 2802).

[0130] At box 4906, the example process involves using magnetic materials (e.g., as described above in conjunction with...). Figure 14 The magnetic material 232 described above fills the hole. At frame 4908, the example process involves drilling an internal through-hole through the magnetic material 232 (e.g., as described above in conjunction with...). Figure 15 The internal through hole 1502 is mentioned.

[0131] At frame 4910, the example process involves plating the walls of the internal through-hole 1502 with a conductive material, thereby opening the central area (as in combination). Figure 16 (As shown and described). At box 4912, the example process involves using a non-magnetic plug (e.g., Figure 16 The non-magnetic plug 228 shown fills the central region. At box 4914, the example process involves polishing the glass core assembly to produce a flat outer surface. Thereafter, Figure 49 The example process ends and returns to complete. Figure 47A and Figure 47B Example process.

[0132] With the information disclosed in this article Figure 2A , Figure 3A, Figure 19 , Figure 20 , Figure 28 , Figure 29 , Figure 37 and Figure 38 Any of the example glass core assemblies 200, 300, 1900, 2000, 2800, 2900, 3700, and 3800 Figure 1 The example IC package 100 can be included in any suitable electronic component. Figures 50-53 Various examples of devices that may be included or can be included in the IC package 100 disclosed herein are shown.

[0133] Figure 50 It can be included in Figure 1 A top view of a wafer 5000 and die 5002 (e.g., as any suitable die 108, 110) in an IC package 100. The wafer 5000 includes semiconductor material and one or more dies 5002 having circuitry. Each die 5002 can be a repeating unit of a semiconductor product. After the semiconductor product manufacturing is complete, the wafer 5000 can undergo a dicing process, in which the dies 5002 are separated from each other to provide discrete “chips.” Each die 5002 includes one or more transistors (e.g., discussed below). Figure 51 The die 5002 may include some of the transistors 5140, support circuitry for transmitting electrical signals to the transistors, passive components (e.g., traces, resistors, capacitors, inductors, and / or other circuitry), and / or any other components. In some examples, the die 5002 may include and / or implement memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), conductive bridged RAM (CBRAM), etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuitry or electronic devices. Multiple such devices may be combined on a single die 5002. For example, a memory array of multiple memory circuits may be formed in conjunction with programmable circuitry (e.g., Figure 53 The processor circuitry 5302 and / or other logic circuitry are located on the same die 5002. Such a memory can store information for use by programmable circuitry. The example IC package 100 disclosed herein can be manufactured using die-to-wafer assembly technology, in which some dies are attached to a wafer 5000 that includes other dies, and the wafer 5000 is subsequently diced.

[0134] Figure 51This is a cross-sectional side view of an IC device 5100 that may be included in an example IC package 100 (e.g., in any of dies 108, 110). One or more of the IC devices 5100 may be included in one or more dies 5002 ( Figure 50 The IC device 5100 can be formed on the die substrate 5102 (e.g., Figure 50 On a 5000 wafer, and may be included in a die (e.g., Figure 50 The die substrate 5102 may be a semiconductor substrate comprising a semiconductor material, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 5102 may include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some examples, the die substrate 5102 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 5102. Although several examples of materials that can form the die substrate 5102 are described herein, any material that can be used as the basis for the IC device 5100 may be used. The die substrate 5102 may be a diced die (e.g., Figure 50 5002 die) or wafer (e.g., Figure 50 The portion of the 5000 wafer.

[0135] IC device 5100 may include one or more device layers 5104 disposed on and / or above die substrate 5102. Device layer 5104 may include features of one or more transistors 5140 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on die substrate 5102. Device layer 5104 may include, for example, one or more source and / or drain (S / D) regions 5120, a gate 5122 for controlling current flow between S / D regions 5120, and one or more S / D contacts 5124 for transmitting electrical signals to / from S / D regions 5120. Transistor 5140 may include additional features, such as device isolation regions, gate contacts, etc., not shown for clarity. Transistor 5140 is not limited to... Figure 51 The types and configurations described herein may include a wide variety of other types and / or configurations, such as planar transistors, non-planar transistors, or combinations thereof. Non-planar transistors may include fin-type transistors (FinFET transistors), such as dual-gate or tri-gate transistors, as well as gate-around or fully-around transistors, such as nanoribbon and nanowire transistors.

[0136] Each transistor 5140 may include a gate 5122, which includes a gate dielectric and a gate electrode. The gate dielectric may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some examples, when using a high-k material, an annealing process may be performed on the gate dielectric to improve its quality.

[0137] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 5140 is a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, the gate electrode may comprise a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any metal discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and / or aluminum carbide), and / or any metal discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0138] In some examples, when a cross-section of transistor 5140 is viewed along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom portion substantially parallel to the surface of die substrate 5102 and two sidewall portions substantially perpendicular to the top surface of die substrate 5102. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer substantially parallel to the top surface of die substrate 5102 and does not include sidewall portions substantially perpendicular to the top surface of die substrate 5102. In other examples, the gate electrode may include a combination of a U-shaped structure and / or a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0139] In some examples, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching operations. In some examples, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0140] The S / D region 5120 can be formed within a die substrate 5102 adjacent to the gate 5122 of the corresponding transistor 5140. For example, the S / D region 5120 can be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be implanted into the die substrate 5102 to form the S / D region 5120. An annealing process to activate the dopant and further diffuse them into the die substrate 5102 can be performed after the ion implantation process. In the latter process, the die substrate 5102 can be etched first to form a trench at the location of the S / D region 5120. An epitaxial deposition process can then be performed to fill the trench with the material used to fabricate the S / D region 5120. In some embodiments, the S / D region 5120 can be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy can be in situ doped with dopant such as boron, arsenic, or phosphorus. In some examples, one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys, may be used to form the S / D region 5120. In other examples, one or more layers of metal and / or metal alloys may be used to form the S / D region 5120.

[0141] Electrical signals such as power and / or input / output (I / O) signals can be transmitted through one or more interconnect layers disposed on device layer 5104 (in Figure 51 The interconnect layers 5106-5110 are shown as interconnect layers 5106-5110, which transfer devices (e.g., transistor 5140) to and / or from device layers 5104 (e.g., transistor 5140). For example, conductive features of device layers 5104 (e.g., gate 5122 and S / D contact 5124) may be electrically coupled to interconnect structures 5128 of interconnect layers 5106-5110. One or more interconnect layers 5106-5110 may form a metallized stack (also referred to as an "ILD stack") 5119 of IC device 5100.

[0142] Interconnection structure 5128 can be arranged within interconnect layers 5106-5110 to transmit electrical signals according to various designs (in particular, the arrangement is not limited to...). Figure 51 The specific configuration of the interconnect structure 5128 depicted in the diagram). Although in Figure 51 The disclosure depicts a specific number of interconnect layers 5106-5110, but examples of this disclosure include IC devices having more or fewer interconnect layers than depicted.

[0143] In some examples, the interconnect structure 5128 may include lines 5128A and / or vias 5128B filled with a conductive material such as a metal. Line 5128A may be arranged to transmit electrical signals in a direction substantially parallel to a plane parallel to the surface of the die substrate 5102 on which the device layer 5104 is formed. For example, from Figure 51 From this angle, line 5128A can transmit electrical signals in the direction of entering and exiting the page. Via 5128B can be arranged to transmit electrical signals in a direction substantially perpendicular to the plane of the die substrate 5102 on which the device layer 5104 is formed. In some examples, via 5128B can electrically couple lines 5128A of different interconnect layers 5106-5110 together.

[0144] Interconnect layers 5106-5110 may include dielectric material 5126 disposed between interconnect structures 5128, such as Figure 51 As shown. In some examples, the dielectric material 5126 disposed between interconnect structures 5128 in different interconnect layers 5106-5110 may have different compositions; in other examples, the composition of the dielectric material 5126 between different interconnect layers 5106-5110 may be the same.

[0145] A first interconnect layer 5106 (referred to as metal 1 or "M1") may be formed directly on device layer 5104. In some examples, the first interconnect layer 5106 may include a line 5128A and / or a via 5128B, as shown. The line 5128A of the first interconnect layer 5106 may be coupled to a contact portion (e.g., S / D contact 5124) of device layer 5104.

[0146] The second interconnect layer 5108 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 5106. In some examples, the second interconnect layer 5108 may include vias 5128B to couple lines 5128A of the second interconnect layer 5108 to lines 5128A of the first interconnect layer 5106. Although for clarity, lines 5128A and vias 5128B are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 5108), in some examples, lines 5128A and vias 5128B may be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).

[0147] The third interconnect layer 5110 (referred to as metal 3 or "M3") (and any additional interconnect layers as needed) may be formed sequentially on the second interconnect layer 5108 according to similar techniques and / or configurations described in conjunction with the second interconnect layer 5108 or the first interconnect layer 5106. In some examples, the interconnect layers that are "higher" (i.e., further away from the device layer 5104) in the metallization stack 5119 of the IC device 5100 may be thicker.

[0148] IC device 5100 may include solder resist material 5134 (e.g., polyimide or similar material) and one or more conductive contacts 5136 formed on interconnect layers 5106-5110. Figure 51 In the diagram, conductive contact 5136 is shown in the form of a bonding pad. Conductive contact 5136 may be electrically coupled to interconnect structure 5128 and configured to transmit electrical signals from transistor 5140 to other external devices. For example, solder bonding portions may be formed on one or more conductive contacts 5136 to mechanically and / or electrically couple a chip including IC device 5100 to another component (e.g., a circuit board). IC device 5100 may include additional or alternative structures to transmit electrical signals from interconnect layers 5106-5110; for example, conductive contact 5136 may include other similar features (e.g., posts) for transmitting electrical signals to external components.

[0149] Figure 52 This may be a cross-sectional side view of an IC device assembly 5200 that may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 5200 includes a plurality of components disposed on a circuit board 5202 (which may be, for example, a motherboard). The IC device assembly 5200 includes components disposed on a first surface 5240 and an opposing second surface 5242 of the circuit board 5202; typically, the components may be disposed on one or both of surfaces 5240 and 5242. Any IC package discussed below with reference to the IC device assembly 5200 may take the form of... Figure 1 The example IC is packaged in the form of 100.

[0150] In some examples, circuit board 5202 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 5202 (optionally in combination with other metal layers). In other examples, circuit board 5202 may be a non-PCB substrate.

[0151] Figure 52The IC device assembly 5200 shown includes an on-intermediate package structure 5236 coupled to a first side 5240 of a circuit board 5202 via a coupling member 5216. The coupling member 5216 can electrically and mechanically couple the on-intermediate package structure 5236 to the circuit board 5202 and may include solder balls (such as...). Figure 52 (as shown), the convex and concave portions of the socket, adhesive, bottom filler material and / or any other suitable electrical and / or mechanical coupling structure.

[0152] The interposer-on-package structure 5236 may include an IC package 5220 coupled to the interposer 5204 via a coupling member 5218. The coupling member 5218 may take any suitable form for the application, such as the form discussed above with reference to coupling member 5216. Although in Figure 52 A single IC package 5220 is shown, but multiple IC packages can be coupled to an interposer 5204; in fact, additional interposers can be coupled to interposer 5204. Interposer 5204 can provide an intermediary substrate for bridging the circuit board 5202 and the IC package 5220. The IC package 5220 can be or includes, for example, a die ( Figure 50 5002 die), IC device (e.g., Figure 51 This can be an IC device 5100 or any other suitable component. Typically, the interposer 5204 can extend connections to wider spacing or rewire connections to different connections. For example, the interposer 5204 can couple an IC package 5220 (e.g., a die) to a set of BGA conductive contacts on a coupling member 5216 to couple to a circuit board 5202. Figure 52 In the example shown, IC package 5220 and circuit board 5202 are attached to opposite sides of interposer 5204; in other examples, IC package 5220 and circuit board 5202 may be attached to the same side of interposer 5204. In some examples, three or more components may be interconnected via interposer 5204.

[0153] In some examples, the interposer 5204 may be formed as a PCB comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some examples, the interposer 5204 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some examples, the interposer 5204 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. Interposer 5204 may include metal interconnects 5208 and vias 5210, including but not limited to through-silicon vias (TSVs) 5206. Interposer 5204 may also include embedded devices 5214, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on interposer 5204. The on-interposer package structure 5236 may take the form of any on-interposer package structure known in the art.

[0154] IC device assembly 5200 may include an IC package 5224 coupled to a first side 5240 of circuit board 5202 via a coupling member 5222. The coupling member 5222 may take the form of any of the examples discussed above with reference to coupling member 5216, and the IC package 5224 may take the form of any of the examples discussed above with reference to IC package 5220.

[0155] Figure 52 The IC device assembly 5200 shown includes a package-on-package structure 5234 coupled to a second side 5242 of a circuit board 5202 via a coupling member 5228. The package-on-package structure 5234 may include a first IC package 5226 and a second IC package 5232 coupled together via a coupling member 5230, such that the first IC package 5226 is disposed between the circuit board 5202 and the second IC package 5232. The coupling members 5228 and 5230 may take the form of any example of the coupling member 5216 discussed above, and the IC packages 5226 and 5232 may take the form of any example of the IC package 5220 discussed above. The package-on-package structure 5234 can be configured according to any package-on-package structure known in the art.

[0156] Figure 53This is a block diagram of an example electrical device 5300 that may include one or more of the example IC package 100. For example, any suitable component of the electrical device 5300 may include one or more of the device assembly 5200, IC device 5100, or die 5002 disclosed herein, and may be arranged in the example IC package 100. Figure 53 The diagram illustrates several components included in electrical device 5300, but any one or more of these components may be omitted or copied to suit an application. In some examples, some or all of the components included in electrical device 5300 may be attached to one or more motherboards. In some examples, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0157] Additionally, in various examples, electrical device 5300 may not include... Figure 53 The electrical device 5300 may include one or more components as shown, but may include interface circuitry for coupling to one or more components. For example, the electrical device 5300 may not include the display 5306, but may include display interface circuitry (e.g., connector and driver circuitry) to which the display 5306 may be coupled. In another set of examples, the electrical device 5300 may not include an audio input device 5318 (e.g., a microphone) or an audio output device 5308 (e.g., a speaker, headphones, earbuds, etc.), but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 5318 or audio output device 5308 may be coupled.

[0158] Electrical device 5300 may include programmable circuitry 5302 (e.g., one or more processing devices). Programmable circuitry 5302 may include one or more digital signal processors (DSPs, application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. Electrical device 5300 may include memory 5304, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives). In some examples, memory 5304 may include memory sharing a die with programmable circuitry 5302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0159] In some examples, electrical device 5300 may include communication chip 5312 (e.g., one or more communication chips). For example, communication chip 5312 may be configured to manage wireless communication for transmitting data to and from electrical device 5300. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can transmit data by using modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated devices do not contain any wires, although in some examples they may not.

[0160] The 5312 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to IEEE standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) projects, and any revisions, updates, and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Global Microwave Access Interoperability, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The 5312 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), General Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The 5312 communication chip can operate according to Enhanced Data Evolution (EDGE), GSM... The communication chip 5312 can operate according to EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 5312 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other examples, the communication chip 5312 can operate according to other wireless protocols. The electrical device 5300 may include an antenna 5322 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0161] In some examples, communication chip 5312 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, communication chip 5312 may include multiple communication chips. For example, a first communication chip 5312 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 5312 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some examples, the first communication chip 5312 may be dedicated to wireless communications, and the second communication chip 5312 may be dedicated to wired communications.

[0162] Electrical device 5300 may include battery / power circuit 5314. Battery / power circuit 5314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 5300 to an energy source (e.g., AC line power) separate from electrical device 5300.

[0163] Electrical device 5300 may include display 5306 (or corresponding interface circuitry, as described above). Display 5306 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0164] Electrical device 5300 may include audio output device 5308 (or corresponding interface circuitry, as described above). Audio output device 5308 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0165] Electrical device 5300 may include audio input device 5318 (or corresponding interface circuitry, as described above). Audio input device 5318 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0166] Electrical device 5300 may include GPS circuitry 5316. GPS circuitry 5316 may communicate with satellite-based systems and may receive the location of electrical device 5300, as is known in the art.

[0167] Electrical device 5300 may include any other output device 5310 (or corresponding interface circuitry, as described above). Examples of other output devices 5310 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0168] Electrical device 5300 may include any other input device 5320 (or corresponding interface circuitry, as described above). Examples of other input devices 5320 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices (such as mice, styluses, touchpads), barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0169] Electrical device 5300 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop electrical device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some examples, electrical device 5300 can be any other electronic device that processes data.

[0170] "Comprising" and "including" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "include" or "comprise" (e.g., includes, includes, comprising, including, having, etc.) as a preamble or within any kind of claim statement, it should be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or statement. As used herein, when the phrase "at least" is used as a transitional term, for example, in the preamble of a claim, it is open-ended in the same way that the terms "comprising" and "including" are open-ended. When used, for example, in the form of A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or operation of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or operation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0171] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude plural. As used herein, the term "a" or "an" refers to one or more of that object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that the combination of features is impractical and / or disadvantageous.

[0172] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the Earth. The first part is above the second part if the second part has at least one portion between the Earth and the first part. Similarly, as used herein, the first part is "below" the second part when the first part is closer to the Earth than the second part. As stated above, the first part may be above or below the second part and may have one or more of the following: other portions between them, no other portions between them, the first and second parts in contact, or the first and second parts not in direct contact with each other.

[0173] Nevertheless, in the context of a semiconductor device (e.g., a transistor), a semiconductor die containing the semiconductor device, and / or an integrated circuit (IC) package containing the semiconductor die during fabrication or manufacturing, "above" does not refer to the Earth, but rather to the substrate on which the relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Therefore, as used herein and unless the context otherwise states or implies, when a first component (e.g., a transistor or other semiconductor device) within a semiconductor die is located further away from the substrate (e.g., a semiconductor wafer) during fabrication / manufacturing than a second component on which both components are fabricated or otherwise provided, the first component is "above" the second component within the semiconductor die. Similarly, unless the context otherwise states or implies, when a first component (e.g., a semiconductor die) within an IC package is located away from the printed circuit board (PCB) to which the IC package is to be mounted or attached, the first component is "above" the second component within the IC package during manufacturing. It should be understood that semiconductor devices are typically used during manufacturing in orientations different from their original orientation. Therefore, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to the earth) will likely be governed by the context of use.

[0174] As used in this patent, a statement that any part (e.g., a layer, film, region, area, or plate) is on another part in any way (e.g., positioned on another part, located on another part, disposed on another part, or formed on another part, etc.) indicates that the referenced part is in contact with the other part or that the referenced part is above the other part, wherein one or more intermediate parts are located therebetween.

[0175] As used herein, unless otherwise stated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include intermediate components between the elements referenced by the connection reference and / or relative movement between these elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected and / or fixed to each other. As used herein, the statement that any part is in “contact” with another part is defined as meaning that there is no intermediate part between the two parts.

[0176] Unless otherwise specified, descriptive terms such as “first,” “second,” “third,” etc., are used herein without imposing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and / or any sorting, but merely as labels and / or arbitrary names to distinguish elements in order to facilitate understanding of the disclosed examples. In some examples, the descriptive term “first” may be used to refer to an element in a specific description, while in the claims the same element may be referred to by different descriptive terms (such as “second” or “third”). In such cases, it should be understood that such descriptive terms are only used to clearly identify those elements in the context of discussion (e.g., in the claims), where elements may otherwise share the same name, for example.

[0177] As used herein, “approximately” and “about” modify their subject / value to identify the potential presence of variations that occur in real-world applications. For example, as those skilled in the art will understand, “approximately” and “about” can modify dimensions that may not be precise due to manufacturing tolerances and / or other real-world defects. For example, unless otherwise stated herein, “approximately” and “about” can indicate that such a dimension is within a tolerance of + / - 10%.

[0178] As used in this article, "substantially real-time" means occurring in a near-instantaneous manner, acknowledging the real-world delays that may exist in computation time, transmission, etc. Therefore, unless otherwise stated, "substantially real-time" means real-time plus 1 second.

[0179] As used herein, the phrase “communication” (including its variations) covers direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals and / or one-off events.

[0180] As used herein, “programmable circuit” is defined as including (i) one or more special-purpose circuits (e.g., special-purpose circuits (ASICs) configured to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform specific functions and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include programmable microprocessors, such as a central processing unit (CPU) capable of executing a first instruction to perform one or more operations and / or functions, an FPGA that can be programmed with a second instruction to configure and / or construct a field-programmable gate array (FPGA) to instantiate one or more operations and / or functions corresponding to the first instruction, a graphics processing unit (GPU) capable of executing a first instruction to perform one or more operations and / or functions, a digital signal processor (DSP), an XPU, a network processing unit (NPU), one or more microcontrollers capable of executing a first instruction to perform one or more operations and / or functions, and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof), and orchestration techniques (e.g., application programming interfaces (APIs)) that can assign computing tasks to any of the multiple types of programmable circuits that is suitable and can be used to perform the computing tasks.

[0181] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0182] Based on the foregoing, it should be understood that the example systems, devices, and articles of manufacture include glass cores having various types of cavities, holes, and / or openings, the sizes of which can vary significantly. Furthermore, example methods have been disclosed that enable the fabrication of such glass cores with various types and / or sizes of cavities, holes, and / or openings during a single LIDE process, thereby avoiding the problems associated with performing multiple LIDE processes at different times to produce different types of cavities, holes, and / or openings. More specifically, in some examples, the different types of openings include through-holes for TGV and larger cavities to house embedded electronic components (e.g., CMILs, capacitors, semiconductor devices, etc.). Moreover, the examples disclosed herein ensure that the features and / or structures to be provided in the different types of openings can be fabricated without affecting each other, improving reliability and achieving better yield reduction.

[0183] Further examples and combinations thereof include the following:

[0184] Example 1 includes an apparatus comprising: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a wider width than the first opening; a conductive material adjacent to a first wall of the first opening; and a dielectric material adjacent to a second wall of the second opening.

[0185] Example 2 includes the device of Example 1, including an electronic component within a second opening, with a dielectric material between the electronic component and a second wall of the second opening.

[0186] Example 3 includes the device of Example 2, wherein the electronic component includes a magnetic material along the inner surface of a circular hole in a dielectric material.

[0187] Example 4 includes the device of Example 3, wherein the conductive material is a first conductive material, and the electronic components are included in a second conductive material within a circular hole, and a magnetic material separates the second conductive material from the dielectric material.

[0188] Example 5 includes the device of Example 4, wherein the electronic component includes a non-magnetic plug and a second conductive material separates the non-magnetic plug from the magnetic material.

[0189] Example 6 includes a device of any one of Examples 3-5, wherein the dielectric material is a first dielectric material, and the device includes a second dielectric material layer across at least one of a first or second opposing outer surface of a glass core, and a magnetic material extends through the second dielectric material layer.

[0190] Example 7 includes a device of any one of Examples 1-6, wherein an open space separates at least a portion of the first wall from at least a portion of the conductive material.

[0191] Example 8 includes the device of Example 7, wherein the open space extends at least half circumferentially around the conductive material.

[0192] Example 9 includes a device of any one of Examples 7 or 8, wherein the open space has a width and a length, the width being in a first direction radially relative to the axis of the first opening, and the length being in a second direction parallel to the axis of the first opening, the length of the open space being greater than the width of the open space.

[0193] Example 10 includes a device of any one of Examples 1-9, wherein the dielectric material corresponds to a liquid-dispensable material.

[0194] Example 11 includes a device of any one of Examples 1-10, wherein the dielectric material is a first dielectric material, and the device includes a second dielectric material different from the first dielectric material, the second dielectric material extending across the outer surface of the glass core and across the outer surface of the first dielectric material.

[0195] Example 12 includes the device of Example 11, wherein the second dielectric material comprises an organic laminated dielectric.

[0196] Example 13 includes an apparatus of any one of Examples 11 or 12, comprising a third dielectric material that is a first wall lining a first opening and a second wall lining a second opening, the second dielectric material being different from both the first and second dielectric materials.

[0197] Example 14 includes the device of Example 13, wherein a second dielectric material separates the second dielectric material from the glass core.

[0198] Example 15 includes an apparatus comprising: a first stacking region; a second stacking region; a glass core assembly between the first and second stacking regions, the glass core assembly comprising: a glass core having a cavity having a first width; and a through-glass via extending through the glass core having a second width, the first width being different from the second width, the through-glass via being spaced apart from the cavity; and electronic components residing within a dielectric material within the cavity.

[0199] Example 16 includes the device of Example 15, wherein the through-glass via does not include a metal seed layer.

[0200] Example 17 includes a device of either Example 15 or 16, wherein the opposite sidewalls of the cavity are not parallel.

[0201] Example 18 includes a device of any one of Examples 15-17, wherein the electronic component includes a coaxial magnetic inductor circuit having a conductive material inside a magnetic outer portion, the device including a first contact pad electrically coupled to a through-glass via, and a second contact pad electrically coupled to the conductive material of the coaxial magnetic inductor circuit, the second contact pad being in contact with the magnetic outer portion.

[0202] Example 19 includes an apparatus comprising: a semiconductor chip; a packaging substrate including a glass layer having a first surface and a second surface opposite to the first surface; a first opening in the glass layer; a second opening in the glass layer, the first surface having a first aspect ratio and the second surface having a second aspect ratio greater than the first aspect ratio; a metal substantially filling the first opening; and a coaxial magnetic inductor circuit of dielectric material extending through the interior of the second opening.

[0203] Example 20 includes the device of Example 19, wherein the dielectric material satisfies at least one of the following: (i) adjacent to the sidewall of the second opening, or (ii) adjacent to the dielectric liner adjacent to the sidewall of the second opening.

[0204] Example 21 includes a method comprising: etching a first opening and a second opening in a glass layer, the first opening being larger than the second opening; filling the first opening with a dielectric material; filling the second opening with a conductive material; drilling a hole through the dielectric material; and providing an electronic component within the hole in the dielectric material.

[0205] Example 22 includes the method of Example 21, wherein the filling of the second opening occurs after the filling of the first opening.

[0206] Example 23 includes the method of Example 22, wherein drilling occurs after the second opening is filled.

[0207] Example 24 includes a method of any one of Examples 21-23, wherein filling the first opening includes dispensing a dielectric material in liquid form into the first opening and curing the dielectric material.

[0208] Example 25 includes the method of any of Examples 21-24, wherein the filling of the second opening is accomplished via a bottom-up plating process.

[0209] Example 26 includes a method of any one of Examples 21-25, wherein etching of the first opening and the second opening is performed during a single laser-induced etching process.

[0210] Example 27 includes a method of any one of Examples 21-26, wherein providing an electronic component includes: depositing a magnetic material in a hole, said hole being a first hole; drilling a second hole in the magnetic material; and plating metal in the second hole.

[0211] Example 28 includes an apparatus comprising: a glass core having a first through-hole and a second through-hole, the first through-hole being spaced apart from and smaller than the second through-hole; a conductive material within the first through-hole; and a dielectric material within the second through-hole, the dielectric material being between electronic components within the second through-hole and the sidewall of the second through-hole.

[0212] Example 29 includes the device of Example 28, wherein the electronic components include a coaxial magnetic inductor circuit.

[0213] Example 30 includes the device of Example 29, wherein the coaxial magnetic inductor circuit includes a first portion and a second portion, and a dielectric material is disposed between the first portion and the second portion.

[0214] Example 31 includes a device of any one of Examples 29 or 30, wherein the conductive material is a first conductive material, and the coaxial magnetic inductor circuit includes a magnetic material and a second conductive material inside the magnetic material.

[0215] Example 32 includes the device of Example 31, wherein a second conductive material extends across a space within a magnetic material.

[0216] Example 33 includes the device of any one of Examples 31 or 32, wherein the end of the magnetic material is substantially flush with the outer surface of the glass core.

[0217] Example 34 includes a device comprising any one of Examples 28-33, comprising a gap between the inner surface of a first through-hole and a conductive material, the gap having no solid material.

[0218] Example 35 includes the device of Example 34, wherein the gap extends for most of the length of the first through hole.

[0219] Example 36 includes an apparatus of any one of Examples 28-35, wherein the dielectric material is a first dielectric material, and the apparatus includes a second dielectric material spanning the outer surface of a glass core and the outer surface of the first dielectric material.

[0220] Example 37 includes the device of Example 36, wherein the second dielectric material is the same material as the first dielectric material within the second via.

[0221] Example 38 includes a device of any one of Examples 36 or 37, wherein the second dielectric material is a different material from the first dielectric material within the second via.

[0222] Example 39 includes the device of Example 38, wherein the first dielectric material within the second through-hole comprises a liquid-dispensable material.

[0223] Example 40 includes the device of Example 39, wherein the second dielectric material comprises an organic laminated dielectric.

[0224] Example 41 includes an apparatus comprising any one of Examples 36-40, comprising a third dielectric material coated on a glass core, the third dielectric material being different from the first dielectric material within the second via and different from the second dielectric material.

[0225] Example 42 includes the device of Example 41, wherein the third dielectric material comprises silicon.

[0226] Example 43 includes an apparatus comprising: a glass core having a first hole and a second hole, the second hole being larger than the first hole; a first stacked region on a first side of the glass core; a second stacked region on a second side of the glass core; a conductive material in the first hole, the conductive material electrically coupling the first stacked region and the second stacked region; and a dielectric material adjacent to the inner wall of the second hole, the dielectric material defining a third hole; and an electronic component included within the third hole.

[0227] Example 44 includes the device of Example 43, wherein the glass core includes a machined hole comprising a magnetic material.

[0228] Example 45 includes a device of either Example 43 or 44, wherein the width of the second hole is a multiple of the width of the first hole.

[0229] Example 46 includes an apparatus comprising: a packaging substrate including a glass layer; a semiconductor die mounted to the packaging substrate; a conductive via in the glass layer; an inductor within a cavity of the glass layer, the cavity being spaced apart from the conductive via; and a dielectric material between the inductor and a sidewall of the cavity.

[0230] Example 47 includes the device of Example 46, wherein there is no metal seed layer between the glass layer and the conductive via.

[0231] Example 48 includes a method comprising: performing a single laser-induced etching process to simultaneously create vias and cavities in a glass core, the vias being spaced apart from the cavities; depositing a dielectric material in the cavities; plating metal within the vias; and providing electronic components in the dielectric material.

[0232] Example 49 includes the method of Example 48, wherein the plating of metal occurs without a seed layer previously deposited in the via.

[0233] Example 50 includes the method of Example 49, wherein the deposition of a dielectric material occurs prior to the plating of a metal, such that the dielectric material prevents the metal from entering the cavity.

[0234] Example 51 includes a method of any one of Examples 48-50, wherein a dielectric material is dispensed into a cavity in liquid form and subsequently cured.

[0235] Example 52 includes a method of any one of Examples 48-51, wherein the electronic component is a coaxial magnetic loop inductor.

[0236] Example 53 includes the method of Example 52, wherein providing the electronic component includes: creating an opening in a dielectric material; adding a magnetic material to the opening; removing the center of the magnetic material; and adding a conductive material to the center of the magnetic material.

[0237] Example 54 includes the method of Example 53, wherein the addition of conductive material and the plating of metal within the through-hole are performed simultaneously.

[0238] Example 55 includes a device comprising: a glass layer having a first hole and a second hole, the second hole being larger than an electronic component disposed therein, the width of the electronic component being larger than the width of the first hole; a conductive material substantially filling the first hole; and a dielectric material substantially filling the space surrounding the electronic component within the second hole.

[0239] Example 56 includes the device of Example 55, wherein the electronic component includes a magnetic material in contact with the dielectric material.

[0240] Example 57 includes the device of Example 56, wherein the conductive material is a first conductive material, and a first portion of the magnetic material surrounds a first portion of the second conductive material, and a second portion of the magnetic material surrounds a second portion of the second conductive material.

[0241] Example 58 includes the device of Example 57, wherein the second portion of the magnetic material is a continuous extension of the first portion of the magnetic material.

[0242] Example 59 includes a device of any of Examples 56-58, wherein the outer surface of the magnetic material is substantially flush with the outer surface of the glass layer.

[0243] Example 60 includes the device of Example 59, which includes a dielectric layer spanning the outer surface of a magnetic material and the outer surface of a glass layer.

[0244] Example 61 includes the device of Example 60, wherein the dielectric layer comprises a material different from the dielectric material.

[0245] Example 62 includes the device of Example 61, wherein the dielectric material corresponds to a liquid-dispensable material and the dielectric layer corresponds to an organic laminated dielectric.

[0246] Example 63 includes a device of any of Examples 55-62, wherein the void is located between the first hole and the facing surfaces of the conductive material within the first hole.

[0247] Example 64 includes the device of Example 63, wherein the conductive material is a first conductive material and the void is a first void, and the electronic component includes a magnetic material surrounding a second conductive material and a second void located between the magnetic material and the facing surfaces of the second conductive material.

[0248] Example 65 includes an apparatus of any one of Examples 63 or 64, comprising a thin-film dielectric on a glass layer within a first aperture, the aperture being between the thin-film dielectric and a conductive material.

[0249] Example 66 includes the device of Example 65, wherein a thin-film dielectric is on a glass layer within a second hole, the thin-film dielectric being between the dielectric material and the sidewall of the second hole in the glass layer.

[0250] Example 67 includes the device of Example 66, wherein a thin-film dielectric is in contact with a glass layer and with a dielectric material.

[0251] Example 68 includes an apparatus comprising: a glass layer having an opening extending from a first surface of the glass layer to a second surface of the glass layer, the second surface being opposite to the first surface; a first redistribution layer adjacent to the first surface of the glass layer; a second redistribution layer adjacent to the second surface of the glass layer; a metal via extending through the glass layer, the metal via being spaced apart from the opening; and a dielectric material extending through the glass layer along the wall of the opening.

[0252] Example 69 includes the device of Example 68, which includes a coaxial magnetic loop inductor within a dielectric material.

[0253] Example 70 includes the device of Example 69, wherein the coaxial magnetic loop inductor includes a coupled coaxial magnetic loop inductor.

[0254] Example 71 includes a device of any one of Examples 69 or 70, wherein the coaxial magnetic loop inductor includes a conductive core surrounded by a magnetic material, and the device includes a dielectric layer extending across a first surface of a glass layer and a substantially parallel surface of the magnetic material, and contact pads electrically coupled to the conductive core, the dielectric layer being between the magnetic material and the contact pads.

[0255] Example 72 includes an apparatus comprising: a semiconductor chip; a substrate on which the semiconductor chip is mounted, the substrate including a glass core having a cavity and a through-hole adjacent to the cavity, the cavity being larger than the through-hole; a conductive material within the through-hole; a dielectric material within the cavity including an opening extending therethrough; and a magnetic material within the opening.

[0256] Example 73 includes the device of Example 72, wherein the magnetic material has a cylindrical shape and is filled with metal.

[0257] Example 74 includes a device of any one of Examples 72 or 73, wherein a portion of the outer surface of the conductive material within the through-hole is separated from the sidewall of the through-hole by a void.

[0258] Example 75 includes a method comprising: adding a via to a glass core; adding a cavity to the glass core, the via and the cavity being added to the glass core during the same process, the cavity having a different size than the via; depositing a dielectric material within the cavity; depositing metal within the via; forming an opening in the dielectric material after the metal has been deposited within the via; and adding an electronic component to the opening.

[0259] Example 76 includes the method of Example 75, wherein the deposition of dielectric material within the cavity occurs before the deposition of metal within the via.

[0260] Example 77 includes the method of any one of Examples 75 or 76, wherein depositing the dielectric material includes dispensing the dielectric material in liquid form.

[0261] Example 78 includes the method of any of Examples 75-77, wherein the deposition of metal is achieved by a bottom-up plating process without a seed layer.

[0262] Example 79 includes a method of any of Examples 75-78, wherein the electronic component is an inductor.

[0263] Example 80 includes the method of Example 79, wherein adding an electronic component includes: depositing a magnetic material within an opening; drilling a hole through the magnetic material; and depositing a conductive material within the hole in the magnetic material.

[0264] Example 81 includes an apparatus comprising: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening between the electronic component and a sidewall of the opening; and a through-glass via comprising a conductive material extending through the glass layer.

[0265] Example 82 includes the device of Example 81, wherein a dielectric material substantially surrounds an electronic component.

[0266] Example 83 includes a device of either Example 81 or 82, wherein the electronic component includes a capacitor.

[0267] Example 84 includes the device of Example 83, wherein the capacitor includes a deep trench capacitor.

[0268] Example 85 includes a device of any one of Examples 81-84, wherein the electronic component includes contact pads that are substantially flush with a first surface of the glass layer.

[0269] Example 86 includes a device of any one of Examples 81-85, wherein the electronic component has a first thickness and the glass layer has a second thickness greater than the first thickness.

[0270] Example 87 includes an apparatus comprising any one of Examples 81-86, comprising a first dielectric layer extending across a first surface of a glass layer and across a first end of an opening, and a second dielectric layer extending across a second surface of a glass layer and across a second end of an opening.

[0271] Example 88 includes the device of Example 87, wherein the dielectric material includes a material different from the first dielectric layer and a material different from the second dielectric layer.

[0272] Example 89 includes an apparatus comprising any one of Examples 87 or 88, comprising a thin film coated on a first surface and a second surface of a glass layer, the thin film being disposed between the glass layer and a first dielectric layer and between the glass layer and a second dielectric layer.

[0273] Example 90 includes the device of Example 89, wherein the thin film separates the dielectric material within the opening from the glass layer.

[0274] Example 91 includes an apparatus of any one of Examples 81-90, wherein the dielectric material comprises a cured liquid-dispensable material.

[0275] Example 92 includes the device of any one of Examples 81-91, wherein the through-glass via does not include a seed layer along the length of the through-glass via.

[0276] Example 93 includes an apparatus comprising: a first stacking region; a second stacking region; a glass core between the first stacking region and the second stacking region, the glass core having a first opening and a second opening extending therethrough, the first opening being smaller than and spaced apart from the second opening; a metallic material along a first wall of the first opening; and a dielectric material along a second wall of the second opening.

[0277] Example 94 includes the device of Example 93, wherein an outward-facing surface of a metallic material is spaced apart from a first wall of a first opening.

[0278] Example 95 includes the device of any one of Examples 93 or 94, wherein the open space extends circumferentially around at least one-quarter of the path surrounding the cross-section of the metallic material within the first opening.

[0279] Example 96 includes a device of any one of Examples 93-95, wherein the open space extends at least 10% of the length of the first opening.

[0280] Example 97 includes a device comprising any one of Examples 93-96, comprising electronic components within a dielectric material inside a second opening.

[0281] Example 98 includes the device of Example 97, wherein the electronic components include a deep trench capacitor.

[0282] Example 99 includes an apparatus comprising: a packaging substrate including a glass core having a first opening and a second opening larger than the first opening; a conductive material in the first opening; a dielectric material in the second opening; a capacitor in the dielectric material of the second opening; and a semiconductor chip attached to the packaging substrate.

[0283] Example 100 includes the device of Example 99, wherein the conductive material in the first opening is separated from the sidewall of the first opening through a gap without solid material.

[0284] Example 101 includes a method comprising: forming a first opening in a glass core, the first opening extending through the glass core and having a first width; forming a second opening in the glass core, the second opening extending through the glass core and having a second width different from the first width; placing an electronic component within the first opening; depositing a dielectric material within the first opening and around the electronic component; and depositing a metal within the second opening.

[0285] Example 102 includes the method of Example 101, wherein a first opening and a second opening are formed in a glass core during the same process.

[0286] Example 103 includes a method of either Example 101 or 102, wherein the deposition of a dielectric material is performed by dispensing the dielectric material in liquid form and subsequently curing the dielectric material.

[0287] Example 104 includes the method of any one of Examples 101-103, wherein metal deposition is performed by a bottom-up plating process without a seed layer.

[0288] Example 105 includes the method of any one of Examples 101-104, wherein the electronic component includes a deep trench capacitor.

[0289] The appended claims are hereby incorporated by reference into this specific embodiment. Although certain example systems, devices, articles of manufacture, and methods have been disclosed herein, the scope of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles of manufacture, and methods that fall fully within the scope of the claims of this patent.

Claims

1. An apparatus comprising: A glass layer having an opening between opposing first and second surfaces of the glass layer; Electronic components, the electronic components being located within the opening; A dielectric material, the dielectric material being located within the opening and between the electronic component and the sidewall of the opening; as well as A through-glass via, the through-glass via comprising a conductive material extending through the glass layer.

2. The device according to claim 1, wherein, The dielectric material generally surrounds the electronic component.

3. The device according to claim 1, wherein, The electronic components include capacitors.

4. The device according to claim 3, wherein, The capacitors include deep trench capacitors.

5. The device according to claim 1, wherein, The electronic component includes contact pads that are substantially flush with the first surface of the glass layer.

6. The device according to any one of claims 1-5, wherein, The electronic component has a first thickness, and the glass layer has a second thickness, which is greater than the first thickness.

7. The device according to any one of claims 1-5, comprising: A first dielectric layer extends across the first surface of the glass layer and across the first end of the opening; as well as A second dielectric layer extends across the second surface of the glass layer and across the second end of the opening.

8. The device according to claim 7, wherein, The dielectric material includes a material different from the first dielectric layer and a material different from the second dielectric layer.

9. The apparatus of claim 7, comprising a thin film coated on the first surface and the second surface of the glass layer, the thin film being between the glass layer and the first dielectric layer and between the glass layer and the second dielectric layer.

10. The device according to claim 9, wherein, The thin film separates the dielectric material within the opening from the glass layer.

11. The device according to any one of claims 1-5, wherein, The dielectric material includes a cured liquid-dispensable material.

12. The device according to any one of claims 1-5, wherein, The through-glass via does not include a seed layer along the length of the through-glass via.

13. An apparatus comprising: First accumulation area; Second accumulation area; A glass core, located between a first stacking region and a second stacking region, having a first opening and a second opening extending through the glass core, the first opening being smaller than the second opening and spaced apart from the second opening; Metallic material, the metallic material being along the first wall of the first opening; as well as A dielectric material, the dielectric material being disposed along the second wall of the second opening.

14. The device according to claim 13, wherein, The outward-facing surface of the metallic material is spaced apart from the first wall of the first opening.

15. The device according to claim 13, wherein, The open space extends circumferentially around at least one-quarter of the path surrounding the cross-section of the metallic material within the first opening.

16. The device according to claim 13, wherein, The open space extends at least 10% of the length of the first opening.

17. The device according to any one of claims 13-16, comprising electronic components within the dielectric material inside the second opening.

18. The device according to claim 17, wherein, The electronic components include deep trench capacitors.

19. An apparatus comprising: An encapsulation substrate, the encapsulation substrate comprising a glass core having a first opening and a second opening larger than the first opening; A conductive material, wherein the conductive material is in the first opening; A dielectric material, wherein the dielectric material is in the second opening; A capacitor, the capacitor being in the dielectric material within the second opening; as well as A semiconductor chip, the semiconductor chip being attached to the packaging substrate.

20. The device according to claim 19, wherein, The conductive material in the first opening is separated from the sidewall of the first opening through a gap that does not contain solid material.

21. A method comprising: A first opening is provided in the glass core, the first opening extending through the glass core, and the first opening having a first width; A second opening is provided in the glass core, the second opening extends through the glass core, and the second opening has a second width, which is different from the first width; The electronic components are placed inside the first opening; Dielectric material is deposited within the first opening and around the electronic component; as well as Metal is deposited within the second opening.

22. The method according to claim 21, wherein, The first opening and the second opening are formed in the glass core during the same process.

23. The method according to claim 21, wherein, The deposition of the dielectric material is carried out by dispensing the dielectric material in liquid form and then curing the dielectric material.

24. The method according to any one of claims 21-23, wherein, The metal is deposited using a bottom-up plating process without a seed layer.

25. The method according to any one of claims 21-23, wherein, The electronic components include deep trench capacitors.

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