Chip architecture and method of forming the same
By placing the signal interconnect layer and the power supply network layer on different sides in the chip architecture and transmitting signals through external power lines, the problems of wiring congestion and inter-layer signal delay are solved, thereby increasing device density and improving signal transmission efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (BEIJING) CORP
- Filing Date
- 2024-12-16
- Publication Date
- 2026-06-19
AI Technical Summary
Existing chip architectures suffer from wiring congestion and inter-layer signal delay, making it particularly difficult to effectively increase device density and reduce signal delay in multi-device architectures.
By placing the signal interconnect layer and power supply network layer of the first and second chips on different sides and extending them to the bonding interface through external power lines, the chips are bonded together to form a stacked chip architecture. The external power lines transmit signals from the bonding section to both sides.
It effectively reduces wiring congestion, increases device density, reduces inter-layer signal delay, and improves the overall performance of the chip.
Smart Images
Figure CN122249081A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a chip architecture and its formation method. Background Technology
[0002] As integrated circuits evolve towards very large-scale integrated circuits (VLSI), the circuit density within integrated circuits is increasing, the number of components is also growing, and the demand for miniaturization of these components is also rising. Therefore, 3D packaging technology is gaining increasing importance for multi-component device architectures.
[0003] In existing 3D packaging technologies, bare functional chips with the same layout can be stacked together. For example, through-silicon via (TSV) technology can be used to stack multiple Dynamic Random Access Memory (DRAM) bare functional chips vertically to save space. Bare functional chips, also known as dies or chiplets, are used to refer to chips that can perform certain functions and are in their pre-packaging state.
[0004] However, existing chip architectures still have many problems. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a chip architecture and its formation method to reduce wiring congestion and inter-layer signal delay.
[0006] To address the aforementioned problems, the present invention provides a chip architecture comprising: a first chip, the first chip including a first signal interconnect layer and a first power supply network layer located on different sides; a second chip, the second chip including a second signal interconnect layer and a second power supply network layer located on different sides; the first chip and the second chip being bonded together, the first power supply network layer and the second power supply network layer being located between the first signal interconnect layer and the second signal interconnect layer, and a bonding interface being provided between the first chip and the second chip; and an external power line located within the first chip or the second chip, the external power line extending to the bonding interface and being electrically connected to the first power supply network layer and the second power supply network layer, respectively.
[0007] Optionally, the first chip further includes: a first substrate, the first substrate including a first side and a second side opposite to each other; a first device layer located on the first substrate, the first device layer being located on the first side; a first signal interconnect layer located on the first side, the first signal interconnect layer being electrically connected to the first device layer; a first power supply network layer located on the first substrate, the first power supply network being located on the second side, the first power supply network layer being electrically connected to the first device layer; and a first bonding layer located on the first power supply network layer, the first bonding layer being located on the second side, the first bonding layer being electrically connected to the first power supply network layer.
[0008] Optionally, the first chip further includes: a first isolation layer located within the first substrate; and a first embedded power rail located within the first substrate, wherein the first isolation layer covers the first embedded power rail, and the first embedded power rail is electrically connected to the first device layer and the first power supply network layer, respectively.
[0009] Optionally, the second chip further includes: a second substrate, the second substrate including opposing third and fourth sides; a second device layer located on the second substrate, the second device layer being located on the third side; a second signal interconnect layer located on the third side, the second signal interconnect layer being electrically connected to the second device layer; a second power supply network layer located on the second substrate, the second power supply network being located on the fourth side, the second power supply network layer being electrically connected to the second device layer; and a second bonding layer located on the second power supply network layer, the second bonding layer being located on the fourth side, the second bonding layer being electrically connected to the second power supply network layer.
[0010] Optionally, the second chip further includes: a second isolation layer located within the second substrate; and a second buried power rail located within the second substrate, the second isolation layer covering the second buried power rail, the second buried power rail being electrically connected to the second device layer and the second power supply network layer respectively.
[0011] Optionally, the first bonding layer and the second bonding layer are bonded together, and a bonding interface is provided between the first bonding layer and the second bonding layer.
[0012] Optionally, it may also include a carrier wafer on which the first chip and the second chip are located.
[0013] Optionally, there is a gap between the edges of the first chip and the second chip and the edge of the substrate.
[0014] Optionally, the first chip and the second chip may be the same chip or different chips.
[0015] Accordingly, the present invention also provides a method for forming a chip architecture, comprising: forming a first chip, wherein forming the first chip includes forming a first signal interconnect layer and a first power supply network layer located on different sides; forming a second chip, wherein forming the second chip includes forming a second signal interconnect layer and a second power supply network layer located on different sides; bonding the first chip and the second chip, wherein the first power supply network layer and the second power supply network layer are located between the first signal interconnect layer and the second signal interconnect layer, and a bonding interface is provided between the first chip and the second chip; and an external power line within the first chip or the second chip, wherein the external power line extends to the bonding interface and is electrically connected to the first power supply network layer and the second power supply network layer, respectively.
[0016] Optionally, forming the first chip further includes: forming a first substrate, the first substrate including a first side and a second side opposite to each other; forming a first device layer on the first substrate, the first device layer being located on the first side; a first signal interconnect layer being located on the first side and electrically connected to the first device layer; forming a first power supply network layer on the first substrate, the first power supply network being located on the second side and electrically connected to the first device layer; and forming a first bonding layer on the first power supply network layer, the first bonding layer being located on the second side and electrically connected to the first power supply network layer.
[0017] Optionally, forming the first chip further includes: forming a first isolation layer in the first substrate; forming a first buried power rail in the first substrate, the first isolation layer covering the first buried power rail, and the first buried power rail being electrically connected to the first device layer and the first power supply network layer respectively.
[0018] Optionally, forming the second chip further includes: forming a second substrate, the second substrate including opposing third and fourth sides; forming a second device layer on the second substrate, the second device layer being located on the third side; a second signal interconnect layer being located on the third side and electrically connected to the second device layer; forming a second power supply network layer on the second substrate, the second power supply network being located on the fourth side and electrically connected to the second device layer; and forming a second bonding layer on the second power supply network layer, the second bonding layer being located on the fourth side and electrically connected to the second power supply network layer.
[0019] Optionally, forming the second chip further includes: forming a second isolation layer in the second substrate; forming a second buried power rail in the second substrate, the second isolation layer covering the second buried power rail, and the second buried power rail being electrically connected to the second device layer and the second power supply network layer, respectively.
[0020] Optionally, the method for bonding the first chip and the second chip includes: bonding the first bonding layer and the second bonding layer together, wherein the first bonding layer and the second bonding layer have a bonding interface.
[0021] Optionally, it may also include: providing a carrier on which the first chip and the second chip are located.
[0022] Optionally, there is a gap between the edges of the first chip and the second chip and the edge of the substrate.
[0023] Optionally, the first chip and the second chip may be the same chip or different chips.
[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0025] In the chip architecture of this invention, the first signal interconnect layer and the first power supply network layer, as well as the second signal interconnect layer and the second power supply network layer, are disposed on different sides of the first chip and the second chip to reduce wiring congestion. Furthermore, the stacked chip architecture formed by bonding the first chip and the second chip effectively increases device density. Additionally, the external power line extends to the bonding interface, transmitting signals simultaneously from the bonding cross-section to the chips on both sides, effectively reducing inter-layer signal delay.
[0026] In the chip architecture formation method of the present invention, the first signal interconnect layer and the first power supply network layer, as well as the second signal interconnect layer and the second power supply network layer, are disposed on different sides of the first chip and the second chip to reduce wiring congestion. Furthermore, the stacked chip architecture formed by bonding the first chip and the second chip effectively improves device density. Additionally, the external power line extends to the bonding interface, transmitting signals simultaneously from the bonding cross-section to the chips on both sides, effectively reducing inter-layer signal delay. Attached Figure Description
[0027] Figures 1 to 10 This is a schematic diagram of the steps in the chip architecture formation method according to an embodiment of the present invention. Detailed Implementation
[0028] As described in the background section, existing chip architectures still have many problems. These will be explained in detail below.
[0029] As Moore's Law approaches its physical limits, increasing chip computing power by miniaturizing transistor feature sizes becomes increasingly unsustainable. 3D packaging technology has become a breakthrough for increasing transistor density and thus chip computing power. Hybrid bonding and through-silicon vias (TSVs), as key technologies in 3D stacking, achieve high-density interconnects between chips through alignment, bonding, thinning, and TSV fabrication, and have been widely used in vertical interconnects between chips.
[0030] In the interconnect network of a chip, the power supply network shares wiring resources with the signal lines. As transistors become smaller and denser, the number of stacked layers in the back-end wiring increases, which not only leads to serious power loss problems but also causes mutual interference between the signal source and the signal lines.
[0031] Existing hybrid bonding processes use a front power supply network (Front PDN), which can increase transistor density by increasing the number of chip layers in the vertical direction, but still does not solve the problem of wiring congestion on a single wafer. In addition, although 3D processes such as hybrid bonding can increase the number of transistors in the vertical direction, the power supply network needs to be passed from bottom to top between stacked chips, resulting in signal delay between adjacent stacked structures.
[0032] Based on this, the present invention provides a chip architecture and its formation method. In the first chip and the second chip, by placing the first signal interconnect layer and the first power supply network layer, as well as the second signal interconnect layer and the second power supply network layer, on different sides, the problem of wiring congestion is reduced. Moreover, the first chip and the second chip are bonded together to form a stacked chip architecture, which can effectively improve device density. In addition, the external power line extends to the bonding interface, transmitting signals from the bonding cross-section to the chips on both sides simultaneously, which can effectively reduce the problem of inter-layer signal delay.
[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0034] Figures 1 to 10 This is a schematic diagram of the steps in the chip architecture formation method according to an embodiment of the present invention.
[0035] The first chip is formed. For the specific process of forming the first chip, please refer to [link / reference needed]. Figures 1 to 8 .
[0036] Please refer to Figure 1 , providing the first wafer 100.
[0037] In this embodiment, the first wafer 100 serves as the substrate for forming the first chip.
[0038] Please continue to refer to this. Figure 1 A first polishing stop layer 101 is formed on the first wafer 100; a first substrate 102 is formed on the first polishing stop layer 101.
[0039] In this embodiment, the first substrate 102 has a first side 102a and a second side 102b opposite to each other. The first side 102a is the front side of the first chip, and the second side 102b is the back side of the first chip. The first polishing stop layer 101 and the first wafer 100 are located on the second side 102b.
[0040] It should be noted that in this embodiment, the first wafer 100 needs to be removed by chemical mechanical polishing (CMP) in subsequent process steps. However, the surface flatness formed by CMP is relatively poor. Therefore, in order to ensure that a relatively flat surface can be formed on the back side of the first substrate 102 after the first wafer 100 is removed by CMP, an epitaxial process is used to form the first polishing stop layer 101 between the first wafer 100 and the first substrate 102. When the first wafer 100 is polished to the first polishing stop layer 101, the CMP process is stopped. Subsequently, the first polishing stop layer 101 is removed by wet etching. Wet etching can form a relatively flat surface, ensuring that the back side of the first substrate 102 has a relatively flat surface after the first polishing stop layer 101 is removed.
[0041] In this embodiment, both the first substrate 102 and the first wafer 100 are made of silicon. The material of the first polishing stop layer 101 needs to be different from both of them. On the one hand, it is necessary to ensure that the polishing of the first wafer 100 is well stopped. On the other hand, when the first polishing stop layer 101 is etched away, the etching damage to the first substrate 102 should be minimized.
[0042] In this embodiment, the first grinding stop layer 101 is made of silicon germanium.
[0043] In this embodiment, both the first polishing stop layer 101 and the first substrate 102 are formed using epitaxial growth technology. The thickness of the first polishing stop layer 101 does not need to be large, approximately 10 nm is sufficient. The first substrate 102 will subsequently serve as the base for the first device layer, and the thickness of the first substrate 102 is 100 nm to 500 nm.
[0044] Please refer to Figure 2 A first isolation layer 103 is formed in the first substrate 102; a first buried power rail 104 is formed in the first substrate 102, and the first isolation layer 103 covers the first buried power rail 104.
[0045] In this embodiment, the method for forming the first isolation layer 103 and the first embedded power rail 104 includes: etching the first substrate 102 from the first side 102a to the second side 102b to form a first isolation trench (not shown) in the first substrate 102; after forming the first isolation trench, forming the first embedded power rail 104 in the first isolation trench; and after forming the first embedded power rail 104, filling the first isolation trench with the isolation material to form the first isolation layer 103.
[0046] By pre-forming the first embedded power rail 104, it serves as a connector for the electrical connection between the subsequently formed first device layer and the first power supply network layer, and also as an interface for the back-side power supply network. Furthermore, since the first embedded power rail 104 is formed within the first isolation trench, it does not require additional chip area, thereby increasing the density of the device structure.
[0047] In this embodiment, the first isolation layer 103 is made of silicon oxide.
[0048] Please refer to Figure 3 A first device layer 105 is formed on the first substrate 102, and the first device layer 105 is located on the first side 102a; a first signal interconnect layer 106 is formed on the first device layer 105, and the first signal interconnect layer 106 is located on the first side 102a and is electrically connected to the first device layer 105.
[0049] It should be noted that, in this embodiment, the first device layer 105 contains device structures, such as one or more of transistors, resistors, capacitors, and inductors. The first signal interconnect layer 106 contains several layers of signal lines, and the signal lines between adjacent layers are electrically connected through conductive plugs. The signal lines are also electrically connected to the device structures.
[0050] In this embodiment, the first embedded power rail 104 is electrically connected to the first device layer 105. Specifically, before forming the first device layer 105, several conductive plugs (not shown) need to be formed to bring out the first embedded power rail 104. The device structure in the first device layer 105 is then electrically connected to the conductive plugs, thereby making the first embedded power rail 104 electrically connected to the first device layer 105.
[0051] Please refer to Figure 4 Provide a first carrier 107; bond the first signal interconnect layer 106 to the first carrier 107; remove the first wafer 100.
[0052] It should be noted that in this embodiment, a first power supply network layer needs to be formed on the second side 102b in subsequent processes, which requires flipping the first substrate 102. Therefore, the first carrier 107 is required to support the flipped first substrate 102.
[0053] In this embodiment, the first wafer 100 is removed using a chemical mechanical polishing (CMP) process. It should be noted that because CMP creates a recessed area in the center during the polishing process, to ensure good surface flatness after polishing, edge trimming is required when the first wafer 100 is polished to half its thickness. This trimming removes the more protruding edges, and the edges of the first substrate 102, the first device layer 105, and the first signal interconnect layer 106 have gaps with the edge of the first carrier 107. After the edge trimming, the remaining half of the first wafer 100 is then polished away.
[0054] Please refer to Figure 5 After removing the first wafer 100, the first grinding stop layer 101 is removed.
[0055] In this embodiment, the process of removing the first polishing stop layer 101 is a wet etching process. The wet etching process can form a relatively flat surface, ensuring that the back side of the first substrate 102 has a relatively flat surface after the first polishing stop layer 101 is removed.
[0056] After removing the first polishing stop layer 101, a first power supply network layer is formed on the first substrate 102. The first power supply network is located on the second side 102b, and the first power supply network layer is electrically connected to the first device layer 105. For details of the formation process, please refer to [link to documentation]. Figure 6 and Figure 7 .
[0057] Please refer to Figure 6 After removing the first grinding stop layer 101, a plurality of nano-scale through-silicon vias 110 (nano-TSVs) are formed from the second side 102b toward the first side 102a. The nano-scale through-silicon vias 110 expose the first embedded power rail 104. The nano-scale through-silicon vias 110 are filled with conductive material.
[0058] In this embodiment, a plurality of nanoscale through-silicon vias 110 are formed to bring out the first embedded power rail 104.
[0059] Please refer to Figure 7 After the first embedded power rail 104 is led out, the first power supply network layer 108 is formed on the substrate.
[0060] In this embodiment, the first power supply network layer 108 is electrically connected to the first embedded power rail 104, thereby realizing the electrical connection between the first power supply network layer 108 and the first device layer 105.
[0061] Please refer to Figure 8 A first bonding layer 109 is formed on the first power supply network layer 108. The first bonding layer 109 is located on the second side 102b and is electrically connected to the first power supply network layer 108.
[0062] At this point, the manufacturing process of the first chip was complete.
[0063] Please refer to Figure 9 A second chip is formed; the first chip and the second chip are then bonded together.
[0064] In this embodiment, forming the first chip includes forming the second chip, which includes forming a second signal interconnect layer 200 and a second power supply network layer 201 located on different sides.
[0065] In this embodiment, forming the first chip further includes: forming a second substrate 202, the second substrate 202 including a third side 202a and a fourth side 202b opposite to each other; forming a second device layer 203 on the second substrate 202, the second device layer 203 being located on the third side 202a; a second signal interconnect layer 200 being located on the third side 202a, the second signal interconnect layer 200 being electrically connected to the second device layer 203; forming a second power supply network layer 201 on the second substrate 202, the second power supply network layer 201 being located on the fourth side 202b, the second power supply network layer 201 being electrically connected to the second device layer 203; and forming a second bonding layer 204 on the second power supply network layer 201, the second bonding layer 204 being located on the fourth side 202b, the second bonding layer 204 being electrically connected to the second power supply network layer 201.
[0066] In this embodiment, forming the second chip further includes: forming a second isolation layer 205 in the second substrate 202; forming a second buried power rail 206 in the second substrate 202, the second isolation layer 205 covering the second buried power rail 206, and the second buried power rail 206 being electrically connected to the second device layer 203 and the second power supply network layer 201 respectively.
[0067] In this embodiment, the process of forming the second chip is the same as the process of forming the first chip, and will not be described again here. For details, please refer to [link / reference needed]. Figures 1 to 9 As stated in the relevant explanations.
[0068] In this embodiment, after the first chip and the second chip are bonded, the first power supply network layer 108 and the second power supply network layer 201 are located between the first signal interconnect layer 106 and the second signal interconnect layer 200, and the first chip and the second chip have a bonding interface.
[0069] In this embodiment, the method for bonding the first chip and the second chip includes: bonding the first bonding layer 109 and the second bonding layer 204 together, wherein the first bonding layer 109 and the second bonding layer 204 have a bonding interface.
[0070] In this embodiment, the first chip and the second chip are different chips.
[0071] In other embodiments, the first chip and the second chip may be the same chip.
[0072] In this embodiment, after the first chip and the second chip are removed, the second carrier (not shown) used to support the second chip is removed.
[0073] In other embodiments, after the first chip and the second chip are assembled, the first carrier used to support the first chip may also be removed.
[0074] It should be noted that in this embodiment, the chemical mechanical polishing process is still used to remove the second substrate, which also suffers from the problem of central area depression during the polishing process. Therefore, when polishing away half the thickness of the second substrate, both the first and second chips are simultaneously trimmed to remove the more protruding edges. After the trimming, the remaining half of the second substrate is then polished away.
[0075] There is a gap between the edges of the first chip and the second chip and the edge of the substrate.
[0076] In this embodiment, since the second substrate is removed, there is a gap between the edges of the first chip and the second chip and the edge of the first substrate 107.
[0077] It should be noted that the first chip and the second chip undergo two edge trimming processes at this time, resulting in a gap between the edges of the first chip and the second chip and the edge of the first substrate 107 (please refer to...). Figure 9The edges of the first device layer 105 and the first signal interconnect layer 106 must have a gap with the edge of the first substrate 107 (see reference). Figure 4 ).
[0078] In other embodiments, when the first substrate is removed, there is a gap between the edges of the first chip and the second chip and the edge of the second substrate.
[0079] Please refer to Figure 10 An external power line 300 is located within the second chip, extending to the bonding interface and electrically connected to the first power supply network layer 108 and the second power supply network layer 201, respectively.
[0080] In the first chip and the second chip, by placing the first signal interconnect layer 106 and the first power supply network layer 108, and the second signal interconnect layer 200 and the second power supply network layer 201 on different sides, wiring congestion is reduced. Furthermore, the stacked chip architecture formed by bonding the first chip and the second chip effectively increases device density. Additionally, the external power line 300 extends to the bonding interface, transmitting signals simultaneously from the bonding cross-section to the chips on both sides, effectively reducing inter-layer signal delay.
[0081] In this embodiment, since the second carrier is removed, the external power line 300 is formed within the second chip.
[0082] In other embodiments, when the first carrier is removed, the corresponding external power line is formed within the first chip.
[0083] In this embodiment, the external power line 300 is formed using a through silicon via (TSV) process.
[0084] Accordingly, this invention also provides a chip architecture, please refer to the following: Figure 10 The device includes: a first chip, which includes a first signal interconnect layer 106 and a first power supply network layer 108 located on different sides; a second chip, which includes a second signal interconnect layer 200 and a second power supply network layer 201 located on different sides; the first chip and the second chip are bonded together, the first power supply network layer 108 and the second power supply network layer 201 are located between the first signal interconnect layer 106 and the second signal interconnect layer 200, and a bonding interface is provided between the first chip and the second chip; and an external power line 300 located within the first chip or the second chip, the external power line 300 extending to the bonding interface and electrically connected to the first power supply network layer 108 and the second power supply network layer 201 respectively.
[0085] In the first chip and the second chip, by placing the first signal interconnect layer 106 and the first power supply network layer 108, and the second signal interconnect layer 200 and the second power supply network layer 201 on different sides, wiring congestion is reduced. Furthermore, the stacked chip architecture formed by bonding the first chip and the second chip effectively increases device density. Additionally, the external power line 300 extends to the bonding interface, transmitting signals simultaneously from the bonding cross-section to the chips on both sides, effectively reducing inter-layer signal delay.
[0086] In this embodiment, the first chip further includes: a first substrate 102, the first substrate 102 including a first side 102a and a second side 102b opposite to each other; a first device layer 105 located on the first substrate 102, the first device layer 105 being located on the first side 102a; a first signal interconnect layer 106 located on the first side 102a, the first signal interconnect layer 106 being electrically connected to the first device layer 105; a first power supply network layer 108 located on the first substrate 102, the first power supply network layer 108 being located on the second side 102b, the first power supply network layer 108 being electrically connected to the first device layer 105; and a first bonding layer 109 located on the first power supply network layer 108, the first bonding layer 109 being located on the second side 102b, the first bonding layer 109 being electrically connected to the first power supply network layer 108.
[0087] In this embodiment, the first chip further includes: a first isolation layer 103 located within the first substrate 102; and a first embedded power rail 104 located within the first substrate 102, wherein the first isolation layer 103 covers the first embedded power rail 104, and the first embedded power rail 104 is electrically connected to the first device layer 105 and the first power supply network layer 108, respectively.
[0088] In this embodiment, the second chip further includes: a second substrate 202, the second substrate 202 including opposing third sides 202a and fourth sides 202b; a second device layer 203 located on the second substrate 202, the second device layer 203 being located on the third side 202a; a second signal interconnect layer 200 located on the third side 202a, the second signal interconnect layer 200 being electrically connected to the second device layer 203; a second power supply network layer 201 located on the second substrate 202, the second power supply network layer 201 being located on the fourth side 202b, the second power supply network layer 201 being electrically connected to the second device layer 203; and a second bonding layer 204 located on the second power supply network layer 201, the second bonding layer 204 being located on the fourth side 202b, the second bonding layer 204 being electrically connected to the second power supply network layer 201.
[0089] In this embodiment, the second chip further includes: a second isolation layer 205 located within the second substrate 202; and a second embedded power rail 206 located within the second substrate 202, wherein the second isolation layer 205 covers the second embedded power rail 206, and the second embedded power rail 206 is electrically connected to the second device layer 203 and the second power supply network layer 201, respectively.
[0090] In this embodiment, the first bonding layer 109 and the second bonding layer 204 are bonded together, and a bonding interface is provided between the first bonding layer 109 and the second bonding layer 204.
[0091] The chip architecture further includes a carrier wafer, on which the first chip and the second chip are located; and a gap exists between the edges of the first chip and the second chip and the edges of the carrier wafer.
[0092] In this embodiment, the carrier is a first carrier 107, and the first chip and the second chip are located on the first carrier 107. The first carrier 107 is directly bonded to the first chip. There is a gap between the edges of the first chip and the second chip and the first edge of the carrier.
[0093] In other embodiments, the carrier may also be a second carrier, with the first chip and the second chip located on the second carrier, and the second carrier directly bonded to the second chip; there is a gap between the edges of the first chip and the second chip and the second edge of the carrier.
[0094] In this embodiment, the first chip and the second chip are different chips.
[0095] In other embodiments, the first chip and the second chip may be the same chip.
[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A chip architecture, characterized in that, include: A first chip, the first chip including a first signal interconnect layer and a first power supply network layer located on different sides; The second chip includes a second signal interconnect layer and a second power supply network layer located on different sides; The first chip and the second chip are bonded together, the first power supply network layer and the second power supply network layer are located between the first signal interconnect layer and the second signal interconnect layer, and there is a bonding interface between the first chip and the second chip; An external power line located within the first chip or the second chip extends to the bonding interface and is electrically connected to the first power supply network layer and the second power supply network layer, respectively.
2. The chip architecture as described in claim 1, characterized in that, The first chip further includes: a first substrate, the first substrate including a first side and a second side opposite to each other; a first device layer located on the first substrate, the first device layer being located on the first side; a first signal interconnect layer located on the first side, the first signal interconnect layer being electrically connected to the first device layer; a first power supply network layer located on the first substrate, the first power supply network being located on the second side, the first power supply network layer being electrically connected to the first device layer; and a first bonding layer located on the first power supply network layer, the first bonding layer being located on the second side, the first bonding layer being electrically connected to the first power supply network layer.
3. The chip architecture as described in claim 2, characterized in that, The first chip further includes: a first isolation layer located within the first substrate; and a first embedded power rail located within the first substrate, wherein the first isolation layer covers the first embedded power rail, and the first embedded power rail is electrically connected to the first device layer and the first power supply network layer, respectively.
4. The chip architecture as described in claim 2, characterized in that, The second chip further includes: a second substrate, the second substrate including opposing third and fourth sides; a second device layer located on the second substrate, the second device layer being located on the third side; a second signal interconnect layer located on the third side, the second signal interconnect layer being electrically connected to the second device layer; a second power supply network layer located on the second substrate, the second power supply network being located on the fourth side, the second power supply network layer being electrically connected to the second device layer; and a second bonding layer located on the second power supply network layer, the second bonding layer being located on the fourth side, the second bonding layer being electrically connected to the second power supply network layer.
5. The chip architecture as described in claim 4, characterized in that, The second chip further includes: a second isolation layer located within the second substrate; and a second embedded power rail located within the second substrate, the second isolation layer covering the second embedded power rail, the second embedded power rail being electrically connected to the second device layer and the second power supply network layer respectively.
6. The chip architecture as described in claim 4, characterized in that, The first bonding layer and the second bonding layer are bonded together, and there is a bonding interface between the first bonding layer and the second bonding layer.
7. The chip architecture as described in claim 1, characterized in that, Also includes: A carrier wafer on which the first chip and the second chip are located.
8. The chip architecture as described in claim 7, characterized in that, There is a gap between the edges of the first chip and the second chip and the edge of the substrate.
9. The chip architecture as described in claim 1, characterized in that, The first chip and the second chip may be the same chip or different chips.
10. A method for forming a chip architecture, characterized in that, include: Forming a first chip, wherein forming the first chip includes forming a first signal interconnect layer and a first power supply network layer located on different sides; Forming a second chip, wherein forming the second chip includes forming a second signal interconnect layer and a second power supply network layer located on different sides; The first chip and the second chip are bonded together, the first power supply network layer and the second power supply network layer are located between the first signal interconnect layer and the second signal interconnect layer, and there is a bonding interface between the first chip and the second chip; An external power line is located within the first chip or the second chip, extending to the bonding interface and electrically connected to the first power supply network layer and the second power supply network layer, respectively.
11. The method for forming a chip architecture as described in claim 10, characterized in that, Forming the first chip further includes: forming a first substrate, the first substrate including a first side and a second side opposite to each other; forming a first device layer on the first substrate, the first device layer being located on the first side; a first signal interconnect layer being located on the first side and electrically connected to the first device layer; forming a first power supply network layer on the first substrate, the first power supply network being located on the second side and electrically connected to the first device layer; and forming a first bonding layer on the first power supply network layer, the first bonding layer being located on the second side and electrically connected to the first power supply network layer.
12. The method for forming a chip architecture as described in claim 11, characterized in that, The formation of the first chip further includes: forming a first isolation layer in the first substrate; forming a first embedded power rail in the first substrate, the first isolation layer covering the first embedded power rail, and the first embedded power rail being electrically connected to the first device layer and the first power supply network layer respectively.
13. The method for forming a chip architecture as described in claim 11, characterized in that, Forming the second chip further includes: forming a second substrate, the second substrate including opposing third and fourth sides; forming a second device layer on the second substrate, the second device layer being located on the third side; a second signal interconnect layer being located on the third side and electrically connected to the second device layer; forming a second power supply network layer on the second substrate, the second power supply network being located on the fourth side and electrically connected to the second device layer; and forming a second bonding layer on the second power supply network layer, the second bonding layer being located on the fourth side and electrically connected to the second power supply network layer.
14. The method for forming a chip architecture as described in claim 13, characterized in that, The formation of the second chip further includes: forming a second isolation layer in the second substrate; forming a second buried power rail in the second substrate, the second isolation layer covering the second buried power rail, and the second buried power rail being electrically connected to the second device layer and the second power supply network layer, respectively.
15. The method for forming a chip architecture as described in claim 13, characterized in that, The method for bonding the first chip and the second chip includes: bonding the first bonding layer and the second bonding layer together, wherein the first bonding layer and the second bonding layer have a bonding interface.
16. The method for forming a chip architecture as described in claim 10, characterized in that, Also includes: A carrier is provided, on which the first chip and the second chip are located.
17. The method for forming a chip architecture as described in claim 16, characterized in that, There is a gap between the edges of the first chip and the second chip and the edge of the substrate.
18. The method for forming a chip architecture as described in claim 10, characterized in that, The first chip and the second chip may be the same chip or different chips.