Semiconductor devices and electronic devices

Abstract

This disclosure relates to semiconductor devices and electronic devices. A plurality of external terminals disposed on a first bottom surface of an interposer substrate include a plurality of power terminals capable of supplying a first power potential from an external source to a first circuit. A second bottom surface includes a terminal arrangement region on which the plurality of external terminals are disposed and a peripheral region surrounding the periphery of the terminal arrangement region. The terminal arrangement region includes a first region closest to and extending along a first edge of the interposer substrate. In the first region, only a plurality of the power terminals among the plurality of external terminals are arranged adjacent to each other. The power consumption of the first circuit is the highest among the power consumption of each of the plurality of circuits in the semiconductor chip.

Description

Cross-reference to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-220788, filed on December 17, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Technology

[0002] This invention relates to a semiconductor device and an electronic device.

[0003] The disclosed technologies are listed below.

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2015-154062

[0005] [Patent Document 2] International Patent Publication No. WO2016 / 046987

[0006] Patent documents 1 and 2 disclose techniques for electronic devices in which multiple solder balls arranged on the bottom surface of a semiconductor device are respectively connected to terminals on a mounting substrate. Summary of the Invention

[0007] In many circuits of semiconductor devices, such as the CPU (Central Processing Unit), high functionality requirements enable the processing of large amounts of data at high speeds, resulting in a significant increase in power consumption per unit time. Therefore, from the perspective of achieving high-speed processing of large amounts of data, it is necessary to develop a technology that can stably supply power to circuits at high power consumption.

[0008] Other issues and novel features will become apparent from the description and accompanying drawings in this specification.

[0009] A semiconductor device according to one embodiment includes a semiconductor chip, an interposer substrate, and a plurality of external terminals. The semiconductor chip has a plurality of circuits including a first circuit. The interposer substrate includes a first surface on which the semiconductor chip is mounted and a second surface opposite to the first surface. The plurality of external terminals are aligned and arranged on the second surface of the interposer substrate. The plurality of external terminals include a plurality of first power terminals capable of supplying a first power potential supplied from an external source to the first circuit. The second surface includes a terminal arrangement region on which the plurality of external terminals are arranged and a peripheral region surrounding the periphery of the terminal arrangement region. The terminal arrangement region includes a first region closest to and extending along a first edge of the interposer substrate. In the first region, only a plurality of the plurality of external terminals are arranged adjacent to each other. The power consumption of the first circuit is the highest among the power consumption of each of the plurality of circuits in the semiconductor chip.

[0010] An electronic device according to another embodiment includes the aforementioned semiconductor device and a wiring substrate. The wiring substrate includes a third surface and a fourth surface adjacent to the third surface. The semiconductor device is mounted on the third surface of the wiring substrate.

[0011] According to the above embodiments, the performance of semiconductor devices or electronic devices including semiconductor devices can be improved. Attached Figure Description

[0012] Figure 1 This is a plan view of the top surface of an electronic device according to one embodiment.

[0013] Figure 2 yes Figure 1 A plan view of the bottom surface of the electronic device shown.

[0014] Figure 3 It is along Figure 1 A cross-sectional view of line AA.

[0015] Figure 4 It shows Figure 3 A plan view of an example of a power plane and a ground plane among the multiple conductor planes of the mounting substrate shown.

[0016] Figure 5 yes Figure 3 A plan view of the bottom surface of the semiconductor device shown.

[0017] Figure 6 It shows Figure 3 An explanatory diagram illustrating an example layout of multiple circuits in a semiconductor chip.

[0018] Figure 7 It shows Figure 6 The multiple circuits shown and Figure 5 An explanatory diagram illustrating an example of the electrical connection status between multiple external terminals.

[0019] Figure 8 This is a plan view showing an example of the relative positions of power supply terminals, reference potential terminals, and differential signal terminal pairs among the multiple external terminals of a semiconductor device.

[0020] Figure 9 It is shown as relative to Figure 8 The modified example is a plan view of a semiconductor device.

[0021] Figure 10 It is shown as relative to Figure 8 Another modified example is a plan view of a semiconductor device.

[0022] Figure 11 It is shown as relative to Figure 8Another modified example is a plan view of a semiconductor device.

[0023] Figure 12 It is shown as relative to Figure 6 Modification example Figure 11 A plan view of an example circuit layout in a semiconductor chip of a semiconductor device.

[0024] Figure 13 It shows Figure 12 The multiple circuits shown and Figure 11 An explanatory diagram illustrating an example of the electrical connection status between multiple external terminals.

[0025] Figure 14 It shows that it is installed Figure 11 A plan view of an example of a power plane and a ground plane in multiple conductor planes of a mounting substrate for an electronic component of a semiconductor device.

[0026] Figure 15 It is shown as relative to Figure 11 The modified example is a plan view of a semiconductor device.

[0027] Figure 16 It is shown as relative to Figure 8 Another modified example is a plan view of a semiconductor device. Detailed Implementation The descriptive format, basic terminology, and explanations used in this application

[0028] In this application, for convenience, embodiments will be described in multiple sections, etc., as necessary. Unless otherwise clearly specified, these sections, etc., are not independent or separate from each other, and a part of an example corresponds to another detailed section, modified example, etc. Furthermore, redundant descriptions of similar parts will be omitted in principle. Further, unless otherwise clearly specified, or theoretically limited to a given number, or obvious from the context that a component is indispensable, each component in the embodiments is not always indispensable.

[0029] Similarly, unless explicitly specified otherwise, or it is obvious from the context that the material, composition, etc., contains only A, the use of phrases such as "X is made of A" in the description of embodiments, etc., in relation to materials, compositions, etc., does not exclude components that include elements other than A. For example, for any component, it may mean "X contains A as a main component," etc. For example, "silicon component," etc., is not limited to components made of pure silicon, but includes components made of SiGe (silicon-germanium) alloys or multi-component alloys containing silicon as a main component, as well as components containing other additives, etc. In addition, unless explicitly specified otherwise, gold plating, Cu layer, nickel plating, etc., are not limited to components made of pure components, but include components that respectively contain gold, Cu, nickel, etc. as main components.

[0030] Furthermore, when referring to a specific numerical value or number, unless otherwise clearly specified or obvious from the context that the value is given as an example, the specific numerical value is given only as an example.

[0031] In addition, in each of the accompanying drawings used to describe the embodiments, the same or similar parts are represented by the same or similar symbols or reference numerals, and redundant descriptions thereof are omitted in principle.

[0032] Furthermore, in the accompanying drawings, if the shading lines complicate the drawing or the difference between components and gaps is obvious, the shading lines, etc., may occasionally be omitted, even if the drawing is a cross-section. In this context, if it is obvious from the description, etc., the outline of the background may occasionally be omitted, even for a closed circle in a plan view. Additionally, even if the drawing is not a cross-section, shading lines or dots may occasionally be added to clarify that the part is not a gap or to clarify the boundary of an area.

[0033] In the following description, the terms "power plane," "ground plane," or "conductor plane" may be used. "Plane" refers to a large-area conductor pattern. "Conductor plane" is a collective term for "power plane" and "ground plane," and refers to a large-area conductor pattern supplied with a fixed potential. "Power plane" refers to a large-area conductor pattern supplied with a power source potential. "Ground plane" refers to a large-area conductor pattern supplied with a reference potential.

[0034] The area of ​​the “conductor plane” varies in various examples, but the area of ​​the “conductor plane” is at least ten times the area of ​​the “wiring pattern” that constitutes the signal transmission path. electronic devices

[0035] First, the electronic device of this embodiment will be described. Figure 1 This is a plan view of the top surface of the electronic device according to this embodiment. Figure 2 yes Figure 1 A plan view of the bottom surface of the electronic device shown. Figure 3 It is along Figure 1 A cross-sectional view of line AA.

[0036] Figures 1 to 3 The X direction is shown (see Figures 1 to 3 ), Y direction (see Figure 1 and 2 ) or Z direction (see Figure 3 The Y direction intersects the X direction, and in the following description, the X and Y directions are orthogonal to each other. The Z direction is perpendicular to both the X and Y directions. In other words, the Z direction is the normal direction (i.e., the perpendicular direction) of the XY plane, which includes the X and Y directions. In the following description, "thickness" generally refers to the length in the Z direction. Additionally, in the following description, "plan view" generally refers to a plan view as viewed from the XY plane.

[0037] like Figure 1 As shown, electronic device ED1 has a mounting substrate (wiring substrate) MB1 and a semiconductor device PKG1 mounted on the mounting substrate MB1. The mounting substrate MB1 has a top surface 1t and a bottom surface 1b opposite the top surface (see...). Figure 2 The semiconductor device PKG1 is mounted on the top surface 1t of the mounting substrate MB1.

[0038] Additionally, in this embodiment and as Figure 2 As shown, the regulator (power supply component) RG1 is mounted on the bottom surface 1b of the mounting substrate MB1. The regulator RG1 is a power supply component capable of supplying potentials of various values. For example, the potential required by each of the multiple circuits operating the semiconductor device PKG1 is supplied from the regulator RG1 to the mounting substrate MB1.

[0039] The semiconductor device PKG1 has an interposer substrate SUB1 and a semiconductor chip CP1 mounted on the interposer substrate SUB1. The detailed structure of the semiconductor device PKG1 will be described below.

[0040] Note that the mounting substrate MB1 and the interposer substrate SUB1 of the semiconductor device PKG1 are wiring substrates, respectively. However, the degree of miniaturization of the conductor patterns forming the signal transmission path or potential supply path differs between the mounting substrate MB1 and the interposer substrate SUB1.

[0041] Specifically, the interposer substrate SUB1 is a wiring substrate used as an interposer for electrically connecting the miniaturized semiconductor chip CP1 and the mounting substrate MB1. Signal transmission paths formed on the interposer substrate SUB1 are electrically connected to each electrode of the semiconductor chip CP1, which is arranged with a narrow pitch. Therefore, the conductor pattern of the signal transmission paths forming the interposer substrate SUB1 needs to be miniaturized compared to the conductor pattern of the signal transmission paths formed on the mounting substrate MB1.

[0042] Mounting substrate MB1 is a wiring substrate on which semiconductor device PKG1 is mounted. Figure 1 Only the semiconductor device PKG1, which is an electronic component mounted on the top surface 1t of the mounting substrate MB1, is shown. Additionally, Figure 2 Only the regulator RG1, which is an electronic component mounted on the bottom surface 1b of the mounting substrate MB1, is shown.

[0043] However, the electronic components mounted on the mounting substrate MB1 can be modified in various ways. For example, multiple electronic components, including the semiconductor device PKG1, can be mounted on the top surface 1t of the mounting substrate MB1. Examples of electronic components other than the semiconductor device PKG1 and the regulator RG1 include passive components such as capacitor elements, resistor elements, or inductor elements.

[0044] like Figure 3 As shown, the mounting substrate MB1 has a thickness direction along the mounting substrate MB1 ( Figure 3 Multiple wiring layers MWL are stacked (in the Z direction). The thickness direction of the mounting substrate MB1 is the direction from one side of the mounting substrate MB1 to the other between the top surface 1t and the bottom surface 1b. Figure 3 In the example shown, the mounting substrate MB1 sequentially has wiring layers MWL1 to MWL8. Wiring layer MWL1 is the wiring layer closest to the top surface 1t among the multiple wiring layers MWL. Wiring layer MWL8 is the wiring layer closest to the bottom surface 1b among the multiple wiring layers MWL. Note that... Figure 3 The eight-layer structure of the routing layers shown is just an example, and the number of stacked routing layers (MWL) can vary, such as seven or fewer or nine or more.

[0045] Additionally, the mounting substrate MB1 has multiple vias THW that are formed to penetrate multiple wiring layers MWL. Each of the multiple vias THW is formed to penetrate from wiring layer MWL1 to wiring layer MWL8.

[0046] A wiring substrate in which multiple wiring layers (MWLs) are stacked, similar to a mounting substrate (MB1), and electrically connected via via wiring (THWs) is called a via multilayer substrate. When fabricating a via multilayer substrate, the required total number of wiring layers (MWLs) are stacked, and then vias (through-holes) are formed to penetrate the multiple wiring layers (MWLs). Subsequently, conductors are embedded in the vias to form the via wiring (THWs).

[0047] Note that in Figure 3 In the case of the interposer substrate SUB1 shown, among the multiple stacked wiring layers SWL, the wiring layers SWL that are adjacent to each other in the thickness direction are connected via via wiring. Figure 3The difference between through-hole (THW) routing and via routing is that it spans three or more routing layers (MWL). Figure 3 The image shows a six-layer structure including routing layers SWL1 to SWL6 as an example of routing layer SWL.

[0048] A wiring substrate in which multiple wiring layers (SWLs) are electrically connected via vias, such as an interposer substrate (SUB1), is called a build-up substrate. During the fabrication of a build-up substrate, vias are formed each time the SWLs are stacked. The method of fabricating a build-up substrate is called a stacking process.

[0049] In the case of a via multilayer substrate, as described above, interlayer conductive paths connecting multiple wiring layers (MWLs) can be formed in a single step, thus improving manufacturing efficiency. Consequently, the manufacturing cost of the mounting substrate (MB1) can be reduced. On the other hand, it is necessary to consider the location of the multiple via wiring layers (THWs) when designing each of the multiple wiring layers (MWLs). Therefore, constraints arise in the layout of the conductor patterns in each of the multiple wiring layers (MWLs).

[0050] Figure 4 It shows Figure 3 A plan view of an example of a power plane and a ground plane among the multiple conductor planes of the mounting substrate shown. Figure 4 An enlarged view is shown. Figure 3 This is a portion of the wiring layer MWL1 shown. Figure 4 In, with Figure 3 The outline of the overlapping region RPKG of the semiconductor device PKG1 shown is indicated by two dashed lines.

[0051] like Figure 4 As shown, the mounting substrate MB1 includes multiple conductor patterns, including a conductor plane 1CP for supplying a fixed potential (such as a power supply potential and a reference potential). The conductor plane 1CP is a large-area conductor pattern. Inserting a large-area conductor plane 1CP into the supply path of the fixed potential allows for an increase in the cross-sectional area of ​​the current path. As a result, a fixed potential can be stably supplied to the power dissipation circuit.

[0052] In the multiple conductor planes on which the substrate MB1 is mounted, Figure 4 The power plane 1PVD1 constituting the supply path for the power supply potential and the ground plane 1PVS1 constituting the supply path for the reference potential are shown. Additionally, Figure 4 A power plane 1PVD2 is shown, which forms a supply path for a power potential different from that supplied to the power plane 1PVD1.

[0053] Additionally, multiple via wirings THW are arranged in wiring layer MWL1. The multiple via wirings THW include a power potential via wiring WVD1 for supplying a power supply potential and a reference potential via wiring WVS1 for supplying a reference potential (e.g., ground potential). Additionally, the multiple via wirings THW include a signal via wiring WSG1 for transmitting signals.

[0054] Various potentials, such as power supply potential, reference potential, and signal potential, are supplied to Figure 3 The semiconductor device PKG1 is shown. Therefore, as... Figure 4 As shown, a large number of via wirings (THW) are densely arranged in the region RPKG that overlaps with the semiconductor device PKG1 (see Figure 1). Figure 3 In other words, the via wiring density (THW) in the regional RPKG is higher than that in the peripheral areas of the regional RPKG.

[0055] Therefore, a large number of openings H1 are formed in the grounding plane 1PVS1 in the area RPKG. Additionally, it is difficult to make the area of ​​the power plane 1PVD2 arranged in the area RPKG large enough.

[0056] On the other hand, in a plan view, it is relatively easy to ensure that the space outside the RPKG area is free of additional via wiring for other potentials or signals. For example, in Figure 4 In the example shown, among the multiple via traces THW arranged at a location overlapping with the power plane 1PVD1, there are two via traces THW that are not power potential via traces WVD1. Therefore, two openings H1 are formed in the power plane 1PVD1.

[0057] From the perspective of stably supplying a fixed potential, it is preferable that the number of openings H1 formed in the power plane 1PVD1 be as small as possible. In particular, it is preferable that in the semiconductor device PKG1 (see...) Figure 3 It is connected to the external terminal SB of the mounting substrate MB1 (see...). Figure 3 The number of openings H1 in the vicinity of the power plane 1PVD1 should be as small as possible. When the number of openings H1 is small, the degree of freedom of charge movement within the power plane 1PVD1 increases. In this case, even if the power demand suddenly increases, a voltage drop is less likely to occur.

[0058] The electronic device ED1 in this embodiment (see...) Figure 3 This reduces the number of openings H1 formed in the power plane 1PVD1 and increases the area of ​​the power plane 1PVD1. This stabilizes the supply to the semiconductor device PKG1 via the power plane 1PVD1 (see [link to relevant documentation]). Figure 3 The power supply potential of ).

[0059] For example, in Figure 4 In the example shown, the via wiring located at a position overlapping with and electrically isolated from power plane 1PVD1 is referred to as via wiring THW1. The via wiring located at a position overlapping with semiconductor device PKG1 (see...) Figure 3 The via routing THW at the overlapping location is called via routing THW2. Figure 4 In this case, the number of through-hole wiring THW1 is less than the number of second through-hole wiring THW2.

[0060] Note that, as mentioned above, from the perspective of stabilizing the power supply potential, it is necessary to modify the structure of the semiconductor device PKG1. The next chapter will describe the details of the structure of the semiconductor device PKG1. semiconductor devices

[0061] Figure 1 This is a plan view of the top surface of the electronic device in this embodiment. Figure 5 yes Figure 3 The diagram shows a plan view of the bottom surface of the semiconductor device, with shaded lines added to the power terminals TVD1 and TVD2 to make them easier to distinguish from the other external terminals SB. Figure 6 It shows Figure 3 An explanatory diagram illustrating an example layout of multiple circuits in a semiconductor chip. Figure 7 It shows Figure 6 The multiple circuits shown and Figure 5 An explanatory diagram illustrating an example of the electrical connection status between multiple external terminals.

[0062] like Figure 1 and 3 As shown, the semiconductor device PKG1 has a semiconductor chip CP1, an interposer substrate SUB1, and multiple external terminals SB.

[0063] like Figure 5 As shown, the bottom surface 2b of the interposer substrate SUB1 is rectangular. In other words, when viewed from above, the bottom surface 2b has a rectangular shape. The bottom surface 2b includes an edge 2s1, an edge 2s2 opposite to edge 2s1, an edge 2s3 extending in a direction perpendicular to edges 2s1 and 2s2, and an edge 2s4 opposite to edge 2s3.

[0064] Note that, as Figure 1 As shown, the top surface 2t of the interposer substrate SUB1 also has edges 2s1, 2s2, 2s3 and 2s4. Figure 5 Each edge of the bottom surface 2b shown is with Figure 1 The corresponding edges of the top surface 2t shown overlap.

[0065] Additionally, the semiconductor chip CP1 includes an edge 3s1, an edge 3s2 opposite to edge 3s1, an edge 3s3 extending in a direction intersecting each of edges 3s1 and 3s2, and an edge 3s4 opposite to edge 3s3. Edge 3s1 is arranged along edge 2s1. Edge 3s2 is arranged along edge 2s2. Edge 3s3 is arranged along edge 2s3. Edge 3s4 is arranged along edge 2s4. Note that the edges of the semiconductor chip CP1 are also... Figure 6 As shown in the image.

[0066] The bottom surface 2b includes a terminal arrangement region RSB on which multiple external terminals SB are arranged, and a peripheral region RPF surrounding the periphery of the terminal arrangement region RSB. In the plan view, the multiple external terminals SB are aligned and arranged on the bottom surface 2b of the interposer substrate SUB1. Figure 5 In the example shown, multiple external terminals SB are arranged in a matrix. Each of the multiple external terminals SB is a solder ball formed, for example, by spherical solder.

[0067] like Figure 6 As shown, the semiconductor chip CP1 includes multiple circuits. These circuits include circuit C1 and circuit C2. Additionally, in... Figure 6 In the example shown, the semiconductor chip CP1 includes multiple circuits C3 and C4.

[0068] Figure 6 The circuit C1 shown is, for example, a CPU circuit. A CPU circuit is a circuit that reads and executes programs. It is used to perform the computer's main arithmetic operations. The CPU circuit is electrically connected to peripheral circuits (such as circuits C3 and C4) via a peripheral bus.

[0069] Multiple circuits C3 are input / output circuits such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). Related to the buffer memory described below, DDR SDRAM, etc., is also referred to as main memory.

[0070] Circuit C4 is a signal input / output circuit. This input / output circuit includes, for example, a SerDes circuit that switches between serial and parallel transmission methods.

[0071] Circuit C2 is the core circuit (or also referred to as the core logic circuit). However, the core circuit constituting circuit C2 differs from the CPU circuit shown in circuit C1. Circuit C2 includes memory control circuitry that controls the operation of circuit C3. Additionally, circuit C2 includes input / output control circuitry that controls the operation of circuit C4. Additionally, circuit C2 includes the aforementioned peripheral bus. Additionally, circuit C2 includes SRAM (Static Random Access Memory) circuitry that can be used as a cache memory circuit.

[0072] focus on Figure 6 The power consumption of each of the multiple circuits shown is as follows: circuit C1 has the highest power consumption among all the circuits in semiconductor chip CP1. Additionally, circuit C2 has the second highest power consumption among all the circuits in semiconductor chip CP1.

[0073] Although not shown, as an example of this embodiment, an embodiment can be considered that has a supply path for supplying power potential to circuit C1, which is a CPU circuit, and a supply path for supplying power potential to circuit C2, which is a core circuit.

[0074] However, from the perspective of stably supplying power to circuit C1, which has the highest power consumption, it is preferable to provide a dedicated path for supplying power potential to circuit C1. For example, providing a dedicated power path for circuit C1 makes it possible to prevent sudden power shortages in circuit C1 depending on the operating state of other circuits.

[0075] like Figure 7 As shown, in this embodiment, the supply paths for power supply potential VD1 and VD2 are electrically isolated from each other. Power supply potentials VD1 and VD2 are at different potentials. However, as a modified example, power supply potentials VD1 and VD2 can be at the same potential. Even when power supply potentials VD1 and VD2 are at the same potential, the supply paths for power supply potential VD1 and VD2 are electrically isolated from each other. Therefore, this embodiment is preferred from the perspective of stably supplying power to the circuit C1, which has the maximum power consumption.

[0076] Note the operation. Figure 6 The power supply path required for each of the multiple circuits C3 and C4 shown is provided separately from the power supply path for power supply potential VD1 and the power supply path for power supply potential VD2. However, in Figure 7 These have been omitted.

[0077] like Figure 7 As shown, each of the multiple external terminals SB of the semiconductor device PKG1 includes a power supply terminal TVD1 capable of supplying a power supply potential VD1 from an external source to circuit C1. Note that in Figure 7 The diagram schematically shows a single power terminal TVD1, but as... Figure 5 As shown, the semiconductor device PKG1 includes multiple power supply terminals TVD1. Additionally, as... Figure 7 In the example shown, each of the multiple external terminals SB also includes a power terminal TVD2 capable of supplying a power potential VD2 from an external source to circuit C2. For example... Figure 5 As shown, the semiconductor device PKG1 includes multiple power supply terminals TVD2.

[0078] like Figure 5 As shown, the terminal arrangement area RSB includes a region RVD1 that is closest to the edge 2s1 of the interposer substrate SUB1 and extends along the edge 2s1. Additionally, in region RVD1, only the power terminal TVD1 of the plurality of external terminals SB is arranged to be adjacent to each other.

[0079] Here, the power supply potential VD1 is referenced. Figure 4 A power plane 1PVD1 is supplied in the wiring layer MWL1 within multiple conductor planes 1CP of the described mounting substrate MB1. In the transparent planar view, the power plane 1PVD1 is arranged across the semiconductor device PKG1 (see [reference]). Figure 5 The interlayer substrate SUB1 (see) Figure 5 The bottom surface 2b of ) (see Figure 5 Edge 2s1 is one of the four edges of ).

[0080] like Figure 5 As shown, when multiple power terminals TVD1 are arranged adjacent to each other in area RVD1, no other types of external terminals are arranged in area RVD1. Therefore, in Figure 4 In the power plane 1PVD1 shown, in relation to Figure 3 The semiconductor device PKG1 shown does not have an opening H1 formed in the overlapping portion arranged in the region RPKG. In other words, in this embodiment, in the power plane 1PVD1 (see... Figure 4 In the case of TVD1, which is arranged in multiple power supply terminals (see...), Figure 5 No opening H1 is formed in the vicinity of (see) Figure 4 Therefore, the increased degree of freedom of charge movement between multiple power terminals TVD1 allows for a stable supply of power potential VD1 to the power supply. Figure 7 The circuit shown is C1.

[0081] As described above, circuit C1 is the CPU circuit. Depending on the timing of the arithmetic processing, the CPU circuit may need to significantly change its power. For example, consider the case where the current flowing through some power terminals TVD1 increases due to a sudden increase in the power required by the CPU circuit.

[0082] When the current flowing through some of the multiple power terminals TVD1 increases, the charge around the power terminals TVD1 becomes insufficient. At this time, if the power plane 1PVD1 (see...) Figure 4 If the power supply is arranged near multiple power terminals TVD1, then the insufficient charge is supplied from the periphery of the power terminals TVD1 through the power plane 1PVD1 where a large current flows.

[0083] However, when in power plane 1PVD1 (see...) Figure 4 An opening H1 is formed in the (see) Figure 4 When the opening H1 is open, it may impede the movement of charge, resulting in a sudden voltage drop.

[0084] On the other hand, in the case of this embodiment and as Figure 4 As shown, no opening H1 is formed in the power plane 1PVD1 within the region RPKG. Therefore, charge movement is unimpeded, and voltage drop can be suppressed. That is, charge can be transferred to... Figure 7 The circuit shown has C1 that stably supplies power potential VD1.

[0085] Note that depends on Figure 4 The arrangement pitch of the external terminals SB and the dimensions of the power plane 1PVD1 shown may have various modifications, differing in the number of power terminals TVD1 arranged consecutively in region RVD1. However, from the perspective of stabilizing the power supply potential, it is necessary to arrange at least a number of power terminals TVD1 adjacent to each other. Additionally, it is preferable to arrange five or more power terminals TVD1 consecutively. Figure 5 In the example shown, ten power terminals TVD1 are arranged in a continuous sequence.

[0086] Additionally, as referenced above Figure 6 The semiconductor chip CP1, as described, also includes circuit C2. (As...) Figure 5 and 7 As shown, the multiple external terminals SB also include multiple power supply terminals TVD2 (see...). Figure 5 ), which can draw power potential VD2 from an external source (see Figure 7 ) supplies to circuit C2 (see Figure 7 ).like Figure 5 As shown, the terminal arrangement area RSB includes area RVD2, which is farther from area RVD1 when viewed from edge 2s1. Multiple power terminals TVD2 are arranged in area RVD2.

[0087] like Figure 5 As shown, the power terminals TVD2 are densely arranged in region RVD2. In other words, the power terminals TVD2 are collectively arranged in region RVD2. Additionally, as... Figure 4 As shown, the power plane 1PVD2 constitutes the supply path for the power supply potential VD2 (see Figure 1). Figure 7 It is arranged in the wiring layer MWL1 of the mounting substrate MB1.

[0088] However, as Figure 5As shown, the external terminals SB, except for the power terminal TVD2, are arranged around the periphery of area RVD2. Therefore, as Figure 4 As shown, it is not possible to make the area of ​​power plane 1PVD2 larger than the area of ​​power plane 1PVD1. Additionally, power plane 1PVD2 is arranged on a different routing layer than routing layer MWL1 (e.g., Figure 3 The configuration on any of the wiring layers MWL2 to MWL8 shown. However, as Figure 4 As shown, a large number of vias are arranged in the RPKG area. Therefore, even if the power plane 1PVD2 is arranged in conjunction with... Figure 4 On different wiring layers of the wiring layer MWL1 shown, a large number of openings H1 will also be formed in the power plane 1PVD2.

[0089] Therefore, as mentioned above, from the perspective of stably supplying a fixed potential, Figure 7 The supply path for power potential VD1 shown is superior to the supply path for power potential VD2. In this embodiment, the focus is on... Figure 7 The power consumption of the multiple circuits in the semiconductor chip CP1 shown is prioritized, with the supply path connected to the power supply potential of the circuit C1, which has the highest power consumption. This is because a sudden voltage drop is less likely to occur in the circuit C2, which has lower power consumption than circuit C1.

[0090] Additionally, as referenced above Figure 7 As described, the plurality of external terminals SB also include a reference potential terminal TVS1 capable of supplying a reference potential VS1 from an external source to circuits C1 and C2.

[0091] like Figure 5 As shown, the terminal arrangement area RSB also includes area R3 located between areas RVD1 and RVD2. At least some of the plurality of reference potential terminals TVS1 are arranged in area R3.

[0092] Note that, as Figure 6 As shown, among the four edges of the semiconductor chip CP1, circuit C1 is arranged closer to edge 3s1 than edge 3s2. Figure 1 As shown, the edge 3s1 of the semiconductor chip CP1 is arranged along the edge 2s1 of the interposer substrate SUB1. Figure 5 As shown, multiple power terminals TVD1 are arranged in the region RVD1 closest to the edge 2s1. In this case, arranging circuit C1 close to the edge 3s1 can shorten the distance of the supply path for the power potential VD1 (see Figure 1). Figure 7 ). Relationship between signal terminals and power terminals

[0093] The following will describe several embodiments. Figure 5The relative positions of the multiple power supply terminals TVD1 and the external terminals SB used for signal transmission are shown. Figure 8 This is a plan view illustrating an example of the relative positions of power supply terminals, reference potential terminals, and differential signal terminal pairs among the various external terminals of a semiconductor device. Although Figure 8 This is a plan view, but to make it easier to identify the type of external terminals SB, some external terminals SB are shaded. The same applies to the description below. Figures 9 to 11 15 and 16.

[0094] Figure 8 The external terminals SB of the semiconductor device PKG2 shown are arranged as follows. Specifically, regions RVD1 and R3 are adjacent to each other, with no other regions inserted between them. The multiple external terminals SB also include multiple differential signal terminal pairs TSG1. The differential signal terminal pairs TSG1 constitute a differential pair capable of transmitting a signal SG1 as a differential signal at a first signal transmission speed (see [link to documentation]). Figure 7 ).

[0095] Multiple reference potential terminals TVS1 are arranged to surround the periphery of each differential signal terminal pair in the multiple differential signal terminal pairs TSG1, and are adjacent to each differential signal terminal pair in the multiple differential signal terminal pairs TSG1. Some of the multiple reference potential terminals TVS1 arranged in the periphery of each differential signal terminal pair in the multiple differential signal terminal pairs TSG1 are adjacent to one of the power supply terminals TVD1 arranged in region RVD1.

[0096] As a signal transmission method, differential signals and single-ended signals are compared. As a method to improve signal transmission speed, there are methods to reduce the signal voltage amplitude. Additionally, in recent years, techniques such as PAM4 (4-level pulse amplitude modulation) have been developed to increase the information content contained in the signal voltage amplitude, in order to achieve high-speed signal transmission.

[0097] In the case of single-ended signals, reducing the amplitude of the signal voltage increases the impact of noise. On the other hand, in the case of differential signals, the potential difference between the paired transmission paths is utilized, so noise can be eliminated when the same noise is applied to both transmission paths. In other words, differential signals have higher noise immunity than single-ended signals when the amplitude of the signal voltage decreases. Therefore, differential signals are used as transmission paths for high-speed signals.

[0098] However, to improve the transmission quality of differential signals, it is necessary to consider the characteristic impedance of the transmission path. The characteristic impedance of the differential signal transmission path is defined by factors such as the distance between transmission paths, the distance between the transmission path and the surrounding conductor pattern, and the polarity of the current flowing in the transmission path. To improve the transmission quality of differential signals, it is preferable to avoid impedance discontinuities in the differential signal transmission path. Therefore, it is preferable that the distance between transmission paths remains constant, and that the conductor pattern with a fixed potential flow is arranged at a constant distance around the periphery of the transmission path.

[0099] exist Figure 8 In the example shown, a reference potential terminal TVS1 supplying ground potential is arranged between each of the multiple differential signal terminal pairs TSG1 and a power supply terminal TVD1. Therefore, the effect of the multiple power supply terminals TVD1 allows for the suppression of impedance discontinuities in the transmission path of the differential signal. As a result, the quality of high-speed transmitted differential signals can be improved.

[0100] Note that when mounting substrate MB1 (see...) Figure 1 In this context, when considering the wiring layout for signal transmission, it is preferable to place the signal transmission terminals close to... Figure 8 The location of the outermost edge of the terminal arrangement area RSB shown. Figure 8 In the example shown, the terminal arrangement area RSB includes area R4 extending along edge 2s2, area R5 extending along edge 2s3, and area R6 extending along edge 2s4. Some of the plurality of differential signal terminal pairs TSG1 are arranged in at least one of areas R4, R5, and R6. Figure 8 In the example shown, multiple differential signal terminal pairs TSG1 are arranged in each of regions R4 and R5.

[0101] As described above, from the perspective of improving the quality of the differential signal, it is preferable that the differential signal terminal pair TSG1 is surrounded by the reference potential terminal TSV1. Therefore, in the outermost part of the terminal arrangement area RSB, that is, in the regions closest to edge 2s2 and closest to edge 2s3, multiple reference potential terminals TSV1 are arranged continuously. The differential signal terminal pair TSG1 is arranged in the second column starting from the outermost part.

[0102] Figure 9 It is shown as relative to Figure 8 The modified example is a plan view of a semiconductor device. Figure 9 The semiconductor device PKG3 shown has multiple external terminals SB and Figure 8 The external terminal SB of the semiconductor device PKG2 shown differs in the following ways.

[0103] The multiple external terminals SB also include multiple signal terminals TSG2. The signal terminals TSG2 are capable of transmitting signals SG2 at a second signal transmission speed (see [link to documentation]). Figure 7 The second signal transmission speed is faster than the first signal transmission speed (i.e., ...). Figure 7 The transmission speed of signal SG1 shown is slow. Signal SG2 is, for example, a single-ended signal. Note that in... Figure 8 The example shown also illustrates the signal terminal TSG2. Multiple signal terminals TSG2 are arranged in area R6.

[0104] exist Figure 9 In the case of the semiconductor device PKG3 shown, multiple signal terminals TSG2 are arranged in region R3. A reference potential terminal TVS1 is inserted between the multiple signal terminals TSG2 and the multiple differential signal terminal pairs TSG1.

[0105] Depending on the layout of the terminals used for signal transmission, signal terminal TSG2 can be positioned close to differential signal terminal TSG1 used for high-speed transmission. In this case, it is necessary to avoid placing it near signal terminal TSG2 (see [link to TSG1]). Figure 7 The signal SG2 flowing in the differential signal terminal and the signal TSG1 (see...) Figure 7 Interference between the signals SG1 flowing in the differential signal terminal pair TSG1 and the signal terminal TSG2 can suppress the aforementioned interference. As in this modified example, inserting a reference potential terminal TVS1 between the differential signal terminal pair TSG1 and the signal terminal TSG2 can suppress the aforementioned interference.

[0106] As mentioned above, Figure 7 The signal SG2 shown is transmitted at a lower speed than signal SG1. Therefore, significantly increasing the signal voltage can reduce the impact of noise. In other words, any external terminal SB can be arranged around signal terminal TSG2. Figure 9 In the example shown, some of the multiple signal terminals TSG2 are adjacent to one of the multiple power terminals TVD1 arranged in region RVD1. Note that, although not shown in the figures, this is relative to... Figure 9 In a modified example shown, the reference potential terminal TVS1 can be inserted between multiple power supply terminals TVD1 and multiple signal terminals TSG2 arranged in area RVD1.

[0107] Figure 10 It is shown as relative to Figure 8 Another modified example is a plan view of a semiconductor device. Figure 10 The semiconductor device PKG4 shown has multiple external terminals SB and Figure 8 The external terminal SB of the semiconductor device PKG2 shown differs in the following ways.

[0108] The terminal arrangement area RSB also includes a region R7 that is closest to and extends along the edge 2s3 of the interposer substrate SUB1. In region R7, only a plurality of power terminals TVD1 among the plurality of external terminals SB are arranged adjacent to each other. In other words, in the case of the semiconductor device PKG4, the plurality of power terminals TVD1 are arranged along multiple edges.

[0109] In cases where the power terminals TVD1 are arranged along multiple edges as in this modified example, the number of... Figure 4 The area of ​​the power plane 1PVD1 near the power terminal TVD1 is shown.

[0110] Figure 11 It is shown as relative to Figure 8 Another modified example is a plan view of a semiconductor device. Figure 12 It is shown as relative to Figure 6 Modification example Figure 11 A plan view of an example circuit layout in a semiconductor chip of a semiconductor device. Figure 13 It shows Figure 12 The multiple circuits shown and Figure 11 An explanatory diagram illustrating an example of the electrical connection status between multiple external terminals. Figure 14 It shows that it is installed Figure 11 A plan view of an example of a power plane and a ground plane in multiple conductor planes of a mounting substrate for an electronic component of a semiconductor device. Figure 11 The semiconductor device PKG5 shown has multiple external terminals SB and Figure 8 The external terminal SB of the semiconductor device PKG2 shown differs in the following ways.

[0111] Figure 11 The semiconductor device PKG5 shown has Figure 12 The semiconductor chip CP2 is shown. The semiconductor chip CP2 also includes multiple circuits. Figure 12 and 13 The circuit C5 shown is a second CPU circuit capable of performing on / off operations independently of circuit C1, which is the CPU circuit. Since circuit C5 can perform on / off operations independently of circuit C1, there are cases where only circuit C1 operates, circuits C1 and C5 operate simultaneously, and only circuit C5 operates.

[0112] When circuits C1 and C5 perform independent on / off operations, it is necessary to separate the power supply paths for circuits C1 and C5. Furthermore, even when they do not perform independent on / off operations, the power consumption of circuit C5 during operation is the same as that of circuit C1, or it is the second largest among the multiple circuits in semiconductor chip CP1. Therefore, it is preferable to separate the power supply paths to the two CPU circuits with the highest power consumption. This is to prevent the power demand of one CPU circuit from affecting the power supply of the other CPU circuit.

[0113] like Figure 13 As shown, the multiple external terminals SB also include multiple power terminals TVD3 capable of supplying a power potential VD3 from an external source to circuit C5. The power potential VD3 may be at the same potential as the power potential VD1, or it may be at a different potential from the power potential VD1. In either case, power terminals TVD3 are electrically isolated from power terminals TVD1.

[0114] like Figure 11 As shown, the terminal arrangement region RSB includes a region RVD3 that extends along the edge 2s1 at a distance from the edge 2s1 of the interposer substrate SUB1 equal to the distance between region RVD1 and the interposer substrate SUB1. In region RVD3, only a plurality of power terminals TVD3 of the plurality of external terminals SB are arranged adjacent to each other.

[0115] In this modified example, each of the multiple power terminals TVD1 and multiple power terminals TVD3 is arranged on the outermost periphery of the terminal arrangement area RSB. The multiple power terminals TVD1 are connected to... Figure 14 The power plane 1PVD1 is shown. Multiple power terminals TVD3 are connected to... Figure 14 The power plane 1PVD3 is shown. Additionally, each of the power planes 1PVD1 and 1PVD3 does not overlap with the via wiring TWH in the area RPKG. That is, each of the multiple power terminals TVD1 and TVD3 is connected to a power plane with a large area near the terminal. Therefore, a potential can be stably supplied to each of the multiple power terminals TVD1 and TVD3.

[0116] Note that when using semiconductor chips with multiple CPU circuits (such as...) Figure 12 In the case of the semiconductor chip CP2 shown, the combination Figure 11 The illustrated embodiments and Figure 10 The modified examples shown are particularly effective. Figure 15 It is shown as relative to Figure 11 The modified example is a plan view of a semiconductor device.

[0117] Figure 15 The semiconductor device PKG6 shown has multiple external terminals SB and Figure 11 The external terminal SB of the semiconductor device PKG5 shown differs in the following ways.

[0118] exist Figure 15 In the example shown, the terminal arrangement area RSB also includes areas R7 and R9. Area R7 is closest to and extends along edge 2s3 of the interposer substrate SUB1. Area R9 is closest to and extends along edge 2s4 of the interposer substrate SUB1. In area R7, only a plurality of power terminals TVD1 of the plurality of external terminals SB are arranged adjacent to each other. In area R9, only a plurality of power terminals TVD3 of the plurality of external terminals SB are arranged adjacent to each other.

[0119] In this modified example, multiple power terminals TVD1 and multiple power terminals TVD3 are arranged along two edges respectively. In this case, with Figure 11 Compared to the semiconductor device PKG5 shown, the number of multiple power terminals TVD1 and multiple power terminals TVD3 can be increased.

[0120] Additionally, although each embodiment described above is described as having a plurality of power terminals TVD1 arranged only at the outermost periphery of the terminal arrangement area RSB, modified examples may have some of the plurality of power terminals TVD1 arranged outside the outermost periphery of the terminal arrangement area RSB, such as Figure 16 The semiconductor device shown is PKG7. Figure 16 It shows relative to Figure 8 Another modified example of a floor plan.

[0121] Figure 16 The semiconductor device PKG7 shown has multiple external terminals SB and Figure 8 The external terminals SB of the semiconductor device PKG2 shown differ in the following ways. The terminal arrangement area RSB also includes area R10. Area R10 is adjacent to area RVD1 and is located between area R3 and area RVD1. Area R10 extends along area RVD1. In area R10, only a plurality of power terminals TVD1 of the plurality of external terminals SB are arranged adjacent to each other.

[0122] In other words, in this modified example, each of the multiple power terminals TVD1 is arranged in two consecutive rows along edge 2s1. Further increases can be achieved by arranging the power terminals TVD1 in this manner only in each of the adjacent regions RVD1 and R10. Figure 4 The area of ​​power plane 1PVD1 in the region RPKG shown.

[0123] Note that, although Figure 16 An embodiment is shown in which each of the multiple power terminals TVD1 is arranged in two rows, but the number of rows can be three or more.

[0124] In the foregoing, the present invention, made by the inventors, has been specifically described based on embodiments. However, it should be understood that the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

[0125] For example, the above-mentioned multiple modification examples can be combined with each other.

[0126] Additionally, Figure 4 It shows that it is installed Figure 5 The semiconductor device PKG1 shown is equipped with electronic device ED1, and Figure 14 It shows that it is installed Figure 11 The semiconductor device PKG5 shown is accompanied by electronic component ED2. However, various modifications to the electronic component are possible. For example, although not shown, references are included. Figures 8 to 16 The electronic device of any one of the described semiconductor devices is capable of stably supplying a power supply potential VD1 (see [link to description]). Figure 7 ).

Claims

1. A semiconductor device, comprising: A semiconductor chip having multiple circuits including a first circuit; An interposer substrate includes a first surface and a second surface opposite to the first surface, the semiconductor chip is mounted on the first surface, and the second surface is rectangular in shape when viewed from above; and Multiple external terminals are aligned and disposed on the second surface of the interposer substrate. The plurality of external terminals include a plurality of first power terminals, which are capable of supplying a first power potential from an external source to the first circuit. The second surface includes a terminal arrangement area and a peripheral area, wherein the plurality of external terminals are arranged in the terminal arrangement area, and the peripheral area surrounds the periphery of the terminal arrangement area. The terminal arrangement region includes a first region that is closest to and extends along the first edge of the interposer substrate. In the first region, only the plurality of first power terminals among the plurality of external terminals are arranged adjacent to each other, and Among the power consumption of each of the plurality of circuits in the semiconductor chip, the first circuit has the highest power consumption.

2. The semiconductor device according to claim 1, The plurality of circuits in the semiconductor chip further include a second circuit. The plurality of external terminals further include a plurality of second power supply terminals, which are capable of supplying a second power potential from an external source to the second circuit. The terminal arrangement area includes a second area that is farther from the first area when viewed from the first edge, and The plurality of second power terminals are arranged in the second region.

3. The semiconductor device according to claim 2, The terminal arrangement area further includes a third area, which is located between the first area and the second area. The plurality of external terminals further include a plurality of reference potential terminals, which are capable of supplying a reference potential from an external source to the first circuit and the second circuit. The plurality of reference potential terminals are arranged in the third region.

4. The semiconductor device according to claim 3, The first region and the third region are adjacent to each other, and no other region is inserted between the first region and the third region. The plurality of external terminals further include a plurality of first differential signal terminal pairs, which are capable of transmitting a first differential signal at a first signal transmission speed. The plurality of reference potential terminals are arranged to surround the periphery of each of the plurality of first differential signal terminal pairs and are adjacent to each of the plurality of first differential signal terminal pairs. Some of the reference potential terminals in the periphery of each of the plurality of first differential signal terminal pairs are adjacent to one of the plurality of first power supply terminals arranged in the first region.

5. The semiconductor device according to claim 4, The plurality of external terminals further include a plurality of first signal terminals, which are capable of transmitting the first signal at a second signal transmission speed lower than the first signal transmission speed. The plurality of first signal terminals are arranged in the third region, and The reference potential terminal is inserted between the plurality of first signal terminals and the plurality of first differential signal terminal pairs.

6. The semiconductor device according to claim 5, The plurality of first signal terminals are adjacent to one of the plurality of first power terminals that is arranged in the first region.

7. The semiconductor device according to claim 4, wherein the interposer substrate comprises: The first edge, the second edge opposite to the first edge, the third edge extending in a direction intersecting each of the first edge and the second edge, and the fourth edge opposite to the third edge. The terminal arrangement area includes: a fourth region extending along the second edge, a fifth region extending along the third edge, and a sixth region extending along the fourth edge. Some of the first differential signal terminals in the plurality of first differential signal terminal pairs are arranged in at least one of the fourth region, the fifth region, and the sixth region.

8. The semiconductor device according to claim 3, wherein the interposer substrate comprises: The first edge, the second edge opposite to the first edge, the third edge extending in a direction intersecting each of the first edge and the second edge, and the fourth edge opposite to the third edge. The terminal arrangement region further includes a seventh region, which is closest to and extends along the third edge of the interposer substrate. In the seventh region, only the plurality of first power terminals among the plurality of external terminals are arranged to be adjacent to each other.

9. The semiconductor device according to claim 2, The plurality of circuits of the semiconductor chip include: CPU circuitry; Multiple memory circuits; as well as Multiple input / output circuits, The first circuit is the CPU circuit, and The second circuit includes a circuit configured to control one of the plurality of memory circuits and the plurality of input / output circuits.

10. The semiconductor device according to claim 2, The semiconductor chip further includes a third circuit. The plurality of external terminals also include a plurality of third power supply terminals, which are capable of supplying a third power potential from an external source to the third circuit. The terminal arrangement region includes an eighth region, the distance between the eighth region and the first edge of the interposer substrate is equal to the distance between the first region and the first edge of the interposer substrate, and the eighth region extends along the first edge. in, In the eighth region, only the plurality of third power terminals among the plurality of external terminals are arranged adjacent to each other, and The power consumption of the third circuit is the same as that of the first circuit, or the power consumption of the third circuit is the second largest among the power consumptions of each of the plurality of circuits in the semiconductor chip.

11. The semiconductor device according to claim 10, The interposer substrate includes: The first edge, the second edge opposite to the first edge, the third edge extending in a direction intersecting each of the first edge and the second edge, and the fourth edge opposite to the third edge. The terminal arrangement area further includes: The seventh region is closest to and extends along the third edge of the interposer substrate; and The ninth region is closest to and extends along the fourth edge of the interposer substrate. In the seventh region, only the plurality of first power terminals among the plurality of external terminals are arranged adjacent to each other, and In the ninth region, only the plurality of third power terminals among the plurality of external terminals are arranged to be adjacent to each other.

12. The semiconductor device according to claim 10, The first circuit is the first CPU circuit, and The third circuit is a second CPU circuit, which is capable of performing on / off operations independently of the first CPU circuit.

13. The semiconductor device according to claim 2, The terminal arrangement area further includes: The third region is located between the first region and the second region; as well as The tenth region is adjacent to the first region and located between the third region and the first region. The tenth region extends along the first region, and In the tenth region, only the plurality of first power terminals among the plurality of external terminals are arranged to be adjacent to each other.

14. An electronic device, comprising: The wiring substrate includes a third surface and a fourth surface adjacent to the third surface; as well as A semiconductor device is mounted on the third surface of the wiring substrate. The semiconductor device includes: A semiconductor chip having multiple circuits including a first circuit; An interposer substrate includes a first surface and a second surface opposite to the first surface, the semiconductor chip is mounted on the first surface, and the second surface is rectangular in shape when viewed from above; and Multiple external terminals are aligned and disposed on the second surface of the interposer substrate. The plurality of external terminals include a plurality of first power supply terminals, which are capable of supplying a first power potential to the first circuit. The second surface includes a terminal arrangement area and a peripheral area, wherein the plurality of external terminals are arranged in the terminal arrangement area, and the peripheral area surrounds the periphery of the terminal arrangement area. The terminal arrangement region includes a first region that is closest to and extends along the first edge of the interposer substrate. In the first region, only the plurality of first power terminals among the plurality of external terminals are arranged adjacent to each other, and Among the power consumption of each of the plurality of circuits in the semiconductor chip, the first circuit has the highest power consumption.

15. The electronic device according to claim 14, The plurality of circuits in the semiconductor chip further include a second circuit. The plurality of external terminals further include a plurality of second power supply terminals, which are capable of supplying a second power potential to the second circuit. The terminal arrangement area includes a second area that is farther from the first area when viewed from the first edge, and The plurality of second power terminals are arranged in the second region.

16. The electronic device according to claim 15, The wiring substrate includes: Multiple wiring layers are stacked in the thickness direction of the wiring substrate; as well as Multiple through-hole wirings are formed to penetrate the multiple wiring layers. Among the plurality of wiring layers, a first wiring layer is formed at the position closest to the first surface. The first wiring layer includes a first power plane, which is a conductor pattern electrically connected to the plurality of first power terminals. The plurality of through-hole wiring includes: The first through-hole wiring is positioned overlapping the first power plane and is electrically isolated from the first power plane; and The second via wiring is arranged at a position overlapping with the semiconductor device. The number of first through-hole wirings is less than the number of second through-hole wirings.

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