Wafer level module integration method with heat dissipation structure and module

Abstract

This invention discloses a wafer-level module integration method and module with a heat dissipation structure. The integration method includes the following steps: S10: providing a sub-core, the surface of which has a first metal electrode array composed of first metal electrodes; S20: providing a mother wafer, in which an array of mother cores are formed, the mother cores having a second metal electrode array composed of second metal electrodes; S30: forming metal interconnects covering the second metal electrodes on the surface of the mother wafer, the metal interconnects being interconnected with the second metal electrodes, and simultaneously forming a metal thermally conductive structure on the surface of the mother wafer. The metal thermally conductive structure and the metal interconnects are formed in the same process, located in the same layer, and are insulated from each other. This invention solves the heat problem caused by three-dimensional integrated packaging by introducing a heat dissipation structure into the integration process, improving product performance, especially for high-power products, significantly improving reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and integration technology. Specifically, it relates to a wafer-level module integration method and module with a heat dissipation structure, which is particularly suitable for applications with stringent requirements for interconnect density, heat dissipation and signal integrity, such as high-performance computing and radio frequency front-end modules. Background Technology

[0002] With the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink, and the requirements for integrated circuit packaging technology are also constantly increasing. Existing packaging technologies include ball grid array (BGA), chip scale package (CSP), wafer level package (WLP), 3D packaging, and system in package (SiP).

[0003] As Moore's Law slows down, the three-dimensional integration of chips with different process nodes and functions through advanced packaging technologies has become the mainstream approach to improving system performance. Existing technologies, such as wafer-level fan-out packaging or micro-bump-based chip bonding, while achieving high-density interconnects, face the following challenges: 1. The interconnect and heat dissipation paths are separated, making it difficult for the heat generated by high-power chips to be effectively dissipated through the interconnect structure, resulting in a thermal bottleneck; 2. After bonding alignment, bump connections are formed by reflow soldering. This requires extremely high bonding alignment accuracy and bump coplanarity, and the reflow process may introduce thermal stress. 3. Traditional metal pillars or bumps are used as interconnect and heat conduction structures. The materials and processes for these two are usually separate, resulting in low integration and complex manufacturing processes.

[0004] Therefore, there is an urgent need for a wafer-level module integration method and module with a heat dissipation structure, which can build efficient electrical interconnects and heat conduction paths in situ and synchronously without sacrificing interconnect density and electrical performance, and reduce the precision sensitivity and thermal stress of the bonding process, thereby meeting the reliable integration requirements of next-generation high-power, high-density three-dimensional system chips. Summary of the Invention

[0005] To address the aforementioned problems, the present invention aims to provide a wafer-level module integration method with a heat dissipation structure, comprising the following steps: S10: Provide a sub-core, the surface of which has a first metal electrode array composed of a first metal electrode; S20: Provide a mother wafer, in which an array of mother core particles are formed, and the mother core particles have a second metal electrode array composed of second metal electrodes; S30: A metal interconnect covering a second metal electrode is formed on the surface of the mother wafer. The metal interconnect is interconnected with the second metal electrode. At the same time, a metal thermally conductive structure is formed on the surface of the mother wafer. The metal thermally conductive structure and the metal interconnect are formed in the same process, located in the same layer, and are insulated from each other. S40: A metal pillar is formed at the first metal electrode position corresponding to the sub-core on the metal interconnect line, and a metal thermally conductive layer is continuously stacked on the metal thermally conductive structure. S50: Bond the sub-core and the mother wafer, and the positions of the first metal electrode and the metal pillar of the mother wafer are perpendicular to each other; S60: Introduce a fluid material containing metal between the first metal electrode and the metal pillar, and grow metal on the surface of the first metal electrode and the metal pillar until the first metal electrode and the metal pillar form a conductive connection.

[0006] Optionally, the bonding step includes forming a bonding layer on the surface of the mother wafer in a region other than the second metal electrode, the bonding layer containing a thermally conductive metal material.

[0007] Optionally, the second metal electrode and the metal interconnect are covered by an insulating layer.

[0008] Optionally, a metal pillar and an electrically connected metal interconnect covering the second metal electrode are formed on the mother wafer at the position of the first metal electrode corresponding to the sub-core.

[0009] Optionally, the bonding layer contains a metal thermally conductive material that is encapsulated by the bonding layer, and the bonding layer is any one or a combination of a dielectric layer, a semiconductor crystal, or an organic material.

[0010] Optionally, the bonding layer is aluminum nitride.

[0011] Optionally, the bonding layer has a bonding metal anti-overflow ring around its periphery, and the anti-overflow ring is one or a combination of a dielectric layer, a metal layer, a metal compound, an organic material, and a semiconductor crystal.

[0012] Optionally, a bonding layer is formed on the surface of the sub-core, the bonding layer on the surface of the sub-core being higher than the first metal electrode and exposing the first metal electrode.

[0013] Optionally, step S60 may employ a chemical plating process or a CVD electroplating process.

[0014] Optionally, the step of forming a metal pillar on the surface of the first metal electrode of the core particle is also included.

[0015] A wafer-level module with a heat dissipation structure formed by the above method includes: A master wafer, in which a master core is formed, the master core having a second metal electrode array composed of a second metal electrode; A metal interconnect line covering a second metal electrode is formed, the metal interconnect line being interconnected with the second metal electrode. Simultaneously, a metal thermally conductive structure is formed on the surface of the mother wafer. The metal thermally conductive structure and the metal interconnect line are located in the same layer and are insulated from each other. A metal pillar is formed at the first metal electrode position corresponding to the sub-core on the metal interconnect line, and a metal heat-conducting layer is formed in the metal heat-conducting structure. The core particle has a first metal electrode array composed of a first metal electrode on its surface; A bonding layer is disposed between the mother wafer and the sub-core to bond and fix the two together. The sub-core is bonded to the mother wafer, and the first metal electrode of the sub-core is perpendicular to the position of the metal pillar on the structure of the mother wafer and is interconnected through metal bumps.

[0016] Optionally, the parent wafer is a reconstructed wafer.

[0017] Optionally, the sub-core is located on a reconfigured wafer.

[0018] Optionally, a metal pillar is formed on the surface of the first metal electrode of the sub-core.

[0019] Optionally, the positions of the first metal electrode and the metal pillar of the mother wafer are perpendicularly opposite each other: either the boundary is aligned or the boundary is partially misaligned.

[0020] Optionally, the second metal electrode and the metal interconnect are covered by an insulating layer.

[0021] Optionally, the bonding layer is aluminum nitride.

[0022] Optionally, the bonding layer has a bonding metal anti-overflow ring around its periphery, and the anti-overflow ring is one or a combination of a dielectric layer, a metal layer, a metal compound, an organic material, and a semiconductor crystal.

[0023] The beneficial effects of this invention are: Superior thermal management performance: While building interconnect wiring, a high thermal conductivity vertical structure is integrated in situ, realizing the coordinated design and synchronous manufacturing of electrical interconnect and heat dissipation path, which greatly reduces the junction temperature of high heat flux density cores.

[0024] Process compatibility and simplification: Metal interconnects and metal thermal conductive structures are completed in the same photolithography and electroplating process, while metal pillars and thermal conductive layers are stacked in another synchronous process, reducing process steps and improving integration.

[0025] High bonding tolerance and high reliability: The chemical plating growth method after bonding provides greater tolerance for minor deviations in bonding alignment (as long as the electrode and metal pillar are within the growth region). The metal connection formed by chemical plating is densely packed and is a low-temperature process (typically <90°C), reducing thermal stress.

[0026] Suitable for heterogeneous integration: Sub-chips and mother wafers can independently select the optimal process and be integrated into the system through the high-density, high-reliability interconnect and heat dissipation solution provided by this invention. It is particularly suitable for heterogeneous modules such as radio frequency and optoelectronics. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart of a wafer-level module integration method according to an embodiment of the present invention; Figures 2-7 This is a cross-sectional schematic diagram of a wafer-level module integration method according to an embodiment of the present invention.

[0029] Label Explanation: Sub-core 10; First metal electrode 11; Mother wafer 20; Mother core 21; Second front side of mother core 201; Second back side of mother core 202; Second metal electrode 22; Bonding layer 23; Metal interconnect 31; Metal thermally conductive structure 32; Metal pillar 41; Patterned dielectric layer 44; Metal thermally conductive layer 42; Metal bump 61. Detailed Implementation

[0030] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0031] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. This invention pertains to electrical devices; therefore, connection and interconnection both refer to conductive interconnection. Since the accompanying drawings describe the same device, the same reference numerals denote the same components. The term "chip front" as used herein refers to the side of the wafer used to form the device during chip manufacturing, and "back" refers to the substrate side of the wafer.

[0032] The embodiments will now be described in detail with reference to the accompanying drawings. Figure 1 This invention provides a wafer-level module integration method with a heat dissipation structure, comprising the following steps: Step S10: As Figure 2 As shown, a sub-core 10 is provided, and the surface of the sub-core 10 has a first metal electrode array composed of a first metal electrode.

[0033] refer to Figure 2 The system provides a sub-chip 10 with completed front-end processing. The sub-chip 10 can be, for example, a high-power radio frequency amplifier chip manufactured using a III-V compound semiconductor process. On its active surface, a first metal electrode array consisting of first metal electrodes 11 is formed through a final passivation layer aperture and rewiring process. The material of the first metal electrodes 11 is typically copper or aluminum, but for high-power radio frequency amplifiers it can also be gold, and the surface may have a thin layer (such as titanium nitride or tantalum) to prevent oxidation.

[0034] Simultaneously, in the non-electrode region of the sub-core 10, a polymer bonding layer (such as polyimide PI or benzocyclobutene BCB) can be pre-formed, with a thickness slightly higher than the first metal electrode 11, exposing the top of the electrode. However, it should be noted that this step is optional; alternatively, metal pillars can be formed on the surface of the first metal electrode of the sub-core for communication with the second metal electrode.

[0035] In this embodiment, the sub-chip 10 can also be an uncut chip located on the wafer to be packaged or on the wafer after wafer reconstruction. The wafer can be fabricated using integrated circuit manufacturing technology, such as forming N-type metal-oxide-semiconductor (NMOS) devices and P-type metal-oxide-semiconductor (PMOS) devices on a semiconductor substrate through processes such as deposition and etching. Dielectric layers, metal interconnect structures, and electrodes electrically connected to the metal interconnect junctions are formed on the devices, thereby forming multiple sub-chips 10 in the wafer, and the multiple sub-chips 10 can be chips of the same type or different types.

[0036] The surface of the sub-core 10 has a first metal electrode 11, which is used to realize the electrical connection between the sub-core 10 and other circuits. In this embodiment, the first metal electrode 11 can be a bondpad, or it can be a through-silicon via without a bondpad, a metal interconnect structure, or an exposed metal interconnect lead.

[0037] Step S20: As Figure 3 As shown, a mother wafer 20 is provided, in which an array of mother cores 21 are formed, and the mother cores 21 have a second metal electrode array composed of second metal electrodes 22.

[0038] refer to Figure 3 A master wafer 20 is provided as an integration carrier. Multiple master chips 21 arranged in an array are integrated within the master wafer 20 through through-silicon vias or redistribution layers. The active surface of each master chip 21 is connected to a second metal electrode array composed of second metal electrodes 22 located on the surface of the master wafer 20 through microbumps or redistribution layers.

[0039] In this embodiment, the semiconductor substrate of the mother wafer 20 is a silicon substrate. In other embodiments, the semiconductor substrate of the mother wafer 20 may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium arsenide, glass, or an organic interposer, or other materials. The semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the semiconductor substrate may be suitable for process requirements or easy to integrate. Depending on actual process requirements, the thickness of the mother wafer 20 is from 10 micrometers to 100 micrometers.

[0040] The mother wafer 20 has a plurality of mother cores 21 with second metal electrodes 22 on their surfaces. The mother wafer 20 can be an uncut silicon wafer that has undergone integrated circuit manufacturing, or a reconstructed wafer formed by temporarily bonding multiple mother cores 21 to other carrier wafers. The surface of each mother core 21 has a second metal electrode 22, and the surface with the second metal electrode is the bonding surface. In this embodiment, the second metal electrode 22 can be a bond pad, a through-silicon via without a bond pad, a metal interconnect structure, or an exposed metal interconnect lead. The mother wafer 20 serves to support the plurality of mother cores 21, thereby facilitating subsequent processes and improving their operability; moreover, the temporary bonding method also facilitates the subsequent separation of the mother cores 21 and the mother wafer 20. In this embodiment, the mother wafer 20 is a carrier wafer. Specifically, the carrier substrate 100 may be a semiconductor substrate (e.g., a silicon substrate), an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, a metal wafer, an organic plastic wafer, an inorganic oxide wafer, or a ceramic material wafer.

[0041] In this embodiment, the surface of the mother chip 21 facing away from the bonding surface (not shown) is temporarily bonded to the mother wafer 20 using an adhesive layer. The adhesive layer serves to temporarily bond the mother chip 21 and the mother wafer 20, facilitating subsequent separation of the mother chip 21 and the mother wafer 20. In this embodiment, the adhesive layer is a die-attach film (DAF). Die-attach films are ultra-thin film adhesives used in semiconductor packaging processes to connect semiconductor chips to packaging substrates and chips to chips. They offer high reliability and ease of processing, facilitating the stacking and thinning of semiconductor packaging. In other embodiments, the adhesive layer may also be a dry film, UV adhesive, or thermosetting adhesive. Dry film photoresist is an adhesive photoresist used in semiconductor chip packaging or printed circuit board manufacturing. Its manufacturing process involves coating a solvent-free photoresist onto a polyester substrate, then covering it with a polyethylene film. In use, the polyethylene film is removed, the solvent-free photoresist is pressed onto the substrate, and after exposure and development, a pattern is formed within the dry film photoresist. UV adhesive, also known as ultraviolet light curable adhesive, is a type of adhesive that requires ultraviolet light irradiation to cure. It cures quickly, exhibits high adhesive strength after curing, and is relatively environmentally friendly. Thermosetting adhesive is an adhesive with thermosetting resin as its main component. Thermosetting adhesives have good solvent resistance and weather resistance, cure quickly, and have high adhesive strength. Depending on the viscosity, curing time, and additives, they can be used for bonding to various surfaces.

[0042] The master chip 21 is used as the chip to be integrated in a wafer-level system-on-a-package (WAPS). It should be noted that the wafer-level packaging method in this embodiment is used to achieve heterogeneous integration; therefore, the multiple master chips 21 are chips made of silicon wafers. In other embodiments, the master chip 21 can also be a chip made of other materials. The functions of the multiple master chips 21 can be different. The master chip 21 can be one or more of the following: active components, passive components, microelectromechanical systems (MEMS), optical components, etc. Specifically, the master chip 21 can be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the master chip 21 can also be other functional chips. In this embodiment, the wafer-level system-on-a-package (WAPS) is used to combine multiple master chips 21 with different functions into a single package structure; therefore, the multiple master chips 21 are obtained by dicing multiple wafers of different functional types. In other embodiments, depending on actual process requirements, the functional types of the multiple master chips can also be the same. By integrating multiple sub-cores 10 into the mother wafer 20 and completing the packaging integration process on the mother wafer 20, the packaging structure area can be significantly reduced, manufacturing costs can be reduced, electrical performance can be optimized, and batch manufacturing can be achieved, which can significantly reduce workload and equipment requirements.

[0043] In this embodiment, the mother chip 21 includes a second front surface 201 on which the second metal electrode 22 is formed, and a second back surface 202 opposite to the second front surface 201 of the mother chip, wherein the second front surface 201 exposes the second metal electrode 22. The second back surface 202 of the mother chip refers to the bottom surface of the semiconductor substrate on the side of the mother chip 21 away from the second metal electrode 22.

[0044] Step S30: A metal interconnect 31 covering the second metal electrode 22 is formed on the surface of the mother wafer 20. The metal interconnect 31 is interconnected with the second metal electrode 22. At the same time, a metal thermally conductive structure 32 is formed on the surface of the mother wafer. The metal thermally conductive structure 32 and the metal interconnect 31 are formed in the same process, located in the same layer, and are insulated from each other.

[0045] refer to Figure 4 For ease of explanation, only the corresponding position of one mother core is illustrated in the figure. This step is one of the key innovations of this invention. In a single patterning process, electrical interconnects and dedicated heat dissipation paths are integrated simultaneously, thus solving the problems of separation of interconnects and heat dissipation paths, and discrete processes. On the surface of the mother wafer 20, two functional structures are simultaneously formed through a single patterning metal deposition process: Metal interconnect 31: Its pattern is designed to cover and electrically connect to the second metal electrode 22, thereby leading the pad of the second metal electrode 22 to the corresponding position of the first metal electrode, and can also serve as a horizontal extension wiring for signal, power and ground.

[0046] Metal thermally conductive structure 32: Its pattern design is located on the same metal layer as the metal interconnects 31, but is physically insulated from them. This structure is not a simple planar pattern, but a grid-like or solid pattern pre-planned to cover the projected area of ​​high-power units (such as power amplifiers) in future sub-cores 10, laying the foundation for vertical heat dissipation paths.

[0047] Specific process: Vapor deposition combined with etching can be used, for example, on aluminum materials; or photolithography and vapor deposition can be used, for example, on copper materials; or electroplating or electroless plating can also be used. First, a seed layer (such as Ti / Cu) is deposited on the entire surface of the mother wafer 20. Then, photoresist is spin-coated and exposed to form a mask that simultaneously defines the patterns of the metal interconnects 31 and the metal thermal conductive structure 32. Subsequently, electroplating is performed to thicken the mask (e.g., electroplating copper to 5-10 μm), and finally, the photoresist and the underlying seed layer are removed to obtain the isolated metal structure.

[0048] Step S40: A metal pillar is formed at the first metal electrode position corresponding to the sub-core on the metal interconnect line 31, while a metal thermally conductive layer is continued to be stacked on the metal thermally conductive structure 32.

[0049] refer to Figure 5 Based on the structure formed in step S30, a second patterned metal deposition is performed: In this embodiment, a patterned dielectric layer 44 of dielectric material is first formed, and an opening is reserved at the position where the metal layer is to be formed, that is, an opening is reserved at the predetermined bonding position and the position where it needs to be interconnected with the first metal electrode point.

[0050] On the metal interconnect 31, at the position corresponding to the first metal electrode 11 of the sub-core 10, a metal pillar 41 is grown. The metal pillar 41 can be made of copper, and its height is designed according to the bonding gap, for example, 10-25 μm.

[0051] On the metal thermally conductive structure 32, a metal thermally conductive layer 42 is continuously stacked and grown in the same process steps. In a preferred embodiment, the metal thermally conductive layer 42 and the metal pillar 41 are formed by the same process. The metal thermally conductive layer 42 and the metal pillar 41 are made of the same material and have the same height, thus creating a "thermally conductive block" with the same height as the interconnecting metal pillars before bonding. In other embodiments, since it does not need to achieve electrical interconnection, it may have a different height from the metal pillar 41.

[0052] In this embodiment, the second metal electrode and the metal interconnect are covered by an insulating layer, and a metal thermally conductive structure spans over the metal interconnect for better heat conduction. In another embodiment, the second metal electrode and the metal interconnect are covered by insulation.

[0053] In this embodiment, a metal pillar is formed on the mother wafer at the position of the first metal electrode corresponding to the sub-core, and a metal interconnect covering the second metal electrode is electrically connected.

[0054] In one embodiment, a metal pillar is formed on the mother core wafer at the position of the first metal electrode corresponding to the daughter core, and a metal interconnect covering the second metal electrode is electrically connected.

[0055] In this embodiment, the bonding step includes forming a bonding layer in a non-second metal electrode region on the surface of the mother wafer, the bonding layer containing a metal thermally conductive material; the metal thermally conductive material contained in the bonding layer is encapsulated by the bonding layer, and the bonding layer is any one or a combination of a dielectric layer, a semiconductor crystal, or an organic material.

[0056] In one embodiment, the bonding layer contains a metal thermally conductive material that is encapsulated by the bonding layer, which is any one or a combination of a dielectric layer, a semiconductor crystal, or an organic material.

[0057] In one embodiment, the bonding layer is aluminum nitride.

[0058] In one embodiment, a bonding metal anti-overflow ring is formed around the bonding layer. The anti-overflow ring is one or a combination of a dielectric layer, a metal layer, a metal compound, an organic material, and a semiconductor crystal.

[0059] Step S50: Bond the sub-core and the mother wafer, with the positions of the first metal electrode and the metal pillars of the mother wafer perpendicular to each other.

[0060] refer to Figure 6 In this embodiment, the bonding surface of the mother core 21 is the second front surface 201 of the mother core. In the non-electrode region of the mother wafer 20, a polymer bonding layer 23 (such as polyimide PI or benzocyclobutene BCB) can be pre-formed, creating a gap between the first metal electrode and the metal pillar after bonding. In one embodiment, the upper surface of the metal pillar can be curved during the metal pillar formation step, thus creating a gap after bonding. Furthermore, the first metal electrode can be higher than or recessed from the surface of the daughter core. A metal pillar can be formed on the surface of the first metal electrode, or it can be left unformed.

[0061] The active surface of the sub-core 10 is precisely aligned with the parent wafer 20. The first metal electrode 11 on the sub-core 10 is perpendicularly aligned with the metal pillar 41 on the parent wafer 20. Figure 6The boundaries can be aligned or partially misaligned. Then, mechanical fixation is achieved by thermo-pressing the bonding layer. Due to the presence of the bonding layer 23, there is a controllable, narrow gap (e.g., 1-5 μm) between the top of the first metal electrode 11 and the top of the metal pillar 41.

[0062] In one embodiment, the bonding layer contains a metal thermally conductive material. Specifically, a metal thermally conductive material can be added to the bonding layer, or the metal thermally conductive structure 32 can be formed in the bonding region, for example, between the bonding layers. In other words, the bonding layer is formed on the metal thermally conductive structure on the surface of the mother wafer.

[0063] In one embodiment, a bonding layer is formed on the surface of the sub-core, the bonding layer on the surface of the sub-core being higher than the first metal electrode and exposing the first metal electrode.

[0064] Step S60: Introduce a fluid material containing metal between the first metal electrode and the metal pillar, and grow metal on the surface of the first metal electrode and the metal pillar until the first metal electrode and the metal pillar form a conductive connection.

[0065] In one embodiment, step S60 is performed using a chemical plating process or a CVD electroplating process.

[0066] refer to Figure 7 In this step, since there is a gap between the first metal electrode 11 and the metal pillar 41, selective metal growth can be used to achieve interconnection.

[0067] This step is another key innovation of the present invention. After bonding, vertical interconnects are achieved using a selective deposition process, chemical plating, without the need for photolithography masks.

[0068] Process preparation: The bonded integral structure is immersed in a chemical plating solution. This plating solution can be a chemical copper plating solution or a chemical nickel plating solution. Due to their metallic properties, the surfaces of the first metal electrode 11 of the core 10 and the metal pillars 41 of the mother wafer 20 can serve as catalytically active surfaces.

[0069] Selective growth: Metal ions (such as Cu²⁺) in the electroless plating solution + Reduction deposition occurs only on the catalytically active metal surface (i.e., the exposed tips of the first metal electrode 11 and the metal pillar 41), while deposition does not occur on the insulating bonding layer 23 and the polymer material. In this step, metal continues to grow on the exposed surface of the thermally conductive metal structure, which is beneficial for improving thermal conductivity.

[0070] Bridging and conduction: Metal grows simultaneously from the surfaces of the first metal electrode 11 and the metal pillar 41. Due to the small gap, the metals growing on both sides quickly meet and merge in the gap, eventually forming a complete, low-resistance metal bump 61, which firmly and electrically connects the two. At the same time, the metal thermally conductive structure 32 and the metal thermally conductive layer 42 above it have constructed a low thermal resistance path directly to the interior of the mother wafer 20. Heat can be conducted from the sub-core 10 through the bonding layer 23 (or through a top heat sink that may be formed in the future) to the metal thermally conductive layer 42, and then dissipated through the metal thermally conductive structure 32.

[0071] In an optional embodiment, the following subsequent steps are also included: S70: Debond the mother core 21 and the temporary carrier plate to remove the temporary carrier plate.

[0072] In one embodiment, the debonding process can be one or more of the following: chemical etching, mechanical peeling, mechanical grinding, thermal baking, ultraviolet irradiation, laser ablation, chemical mechanical polishing, and wet peeling, and the appropriate process is selected according to the material of the temporary bonding adhesive layer.

[0073] S80: After removing the temporary carrier board, a through-silicon via and a back-side redistribution layer are fabricated from the second back side 202 of the mother core 21 to form external interconnect pads.

[0074] The mother core 21 and the temporary carrier (corresponding to step S20, where the mother wafer 20 can be an uncut silicon wafer from integrated circuit manufacturing, or a reconstructed wafer formed by temporarily bonding multiple mother cores 21 to other carriers) undergo debonding. This debonding process separates the mother core 21 and the mother wafer 20, removing the mother wafer 20 and the adhesive layer, thus facilitating subsequent electroplating processes. Specifically, the debonding process can be one or more of the following: chemical etching, mechanical stripping, mechanical polishing, thermal baking, ultraviolet irradiation, laser ablation, chemical mechanical polishing, and wet stripping, with the appropriate process selected based on the material of the adhesive layer.

[0075] Metal bumps are formed in the cavity using an electroplating process to electrically connect the first metal electrode 11 and the second metal electrode 22. The metal bumps are in contact with both the first metal electrode 11 and the metal pillar, thus achieving an electrical connection between the first metal electrode 11 and the metal pillar, and consequently, an electrical connection between the sub-core 10 and the mother core 21. The metal bumps can be formed by an electroplating process. Metal bumps formed by electroplating achieve a good filling effect in the cavity, thereby improving the reliability of the electrical connection between the first metal electrode 11 and the metal pillar.

[0076] In this embodiment, the electroplating is electrodeless electroplating. Specifically, the bonded master core 21 and the device wafer are placed in a solution containing metal ions (e.g., electroless silver plating, nickel plating, copper plating, etc.). Based on the principle of redox reaction, a strong reducing agent is used to reduce the metal ions to metal, which is then deposited on the surface of the first metal electrode 11 or the metal pillar to form a metal coating. After a reaction time, the metal coating fills the cavity, thereby forming the metal bump. Alternatively, gaseous fluid materials can also be used for electroless plating.

[0077] The material of the metal bump includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.

[0078] Specifically, the metal bump is a solder joint. After forming the metal bump, a dielectric layer encapsulation structure covering the sub-core 10 is formed on the mother wafer 20, thereby filling the gaps in the entire structure, improving mechanical strength, and forming an encapsulation. The via interconnect structure is formed in the dielectric layer encapsulation structure. Through the via interconnect structure, the metal pillars of the mother core 20 extend from the side where the back of the sub-core is located to the metal pillars of the mother core 20, realizing the interconnection between the metal pillars on the front of the mother core 20 and the outside, and electrical connection with other circuits. For example, metal pads can also be formed on the encapsulation structure. Moreover, since the sub-core 10 and the mother core 21 are electrically connected through the metal bump, the mother core 21 is electrically connected to other circuits through the metal bump, the interconnect structure formed in the sub-core 10, and the via interconnect structure.

[0079] In this embodiment, the semiconductor substrate of the device wafer is a silicon substrate, and the via interconnect structure is formed using through-silicon via (TSV) technology. In other embodiments, the via interconnect structure can also be formed using other processes.

[0080] In this embodiment, the material of the through-hole interconnect structure is copper. In other embodiments, the material of the through-hole interconnect structure may also be conductive materials such as aluminum, tungsten, and titanium.

[0081] Accordingly, the present invention also provides a wafer-level module with a heat dissipation structure.

[0082] A mother wafer 20, in which a mother core 21 is formed, the mother core 21 having a second metal electrode array composed of a second metal electrode 11; A metal interconnect 31 is formed covering the second metal electrode 22, and the metal interconnect 31 is interconnected with the second metal electrode 22. At the same time, a metal thermally conductive structure 32 is formed on the surface of the mother wafer 20. The metal thermally conductive structure 32 and the metal interconnect 31 are located in the same layer and are insulated from each other. A metal pillar 41 is formed on the metal interconnect 31 at the position of the first metal electrode 11 corresponding to the sub-core 10, and a metal heat-conducting layer is formed on the metal heat-conducting structure 32. The core particle 10 has a first metal electrode array composed of first metal electrodes 11 on its surface; A bonding layer is disposed between the mother wafer 20 and the sub-core 10 to bond and fix the two together. The sub-core 10 is bonded to the mother wafer 20, and the first metal electrode 11 of the sub-core 10 is perpendicularly opposite to the metal pillar 41 on the structure of the mother wafer 10, and is interconnected through metal bumps 61.

[0083] Optionally, the mother wafer 20 is a reconstructed wafer.

[0084] Optionally, the sub-core 10 is located on a reconfigured wafer.

[0085] Optionally, a metal pillar 41 is formed on the surface of the first metal electrode 11 of the sub-core 10.

[0086] Optionally, the first metal electrode 11 of the sub-core 10 and the metal pillar 41 on the mother wafer 20 are perpendicularly opposite each other, either with their boundaries aligned or with their boundaries partially misaligned.

[0087] The mother wafer 20 serves as the carrier, along with its internal mother core 21. Sub-cores 10 are flip-chip mounted via bonding layer 23. A vertical interconnect structure for electrical signal transmission is constructed from metal interconnects 31, metal pillars 41, and metal bumps 61 connected in series. An integrated heat dissipation structure, manufactured concurrently with and isolated from the electrical interconnect structure, consists of a metal thermally conductive structure 32 and a metal thermally conductive layer 42 thereon, providing an efficient vertical heat dissipation channel for the sub-cores 10.

[0088] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A wafer-level module integration method with a heat dissipation structure, characterized in that, Including the following steps: S10: Provide a sub-core, the surface of which has a first metal electrode array composed of a first metal electrode; S20: Provide a mother wafer, in which an array of mother core particles are formed, and the mother core particles have a second metal electrode array composed of second metal electrodes; S30: A metal interconnect covering a second metal electrode is formed on the surface of the mother wafer. The metal interconnect is interconnected with the second metal electrode. At the same time, a metal thermally conductive structure is formed on the surface of the mother wafer. The metal thermally conductive structure and the metal interconnect are formed in the same process, located in the same layer, and are insulated from each other. S40: A metal pillar is formed at the first metal electrode position corresponding to the sub-core on the metal interconnect line, and a metal thermally conductive layer is continuously stacked on the metal thermally conductive structure. S50: Bond the sub-core and the mother wafer, and the positions of the first metal electrode and the metal pillar of the mother wafer are perpendicular to each other; S60: Introduce a fluid material containing metal between the first metal electrode and the metal pillar, and grow metal on the surface of the first metal electrode and the metal pillar until the first metal electrode and the metal pillar form a conductive connection.

2. The wafer-level module integration method as described in claim 1, characterized in that, The bonding step includes forming a bonding layer on the surface of the mother wafer in a region other than the second metal electrode, the bonding layer containing a thermally conductive metal material.

3. The wafer-level module integration method as described in claim 1, characterized in that, The second metal electrode and the metal interconnect are covered by an insulating layer.

4. The wafer-level module integration method as described in claim 1, characterized in that, Metal pillars are formed on the mother wafer at the position of the first metal electrode corresponding to the sub-core, and metal interconnects covering the second metal electrode are electrically connected.

5. The wafer-level module integration method as described in claim 2, characterized in that, The bonding layer contains a metal thermally conductive material that is encapsulated within it. The bonding layer can be any one or a combination of a dielectric layer, a semiconductor crystal, or an organic material.

6. The wafer-level module integration method as described in claim 5, characterized in that, The bonding layer is aluminum nitride.

7. The wafer-level module integration method as described in claim 6, characterized in that, The bonding layer is surrounded by a bonding metal anti-overflow ring, which is one or a combination of dielectric layer, metal layer, metal compound, organic material, and semiconductor crystal.

8. The wafer-level module integration method as described in claim 1, characterized in that, A bonding layer is formed on the surface of the sub-core, the bonding layer on the surface of the sub-core being higher than the first metal electrode and exposing the first metal electrode.

9. The wafer-level module integration method as described in claim 1, characterized in that, Step S60 involves using either chemical plating or CVD electroplating.

10. The wafer-level module integration method as described in claim 1, characterized in that, It also includes the step of forming a metal pillar on the surface of the first metal electrode of the core particle.

11. A wafer-level module with a heat dissipation structure formed by the method according to any one of claims 1 to 10, characterized in that, include: A master wafer, in which a master core is formed, the master core having a second metal electrode array composed of a second metal electrode; A metal interconnect line covering a second metal electrode is formed, the metal interconnect line being interconnected with the second metal electrode. Simultaneously, a metal thermally conductive structure is formed on the surface of the mother wafer. The metal thermally conductive structure and the metal interconnect line are located in the same layer and are insulated from each other. A metal pillar is formed at the first metal electrode position corresponding to the sub-core on the metal interconnect line, and a metal heat-conducting layer is formed in the metal heat-conducting structure. The core particle has a first metal electrode array composed of a first metal electrode on its surface; A bonding layer is disposed between the mother wafer and the sub-core to bond and fix the two together. The sub-core is bonded to the mother wafer, and the first metal electrode of the sub-core is perpendicular to the position of the metal pillar on the structure of the mother wafer and is interconnected through metal bumps.

12. The wafer-level module as described in claim 11, characterized in that, The mother wafer is a reconstructed wafer.

13. The wafer-level module as described in claim 11, characterized in that, The sub-core is located on a reconstructed wafer.

14. The wafer-level module as described in claim 11, characterized in that, Metal pillars are formed on the surface of the first metal electrode of the core particle.

15. The wafer-level module as described in claim 11, characterized in that, The positions of the first metal electrode and the metal pillar of the mother wafer are perpendicular to each other, either with the boundary aligned or with the boundary partially misaligned.

16. The wafer-level module as described in claim 11, characterized in that, The second metal electrode and the metal interconnect are covered by an insulating layer.

17. The wafer-level module as described in claim 11, characterized in that, The bonding layer is aluminum nitride.

18. The wafer-level module as described in claim 11, characterized in that, The bonding layer is surrounded by a bonding metal anti-overflow ring, which is one or a combination of dielectric layer, metal layer, metal compound, organic material, and semiconductor crystal.

Images