Semiconductor device

Abstract

A semiconductor device includes: a first semiconductor die including a first pad and a first adhesive layer covering an upper portion of a sidewall of the first pad; a second semiconductor die including a second pad and a second adhesive layer covering a lower portion of a sidewall of the second pad; and a first protective layer between the first pad and the second adhesive layer. The average die size of each of the first and second pads ranges from 25 nm to 70 nm. The second pad may be on the first pad, the top surface of the first pad including a portion exposed by the second pad, and the second adhesive layer may be on the exposed portion of the first pad. The first protective layer may be between the exposed portion of the first pad and the second adhesive layer.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0186411, filed on December 13, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices. Background Technology

[0004] Semiconductor packages are configured to facilitate the use of integrated circuit chips as components in electronic products. Traditionally, a semiconductor package includes a printed circuit board (PCB) and a semiconductor die mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, much research is being conducted to improve the reliability of semiconductor packages and reduce their size. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide semiconductor devices with improved electrical and / or reliability characteristics.

[0006] Some exemplary embodiments of the present invention provide methods for manufacturing semiconductor devices with improved electrical and / or reliability characteristics.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first semiconductor die including a first pad and a first adhesive layer, the first adhesive layer covering an upper portion of a sidewall of the first pad; a second semiconductor die including a second pad and a second adhesive layer, the second adhesive layer covering a lower portion of a sidewall of the second pad; and a first protective layer between the first pad and the second adhesive layer, wherein each of the first pad and the second pad has an average die size of 25 nm to 70 nm, the second pad is on the first pad, the top surface of the first pad includes an exposed top surface portion exposed by the second pad, the second adhesive layer is on the exposed top surface portion of the first pad, and the first protective layer is between the exposed top surface portion of the first pad and the second adhesive layer.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first semiconductor die; a second semiconductor die on the first semiconductor die; and a first protective layer between the first semiconductor die and the second semiconductor die, wherein the first semiconductor die includes a first substrate, a first interconnect pattern on the first substrate, a first via on the first interconnect pattern, a first insulating layer on the first substrate and covering the first interconnect pattern and the first via, a first adhesive layer on the first insulating layer, and a first pad penetrating the first adhesive layer and the first insulating layer and connected to the first via; the second semiconductor die includes a second substrate, and a first insulating layer on the second substrate. The second interconnect pattern, the second via on the second interconnect pattern, the second insulating layer on the second substrate and covering the second interconnect pattern and the second via, the second adhesive layer on the second insulating layer, and the second pad penetrating the second adhesive layer and the second insulating layer and connected to the second via, the average grain size of each of the first pad and the second pad being in the range of 25 nm to 70 nm, the second pad being on the first pad, and the top surface of the first pad including an exposed top surface portion exposed by the second pad, the second adhesive layer being on the exposed top surface portion of the first pad, and the first protective layer being between the exposed top surface portion of the first pad and the second adhesive layer.

[0009] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a first semiconductor die by forming a first substrate including a first circuit layer; forming a first interconnect pattern on a top surface of the first substrate to electrically connect to the first circuit layer; forming a first insulating layer on the top surface of the first substrate to cover the first interconnect pattern; forming a first adhesive layer on the first insulating layer; forming a first opening using a first mask pattern to penetrate a portion of the first adhesive layer and the first insulating layer; forming a second opening using a second mask pattern to penetrate a portion of the first insulating layer 110 and expose the first interconnect pattern, such that the second opening includes a first portion and a second portion, a first lower portion being the lower portion of the second opening and exposing the top surface of the first interconnect pattern, and a first upper portion being the upper portion of the second opening; forming a first seed pattern and a first protective seed pattern to conformally cover the inner sidewall of the second opening to form a third opening, the third opening including a second lower portion and a second upper portion; forming a preliminary first via in the second lower portion of the third opening and forming a preliminary first pad in the second upper portion of the third opening; and forming a second semiconductor die by forming a second substrate including a second circuit layer. A first semiconductor die is formed with a second interconnect pattern on the bottom surface of a second substrate for electrical connection to a second circuit layer. A second insulating layer is formed on the bottom surface of the second substrate to cover the second interconnect pattern. A second adhesive layer is formed below the second insulating layer. A fourth opening is formed using a third mask pattern to penetrate a portion of the second adhesive layer and the second insulating layer. A fifth opening is formed using a fourth mask pattern to penetrate a portion of the second insulating layer and expose the second interconnect pattern, such that the fifth opening includes a lower portion and an upper portion. A third lower portion is the lower portion of the second opening and exposes the top surface of the second interconnect pattern. A third upper portion is the upper portion of the second opening. A second seed pattern is formed to conformally cover the inner sidewall of the fifth opening to form a sixth opening, which includes a fourth lower portion and a fourth upper portion. A preliminary second via is formed in the fourth lower portion of the sixth opening, and a preliminary second pad is formed in the fourth upper portion of the sixth opening. A second semiconductor die is attached to a first semiconductor die such that the top surface of the first adhesive layer contacts the bottom surface of the second adhesive layer. An annealing process is performed to form a protective layer between a portion of the top surface of the first pad exposed by the second pad and the second adhesive layer.

[0010] Forming the initial first via and the initial first pad can result in the initial first via and the initial first pad having an average grain size ranging from 25 nm to 70 nm.

[0011] The second opening may have a stepped structure at the boundary between the first lower part and the first upper part of the second opening, and the first lower part and the first upper part of the second opening may have different widths from each other in a first direction parallel to the top surface of the first adhesive layer. Attached Figure Description

[0012] Figure 1This is a cross-sectional view illustrating an example embodiment of a semiconductor device according to the present invention.

[0013] Figure 2A , Figure 2C and Figure 2E Each of these presents an example embodiment based on the concept of the present invention. Figure 1 An enlarged cross-sectional view of part "A" in the diagram.

[0014] Figure 2B , Figure 2D and Figure 2F They are Figure 2A , Figure 2C and Figure 2E The diagram shows a plan view of the semiconductor device, which was observed when the semiconductor device was cut at the level of the bottom surface of the second adhesive layer.

[0015] Figures 3 to 13 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention. Detailed Implementation

[0016] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate some exemplary embodiments.

[0017] As used herein, expressions such as “one of…”, “one or more of…”, “any one of…”, and “at least one of…” following a list of elements modify the entire list of elements, not the individual elements within the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0018] Although the terms “identical,” “equal,” or “the same” are used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is identical to the other element within a range of expected manufacturing or operational tolerances (e.g., ±10%).

[0019] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, the associated numerical values ​​are intended to include manufacturing or operational tolerances (e.g., ±10%) near said numerical values. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended not to require precision in the geometry, but rather a tolerance for the shape within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “approximately” or “substantially,” it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical values ​​or shapes.

[0020] Figure 1 This is a cross-sectional view illustrating an example embodiment of a semiconductor device according to the present invention. Figure 2A , Figure 2C and Figure 2E Each illustrates an example embodiment of the concept according to the present invention. Figure 1 An enlarged cross-sectional view of part "A" in the diagram. Figure 2B , Figure 2D and Figure 2F They are Figure 2A , Figure 2C and Figure 2E The diagram shows a plan view of the semiconductor device, which is observed when the semiconductor device is cut at the level of the bottom surface of the second adhesive layer.

[0021] refer to Figure 1 Semiconductor device 1 may include a first semiconductor die CH1 and a second semiconductor die CH2.

[0022] The first semiconductor die CH1 may include a first substrate 100, a first interconnect pattern 101, a first insulating layer 110, a first adhesive layer 140, a first via 120, and a first pad 130.

[0023] The first substrate 100 may extend in a first direction D1 parallel to the top surface 100a of the first substrate 100. In this specification, the first direction D1 may be parallel to the top surface 100a of the first substrate 100, and the second direction D2 may be a vertical direction D2 perpendicular to the top surface 100a of the first substrate 100. For example, the first direction D1 and the second direction D2 may be orthogonal to each other. Furthermore, the first direction D1 may be parallel to the top surface 140a of the first adhesive layer 140 (described below), and the second direction D2 may be perpendicular to the top surface 140a of the first adhesive layer 140.

[0024] The first substrate 100 may include a semiconductor substrate comprising a semiconductor material. The first substrate 100 may be formed of at least one of, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs), or may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs).

[0025] The first substrate 100 may include a first circuit layer SE1. Although not shown, the first circuit layer SE1 may include transistors and may also include a plurality of circuit interconnects and a plurality of contact plugs connected to the transistors. As another example, the first circuit layer SE1 may include logic circuitry or memory circuitry. The first circuit layer SE1 may be connected to a first interconnect pattern 101, which will be described below. Although not shown, the first substrate 100 may also include a plurality of circuit interconnects connecting the first circuit layer SE1 to the first interconnect pattern 101.

[0026] A first interconnect pattern 101 may be disposed on the top surface 100a of the first substrate 100. In an example embodiment, a plurality of first interconnect patterns 101 may be disposed. Each of the first interconnect patterns 101 may be electrically connected to a corresponding first circuit layer SE1 of the first substrate 100. Although not shown, an additional insulating layer and additional circuit interconnects may be disposed between the first interconnect pattern 101 and the first substrate 100. The first interconnect pattern 101 may comprise at least one of a metallic material or a conductive material (e.g., copper).

[0027] A first insulating layer 110 may be disposed on a first substrate 100. The first insulating layer 110 may cover a first interconnect pattern 101. In an example embodiment, unlike the illustrated example, the first insulating layer 110 may include multiple insulating layers. The first insulating layer 110 may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, and / or low-k dielectric materials).

[0028] A first via 120 may be disposed on a first interconnect pattern 101. A first via 120 may be disposed in a first insulating layer 110. In an example embodiment, a plurality of first vias 120 may be disposed. Each of the first vias 120 may be connected to a corresponding first interconnect pattern in the first interconnect pattern 101. Each of the first vias 120 may be electrically connected, through a corresponding first interconnect pattern in the first interconnect pattern 101, to a corresponding first circuit layer SE1 disposed in the first substrate 100.

[0029] The first adhesive layer 140 may be disposed on the first insulating layer 110. In an example embodiment, the first adhesive layer 140 may be formed of or comprise silicon oxide or silicon carbonitride.

[0030] A first pad 130 may be disposed on a first via 120. The first pad 130 may penetrate a portion of the first adhesive layer 140 and the first insulating layer 110. In an example embodiment, multiple first pads 130 may be disposed. Each of the first pads 130 may be connected to a corresponding first via in the first via 120. Each of the first pads 130 may be electrically connected to a corresponding first circuit layer in the first circuit layer SE1 via the corresponding first via in the first via 120.

[0031] The second semiconductor die CH2 may include a second substrate 200, a second interconnect pattern 201, a second insulating layer 210, a second adhesive layer 240, a second via 220, and a second pad 230.

[0032] The second substrate 200 may extend in the first direction D1. The second substrate 200 may include a semiconductor substrate comprising a semiconductor material. The second substrate 200 may be formed of at least one of, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs), or may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs).

[0033] The second substrate 200 may include a second circuit layer SE2. Although not shown, the second circuit layer SE2 may include transistors and may also include a plurality of circuit interconnects and a plurality of contact plugs connected to the transistors. As another example, the second circuit layer SE2 may include logic circuitry or memory circuitry. The second circuit layer SE2 may be connected to a second interconnect pattern 201, which will be described below. Although not shown, the second substrate 200 may also include a plurality of circuit interconnects connecting the second circuit layer SE2 to the second interconnect pattern 201.

[0034] The second interconnect pattern 201 may be disposed on the bottom surface of the second substrate 200. In an example embodiment, a plurality of second interconnect patterns 201 may be disposed. Each of the second interconnect patterns 201 may be electrically connected to a corresponding second circuit layer SE2 of the second substrate 200. Although not shown, an additional insulating layer and additional circuit interconnects may be disposed between the second interconnect patterns 201 and the second substrate 200. The second interconnect pattern 201 may comprise at least one of a metallic material or a conductive material (e.g., copper).

[0035] The second insulating layer 210 may be disposed on the bottom surface of the second substrate 200. The second insulating layer 210 may cover the second interconnect pattern 201. In an example embodiment, unlike the example shown, the second insulating layer 210 may include multiple insulating layers. The second insulating layer 210 may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, and / or low-k dielectric materials).

[0036] The second via 220 can be disposed on the second interconnect pattern 201. The second via 220 can be disposed in the second insulating layer 210. In an example embodiment, a plurality of second vias 220 can be disposed. Each of the second vias 220 can be connected to a corresponding second interconnect pattern in the second interconnect pattern 201. Each of the second vias 220 can be electrically connected through a corresponding second interconnect pattern in the second interconnect pattern 201 to a corresponding second circuit layer SE2 disposed in the second substrate 200.

[0037] The second adhesive layer 240 may be disposed on the second insulating layer 210. The second adhesive layer 240 may be formed of silicon oxide or silicon carbonitride, or may include silicon oxide or silicon carbonitride.

[0038] The second pad 230 may be disposed on the second via 220. The second pad 230 may penetrate a portion of the second adhesive layer 240 and the second insulating layer 210. In an example embodiment, multiple second pads 230 may be disposed. Each of the second pads 230 may be connected to a corresponding second via in the second via 220. Each of the second pads 230 may be electrically connected to a corresponding second circuit layer SE2 through a corresponding second via in the second via 220.

[0039] refer to Figure 2A The first adhesive layer 140 of the first semiconductor die CH1 can contact the second adhesive layer 240 of the second semiconductor die CH2. Specifically, the top surface 140a of the first adhesive layer 140 can contact the bottom surface 240b of the second adhesive layer 240. Furthermore, the first pad 130 can contact the second pad 230. (See reference...) Figures 2A to 2F Some exemplary embodiments of the inventive concept are described in more detail below.

[0040] refer to Figure 2A and Figure 2B Semiconductor device 1 may have a hybrid bonding structure. The uppermost part of the first pad 130 may contact the lowermost part of the second pad 230, and the top surface 140a of the first adhesive layer 140 may contact the bottom surface 240b of the second adhesive layer 240.

[0041] The first via 120 may include a first via seed pattern 120a and a first via conductive pattern 120b. The first via conductive pattern 120b may be disposed on the first via seed pattern 120a.

[0042] The first pad 130 may include a first pad seed pattern 130a and a first pad conductive pattern 130b. The first pad conductive pattern 130b may be disposed on the first pad seed pattern 130a.

[0043] The average grain size of the first via 120 and the first pad 130 can range from 25 nm to 70 nm.

[0044] The second via 220 may include a second via seed pattern 220a and a second via conductive pattern 220b. The second via conductive pattern 220b may be disposed on the second via seed pattern 220a.

[0045] The second pad 230 may include a second pad seed pattern 230a and a second pad conductive pattern 230b. The second pad conductive pattern 230b may be disposed on the second pad seed pattern 230a.

[0046] The average grain size of the second via 220 and the second pad 230 can range from 25 nm to 70 nm.

[0047] The first via seed pattern 120a, the first via conductive pattern 120b, the first pad seed pattern 130a, the first pad conductive pattern 130b, the second via seed pattern 220a, the second via conductive pattern 220b, the second pad seed pattern 230a, and the second pad conductive pattern 230b may comprise the same or substantially similar materials. In an example embodiment, the first via seed pattern 120a, the first via conductive pattern 120b, the first pad seed pattern 130a, the first pad conductive pattern 130b, the second via seed pattern 220a, the second via conductive pattern 220b, the second pad seed pattern 230a, and the second pad conductive pattern 230b may be formed of or comprise a metallic material (e.g., copper (Cu)).

[0048] The first pad 130 may have a first width W1 in the first direction D1. The first width W1 may increase as the distance from the top surface 100a of the substrate 100 in the second direction D2 increases. In other words, the first width W1 may decrease as the distance from the top surface 140a of the first adhesive layer 140 increases (e.g., in the direction opposite to the second direction D2). The first width W1 may change continuously as the distance from the top surface 100a of the substrate 100 in the second direction D2 increases. The first width W1 may have a maximum value at the very top (e.g., at the highest level) of the first pad 130.

[0049] The second pad 230 may have a second width W2 in the first direction D1. The second width W2 may decrease as the distance from the top surface 100a of the substrate 100 in the second direction D2 increases. In other words, the second width W2 may decrease as the distance from the top surface 140a of the first adhesive layer 140 increases (e.g., in the second direction D2). The second width W2 may change continuously as the distance from the top surface 100a of the substrate 100 in the second direction D2 increases. The second width W2 may have a maximum value at the lowermost part of the second pad 230 (e.g., at the lowest horizontal level).

[0050] The first width W1 of the first pad 130 may be different from the second width W2 of the second pad 230. In an example embodiment, the first width W1 may be greater than the second width W2. In an example embodiment, the first width W1 at the uppermost part of the first pad 130 may be greater than the second width W2 at the lowermost part of the second pad 230.

[0051] In an example embodiment, the maximum value of the first width W1 of the first pad 130 can range from 400nm to 600nm. The maximum value of the second width W2 of the second pad 230 can be 0.6 to 0.8 times the maximum value of the first width W1. In an example embodiment, the maximum value of the second width W2 can range from 240nm to 320nm, 360nm to 480nm, or 240nm to 480nm.

[0052] The sidewalls SW1 of the first pad 130 and SW2 of the second pad 230 may be spaced apart from each other in the first direction D1. The sidewalls SW1 and SW2 of the first pad 130 may have profiles opposite to each other. For example, the sidewall SW1 of the first pad 130 may have a shape that is inclined outwards in the first direction D1 relative to the normal NL perpendicular to the top surface 100a of the substrate 100. The sidewall SW2 of the second pad 230 may have a shape that is inclined inwards in the first direction D1 relative to the normal NL.

[0053] The sidewall SW1 of the first pad 130 may be tilted at a first angle 10 relative to the top surface 140a of the first adhesive layer 140. The sidewall SW2 of the second pad 230 may be tilted at a second angle 20 relative to the top surface 140a of the first adhesive layer 140. In an example embodiment, the first angle 10 and the second angle 20 may be obtuse angles.

[0054] The first semiconductor die CH1 and the second semiconductor die CH2 can be joined to each other via a first pad 130, a second pad 230, a first adhesive layer 140, and a second adhesive layer 240. For example, the second pad 230 can be disposed on the first pad 130. Furthermore, the second adhesive layer 240 can be disposed on the first adhesive layer 140. The first pad 130 can contact the second pad 230. The first adhesive layer 140 can contact the second adhesive layer 240. When viewed in plan view, the center C1 of the first pad 130 and the center of the second pad 230 can vertically overlap each other (e.g., in the second direction D2). The entire second pad 230 can vertically overlap the first pad 130.

[0055] The first pad 130 has a top surface exposed, not covered by the second pad 230. A second adhesive layer 240 may be disposed on the exposed top surface of the first pad 130. A first protective layer 150 may be located between the exposed top surface of the first pad 130 and the second adhesive layer 240. When viewed in plan view, the first protective layer 150 may be symmetrically disposed in a first direction D1. The first protective layer 150 may be positioned at a height similar to or the same as the boundary between the first adhesive layer 140 and the second adhesive layer 240. The first pad 130 may be spaced apart from the second adhesive layer 240, and the first protective layer 150 may be located between the first pad 130 and the second adhesive layer 240.

[0056] The first protective layer 150 may include manganese (Mn). In an example embodiment, the first protective layer 150 may include manganese oxide. Manganese oxide may include, for example, MnO, Mn3O4, Mn2O3, MnO2, MnO3, or Mn2O7.

[0057] Figure 2C and Figure 2D It shows the relationship with Figure 2A and Figure 2B These are different example embodiments from the previous examples. For the sake of brevity, the elements previously described can be identified by the same reference numerals and will not be repeated.

[0058] refer to Figure 2C and Figure 2DThe first semiconductor die CH1 and the second semiconductor die CH2 can be bonded to each other. For example, a second pad 230 can be disposed on the first pad 130. Furthermore, a second adhesive layer 240 can be disposed on the first adhesive layer 140. The first pad 130 can contact the second pad 230. The first adhesive layer 140 can contact the second adhesive layer 240. When viewed in plan view, the center C1 of the first pad 130 and the center C2 of the second pad 230 can be spaced apart from each other in the first direction D1. That is, the center C1 of the first pad 130 may not be vertically aligned with the center C2 of the second pad 230. The entire second pad 230 can vertically overlap the first pad 130.

[0059] The first pad 130 has a top surface exposed, not covered by the second pad 230. A second adhesive layer 240 may be disposed on the exposed top surface of the first pad 130. A first protective layer 150 may be located between the exposed top surface of the first pad 130 and the second adhesive layer 240. When viewed in plan view, the first protective layer 150 may be asymmetrically disposed in the first direction D1.

[0060] Figure 2E and Figure 2F It shows the relationship with Figures 2A to 2D These are different example embodiments from the previous examples. For the sake of brevity, the elements previously described can be identified by the same reference numerals and will not be repeated.

[0061] refer to Figure 2E and Figure 2F The first semiconductor die CH1 and the second semiconductor die CH2 can be bonded to each other. For example, a second pad 230 can be disposed on the first pad 130. Furthermore, a second adhesive layer 240 can be disposed on the first adhesive layer 140. The first pad 130 can partially contact the second pad 230. The first adhesive layer 140 can contact the second adhesive layer 240. When viewed in plan view, the center C1 of the first pad 130 and the center of the second pad 230 can be spaced apart from each other in a first direction D1. The centers of the first pad 130 and the second pad 230 may not be vertically aligned. A portion of the first pad 130 and a portion of the second pad 230 can vertically overlap each other.

[0062] The first pad 130 has a top surface that is exposed and not covered by the second pad 230. The second adhesive layer 240 may be disposed on the exposed top surface of the first pad 130 that is not covered by the second pad 230. The first protective layer 150 may be located between the exposed top surface of the first pad 130 that is not covered by the second pad 230 and the second adhesive layer 240.

[0063] The second pad 230 may have a bottom surface exposed by the first pad 130. A first adhesive layer 140 may be disposed on the exposed bottom surface of the second pad 230 exposed by the first pad 130. A second protective layer 250 may be located between the exposed bottom surface of the second pad 230 exposed by the first pad 130 and the first adhesive layer 140. The second pad 230 may be spaced apart from the first adhesive layer 140, and the second protective layer 250 may be located between the second pad 230 and the first adhesive layer 140.

[0064] The second protective layer 250 may include manganese (Mn). In an example embodiment, the second protective layer 250 may include manganese oxide. Manganese oxide may include, for example, MnO, Mn3O4, Mn2O3, MnO2, MnO3, or Mn2O7. In an example embodiment, the second protective layer 250 may include a material that is the same as or substantially similar to the first protective layer 150.

[0065] According to an exemplary embodiment of the present invention, in the bonding structure between the first semiconductor die CH1 and the second semiconductor die CH2, a first protective layer 150 containing manganese oxide may be located between the first pad 130 and the second adhesive layer 240. Furthermore, a second protective layer 250 containing manganese oxide may be located between the second pad 230 and the first adhesive layer 140. Since the first protective layer 150 or the second protective layer 250 containing manganese oxide is disposed at the interface between the first conductive pad 130 or the second conductive pad 230 and the first adhesive layer 140 or the second adhesive layer 240, the adhesive strength between the first conductive pad 130 or the second conductive pad 230 and the first adhesive layer 140 or the second adhesive layer 240 can be improved. Furthermore, the average grain size of all the first via 120, the first pad 130, the second via 220, and the second pad 230 can range from 25 nm to 70 nm. When the average grain size is within the aforementioned range, it is possible to prevent or stop the diffusion of manganese (Mn) included in the first protective layer 150 or the second protective layer 250 to the bonding interface between the first pad 130 and the second pad 230. Accordingly, the first protective layer 150 or the second protective layer 250 containing manganese oxide can be locally configured as an interface element between the first conductive pad 130 or the second conductive pad 230 and the first adhesive layer 140 or the second adhesive layer 240. That is, manganese will not diffuse into the region between the first conductive pad 130 and the second conductive pad 230 that are bonded to each other. Therefore, a semiconductor device with improved electrical characteristics and / or reliability characteristics can be provided.

[0066] Figures 3 to 13 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention. Specifically, Figures 3 to 7 It shows Figure 1 Enlarged cross-sectional view of the middle part "B". Figure 8 and Figure 9 This is a diagram illustrating a hybrid bonding process according to an example embodiment of the concept of the present invention. Figures 10 to 13 This is a diagram illustrating a hybrid bonding process according to another exemplary embodiment of the concept of the present invention. In the following, reference will be made to... Figure 1 and Figures 3 to 13 Methods for manufacturing semiconductor devices according to some exemplary embodiments of the present invention will be described in more detail. However, repeated descriptions will be omitted.

[0067] refer to Figure 1 and Figure 3 A first substrate 100 including a first circuit layer SE1 may be provided. A first interconnect pattern 101 electrically connected to the first circuit layer SE1 may be formed on the top surface 100a of the first substrate 100. In an example embodiment, the formation of the first interconnect pattern 101 may include forming a first interconnect layer (not shown) and patterning the first interconnect layer.

[0068] A first insulating layer 110 may be formed on a first substrate 100 to cover a first interconnect pattern 101. Unlike the illustrated structure, the first insulating layer 110 may comprise a single insulating layer or may comprise multiple insulating layers. A first adhesive layer 140 may be formed on the first insulating layer 110. The first insulating layer 110 and the first adhesive layer 140 may be formed using a layer forming method (e.g., chemical vapor deposition (CVD) or physical vapor deposition (PVD)).

[0069] refer to Figure 4 A first opening OP1 can be formed to penetrate a portion of the first adhesive layer 140 and the first insulating layer 110. The first opening OP1 can be configured to partially penetrate the upper portion of the first insulating layer 110. In an example embodiment, forming the first opening OP1 may include: forming a first mask pattern (not shown) on the first adhesive layer 140; performing a first etching process using the first mask pattern as an etching mask; and removing the first mask pattern. The first opening OP1 can be formed to vertically overlap with the first interconnect pattern 101.

[0070] refer to Figure 5 The second opening OP2 can be formed to penetrate a portion of the first insulating layer 110 and expose the first interconnect pattern 101. In an example embodiment, forming the second opening OP2 may include: forming a second mask pattern (not shown) on the first adhesive layer 140; performing a second etching process using the second mask pattern as an etching mask; and removing the second mask pattern. In an example embodiment, the second etching process may include an anisotropic etching process.

[0071] The second opening OP2 may include a first part OP2a and a second part OP2b. The first part OP2a of the second opening OP2 may be a reference formed therein. Figures 2A to 2C The first via 120 is described in part. The first portion OP2a can be formed to expose a portion of the top surface of the first interconnect pattern 101. The second portion OP2b of the second opening OP2 can be formed therein as a reference. Figures 2A to 2C The first pad 130 is described.

[0072] The second opening OP2 may have a stepped structure at the boundary between the first part OP2a and the second part OP2b. The first part OP2a and the second part OP2b may have different widths in the first direction D1. The sidewalls of the first part OP2a and the sidewalls of the second part OP2b may be spaced apart from each other in the first direction D1. The width of the second opening OP2 in the first direction D1 may change abruptly or discontinuously at the boundary between the first part OP2a and the second part OP2b.

[0073] refer to Figure 6 A first seed pattern 111 and a first protective seed pattern 112 can be formed to conformally cover the inner wall of the second opening OP2. The first seed pattern 111 and the first protective seed pattern 112 can extend to the region on the top surface 140a of the first adhesive layer 140. The first seed pattern 111 and the first protective seed pattern 112 can be formed using layer formation methods with relatively good step coverage characteristics (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) methods).

[0074] The third opening OP3 can be formed by forming a first seed crystal pattern 111 and a first protective seed crystal pattern 112 in the second opening OP2. The third opening OP3 may include a first portion OP3a and a second portion OP3b. The first portion OP3a of the third opening OP3 may refer to the remaining portion of the first portion OP2a of the second opening OP2, in which the first seed crystal pattern 111 and the first protective seed crystal pattern 112 are formed and retained. The second portion OP3b of the third opening OP3 may refer to the remaining portion of the second portion OP2b of the second opening OP2, in which the first seed crystal pattern 111 and the first protective seed crystal pattern 112 are formed and retained.

[0075] The first seed crystal pattern 111 may include a conductive metal. The first seed crystal pattern 111 may include, for example, copper (Cu).

[0076] The first protective seed pattern 112 may include a copper compound. The first protective seed pattern 112 may include, for example, a copper-manganese (CuMn) alloy. In an example embodiment, the first protective seed pattern 112 may include a copper-manganese (CuMn) alloy wherein the mass percentage of manganese (Mn) is less than 1 wt%. In an example embodiment, the first protective seed pattern 112 may include a copper-manganese (CuMn) alloy wherein the mass percentage of manganese (Mn) ranges from 0.4 wt% to 0.6 wt%.

[0077] The formation of the first seed pattern 111 and the first protective seed pattern 112 may include depositing a seed material and a growth inhibitor. The seed material may include a metallic material. The metallic material may include, for example, copper. The growth inhibitor may include an organic material and may include, for example, hydroxyl, amino, thiol, and / or sulfite groups.

[0078] refer to Figure 7 A preliminary first via p120 and a preliminary first pad p130 can be formed in the third opening OP3. For example, the preliminary first via p120 can be formed in the first portion OP3a of the third opening OP3, and the preliminary first pad p130 can be formed in the second portion OP3b of the third opening OP3. In an example embodiment, the formation of the preliminary first via p120 and the preliminary first pad p130 may include an electroplating process using a first seed pattern 111 and a first protective seed pattern 112 as electrodes.

[0079] A first conductive layer (not shown) can be formed by an electroplating process. Next, a planarization process can be performed on the first conductive layer. The planarization process can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The planarization process can be performed to expose the top surface 140a of the first adhesive layer 140. After the planarization process, the initial first pad p130 can have a recessed top surface p130R that is recessed towards the first substrate 100. The recessed top surface p130R of the initial first pad p130 can be positioned at a level lower than the top surface 140a of the first adhesive layer 140.

[0080] The average grain size of the initial first via p120 and the initial first pad p130 can be adjusted using growth inhibitors. In this case, the average grain size of the initial first via p120 and the initial first pad p130 can be reduced. In an example embodiment, the initial first via p120 and the initial first pad p130 can be formed to have an average grain size ranging from 25 nm to 70 nm.

[0081] refer to Figure 8This allows the formation of a second substrate 200, a second interconnect pattern 201, a second insulating layer 210, a second adhesive layer 240, a second seed pattern 211, a preliminary second via p220, and a preliminary second pad p230. The second substrate 200, second interconnect pattern 201, second insulating layer 210, second adhesive layer 240, second seed pattern 211, preliminary second via p220, and preliminary second pad p230 can be connected to a reference... Figures 3 to 7 The same or substantially similar methods are used to form the components. Furthermore, the second substrate 200, second interconnect pattern 201, second insulating layer 210, second adhesive layer 240, second seed pattern 211, preliminary second via p220, and preliminary second pad p230 may each comprise the same or substantially similar materials as the first substrate 100, first interconnect pattern 101, first insulating layer 110, first adhesive layer 140, first seed pattern 111, preliminary first via p120, and preliminary first pad p130. Additionally, the preliminary second pad p230 may have a recessed bottom surface p230R recessed towards the second substrate 200. The recessed bottom surface p230R of the preliminary second pad p230 may be positioned at a level higher than the bottom surface 240b of the second adhesive layer 240.

[0082] refer to Figure 9 The top surface 140a of the first adhesive layer 140 and the bottom surface 240b of the second adhesive layer 240 can be attached to each other. Accordingly, the top surface 140a of the first adhesive layer 140 can contact the bottom surface 240b of the second adhesive layer 240.

[0083] A gap can be formed between the recessed top surface p130R of the initial first pad p130 and the recessed bottom surface p230R of the initial second pad p230.

[0084] Return to reference Figure 2A , can be Figure 9 The resulting structure undergoes an annealing process. During the annealing process, the material included in the initial first pad p130 and the initial second pad p230 can diffuse to fill the void between the recessed top surface p130R of the initial first pad p130 and the recessed bottom surface p230R of the initial second pad p230. Therefore, as Figure 2A As shown, the first pad 130 can contact the second pad 230.

[0085] Furthermore, the material included in the first protective seed pattern 112 can diffuse to form the first protective layer 150. In an example embodiment, the manganese (Mn) included in the first protective seed pattern 112 can diffuse into the region between the first pad 130 and the second adhesive layer 240, and can react with oxygen present in that region to form the first protective layer 150. In an example embodiment conceived according to the present invention, since the average grain size of the first pad 130 and the second pad 230 ranges from 25 nm to 70 nm, the manganese (Mn) in the first protective seed pattern 112 will not diffuse into the region between the first pad 130 and the second pad 230. Therefore, the first pad 130 can be spaced apart from the second adhesive layer 240, and the first protective layer 150 is located between the first pad 130 and the second adhesive layer 240.

[0086] Figure 10 and Figure 11 This is a cross-sectional view illustrating a hybrid bonding process according to an exemplary embodiment of the present invention, which is related to... Figure 8 and Figure 9 The example embodiments shown are different. In the following description, previous references Figure 8 and Figure 9 The elements described may be identified using the same reference numerals, and will not be repeated hereafter.

[0087] refer to Figure 10 ,and Figure 8 Compared to the example embodiment, the first protective seed pattern 112 can be omitted. However, a second protective seed pattern 212 can be formed. The second protective seed pattern 212 can be formed to conformally cover the second seed pattern 211. The second protective seed pattern 212 may include elements related to the reference... Figure 7 The material is the same as or substantially similar to the first protective seed pattern 112, and can be formed by a method that is the same as or substantially similar to the first protective seed pattern 112.

[0088] refer to Figure 11 The top surface 140a of the first adhesive layer 140 and the bottom surface 240b of the second adhesive layer 240 can be attached to each other. Therefore, the top surface 140a of the first adhesive layer 140 can contact the bottom surface 240b of the second adhesive layer 240.

[0089] A gap can be formed between the recessed top surface p130R of the initial first pad p130 and the recessed bottom surface p230R of the initial second pad p230.

[0090] Return to reference Figure 2A , can be Figure 11The resulting structure undergoes an annealing process. During the annealing process, the material included in the initial first pad p130 and the initial second pad p230 can diffuse to fill the void between the recessed top surface p130R of the initial first pad p130 and the recessed bottom surface p230R of the initial second pad p230. Therefore, as Figure 2A As shown, the first pad 130 can contact the second pad 230.

[0091] Furthermore, the material included in the second protective seed pattern 212 can diffuse to form the first protective layer 150. In an example embodiment, the manganese (Mn) included in the second protective seed pattern 212 can diffuse into the region between the first pad 130 and the second adhesive layer 240, and can react with oxygen present in that region to form the first protective layer 150.

[0092] Figure 12 and Figure 13 This is a cross-sectional view illustrating a hybrid bonding process according to an exemplary embodiment of the present invention, which is related to... Figure 8 and Figure 9 The example embodiments shown are different. In the following description, previous references Figure 8 and Figure 9 The elements described may be identified using the same reference numerals, and will not be repeated hereafter.

[0093] refer to Figure 12 ,and Figure 8 Compared to the example embodiment, a second protective seed pattern 212 may be additionally formed. The second protective seed pattern 212 may be formed to conformally cover the second seed pattern 211. The second protective seed pattern 212 may include elements related to the reference seed pattern 211. Figure 7 The material is the same as or substantially similar to the first protective seed pattern 112, and can be formed by a method that is the same as or substantially similar to the first protective seed pattern 112.

[0094] refer to Figure 13 The top surface 140a of the first adhesive layer 140 and the bottom surface 240b of the second adhesive layer 240 can be attached to each other. Therefore, the top surface 140a of the first adhesive layer 140 can contact the bottom surface 240b of the second adhesive layer 240.

[0095] A gap can be formed between the recessed top surface p130R of the initial first pad p130 and the recessed bottom surface p230R of the initial second pad p230.

[0096] Return to reference Figure 2A , can be Figure 12The resulting structure undergoes an annealing process. During the annealing process, the material included in the initial first pad p130 and the initial second pad p230 can diffuse to fill the void between the recessed top surface p130R of the initial first pad p130 and the recessed bottom surface p230R of the initial second pad p230. Therefore, as Figure 2A As shown, the first pad 130 can contact the second pad 230.

[0097] Furthermore, the materials included in the first protective seed pattern 112 and the second protective seed pattern 212 can diffuse to form the first protective layer 150. In an example embodiment, the manganese (Mn) included in the first protective seed pattern 112 and the second protective seed pattern 212 can diffuse into the region between the first pad 130 and the second adhesive layer 240, and can react with the oxygen present in the region to form the first protective layer 150.

[0098] According to an exemplary embodiment of the present invention, in a structure formed by bonding a first semiconductor die to a second semiconductor die, a protective layer may be situated between the pads and the adhesive layer. Therefore, the adhesive strength between the first semiconductor die and the second semiconductor die can be improved.

[0099] Furthermore, by adjusting the average grain size of the pads, it is possible to prevent or stop the diffusion of material from the protective layer to the bonding interface between the pads. Therefore, semiconductor devices with improved electrical and / or reliability characteristics can be provided.

[0100] Although some exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A first semiconductor die includes a first pad and a first adhesive layer, the first adhesive layer covering the upper part of the sidewall of the first pad; The second semiconductor die includes a second pad and a second adhesive layer, the second adhesive layer covering the lower part of the sidewall of the second pad; as well as A first protective layer is located between the first solder pad and the second adhesive layer, wherein... The average grain size of each of the first and second pads ranges from 25 nm to 70 nm. The second pad is on the first pad. The top surface of the first pad includes an exposed top surface portion exposed by the second pad. The second adhesive layer is on the exposed top surface portion of the first pad, and The first protective layer is located between the exposed top surface portion of the first pad and the second adhesive layer.

2. The semiconductor device according to claim 1, wherein, The sidewalls of the first pad and the sidewalls of the second pad are spaced apart from each other in a first direction, which is parallel to the top surface of the first adhesive layer.

3. The semiconductor device according to claim 2, wherein, The sidewall of the first pad is inclined at a first angle relative to the top surface of the first adhesive layer. The sidewall of the second pad is inclined at a second angle relative to the top surface of the first adhesive layer, and The first angle and the second angle are obtuse angles.

4. The semiconductor device according to claim 1, wherein, The first pad has a first width in a first direction, which is parallel to the top surface of the first adhesive layer. The second pad has a second width in the first direction, and The first width and the second width decrease as the distance from the top surface of the first adhesive layer increases.

5. The semiconductor device according to claim 1, wherein, When viewed from a plan view, the centers of the first pad and the second pad overlap each other.

6. The semiconductor device according to claim 1, wherein, When viewed from a plan view, the centers of the first pad and the second pad are spaced apart from each other.

7. The semiconductor device according to claim 1, further comprising: A second protective layer is located between the second pad and the first adhesive layer. The bottom surface of the second pad includes the exposed bottom surface portion exposed by the first pad. The exposed bottom surface portion of the second pad is on the first adhesive layer, and The second protective layer is located between the exposed bottom surface portion of the second pad and the first adhesive layer.

8. The semiconductor device according to claim 1, wherein, The first pad and the second pad partially overlap each other in a direction perpendicular to the top surface of the first adhesive layer.

9. The semiconductor device according to claim 1, wherein, The first pad has a first width in a first direction, which is parallel to the top surface of the first adhesive layer. The second pad has a second width in the first direction, and The first width and the second width are different from each other.

10. The semiconductor device according to claim 9, wherein, The first width is greater than the second width.

11. The semiconductor device according to claim 1, wherein, The first protective layer comprises manganese oxide.

12. A semiconductor device, comprising: First Semiconductor Chip; The second semiconductor die is on the first semiconductor die; as well as A first protective layer is located between the first semiconductor die and the second semiconductor die, wherein... The first semiconductor die includes: First substrate, The first interconnect pattern is on the first substrate. The first via is on the first interconnect pattern. A first insulating layer is formed on the first substrate and covers the first interconnect pattern and the first via. The first adhesive layer, on the first insulating layer, and The first pad penetrates the first adhesive layer and the first insulating layer and connects to the first via. The second semiconductor die includes: Second substrate, The second interconnect pattern is on the second substrate. The second via is located on the second interconnect pattern. A second insulating layer is formed on the second substrate and covers the second interconnect pattern and the second via. The second adhesive layer, on the second insulating layer, and The second pad penetrates the second adhesive layer and the second insulating layer and connects to the second via. The average grain size of each of the first and second pads ranges from 25 nm to 70 nm. The second pad is on the first pad. The top surface of the first pad includes an exposed top surface portion exposed by the second pad. The second adhesive layer is on the exposed top surface portion of the first pad, and The first protective layer is located between the exposed top surface portion of the first pad and the second adhesive layer.

13. The semiconductor device according to claim 12, wherein, The sidewalls of the first pad and the sidewalls of the second pad are spaced apart from each other in a first direction, which is parallel to the top surface of the first substrate.

14. The semiconductor device according to claim 12, wherein, The first pad has a first width in a first direction, which is parallel to the top surface of the first substrate; The second pad has a second width in the first direction. The first width increases with increasing distance in the vertical direction from the top surface of the first substrate, where the vertical direction is perpendicular to the top surface of the first substrate; and The second width decreases as the distance from the top surface of the first substrate in the vertical direction increases.

15. The semiconductor device according to claim 14, wherein, The first width of the uppermost part of the first pad is greater than the second width of the lowermost part of the second pad.

16. The semiconductor device according to claim 12, wherein, When viewed from a plan view, the centers of the first pad and the second pad overlap each other.

17. The semiconductor device according to claim 12, wherein, When viewed from a plan view, the centers of the first pad and the second pad are spaced apart from each other.

18. The semiconductor device of claim 12, further comprising: A second protective layer is located between the first semiconductor die and the second semiconductor die. The bottom surface of the second pad includes the exposed bottom surface portion exposed by the first pad. The exposed bottom surface portion of the second pad is on the first adhesive layer, and The second protective layer is located between the exposed bottom surface portion of the second pad and the first adhesive layer.

19. The semiconductor device according to claim 18, wherein, The first protective layer and the second protective layer comprise manganese oxide.

20. The semiconductor device according to claim 12, wherein, The average grain size of each of the first and second vias ranges from 25 nm to 70 nm.

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