Semiconductor device and method of forming the same

Abstract

The device includes a substrate package comprising a component substrate and a first sealant located around and between the component substrate. A wafer package is attached to a first side of the substrate package and includes an integrated circuit device and a second sealant located around and between the integrated circuit device. A voltage regulator is attached to a second side of the substrate package, wherein the component substrate electrically connects the voltage regulator to the integrated circuit device. An external interconnect is also attached to a second side of the substrate package, wherein the component substrate electrically connects the external interconnect to the integrated circuit device. Embodiments of this application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density is due to the iterative reduction in the smallest component size, which allows more components to be integrated into a given area. With the growing demand for miniaturized electronics, there has been a need for smaller and more innovative packaging technologies for semiconductor dies. Summary of the Invention

[0003] One embodiment of this application provides a semiconductor device, comprising: a substrate package including a plurality of component substrates and a first sealant located between and around the component substrates; a wafer package attached to a first side of the substrate package, the wafer package including a plurality of integrated circuit devices and a second sealant located between and around the integrated circuit devices; a plurality of voltage regulators attached to a second side of the substrate package, the component substrates electrically connecting the voltage regulators to the integrated circuit devices; and a plurality of external connectors attached to the second side of the substrate package, the component substrates electrically connecting the external connectors to the integrated circuit devices.

[0004] Another embodiment of this application provides a semiconductor device, including: a thermal module; a frame including an opening; and a system package located between the thermal module and the frame. The system package includes: a substrate package including a plurality of connector substrates, a sealant located between and around the connector substrates, and a redistribution structure located on the sealant; a wafer package attached to the redistribution structure of the substrate package, the substrate package having a width greater than the width of the wafer package, the wafer package including an integrated circuit device; and a plurality of external connectors attached to the connector substrates of the substrate package, the connector substrates electrically connecting the external connectors to the integrated circuit device, the opening of the frame exposing the external connectors.

[0005] Another aspect of this application provides a method for forming a semiconductor device, including:

[0006] The substrate package is formed by the following steps: sealing a connector substrate and a power distribution substrate using a molding compound; planarizing the molding compound until the upper surface of the molding compound is coplanar with the upper surface of the connector substrate and the upper surface of the power distribution substrate; and forming a redistribution structure on the molding compound, the redistribution structure including redistribution lines electrically connected to the connector substrate and the power distribution substrate;

[0007] The redistribution structure that attaches the wafer package to the substrate package; and

[0008] The external connector and voltage regulator are respectively attached to the lower surface of the connector substrate and the lower surface of the power distribution substrate. Attached Figure Description

[0009] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0010] Figure 1 This is a cross-sectional view of an integrated circuit die.

[0011] Figures 2A to 2B This is a cross-sectional view of the die stack.

[0012] Figures 3 to 8 This is a cross-sectional view of an intermediate stage in the manufacturing of a wafer package according to some embodiments.

[0013] Figure 9 This is a cross-sectional view of a wafer package according to some embodiments.

[0014] Figures 10 to 19 This is a cross-sectional view of an intermediate stage in the fabrication of a component substrate according to some embodiments.

[0015] Figures 20 to 25 This is a view of an intermediate stage in the manufacturing of a substrate package according to some embodiments.

[0016] Figure 26 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments.

[0017] Figures 27 to 28 This is a view of an intermediate stage in the manufacturing of a substrate package according to some embodiments.

[0018] Figure 29 This is a cross-sectional view of a system-on-a-wafer assembly according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0021] According to various embodiments, the system package includes a wafer package attached to a substrate package. The substrate package includes a plurality of component substrates sealed in a first sealant, while the wafer package includes a plurality of integrated circuit devices sealed in a second sealant. The wafer package is attached to a first side of the substrate package. Voltage regulators and external connections are attached to a second side of the substrate package, wherein the component substrates electrically connect these components to the integrated circuit devices.

[0022] Substrate packages can incorporate separate component substrates for power distribution and external connectivity. Component substrates can be individually tested and validated as known good substrates before integration into the substrate package, potentially improving overall yield and reliability. Furthermore, different types of component substrates can be used within the same package; for example, some component substrates may include passive devices, while others may be coreless, allowing for customization based on specific power, signal, or space requirements in different areas within the system package.

[0023] Figure 1This is a cross-sectional view of an integrated circuit die 50. Multiple integrated circuit dies 50 will be packaged in subsequent processing. Each integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC) die, microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or a combination thereof. The integrated circuit dies 50 may be formed in a wafer, which may include different die regions that are segmented in subsequent steps to form multiple integrated circuit dies 50. Each integrated circuit die 50 includes a semiconductor substrate 52, interconnect structures 54, die connectors 56, and a dielectric layer 58.

[0024] Semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Semiconductor substrate 52 has an active surface (e.g., Figure 1 (Surface facing upwards) and passive surfaces (e.g., Figure 1 The surface facing downwards. Devices (not shown separately) are located at the active surface of the semiconductor substrate 52. Devices can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. Passive surfaces may be without devices.

[0025] Interconnect structure 54 is located above the active surface of semiconductor substrate 52 and is used to electrically connect devices on semiconductor substrate 52 together to form an integrated circuit. Interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers located within the dielectric layers. Acceptable dielectric materials for dielectric layers include oxides (such as silicon oxide or aluminum oxide), nitrides (such as silicon nitride), combinations thereof (such as silicon oxynitride), etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene-based polymers (BCB), etc. Metallization layers may include conductive vias and / or wires to interconnect devices on semiconductor substrate 52. Metallization layers may be formed of conductive materials, such as metals, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The metallization layers of interconnect structure 54 may be formed by damascene processes, such as single damascene processes, dual damascene processes, etc.

[0026] The die connector 56 is located at the front side 50F of the integrated circuit die 50. The die connector 56 can be a conductive pillar, pad, etc., for external connection. The die connector 56 can be located in and / or on the interconnect structure 54. For example, the die connector 56 can be a portion of the upper metallization layer of the interconnect structure 54. The die connector 56 can be formed of a metal such as copper or aluminum, and can be formed by, for example, plating.

[0027] Optionally, during the formation of the integrated circuit die 50, a solder region (not shown separately) may be provided on the die connector 56. The solder region can be used to perform chip probe (CP) testing on the integrated circuit die 50. For example, the solder region may be a solder ball, solder bump, etc., for attaching the chip probe to the die connector 56. The chip probe test can be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only KGD integrated circuit dies 50 that have undergone subsequent processing are packaged, and dies that fail the chip probe test are not packaged. After testing, the solder region can be removed.

[0028] Dielectric layer 58 is located at the front side 50F of integrated circuit die 50. Dielectric layer 58 may be located in and / or on interconnect structure 54. For example, dielectric layer 58 may be an upper dielectric layer of interconnect structure 54. Dielectric layer 58 may be an oxide, nitride, polymer, or combination thereof, which may be formed by, for example, spin coating, lamination, chemical vapor deposition (CVD), etc. Dielectric layer 58 may laterally seal die connector 56. The front surfaces of die connector 56 and dielectric layer 58 may be substantially coplanar at the front side 50F of integrated circuit die 50 (within process variations).

[0029] Figures 2A to 2BThese are cross-sectional views of die stacks 60A and 60B, respectively. Each of die stacks 60A and 60B may have a single function (e.g., a logic device, a memory die, etc.) or each may have multiple functions. In some embodiments, die stack 60A is a logic device such as a system-on-a-chip (SoIC) device, and die stack 60B is a memory device such as a high-bandwidth memory (HBM) device.

[0030] like Figure 2A As shown, the die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die, and the second integrated circuit die 50B is an interface die. The interface die bridges the logic die to a memory die and translates commands between the logic die and the memory die. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded such that their active surfaces face each other (e.g., "face-to-face" bonding). A conductive via 62 may be formed through one of the integrated circuit dies 50, allowing an external connection to the die stack 60A to be made. The conductive via 62 may be a substrate via (TSV), such as a through-silicon via (TSV). In the illustrated embodiment, the conductive via 62 is formed in the second integrated circuit die 50B (e.g., the interface die). The conductive via 62 extends through the semiconductor substrate 52 of the respective integrated circuit die 50 to physically and electrically connect to the metallization layer of the interconnect structure 54.

[0031] like Figure 2B As shown, the die stack 60B is a stacked device comprising multiple semiconductor substrates 52. For example, the die stack 60B may be a stacked memory device comprising multiple memory dies (such as hybrid memory cube (HMC) devices, high bandwidth memory (HBM) cubes, etc.). Each semiconductor substrate 52 may (or may not) have a separate interconnect structure 54. The semiconductor substrates 52 are connected via conductive vias 62 (such as TSVs).

[0032] As described below, a system package will be formed by packaging integrated circuit devices. The integrated circuit device can be an integrated circuit chip (similar to...). Figure 1 The integrated circuit die 50 described in the document can be a die stack (similar to the one in the document). Figures 2A to 2BThe die stacks 60A and 60B described herein. This system package has multiple compute stations and multiple connectivity stations. Each integrated circuit device in the system package may have, for example, logic functions, memory functions, etc., and the system package may be a single computing system including compute stations and connectivity stations, such as a system-on-wafer (SoW). For example, the system package may be an artificial intelligence (AI) accelerator, and each compute station may be a neural network node for the AI ​​accelerator. Connectivity stations may include external connectors for connecting compute stations to external systems. Example external systems that can implement the system package include AI servers, high-performance computing (HPC) systems, high-power computing devices, cloud computing systems, edge computing systems, etc.

[0033] Figures 3 to 8 It is a wafer package 100A according to some embodiments (see Figure 8 This is a cross-sectional view of an intermediate stage in the manufacturing process of the wafer package 100A. The wafer package 100A is a reconstructed wafer comprising integrated circuit devices encapsulated in a sealant. The wafer package 100A will then be attached to a substrate package to form a system package.

[0034] exist Figure 3 In this process, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 can be a wafer.

[0035] Release layer 104 may be formed of a polymer-based material, which may be removed together with the carrier substrate 102 from the structure to be formed in subsequent steps. In some embodiments, release layer 104 is an epoxy-based thermal release material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 104 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. Release layer 104 may be dispensed as a liquid and cured, and may be a laminated film, etc., laminated onto the carrier substrate 102. The upper surface of release layer 104 may be flush and may have a high degree of flatness.

[0036] A back-side redistribution structure 110 is formed on the release layer 104. The back-side redistribution structure 110 includes a dielectric layer 112 and a metallization layer 114 (sometimes referred to as a redistribution layer or redistribution line) located between the dielectric layers. Thus, the back-side redistribution structure 110 includes metallization layers 114 that are separated from each other by respective dielectric layers 112.

[0037] Each of the dielectric layers 112 can be formed of a suitable dielectric material. In some embodiments, the dielectric layers 112 are formed of silicon oxide, silicon nitride, silicon oxynitride, etc., which can be formed by a suitable deposition process (such as CVD, ALD, etc.). In some embodiments, the dielectric layers 112 are formed of a polymer, which can be a photosensitive material, such as PBO, polyimide, BCB-based polymer, etc., and can be patterned using a photomask formed by spin coating, lamination, CVD, etc. In some embodiments, the dielectric layers 112 are formed of a molding compound, which can include a resin in which fillers are disposed. Examples of resins include epoxy resins, acrylic resins, or polyimide-based materials. Examples of fillers include silicon dioxide, etc. The molding compound can be applied by compression molding, transfer molding, etc., and can be applied in liquid or semi-liquid form, followed by curing.

[0038] Each of the metallization layers 114 includes a conductive via and / or a conductive wire. The conductive via extends through the corresponding dielectric layer 112, and the conductive wire extends along the corresponding dielectric layer 112. The metallization layer 114 may be formed of a conductive material. The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. The metallization layer 114 may be a composite layer comprising multiple sublayers formed of different materials.

[0039] As an example of a layer forming the back-side redistribution structure 110, the dielectric layer 112 may be formed of a polymer. After forming the dielectric layers 112, they may be patterned to expose underlying conductive components (if present), such as the underlying metallization layer. Patterning may be performed by any acceptable process, such as by exposing the dielectric layer to light when the dielectric layer 112 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 112 is a photosensitive material, it may be developed after exposure. The metallization layer 114 is then formed. For example, a seed layer (not shown separately) may be formed over the corresponding underlying component. The seed layer may be formed on the dielectric layer 112 and in any openings through the dielectric layer 112. In some embodiments, the seed layer comprises a titanium layer and a copper layer located above the titanium layer. The seed layer may be formed using a deposition process, such as physical vapor deposition (PVD). Photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 114. Patterning is formed through openings in the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as chemical plating or electroplating from the seed layer. The photoresist and the portions of the seed layer on which the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization layer 114.

[0040] As another example of a layer forming the back-side redistribution structure 110, a metallization layer 114 may be formed. For example, a seed layer (not shown separately) may be formed above a corresponding underlying component, such as an underlying dielectric layer. In some embodiments, the seed layer comprises a titanium layer and a copper layer located above the titanium layer. The seed layer may be formed using a deposition process, such as physical vapor deposition (PVD). A first photoresist is then formed on the seed layer and patterned. The first photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the first photoresist corresponds to the conductive lines for the metallization layer 114. Patterning is formed through openings in the first photoresist to expose the seed layer. A conductive material is formed in the openings of the first photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as chemical plating or electroplating from the seed layer. The first photoresist is then removed. The first photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma. A second photoresist is then formed on the seed layer and the conductive lines and patterned. The second photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the second photoresist corresponds to the conductive vias for the metallization layer 114. Patterning forms openings through the second photoresist to expose wires. Additional conductive material is formed in the openings of the second photoresist and on the exposed portions of the wires. The conductive material can be formed by plating, such as chemical plating or electroplating from the wires. In some embodiments, no seed layer is formed between the wires and the conductive vias. The second photoresist and portions thereon where no conductive material is formed are then removed. The second photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. After removing the second photoresist, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization layer 114. A dielectric layer 112 is formed around the metallization layer 114. The dielectric layer 112 can be formed of molding compound. A dielectric layer 112 can be formed over a metallization layer 114, such that the metallization layer 112 is buried or covered. A planarization process can then be performed on the dielectric layer 112 to expose the conductive vias of the metallization layer 114. After the planarization process, the upper surfaces of the dielectric layer 112 and the metallization layer 114 are substantially coplanar (within process variations). The planarization process can be, for example, chemical mechanical polishing (CMP).

[0041] The back-side redistribution structure 110 may include a combination of different types of dielectric layers 112. In some embodiments, certain dielectric layers 112 may be formed of polymers (as previously described), while other dielectric layers 122 within the same structure may be formed of molding compounds (as previously described). This hybrid approach can allow for customization of properties in different regions of the redistribution structure. For example, polymer-based dielectric layers may be used for regions where precise patterning is performed via photolithography, while molding compound layers may be used for regions that benefit from their specific mechanical or electrical properties.

[0042] The back-side redistribution structure 110 is shown as an example. More or fewer dielectric layers 112 and metallization layers 114 than shown can be formed by performing the foregoing steps any desired number of times.

[0043] A bump under-metall layer (UBML) 116 is formed for subsequent connection to the back-side redistribution structure 110. UBML 116 has bump portions located on and extending along the main surface of the upper dielectric layer 112 of the back-side redistribution structure 110, and via portions extending through the upper dielectric layer of the back-side redistribution structure 110 to physically and electrically couple the upper metallization layer 114 of the back-side redistribution structure 110. UBML 116 may be formed of the same material as metallization layer 114 and may be formed by a similar process to metallization layer 114. In some embodiments, UBML 116 has different dimensions than metallization layer 114.

[0044] exist Figure 4 In this configuration, vias 118 are formed on a first subset of UBML 116. Additionally, interconnect dies 120 are attached to a second subset of UBML 116. The second subset of UBML 116 retains the absence of vias 118. The first subset of UBML 116 and the vias 118 will subsequently be used for connections to higher layers of the wafer package. The second subset of UBML 116 and the interconnect dies 120 will subsequently be used for direct communication between integrated circuit devices within the resulting wafer package.

[0045] As an example of forming the through-hole 118, photoresist is formed and patterned on UBML 116 and the back-side redistribution structure 110. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the through-hole 118. The patterning forms openings through the photoresist to expose UBML 116. Conductive material is formed in the openings of the photoresist and on the exposed portions of UBML 116. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material of the through-hole 118 can be directly plated from the conductive material of UBML 116. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist is then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. The remaining portion of the conductive material forms the through-hole 118.

[0046] Each interconnect die 120 may be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, etc. Each interconnect die 120 includes a substrate 122, in which and / or on the substrate 122, conductive components are formed. The substrate 122 may include a semiconductor substrate, one or more dielectric layers, etc. Furthermore, each interconnect die 120 may include a through-substrate via (TSV) 124 extending into or through the substrate 122 and coupling to the conductive components of the interconnect die 120. The interconnect die 120 is attached to the UBML 116 using die connectors 126 disposed on the back side of the interconnect die 120. Some die connectors 126 may be electrically coupled to the front side of the interconnect die 120 via the TSV 124. As described in more detail later, the TSV 124 is small, such as smaller than the through-hole 118. Due to the small size of the TSV 124, they can have a higher density, thereby increasing the amount of connectivity to the interconnect die 120.

[0047] In embodiments where interconnect die 120 is an LSI, interconnect die 120 may be a bridge structure including die bridge 128. Die bridge 128 may be a metallization layer formed in and / or on, for example, substrate 122, and is used to interconnect the above-mentioned integrated circuit devices (described below) with each other. Die bridge 128 is located on the front side of interconnect die 120. Therefore, LSI can be used for direct connection and allows communication between integrated circuit devices. In such embodiments, interconnect die 120 may be placed in a region disposed between subsequently attached integrated circuit devices, such that each interconnect die 120 overlaps with a plurality of above-mentioned integrated circuit devices. In some embodiments, interconnect die 120 may also include logic devices and / or memory devices. In some embodiments, interconnect die 120 may not have logic devices and / or memory devices. Interconnect die 120 is attached to UBML 116 such that die bridge 128 faces away from back-side redistribution structure 110.

[0048] In the illustrated embodiment, interconnect die 120 is attached to back-side redistribution structure 110 (via UBML 116) using solder bonding (such as using conductive connector 130). Conductive connector 130 may be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connector 130 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connector 130 is initially formed by forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed, reflow can be performed to shape the material into the desired bump shape. Attaching the interconnect die 120 to the UBML 116 may include placing the interconnect die 120 on the UBML 116 (e.g., using a pick-and-place process) and returning the conductive connector 130 to physically and electrically couple the die connector 126 to the UBML 116. In another embodiment, the interconnect die 120 is attached to the back-side redistribution structure 110 using the die connector 126 via direct bonding.

[0049] In some embodiments, underfill 132 is formed around the conductive connector 130 and between the back-side redistribution structure 110 and the interconnect die 120. Underfill 132 can reduce stress and protect the joints created by backflow of the conductive connector 130. Underfill 132 can also be used to securely bond the interconnect die 120 to the back-side redistribution structure 110 and provide structural support and environmental protection. Underfill 132 can be formed from molding compounds, epoxy resins, etc. Underfill 132 can be formed by a capillary flow process after attaching the interconnect die 120, or it can be formed by a suitable deposition method before attaching the interconnect die 120. Underfill 132 can be applied in liquid or semi-liquid form and then subsequently cured.

[0050] Optionally, the interconnect die 120 may include a die connector 134 disposed on the front side of the interconnect die 120. The die connector 134 may be electrically coupled to the die bridge 128.

[0051] Interconnect die 120 may be an optional component in the wafer package. The inclusion or exclusion of interconnect die 120 may depend on specific design requirements, performance targets, or manufacturing considerations. Furthermore, while interconnect die 120 may be implemented as a local silicon interconnect (LSI) in some cases, optional components such as integrated voltage regulators (IVRs) or integrated passive devices (IPDs) may be used instead of an LSI. Depending on the specific requirements of the wafer package, these optional components can provide different functionalities or benefits. For example, an IVR can provide improved power management capabilities, while an IPD can provide enhanced passive component integration within the wafer package.

[0052] exist Figure 5 In this process, sealant 136 is formed on and around various components. After formation, sealant 136 seals UBML 116, through-hole 118, interconnect die 120, and / or underfill 132. Sealant 136 can be a molding compound, epoxy resin, etc. Sealant 136 can be applied by compression molding, transfer molding, etc., and can be formed over carrier substrate 102, such that it buries or covers through-hole 118 and / or interconnect die 120. Sealant 136 is also formed in the gap region between interconnect die 120 and through-hole 118. Sealant 136 can be applied in liquid or semi-liquid form and then subsequently cured.

[0053] Optionally, a planarization process can be performed on the sealant 136 to expose the through-hole 118 and the interconnect die 120 (e.g., die connector 134). The planarization process may remove material from the through-hole 118, the interconnect die 120, and / or the sealant 136 until the interconnect die 20 and the through-hole 118 are exposed. After the planarization process, the upper surfaces of the through-hole 118, the die connector 134, and the sealant 136 are substantially coplanar (within process variations). The planarization process may be, for example, chemical mechanical polishing (CMP), lamination, etc. In some embodiments, for example, if the through-hole 118 and / or the die connector 134 are already exposed, planarization may be omitted. After the planarization process, the through-hole 118 extends through the sealant 136. Therefore, the through-hole 118 may be referred to as a molded through-hole (TMV).

[0054] exist Figure 6In this configuration, a front redistribution structure 140 is formed on the front surface of the sealant 136, the interconnect die 120 (e.g., die connector 134), and the through-hole 118. The front redistribution structure 140 includes a dielectric layer 142 and a metallization layer 144 (sometimes referred to as a redistribution layer or redistribution line) located between the dielectric layers 142. Therefore, the front redistribution structure 140 includes metallization layers 144 spaced apart from each other by respective dielectric layers 142. The metallization layer 144 of the front redistribution structure 140 connects to the through-hole 118 and the interconnect die 120 (e.g., die connector 134).

[0055] In some embodiments, the dielectric layer 142 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB-based polymers, etc., and can be patterned using a photomask. In other embodiments, the dielectric layer 142 is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide), etc. The dielectric layer 142 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. After the dielectric layer 142 is formed, it can be patterned to expose underlying conductive components, such as vias 118, die connectors 134, and / or portions of the metallization layer 144. Patterning can be performed by any acceptable process, such as exposing the dielectric layer 142 to light when it is formed of a photosensitive material, or etching using, for example, anisotropic etching. If the dielectric layer 142 is formed of a photosensitive material, it can be developed after exposure.

[0056] Each of the metallization layers 144 includes a conductive via and / or a wire. The conductive via extends through the corresponding dielectric layer 142, and the wire extends along the corresponding dielectric layer 142. As an example of forming the metallization layer 144, a seed layer (not shown separately) is formed over the corresponding underlying component. For example, the seed layer may be formed on the corresponding dielectric layer 142 and in any opening through the corresponding dielectric layer 142. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer may be formed using a deposition process such as PVD. Photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 144. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as chemical plating or electroplating from the seed layer. The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as wet or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization layer 144 of the front redistribution structure 140.

[0057] The front redistribution structure 140 is shown as an example. By performing the aforementioned steps any desired number of times, more or fewer dielectric layers 142 and metallization layers 144 can be formed than shown.

[0058] Other variations of the front redistribution structure 140 can be anticipated. For example, some dielectric layers 142 may be formed from sealants such as molding compounds, epoxy resins, etc. A metallization layer 144 may be formed by plating conductive vias from wires. The dielectric layer 142 may be formed by sealing the metallization layer 144. Any desired material stack may be used for the dielectric layer 142.

[0059] Under-bump metallization (UBM) 146 may be formed through the upper dielectric layer 142 of the front redistribution structure 140. UBM 146 is physically and electrically coupled to the upper metallization layer 144 of the front redistribution structure 140. Each UBM 146 includes a conductive via and a conductive bump. The conductive via extends through the upper dielectric layer 142, and the conductive bump extends along the upper dielectric layer 142. UBM 146 may be formed of the same material as the metallization layer 144. In some embodiments, UBM 146 has different dimensions than the metallization layer 144.

[0060] exist Figure 7In this configuration, integrated circuit devices 70 are attached to the front redistribution structure 140. The desired type and number of integrated circuit devices 70 are arranged adjacent to each other. In some embodiments, the integrated circuit devices 70 include a first type of integrated circuit device (such as a computing device 70A) and a second type of integrated circuit device (such as an interface device 70B). The computing device 70A and the interface device 70B can be formed in a process at the same technology node or in processes at different technology nodes. For example, the computing device 70A can be formed using a more advanced process node than the interface device 70B.

[0061] Each computing device 70A may include logic dies, memory dies, etc. The computing device 70A may be an integrated circuit die (similar to...) Figure 1 The integrated circuit die 50 described in the document can be a die stack (similar to the one in the document). Figures 2A to 2B The die stacks 60A and 60B described herein. In some embodiments, computing device 70A is a system-on-a-chip (SoC) die. In some embodiments, computing device 70A is a die stack, such as an integrated system-on-a-chip (SoIC) device. Each die stack may include a SoC die and one or more HBM dies. In some embodiments, computing device 70A includes various combinations of logic components (such as SoC dies or I / O dies) and other dedicated components. These combinations may incorporate memory modules, silicon photonics elements, or integrated passive devices (IPDs).

[0062] Each interface device 70B may include an input / output interface, memory controller, network interface, or other type of interface circuitry to bridge communication between the computing device 70A and external components. The interface device 70B can translate commands and data between protocols used by the computing device 70A and protocols used by external components. The interface device 70B may be an integrated circuit die (similar to...) Figure 1 The integrated circuit die 50 described in the document can be a die stack (similar to the one in the document). Figures 2A to 2B (Die stacks 60A and 60B described herein). In some embodiments, interface device 70B is an I / O die.

[0063] Interface device 70B can be arranged around computing device 70A to facilitate connectivity with external systems. Specifically, interface device 70B can surround computing device 70A (described later) in a top view. This arrangement allows for a shorter electrical path between interface device 70B and external connectors (described later) that will be attached to the system package.

[0064] In the illustrated embodiment, the integrated circuit device 70 is attached to the front redistribution structure 140 using solder bonding (such as using conductive connector 152). The conductive connector 152 may be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connector 152 is formed by initially forming a solder layer using methods such as evaporation, electroplating, printing, solder transfer, or ball placement. Once the solder layer is formed, reflow can be performed to shape the conductive connector 152 into a desired bump shape. Attaching the integrated circuit device 70 to the front redistribution structure 140 may include placing the integrated circuit device 70 on the front redistribution structure 140 and reflowing the conductive connector 152. The integrated circuit device 70 may be placed on the front redistribution structure 140 using, for example, pick-and-place tools. The return conductive connector 152 attaches the die connector 154 at the front side of the integrated circuit device 70 to the UBM 146 of the front redistribution structure 140, thereby electrically connecting the front redistribution structure 140 to the integrated circuit device 70. In another embodiment, the die connector 154 is used to attach the integrated circuit device 70 to the front redistribution structure 140 via direct bonding.

[0065] In some embodiments, underfill 160 is formed around the conductive connector 152 and between the front redistribution structure 140 and the integrated circuit device 70. Underfill 160 can reduce stress and protect the joint from backflow caused by the conductive connector 152. Underfill 160 can be formed of an underfill material such as molding compound, epoxy resin, etc. Underfill 160 can be formed by a capillary flow process after the integrated circuit device 70 is attached to the front redistribution structure 140, or by a suitable deposition method before the integrated circuit device 70 is attached to the front redistribution structure 140. Underfill 160 can be applied in liquid or semi-liquid form and then subsequently cured.

[0066] A sealant 162 is formed around various components. After formation, the sealant 162 laterally seals the underfill 160 (if present) and the integrated circuit device 70. The sealant 162 can be a molding compound, epoxy resin, etc. The sealant 162 can be applied by compression molding, transfer molding, etc., and can be formed over the front redistribution structure 140, thereby burying or covering the integrated circuit device 70. The sealant 162 is also formed in the gap region between the underfill 160 (if present) and / or the integrated circuit device 70. The sealant 162 can be applied in liquid or semi-liquid form and then subsequently cured.

[0067] Optionally, a removal process can be performed on the sealant 162 to expose the integrated circuit device 70. The removal process may include, for example, planarization processes, such as chemical mechanical polishing (CMP), grinding processes, etc. After the planarization process, the sealant 162 and the upper surface of the integrated circuit device 70 may be substantially coplanar (within process variations). For example, if the integrated circuit device 70 is already exposed, planarization may be omitted.

[0068] exist Figure 8 In this process, carrier substrate debonding can be performed to detach (or “debond”) carrier substrate 102 from back-side redistribution structure 110. According to some embodiments, debonding includes projecting light, such as UV light, onto release layer 104, causing release layer 104 to decompose under the heat of the light, and carrier substrate 102 can be removed. The remaining structure is wafer package 100A, which will then be attached to the substrate package. Wafer package 100A can be placed on a strip, carrier substrate, or another suitable support structure (not shown separately) for subsequent processing.

[0069] A UBM 164 can be formed for subsequent connection to the back-side redistribution structure 110. The UBM 164 has a bump portion located on and extending along the main surface of the lower dielectric layer 112 of the back-side redistribution structure 110, and a via portion extending through the lower dielectric layer of the back-side redistribution structure 110 to physically and electrically couple the lower metallization layer 114 of the back-side redistribution structure 110. The UBM 164 can be formed of the same material as the metallization layer 114 and can be formed by a similar process to the metallization layer 114. In some embodiments, the UBM 164 can have different dimensions than the metallization layer 114.

[0070] Figure 9 This is a cross-sectional view of a wafer package 100B according to some embodiments. In this embodiment, an integrated circuit device 70 is sealed in a sealant 162, and the integrated circuit device 70 may be disposed on a carrier substrate. A redistribution structure 110 is then formed on the sealant 162, wherein a metallization layer 114 of the redistribution structure 110 is electrically coupled to the integrated circuit device 70. The UBM 164 is formed for the redistribution structure 110, such as through an upper dielectric layer 112 of the redistribution structure 110.

[0071] Figures 10 to 19 The component substrate 200 according to some embodiments (see Figure 19This is a cross-sectional view of an intermediate stage in the manufacturing process of [the component]. Multiple component substrates 200 will be packaged in subsequent processes. Each component substrate 200 can be used to connect a voltage regulator module (VRM) or external connector to an integrated circuit device. In some aspects, the component substrate 200 can be a power distribution board or a connector board. The component substrate 200 can allow direct communication between the integrated circuit device (such as a computing device, interface device, etc.) and the external connector or VRM. The component substrate 200 can include an organic core or can be coreless. In some aspects, the component substrate 200 can incorporate devices, such as passive devices. In other aspects, the component substrate 200 may be without devices.

[0072] Although the formation of a single component substrate 200 has been described, it is understood that multiple component substrates 200 can be fabricated simultaneously, such as on a larger panel or wafer. After the fabrication steps are completed, the component substrate 200 can be separated or divided from the larger panel.

[0073] exist Figure 10 The substrate core 202 is provided with a seed layer 204 on opposite sides. The substrate core 202 may be an FR-4 or BT resin core. The substrate core 202 may be formed from pre-impregnated composite fibers (“prepreg”), insulating films or laminated films, paper, glass fibers, nonwoven glass fabrics, silicon, etc. In some embodiments, the substrate core 202 is an organic core formed from an organic material. In some embodiments, the substrate core 202 is formed from a prepreg comprising glass fibers and resin. The seed layer 204 may be one or more layers of copper, titanium, nickel, aluminum, combinations thereof, etc., and may be deposited or laminated onto opposite sides of the substrate core 202. In some embodiments, the substrate core 202 and the seed layer 204 are part of a double-sided copper-clad laminate (CCL) substrate, such as a copper-clad epoxy impregnated glass cloth laminate, a copper-clad polyimide impregnated glass cloth laminate, etc.

[0074] exist Figure 11 In this process, an opening 206 is formed in the substrate core 202 and the seed layer 204. In some embodiments, the opening 206 is formed by laser drilling. Other processes (such as mechanical drilling) may also be used to form the opening 206. The opening 206 can have any top-view shape, such as polygonal, circular, etc. A cleaning process can then be performed to clean the areas near the opening 206, which may have been contaminated by the removal material from the substrate core 202. The cleaning process can be a decontamination process. Decontamination can be achieved by mechanical means (e.g., sandblasting with fine abrasives in a wet slurry), chemical means (e.g., rinsing with a combination of organic solvents, permanganates, etc.), or a combination of mechanical and chemical processes.

[0075] exist Figure 12In this embodiment, a conductive via 208 is formed in an opening 206, and a conductive wire 210 is formed on the opposite side of the substrate core 202. The conductive via 208 and the conductive wire 210 can be formed from conductive materials such as copper, titanium, tungsten, aluminum, etc. The conductive via 208 and the conductive wire 210 can be formed from the same or different materials, and can be formed using the same or different processes. In some embodiments, the conductive via 208 is formed using a first process, and the conductive wire 210 is formed using a second process. For example, a first plating process (such as electroless plating) can be used to deposit conductive material in the opening 206 to form the conductive via 208. In embodiments using electroless plating, a seed layer can be formed in the opening 206. A second plating process, such as electroplating, electroless plating, etc., can be performed using the seed layer 204. Photoresist is formed on the seed layer 204 and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive wire 210. Patterning is formed through openings in the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The photoresist and portions of the seed layer 204 on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer 204 are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer 204 and the conductive material form the conductive wire 210.

[0076] exist Figure 13 In this process, adhesive 212 can be formed on one side of the substrate core 202 and over the conductor 210. Adhesive 212 can be applied using various techniques, such as lamination, spin coating, or spraying. In some aspects, adhesive 212 can be a tape laminated onto a surface. Adhesive 212 can cover the surface of the substrate core 202 and the conductor 210 on one side, or can be selectively applied to specific areas. In some cases, adhesive 212 can be temporarily applied during subsequent processing steps to provide support and can be removed later.

[0077] exist Figure 14Optionally, the opening 214 can be formed by removing portions of the substrate core 202 and the adhesive 212. Removing material to form the opening 214 can be achieved through various processes, such as mechanical drilling using computer numerical control (CNC), laser cutting, or laser drilling. In embodiments using CNC drilling, a computer- or controller-controlled mechanical drill removes material from the desired location. Laser-based processes can also be used for more precise or complex opening shapes. The size and shape of the opening 214 can be customized to accommodate specific components or achieve desired mechanical properties. The opening 214 can extend through the substrate core 202 and the adhesive 212. The remaining material forms a frame-like structure around the opening 214. The opening 214, if present, can accommodate passive devices, allowing these components to be efficiently integrated within the component substrate 200.

[0078] exist Figure 15 In this process, a carrier substrate 222 is provided, and a release layer 224 is formed on the carrier substrate 222. The carrier substrate 222 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 222 can be a wafer.

[0079] Release layer 224 may be formed of a polymer-based material, which may be removed together with carrier substrate 222 from the above structure to be formed in subsequent steps. In some embodiments, release layer 224 is an epoxy-based thermal release material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 224 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. Release layer 224 may be dispensed as a liquid and cured, and may be a laminated film, etc., laminated onto carrier substrate 222. The upper surface of release layer 224 may be flush and may have a high degree of flatness.

[0080] A dielectric layer 226 is formed on the release layer 224. The dielectric layer 226 can be formed of a suitable dielectric material. In some embodiments, the dielectric layer 226 is formed of silicon oxide, silicon nitride, silicon oxynitride, etc., which can be formed by a suitable deposition process (such as CVD, ALD, etc.). In some embodiments, the dielectric layer 226 is formed of a polymer, which can be a photosensitive material, such as PBO, polyimide, BCB-based polymer, etc., and can be patterned using a photomask formed by spin coating, lamination, CVD, etc.

[0081] The substrate core 202 can be adhered to the dielectric layer 226 using an adhesive 212. The adhesive 212 can be activated by applying pressure, heat, or a combination thereof to bond the substrate core 202 to the dielectric layer 226. In some embodiments, the adhesive 212 can be a thermosetting adhesive that cures upon exposure to elevated temperatures and forms a strong bond. Equipment such as a laminator or a vacuum laminator can be used to perform the bonding process to ensure a uniform pressure and temperature distribution at the bonding interface.

[0082] In some embodiments, when the substrate core 202 has an opening 214, a UBM 228 can be formed through the dielectric layer 226. The UBM 228 can be formed before the substrate core 202 is adhered to the dielectric layer 226. Initially, the opening can be patterned in the dielectric layer 226 using photolithography and / or etching techniques. A seed layer can then be deposited to cover the opening and the surface of the dielectric layer 226. Photoresist can be applied and patterned to define the shape and size of the UBM 228. Electroplating or electroless plating processes can be used to form a conductive material (such as copper) in the openings through the photoresist to form the UBM 228. After plating, the photoresist can be removed, and excess seed layer can be etched away. In some cases, additional metal layers can be formed on the UBM 228 to enhance their performance or facilitate bonding with subsequent components. The resulting UBM 228 can extend through the dielectric layer 226. During the adhesion of the substrate core 202 to the dielectric layer 226, the opening 214 in the substrate core 202 can be aligned with the UBM 228.

[0083] exist Figure 16 In this embodiment, passive device 230 is attached to the structure below. Passive device 230 will be included in component substrate 200 to provide specific electrical characteristics, improve signal integrity, perform power distribution within the substrate, etc. Passive device 230 can be placed in the opening 214 through substrate core 202 using, for example, pick-and-place tools; however, any other method of placing passive device 230 may also be utilized. The type and placement of passive device 230 may be determined by factors such as the intended application of the substrate, performance objectives, or space constraints. While a single passive device 230 has been shown and described, it should be understood that some embodiments may include multiple passive devices 230 within component substrate 200.

[0084] Passive device 230 can be formed or processed according to applicable manufacturing processes. For example, passive device 230 may be an IPD that includes one or more passive devices in a main structure. The main structure may include a substrate and / or a sealant. In embodiments that include a substrate, the substrate may be a semiconductor substrate (such as doped or undoped silicon) or an active layer of an SOI substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Passive devices may include capacitors, resistors, inductors, etc., or combinations thereof. In some embodiments, passive device 230 is a completely passive device (e.g., the substrate has no active or doped regions, such that it does not include active devices), such as an integrated voltage regulator (IVR). In some embodiments, the passive device 230 may be partially passive, for example, it may include some active devices. The passive devices may be formed in and / or on the semiconductor substrate and / or within a sealant, and may be interconnected by interconnect structures to form the passive device 230, the interconnect structures being formed by metallization patterns in one or more dielectric layers, for example, on the main structure.

[0085] The passive device 230 also includes a device connector 232 that is mechanically and electrically connected to the components of the passive device 230. The device connector 232 may be, for example, a microbump, UBM, etc., and may be formed of a conductive material, such as copper, aluminum, tungsten, nickel, or alloys thereof, which may be formed by plating or the like. A dielectric material may laterally seal the device connector 232.

[0086] The passive device 230 may further include a device connector 234 formed on the side of the passive device 230 opposite to the device connector 232. The device connector 234 may be similar to the device connector 232 and may be formed of a similar material. The device connector 234 is mechanically and electrically connected to a component of the passive device 230. The device connector 234 may be formed, for example, by plating. A dielectric material may laterally seal the device connector 234.

[0087] The passive device 230 may also include a substrate via (TSV) 236. The TSV 236 extends through the substrate of the passive device 230 and connects device connectors 234 to device connectors 232. It should be understood that each device connector 232 may not be connected to a corresponding device connector 234. For example, some device connectors 232 (e.g., a first subset) may be connected to the passive components of the passive device 230, while other device connectors 232 (e.g., a second subset) may be connected to the corresponding device connectors 234 via the TSV 236. Additionally, some device connectors 232 may be connected to both the passive components of the passive device 230 and the corresponding device connectors 234.

[0088] The TSV 236 can be formed by applying and developing a suitable photoresist onto the substrate of the passive device 230, and then etching the substrate to form a TSV opening. The TSV opening can be filled with, for example, a pad (not shown), a barrier layer (also not shown), and a conductive material. In embodiments, the pad can be a dielectric material, such as silicon nitride, silicon oxide, dielectric polymers, combinations thereof, etc., formed by processes such as chemical vapor deposition, oxidation, physical vapor deposition, atomic layer deposition, etc. The barrier layer can include a conductive material, such as titanium nitride, but other materials such as tantalum nitride, titanium, another dielectric, etc. can be optionally used. The barrier layer can be formed using a CVD process (such as PECVD). The barrier layer can be formed to match the shape below the TSV opening. The conductive material can include copper, but other suitable materials such as aluminum, tungsten, alloys, doped polysilicon, combinations thereof, etc. can be optionally used. The conductive material can be formed by depositing a seed layer and then electroplating copper onto the seed layer to fill (and possibly overfill) the TSV opening. Once the TSV opening has been filled, excess barrier layer and excess conductive material outside the TSV opening can be removed by planarization processes (such as CMP or grinding processes), but any suitable removal process can be used.

[0089] A conductive connector 238 is formed on the end of the device connector 232 of the passive device 230. The conductive connector 238 may be, for example, a solder ball, and a solder joint is formed between the device connector 232 and the UBM 228. Attaching the passive device 230 to the following structure includes forming the conductive connector 238. Forming the conductive connector 238 may include forming solder balls and reflowing solder balls to form a connection between the device connector 232 and the UBM 228.

[0090] Underfill 240 can be filled into the gap between passive device 230 and dielectric layer 226, and around device connector 232 and conductive connector 238. Underfill 240 can be molding compound, epoxy resin, resin, etc. Underfill 240 provides structural support for passive device 230 and can be distributed using capillary force after passive device 230 is attached to UBM 228. Other processes such as lamination, compression molding, transfer molding, etc., can be used. A curing step can then be performed to cure and harden underfill 240.

[0091] In some embodiments, the passive device 230 may be provided on a substrate (not shown separately). The substrate may be formed of a semiconductor material or other suitable material. After the passive device 230 is attached to the opening 214, the substrate may optionally undergo a thinning process. Such a thinning process may involve techniques such as back-side grinding, chemical mechanical polishing (CMP), or wet etching to reduce (or possibly remove) the thickness of the substrate.

[0092] exist Figure 17 In this configuration, dielectric material 242 is formed above substrate core 202 and in opening 214, for example, around passive device 230 and underfill 240. Dielectric material 242 can be formed from Ajinomoto multilayer film (ABF), epoxy resin, molding compound, epoxy molding compound, glass fiber reinforced resin material, silica filler, polymer material, polyimide material, other multilayer materials, other laminates, or combinations thereof. In some cases, dielectric material 242 can be formed by lamination, where a pre-formed dielectric film is applied using heat and pressure. For example, ABF can be laminated onto the structure using a vacuum lamination process. In other cases, dielectric material 242 can be applied by spin coating, such as when using liquid epoxy resin or polyimide material. Molding compound or epoxy molding compound can be applied using compression molding or transfer molding techniques. In some embodiments, dielectric material 242 can be deposited using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) methods, particularly for certain polymer materials. After application, the dielectric material 242 can undergo a curing process, which may involve heat treatment, UV exposure, or a combination thereof, depending on the specific material used.

[0093] After the dielectric material 242 is formed, it may optionally undergo a thinning process to expose the passive device 230. This thinning process may involve techniques such as chemical mechanical polishing (CMP), grinding, or etching. In some embodiments, a planarization process may be performed to remove excess material and create a substantially flat surface. The thinning process can be controlled to expose the upper surface of the passive device 230. In some cases, a combination of thinning methods, such as an initial grinding step followed by a CMP process, may be used to improve surface finish. After thinning, the exposed surface of the passive device 230 may be substantially coplanar with the surrounding dielectric material 242 (within process variations).

[0094] exist Figure 18 In this process, carrier substrate debonding can be performed to detach (or "debond") the carrier substrate 222 from the structure above it. According to some embodiments, debonding includes projecting light, such as UV light, onto the release layer 224, causing the release layer 224 to decompose under the heat of the light, and the carrier substrate 222 can be removed.

[0095] After substrate debonding, openings 244 can be formed through dielectric material 242, and openings 246 can be formed through dielectric layer 226 and adhesive 212. Various techniques can be used to form openings 244 and 246, such as photolithography followed by etching, laser drilling, mechanical drilling, etc. In some cases, a combination of methods can be used for different layers. Openings 244 and 246 expose conductors 210, providing access to the components beneath them. Furthermore, cleaning processes can be performed to remove any debris or residue, such as that generated by opening formation. This cleaning step can involve techniques such as plasma cleaning, wet chemical cleaning, or mechanical scrubbing to ensure that the openings are free of contaminants that could affect subsequent processing or device performance.

[0096] exist Figure 19 In this configuration, a first routing structure 250 is formed on one side of the substrate core 202. Furthermore, a second routing structure 252 is formed on the other side of the substrate core 202.

[0097] The first routing structure 250 may include multiple routing layers, including conductors, conductive vias, conductive pads, metallization patterns, or redistribution layers. The first routing structure 250 may include multiple routing layers embedded within multiple insulating layers. The routing layers may include one or more conductive materials, such as copper, nickel, aluminum, or combinations thereof. The insulating layers may be formed of materials such as laminated materials, ABF, prepreg, laminated materials, oxides, nitrides, or polymers. In some cases, the outermost routing layer of the first routing structure 250 may include bonding pads to allow physical and electrical connections with other package components. These bonding pads may include conductive pads, conductive pillars, solder bumps, or under-bump metallization (UBM).

[0098] The second routing structure 252 may include multiple routing layers, including conductors, conductive vias, conductive pads, metallization patterns, or redistribution layers. The second routing structure 252 may include multiple routing layers embedded within multiple insulating layers. Routing layers may include one or more conductive materials, such as copper, nickel, aluminum, or combinations thereof. Insulating layers may be formed of materials such as laminates, ABF, prepregs, laminations, oxides, nitrides, or polymers. In some cases, the outermost routing layer of the second routing structure 252 may include bonding pads to allow physical and electrical connections with other package components. These bonding pads may include conductive pads, conductive pillars, solder bumps, or under-bump metallization (UBM).

[0099] The first routing structure 250 and the second routing structure 252 can be coupled to the conductor 210 via vias formed in openings 244 and 246, respectively. Thus, the conductive via 208 in the substrate core 202 can electrically connect the first routing structure 250 to the second routing structure 252. Furthermore, in some embodiments, the first routing structure 250 and the second routing structure 252 can be electrically coupled to the passive device 230. This configuration allows for efficient routing of electrical signals between different layers of the package and to various components including the passive device 230.

[0100] Similar processes can be used to form the first routing structure 250 and the second routing structure 252. These processes may involve creating alternating layers of dielectric material and conductive components. Conductive components (including traces, vias, and pads) can be formed within and between the dielectric layers using techniques such as photolithography, etching, and plating. Each layer can be formed sequentially, with vias providing electrical connections between different metal layers. The process can be repeated multiple times to create a desired number of routing layers.

[0101] A solder resist layer 254 may be formed on the outer surface of the first routing structure 250. The solder resist layer 254 may be applied as a liquid or dry film using techniques such as screen printing, spraying, or lamination. After application, the solder resist layer 254 may be patterned using photolithography to create openings that expose the underlying conductive pads or components to which electrical connections are desired. The patterned solder resist layer 254 may then undergo a curing process, which may involve heat treatment, UV exposure, or a combination thereof, depending on the specific materials used. This solder resist layer 254 helps protect the underlying circuitry from environmental factors and prevents solder bridging during subsequent assembly processes.

[0102] Subsequently, the module substrate 200 can be segmented from adjacent module substrates. The segmentation process can involve sawing, laser cutting, or mechanical separation to divide the larger substrate into smaller, discrete module substrates. The resulting individual module substrates 200 can be included in a substrate package, where they can be combined with other components to form more complex modules.

[0103] After its individual processing is complete, the module substrate 200 can be tested. For example, probe testing can be performed on the module substrate 200 to determine if it is a known good substrate. This testing may involve using automated test equipment with probe cards to make temporary electrical connections to test pads or terminals on the module substrate 200. Testing may include electrical continuity checks, resistance measurements, capacitance measurements, and functional tests to verify the integrity of conductive paths, interlayer insulation, and proper operation of any embedded passive components. In some cases, testing may also involve thermal cycling or stress testing to ensure reliability under various operating conditions. Therefore, only module substrates 200 that are known good substrates undergo subsequent processing, and substrates that fail the probe test are not packaged.

[0104] Other variations of the component substrate 200 are anticipated. In some embodiments, devices (including passive devices) may be omitted from the component substrate 200. Such a component substrate 200 may include a substrate core 202 on which no devices are disposed. This configuration can provide a simpler structure that can still be used as part of the overall package assembly. In some embodiments, the component substrate 200 may be a coreless substrate. A coreless substrate can refer to a substrate without a solid substrate core, such as an FR-4 or BT resin core. Instead, it is constructed of alternating dielectric and conductive layers. A coreless substrate can be formed by sequentially forming and patterning dielectric and conductive materials on a temporary carrier (to be removed later). This type of substrate can provide advantages in certain applications, such as reduced thickness and improved electrical performance. Coreless designs can allow for interconnects with finer pitch and can facilitate easier integration with other package assemblies. Furthermore, coreless substrates can provide better thermal management due to the absence of a thick core layer.

[0105] Figures 20 to 25 It is a system package 300 according to some embodiments (see Figures 24 to 25 A cross-sectional view of an intermediate stage in the manufacturing process of ( ). Figures 20 to 24 This is a cross-sectional view; for clarity, only a portion (e.g., half) of the system package 300 is shown. Figure 25 This is a top view.

[0106] exist Figure 20In this process, a carrier substrate 302 is provided, and a release layer 304 is formed on the carrier substrate 302. The carrier substrate 302 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 302 can be a wafer.

[0107] Release layer 304 may be formed of a polymer-based material, which may be removed together with the carrier substrate 302 from the structure to be formed in subsequent steps. In some embodiments, release layer 304 is an epoxy-based thermally release material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 304 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. Release layer 304 may be dispensed and cured as a liquid, and may be a laminated film, etc., laminated onto the carrier substrate 302. The upper surface of release layer 304 may be flush and may have a high degree of flatness.

[0108] Multiple component substrates 200 are then attached to the release layer 304. The component substrates 200 of desired type and number are placed adjacent to each other. In some embodiments, the component substrates 200 include one or more power distribution substrates and one or more connector substrates. The component substrates 200 can be placed on the release layer 304 using, for example, a pick-and-place tool. In some embodiments, the component substrates 200 are positioned such that their solder resist 254 faces the carrier substrate 302.

[0109] Although not shown separately, it should be understood that some or all of the component substrate 200 may include passive devices (previously described for...). Figure 16 (Description). Furthermore, a subset of the component substrate 200 (such as a power distribution substrate) may include devices, while another subset of the component substrate 200 (such as a connector substrate) may not have devices.

[0110] exist Figure 21 In this process, a sealant 306 is formed on and around various components. After formation, the sealant 306 can seal the component substrate 200. The sealant 306 can be a molding compound, epoxy resin, etc., and can be applied by compression molding, transfer molding, etc. The sealant 306 can be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the sealant 306 is formed over a carrier substrate 302 such that it buries or covers the component substrate 200, and then a planarization process can be performed on the sealant 306 to expose the component substrate 200. The planarization process can be, for example, chemical mechanical polishing (CMP), grinding, etc. After the planarization process, the sealant 306 and the upper surface of the component substrate 200 can be substantially coplanar (within process variations).

[0111] exist Figure 22In this configuration, a redistribution structure 310 is formed over the sealant 306 and the component substrate 200. The redistribution structure 310 includes a dielectric layer 312 and a metallization layer 314 (sometimes referred to as a redistribution layer or redistribution line) located between the dielectric layers 312. Therefore, the redistribution structure 310 includes metallization layers 314 spaced apart from each other by respective dielectric layers 312. The metallization layers 314 of the redistribution structure 310 are connected to conductive components of the upper routing structure of the component substrate 200.

[0112] In some embodiments, the dielectric layer 312 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB-based polymers, etc., and can be patterned using a photolithographic mask. In other embodiments, the dielectric layer 312 is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide), etc. The dielectric layer 312 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. After the dielectric layer 312 is formed, it can be patterned to expose conductive components beneath the component substrate 200 and / or the metallization layer 314. Patterning can be performed by any acceptable process, such as exposing the dielectric layer 312 to light when it is formed of a photosensitive material, or etching using, for example, anisotropic etching. If the dielectric layer 312 is formed of a photosensitive material, it can be developed after exposure.

[0113] Each of the metallization layers 314 includes a conductive via and / or a wire. The conductive via extends through the corresponding dielectric layer 312, and the wire extends along the corresponding dielectric layer 312. As an example of forming the metallization layer 314, a seed layer (not shown separately) is formed over the corresponding underlying component. For example, the seed layer may be formed on the corresponding dielectric layer 312 and in any opening through the corresponding dielectric layer 312. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using a deposition process such as PVD. Photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 314. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as chemical plating or electroplating from the seed layer. The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as wet or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization layer 314 of the redistribution structure 310.

[0114] The redistribution structure 310 is shown as an example. By performing the foregoing steps any desired number of times, more or fewer dielectric layers 312 and metallization layers 314 can be formed than shown.

[0115] Other variations of the redistribution structure 310 are anticipated. For example, some dielectric layers 312 may be formed from sealants such as molding compounds, epoxy resins, etc. A metallization layer 314 may be formed by plating conductive vias from wires. The dielectric layer 312 may be formed by sealing this metallization layer 314. Any desired material stack may be used for the dielectric layer 312.

[0116] Under-bump metallization (UBM) 316 may be formed through the upper dielectric layer 312 of the redistribution structure 310. UBM 316 is physically and electrically coupled to the upper metallization layer 314 of the redistribution structure 310. Each UBM 316 includes a conductive via and a conductive bump. The conductive via extends through the upper dielectric layer 312, and the conductive bump extends along the upper dielectric layer 312. UBM 316 may be formed of the same material as the metallization layer 314. In some embodiments, UBM 316 has different dimensions than the metallization layer 314.

[0117] The structure formed above the carrier substrate 302 at this processing step is a substrate package 320. The substrate package 320 is a reconstructed wafer comprising a plurality of component substrates 200 in a sealant 306, on which a redistribution structure 310 is disposed.

[0118] exist Figure 23 In this example, the wafer package 100 is attached to the redistribution structure 310 of the substrate package 320. Figure 8 The wafer package described herein. Optionally, Figure 9 The wafer package or another wafer package described herein may be attached to the redistribution structure 310.

[0119] In the illustrated embodiment, the wafer package 100 is attached to the substrate package 320 using solder bonding (such as using conductive connectors 322). The conductive connectors 322 may be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connectors 322 are formed by initially forming a solder layer using methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed, reflow can be performed to shape the conductive connectors 322 into a desired bump shape. Attaching the wafer package 100 to the redistribution structure 310 may include placing the wafer package 100 on the redistribution structure 320 and reflowing the conductive connectors 322. The wafer package 100 may be placed on the redistribution structure 310 using, for example, pick-and-place tools. The return conductive connector 322 attaches the UBM 164 of the wafer package 100 to the UBM 316 of the redistribution structure 310, thereby electrically connecting the redistribution structure 310 to the wafer package 100. In another embodiment, the wafer package 100 is attached to the substrate package 320 using direct bonding.

[0120] After the wafer package 100 is attached to the substrate package 320, carrier substrate debonding can be performed to detach (or “debond”) the carrier substrate 302 from the substrate package 320. According to some embodiments, debonding includes projecting light, such as UV light, onto a release layer 304, causing the release layer 304 to decompose under the heat of the light, and allowing the carrier substrate 302 to be removed. Removing the carrier substrate 302 can expose the lower surface of the component substrate 200 (of the substrate package 320) for subsequent attachment of additional components to the substrate package 320.

[0121] exist Figure 24 In this configuration, voltage regulator 324 and external connector 326 are attached to the side of substrate package 320 opposite to wafer package 100. These components allow for efficient power distribution and external connectivity to the resulting system package. Placing these components on the side of substrate package 320 opposite wafer package 100 facilitates easier system maintenance or upgrades.

[0122] Voltage regulator 324 can be a power management device used to maintain a stable voltage level for various components in wafer package 100. These regulators can be implemented in various forms, such as integrated circuit dies, discrete components on a circuit board, multi-chip modules, etc. In some embodiments, voltage regulator 324 can be a system-in-package (SiP) device integrating multiple functions, including power regulation, current sensing, and thermal management. Depending on the specific power requirements of the system, voltage regulator 324 can also be implemented as a switching regulator, a linear regulator, or a combination of both.

[0123] External connectors 326 can serve as interfaces for connecting system components (e.g., wafer package 100) to external systems or components. These connectors can be implemented as ribbon cable receivers, flexible printed circuit receivers, or other types of high-density interconnects. In some embodiments, external connectors 326 can support various communication protocols, such as PCI Express, USB, InfiniBand, custom high-speed interfaces, etc. The design of these connectors allows for easy attachment and removal of external cables or modules, facilitating integration of the resulting system package with external systems.

[0124] The component substrate 200 electrically connects the voltage regulator 324 to the integrated circuit device in the wafer package 100. Similarly, the component substrate 200 electrically connects the external connector 326 to the integrated circuit device in the wafer package 100, enabling communication between the integrated circuit device and an external system.

[0125] Voltage regulator 324 and external connector 326 can be attached to substrate package 320 using reflowable connectors that connect the component to the lower routing structure of component substrate 200. The reflowable connectors can be formed of conductive materials such as solder, copper, aluminum, gold, nickel, silver, tin, or combinations thereof. In some embodiments, the reflowable connectors can be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, etc. The reflowable connectors can be formed by initially forming openings in solder resist layer 254 of component substrate 200. Next, conductive material can be formed in the openings by methods such as evaporation, electroplating, printing, solder transfer, or ball placement. After forming the conductive material, a reflow process can be performed to shape the material into the desired connector structure.

[0126] Attaching the voltage regulator 324 and external connector 326 to the substrate package 320 may involve placing the component onto the substrate package 320 using pick-and-place techniques (e.g., a reflowable connector extending through the solder mask 254), followed by a reflow process to establish a reliable electrical and mechanical connection to the lower routing structure of the component substrate 200. In some embodiments, a jig may be used to facilitate the attachment process. The jig may include an adjustable portion that can be positioned to support the substrate package 320 and the attached component during placement and reflow. The jig may be removed after attaching the voltage regulator 324 and external connector 326. The remaining structure is the system package 300, which may be a SoW (System-on-Wait). The SoW is a complete computing system including computing sites (including devices in the wafer package 100 and the associated voltage regulator 324) and connection sites (including the external connector 326).

[0127] In some embodiments, the voltage regulator 324 and the external connector 326 may correspond one-to-one with the component substrate 200, wherein each component substrate 200 is associated with a single voltage regulator 324 or external connector 326. In other embodiments, multiple voltage regulators 324 or external connectors 326 may be attached to a single component substrate 200, allowing for more flexible power distribution and connectivity options. For example, multiple voltage regulators 324 may be attached to a power distribution substrate, while multiple external connectors 326 may be attached to a connector substrate.

[0128] The component substrate 200 may include a dedicated power distribution substrate for the voltage regulator 324 and a separate dedicated connector substrate for the external connector 326. These different types of component substrates 200 may have different structures, functions, and integrated devices tailored to their specific roles. For example, the power distribution substrate may incorporate components optimized for efficient power delivery, while the connector substrate may be designed with high-speed signal routing and impedance matching in mind. The power distribution substrate may have a different structure compared to the connector substrate. In some aspects, the power distribution substrate may include devices, while the connector substrate may not.

[0129] The substrate package 320 can incorporate any number of component substrates 200. For example, the substrate package 320 may include four component substrates 200 arranged in a 2x2 grid configuration. The number of component substrates 200 can be selected based on factors such as the desired functionality, power requirements, and connectivity needs of the system package 300. This modular approach provides flexibility in system design and allows the substrate package 320 to be customized to meet a variety of application requirements.

[0130] While each component substrate 200 may be smaller than the wafer package 100, the substrate package 320 (comprising multiple component substrates 200) is larger than the wafer package 100. The outer periphery of the substrate package 320 extends beyond the outer periphery of the wafer package 100. In other words, in a cross-sectional view, the width of the substrate package 320 may be greater than the width of the wafer package 100, while in a cross-sectional view, the width of each component substrate 200 may be less than the width of the wafer package 100. The larger size of the substrate package 320 relative to the wafer package 100 allows for the integration of additional routing components and external connections around the wafer package 100, including those that would overhang the edges of the wafer package 100 if directly attached to it.

[0131] The portion of the substrate package 320 extending beyond the outer periphery of the wafer package 100 can be used to attach external connectors 326. These extended regions can provide dedicated areas for incorporating high-density interconnects, such as ribbon cable receivers, flexible printed circuit receivers, or other types of connectors facilitating communication with external systems or components. Simultaneously, the internal portion of the substrate package 320 overlapping with the wafer package 100 can be used to attach voltage regulators 324. This arrangement allows for efficient power distribution to components within the wafer package 100, as the voltage regulators 324 can be located near the devices they support.

[0132] refer to Figure 25 The system package 300 is shown in more detail. Although for clarity... Figure 25 All components discussed below are shown, but it should be understood that wafer package 100 may be located below substrate package 320 (e.g., going to page), and voltage regulator 324 and external connector 326 may be located above wafer package 100 (e.g., leaving page).

[0133] Voltage regulators 324 can be located directly above wafer package 100, with each voltage regulator 324 corresponding to a computing device 70A of wafer package 100 (e.g., a logic die, a memory die, a combination thereof, etc.). Each voltage regulator 324 can provide power to wafer package 100 via routing components in substrate package 320. Positioning the voltage regulators 324 near the devices in wafer package 100 can reduce power loss and / or voltage drop.

[0134] The external connector 326 may be located at the outer periphery of the substrate package 320, positioned along its edge. This placement facilitates easier connection to external components or systems because the external connector 326 is easily accessible at the outer boundary of the system package 300.

[0135] Interface device 70B is located at the edge of wafer package 100, possibly very close to external connector 326. In a top view, interface device 70B is positioned between external connector 326 and the array of voltage regulator 324 and computing device 70A. Interface device 70B can be positioned to reduce the signal path length to external connector 326. Interface device 70B can mediate communication between external connector 326 and computing device 70A, performing signal routing and data transmission within system package 300.

[0136] In the top view, the layout of the components within the system package 300 can be arranged relative to the outer periphery of the wafer package 100. The voltage regulator 324 can be located within the outer periphery of the wafer package 100. Meanwhile, the external connector 326 can be located outside the outer periphery of the wafer package 100. Other variations are possible.

[0137] The substrate package 320 and the wafer package 100 may have different shapes in the top view. The wafer package 100 may be circular (truncated or untruncated), while the substrate package 320 may be square.

[0138] In addition, Figure 25 In the example, the components of system package 300 are symmetrically arranged. In another embodiment, an asymmetrical layout may be used. The layout of system package 300 can be determined based on specific application requirements.

[0139] Figure 26 This is a cross-sectional view of a system-on-a-wafer assembly 400 according to some embodiments. By... Figures 24 to 25 The system package 300 is fixed between the thermal module 402 and the frame 404 to form a system-on-wafer assembly 400. By fixing the system package 300 between the thermal module 402 and the frame 404, the warpage of the system package 300 can be reduced. In this embodiment, the width of the wafer package 100 is smaller than the width of the substrate package 320.

[0140] The thermal module 402 may be attached to the bottom of the system package 300, located on the same side as the wafer package 100. The thermal module 402 is in thermal contact with the wafer package 100. The thermal module 402 may be a heat sink, a heat fin, a cold plate, or a similar device designed to manage heat dissipation of components within the system assembly 400 on the wafer. In some embodiments, the thermal module 402 may have a recess to receive the wafer package 100. The recess may allow the thermal module 402 to make closer contact with the heat-generating components of the wafer package 100 while providing space for other protruding elements.

[0141] Frame 404 is attached to the top of system package 300 to provide structural support and protection for internal components such as voltage regulator 324 and external connector 326. Frame 404 is a rigid support and may be formed of a material with high stiffness, such as a metal, for example, steel, titanium, cobalt, etc. In some embodiments, the on-wafer system assembly 400 may include a spacer (not shown separately) located between frame 404 and substrate package 320. Frame 404 (or spacer, if present) physically engages portions of substrate package 320. Frame 404 has recesses and / or openings for receiving voltage regulator 324 and external connector 326 on this side of substrate package 320. Frame 404 may also have openings for receiving connections (e.g., wires, cables, etc.) from external systems to external connector 326.

[0142] Bolt 406 can be used to secure system package 300 between thermal module 402 and frame 404. Bolt 406 can extend into or pass through thermal module 402 and / or frame 404. Specifically, thermal module 402 and frame 404 can include corresponding bolt holes, which can be threaded or unthreaded. During the assembly process, bolt holes can be drilled in substrate package 320 and wafer package 100 to accommodate bolt 406. When the bolt hole is threaded, bolt 406 can be screwed directly into the threaded hole. When the bolt hole is unthreaded, bolt 406 can be secured using fasteners (not shown separately), such as nuts, washers, etc. Bolt 406 secures the components of system-on-wafer assembly 400 together, providing structural integrity. Bolt 406 (or fasteners on it) can be tightened to a specific torque to apply a desired clamping force on system-on-wafer assembly 400, which can reduce component warpage.

[0143] In some embodiments, a thermal interface material 408 may be applied between the thermal module 402 and the wafer package 100. The thermal interface material 408 enhances the thermal conductivity between the wafer package 100 and the thermal module 402, improving overall heat dissipation in the system-on-wafer assembly 400. The thermal interface material 408 may be a film comprising a material such as indium or other thermally conductive substances.

[0144] In some embodiments, the cooling system 410 may be attached to the frame 404 of the system-on-wafer assembly 400. The cooling system 410 may be part of an external system designed to enhance the thermal management of the assembly. The cooling system may take various forms, such as a liquid cooling system that circulates coolant through channels or pipes integrated into or attached to the frame 404. For example, the cooling system 410 may include a water-cooled device with a pump, radiator, and reservoir. Alternatively, the cooling system 410 may be an air-cooled system with a fan or blower that forces air through a radiator or fin attached to the frame 404. Integration of the cooling system 410 may allow for more efficient heat dissipation from the components within the system-on-wafer assembly 400, potentially enabling higher performance or a more compact design.

[0145] Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to improve yield and reduce costs.

[0146] Figures 27 to 28 This is a view of an intermediate stage in the manufacturing of a substrate package according to some embodiments. This embodiment is similar to... Figures 20 to 25 In one embodiment, the wafer package 100 is formed after (and above) the substrate package 320. Figures 27 to 28 This is a cross-sectional view; for clarity, only a portion (e.g., half) of the system package 300 is shown.

[0147] exist Figure 27 In, to form or obtain Figure 22 The structure can omit UBM 316, except that the wafer package 100 is formed on the redistributed structure 310. The wafer package 100 can be formed, for example, with... Figures 3 to 8 The process described above involves a similar fabrication method, except that the back-side redistribution structure 110 can be built on top of the redistribution structure 310 instead of a separate carrier substrate. This reduces warpage caused by the formation of the back-side redistribution structure 110. Furthermore, the UBM can be omitted from the back-side redistribution structure 110; instead, the metallization layer 114 of the back-side redistribution structure 110 can be directly connected to the metallization layer 314 of the redistribution structure 310. In some cases, this direct connection between redistribution structures can allow for a more compact monolithic package structure.

[0148] In some embodiments, in addition to functional integrated circuit devices, the wafer package 100 may include dummy dies 166. These dummy dies 166 may be located at desired locations within the wafer package 100, possibly overlapping with areas where external interconnects 326 are attached to the substrate package 320. Including dummy dies 166 can be used for various purposes, such as maintaining structural uniformity, improving heat distribution, reducing warpage, or enhancing the overall mechanical stability of the wafer package 100. Where the dummy dies 166 overlap with external interconnects 326 and / or interconnect substrates, they can provide additional support or act as spacers, potentially facilitating a more reliable connection between the wafer package 100 and the substrate package 320.

[0149] exist Figure 28 In the process of forming the wafer package 100, the carrier substrate 302 can be removed. A similar process to that described previously can be performed to complete the system package 300.

[0150] In this embodiment, the wafer package 100 and the substrate package 320 may have substantially the same width. This configuration allows for efficient use of space within the system package 300. In the top view, the voltage regulator 324 and the external connector 326 may be disposed within the outer periphery of the wafer package 100. However, the external connector 326 may still be located outside the integrated circuit device of the wafer package 100. The dummy die 166 included in the wafer package 100 overlaps with the external connector 326, possibly providing additional mechanical support or serving as a spacer.

[0151] Figure 29 This is a cross-sectional view of a system-on-a-wafer assembly 400 according to some embodiments. By... Figure 28 The system package 300 is fixed between the thermal module 402 and the frame 404 to form a system-on-wafer assembly 400, similar to... Figure 26 An embodiment of the present invention. In this embodiment, the width of the wafer package 100 is equal to the width of the substrate package 320.

[0152] The embodiments offer advantages. By implementing the substrate package 320 using the component substrate 200, the outer peripheral region of the substrate package 320 can be effectively used for attaching external connectors 326. With previously unused peripheral regions of the wafer package 100 available for device placement, this approach allows the wafer package 100 to accommodate a greater number of computing devices 70A and interface devices 70B. As a result, overall system density and functionality can be increased without having to increase the footprint of the wafer package 100. Furthermore, this configuration, by strategically and closely placing the voltage regulator 324 and the external connectors 326 near the computing devices 70A and interface devices 70B respectively, can lead to improved power delivery, enhanced signal integrity, and more efficient thermal management.

[0153] The embodiment device includes: a substrate package including a plurality of component substrates and a first sealant surrounding and between the component substrates; a wafer package attached to a first side of the substrate package, the wafer package including a plurality of integrated circuit devices and a second sealant surrounding and between the integrated circuit devices; a plurality of voltage regulators attached to a second side of the substrate package, the component substrates electrically connecting the voltage regulators to the integrated circuit devices; and a plurality of external connectors attached to the second side of the substrate package, the component substrates electrically connecting the external connectors to the integrated circuit devices. In some embodiments of the device, the substrate package further includes a first redistribution structure, the wafer package further includes a second redistribution structure, and the first redistribution structure is attached to the second redistribution structure. In some embodiments of the device, in a top view, the component substrates are arranged in a grid within the substrate package. In some embodiments of the device, the component substrate includes a power distribution substrate and a connector substrate, the voltage regulators are attached to the power distribution substrate, and the external connectors are attached to the connector substrate. In some embodiments of the device, in a top view, the voltage regulators are disposed within the outer periphery of the wafer package, and in a top view, the external connectors are disposed outside the outer periphery of the wafer package. In some embodiments of the device, in a top view, the voltage regulator is disposed within the outer periphery of the wafer package, and in a top view, the external connector is disposed within the outer periphery of the wafer package. In some embodiments of the device, the external connector is a ribbon cable receiver. In some embodiments of the device, the wafer package is circular, and the substrate package is square. In some embodiments of the device, it further includes: a thermal module; a frame having an opening exposing the external connector, wherein the substrate package and the wafer package are disposed between the frame and the thermal module; and a plurality of bolts extending through the thermal module and the frame.

[0154] The embodiment device includes: a thermal module; a frame including an opening; and a system package located between the thermal module and the frame, the system package including: a substrate package including a plurality of connector substrates, a sealant surrounding and between the connector substrates, and a redistribution structure on the sealant; a wafer package attached to the redistribution structure of the substrate package, the width of the substrate package being greater than the width of the wafer package, the wafer package including an integrated circuit device; and a plurality of external connectors attached to the connector substrates of the substrate package, the connector substrates electrically connecting the external connectors to the integrated circuit device, the opening of the frame exposing the external connectors. In some embodiments of the device, the device further includes: a plurality of bolts extending through the thermal module and the frame. In some embodiments of the device, the upper surface of the sealant is coplanar with the upper surface of the connector substrates, and the redistribution structure is located on the upper surface of the sealant and the upper surface of the connector substrates. In some embodiments of the device, at least one connector substrate includes a substrate core and a passive device located within the substrate core. In some embodiments of the device, at least one connector substrate is a coreless substrate.

[0155] The method includes forming a substrate package by: sealing a connector substrate and a power distribution substrate using a molding compound; planarizing the molding compound until its upper surface is coplanar with the upper surfaces of the connector substrate and the power distribution substrate; forming a redistribution structure on the molding compound, the redistribution structure including redistribution lines electrically connected to the connector substrate and the power distribution substrate; attaching a wafer package to the redistribution structure of the substrate package; and attaching an external connector and a voltage regulator to the lower surfaces of the connector substrate and the power distribution substrate, respectively. In some embodiments of the method, the substrate package is formed on a carrier substrate, and forming the substrate package further includes removing the carrier substrate to expose the lower surfaces of the connector substrate and the power distribution substrate. In some embodiments of the method, it further includes forming the power distribution substrate by: forming an opening in the substrate core; and placing a passive device in the opening. In some embodiments of the method, the width of the connector substrate is smaller than the width of the wafer package, the width of the power distribution substrate is smaller than the width of the wafer package, and the width of the substrate package is larger than the width of the wafer package. In some embodiments of the method, it further includes drilling bolt holes in the substrate package and the wafer package; and securing the substrate package and the wafer package between the thermal module and the frame using bolts extending through the bolt holes. In some embodiments of the method, in a top view, the voltage regulator is positioned within the outer periphery of the wafer package, and in a top view, the external connector is positioned outside the outer periphery of the wafer package.

[0156] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A substrate package comprising a plurality of component substrates and a first sealant located between and around the component substrates; A wafer package is attached to a first side of the substrate package, the wafer package including a plurality of integrated circuit devices and a second sealant located between and around the integrated circuit devices; Multiple voltage regulators are attached to a second side of the substrate package, and the component substrate electrically connects the voltage regulators to the integrated circuit device; as well as Multiple external connectors are attached to the second side of the substrate package, and the component substrate electrically connects the external connectors to the integrated circuit device.

2. The semiconductor device according to claim 1, wherein, The substrate package further includes a first redistribution structure, the wafer package further includes a second redistribution structure, and the first redistribution structure is attached to the second redistribution structure.

3. The semiconductor device according to claim 1, wherein, In the top view, the component substrate is arranged in a grid within the substrate package.

4. The semiconductor device according to claim 1, wherein, The component substrate includes a power distribution substrate and a connector substrate, the voltage regulator is attached to the power distribution substrate, and the external connector is attached to the connector substrate.

5. The semiconductor device according to claim 1, wherein, In the top view, the voltage regulator is disposed within the outer periphery of the wafer package, and in the top view, the external connector is disposed outside the outer periphery of the wafer package.

6. The semiconductor device according to claim 1, wherein, In the top view, the voltage regulator is disposed within the outer periphery of the wafer package, and in the top view, the external connector is disposed within the outer periphery of the wafer package.

7. The semiconductor device according to claim 1, wherein, The external connector is a ribbon cable receiver.

8. The semiconductor device according to claim 1, wherein, The wafer package is circular, and the substrate package is square.

9. A semiconductor device, comprising: Hot module; A frame, the frame including an opening; as well as A system package, located between the thermal module and the frame, includes: A substrate package comprising a plurality of connector substrates, a sealant located between and around the connector substrates, and a redistribution structure located on the sealant; A wafer package, attached to the redistribution structure of the substrate package, the substrate package having a width greater than the width of the wafer package, the wafer package including an integrated circuit device; and Multiple external connectors are attached to the connector substrate of the substrate package, the connector substrate electrically connecting the external connectors to the integrated circuit device, and the opening of the frame exposes the external connectors.

10. A method of forming a semiconductor device, comprising: The substrate package is formed through the following steps: Utilizing molding compound sealing connector substrate and power distribution substrate; Planarize the molding compound until the upper surface of the molding compound is coplanar with the upper surface of the connector substrate and the upper surface of the power distribution substrate; and A redistribution structure is formed on the molding compound, the redistribution structure including redistribution lines electrically connected to the connector substrate and the power distribution substrate; The redistribution structure that attaches the wafer package to the substrate package; and The external connector and voltage regulator are respectively attached to the lower surface of the connector substrate and the lower surface of the power distribution substrate.

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