Method for forming a polyimide protective layer on a wafer and wafer stack structure

Abstract

This invention relates to the field of semiconductor processing, and discloses a method for forming a polyimide protective layer on a wafer and a wafer stacking structure. A method for forming a polyimide protective layer on a wafer includes: S1: providing a wafer; S2: forming a polyimide layer on a passivation protective layer; S3: forming a buffer layer over the polyimide layer; S4: coating photoresist over the buffer layer; S5: exposing the photoresist using a mask including a shape associated with the shape of a metal layer; S6: developing the photoresist using a first developer; S7: removing the portion of the buffer layer and the polyimide layer not covered by the photoresist; S8: removing the developed photoresist; and S9: removing the remaining buffer layer. The method according to the invention overcomes the defect of polyimide layer cracking in wafer stacking structures produced in the prior art, thus reliably protecting the internal structure of the chip, improving yield, and reducing manufacturing costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processes, and more particularly to a method for forming a polyimide protective layer on a wafer and a wafer stacking structure. Background Technology

[0002] With the rapid development of artificial intelligence technology, the demand for computing power to support related power and supporting industries has increased significantly. Consequently, the market demand and technical performance requirements for power chips used in power control scenarios have risen simultaneously. As the operating voltage control range of power chips continues to expand, the material performance requirements and design thickness of the polyimide (PI) protective layer used for chip protection are constantly increasing, and the compatibility issues of corresponding new materials and processes are gradually becoming more prominent.

[0003] To achieve better protection and insulation of the chip's internal structure and reduce the interference of external environmental factors on the chip's operational stability, existing technologies typically employ a solution of increasing the thickness of the polyimide protective layer to adapt to the continuously increasing operating voltage requirements of power chips. To form a patterned polyimide protective layer, a patterning process using photoresist is required. Due to limitations in the selectivity of the photoresist used with the polyimide protective layer, a thicker polyimide protective layer necessitates the use of a thicker photoresist.

[0004] On the other hand, for non-photosensitive polyimide systems, a step difference is formed when the polyimide layer covers the passivation protective layer on the chip surface. As the thickness of the polyimide layer increases, the stress concentration effect at this step location intensifies. Therefore, the presence of thicker photoresist and the step difference makes the polyimide layer highly susceptible to fracture defects during the photoresist removal process after development, leading to defects in the final product. While current practices can reduce the probability of polyimide layer cracking to some extent by adjusting the temperature and time parameters of the hot plate baking, they cannot fundamentally eliminate this type of process anomaly.

[0005] Furthermore, the existing standard processing flow for non-photosensitive polyimide is as follows: after the polyimide layer coating and baking processes are completed, the photoresist is directly coated and baked, followed by a simultaneous development process for both the photoresist and the polyimide layer. However, as the thickness of the polyimide layer increases, the thickness of the accompanying photoresist also needs to increase accordingly. The interaction force between the polyimide layer and the photoresist increases accordingly, ultimately leading to cracks in the polyimide film after development due to stress changes and other factors, severely restricting the processing yield of power chips.

[0006] There is a need in the art for a method that can improve the cracking phenomenon of polyimide protective layers in at least one of the above aspects. Summary of the Invention

[0007] The present invention is provided to provide a further improved method for forming a polyimide protective layer on a wafer.

[0008] One aspect of the present invention provides a method for forming a polyimide protective layer on a wafer, comprising the following steps: S1: providing a wafer including a substrate, one or more material layers on the substrate, and a passivation protective layer, the top layer of the one or more material layers including a metal layer, the passivation protective layer being conformally formed with the metal layer; S2: forming a polyimide layer on the passivation protective layer, the polyimide layer including non-photosensitive polyimide; S3: forming a buffer layer over the polyimide layer; S4: coating a photoresist over the buffer layer; S5: exposing the photoresist with a mask including a shape associated with the shape of the metal layer; S6: developing the photoresist using a first developer; S7: removing the portion of the buffer layer and the polyimide layer not covered by the photoresist; S8: removing the developed photoresist; and S9: removing the remaining buffer layer to obtain the polyimide protective layer conformally formed with the passivation protective layer.

[0009] The method described above includes, in step S7: S71: using the first developer to remove the portion of the buffer layer not covered by photoresist; and S72: using a liquid different from the first developer to remove the portion of the polyimide layer not covered by photoresist.

[0010] The method described above includes, in step S7: S73: removing the portion of the buffer layer not covered by photoresist using a second liquid different from the first developer; and S74: removing the portion of the polyimide layer not covered by photoresist using a third liquid different from the first developer and different from the second liquid, or using the second liquid.

[0011] As described above, step S7 is performed during the photolithography process.

[0012] The method described above includes, in step S7: S75: developing the buffer layer using the first developer; and S76: developing the polyimide layer using a developer different from the first developer.

[0013] The method described above includes, in step S7: S77: developing the buffer layer using a second developer that is different from the first developer; and S78: developing the polyimide layer using a third developer that is different from both the first and second developers, or using the second developer.

[0014] As described above, the material of the buffer layer is a photolithography auxiliary material that can be developed using a developer different from the first developer.

[0015] As described above, the buffer layer includes a bottom anti-reflective coating or a spin-coated carbon layer.

[0016] As described above, the thickness of the buffer layer is determined based on the stress of the material of the buffer layer.

[0017] The method described above further includes: S10: pre-baking the buffer layer.

[0018] As described above, the pre-baking temperature of the buffer layer is set to a temperature that does not change the properties of the polyimide layer.

[0019] As described above, the mask includes a shape associated with an opening for electrical connection between the metal layer and the outside.

[0020] Another aspect of the present invention provides a wafer stack structure comprising: a substrate; one or more material layers on the substrate, the top layer of the one or more material layers comprising a metal layer; a passivation protection layer conformally formed on the metal layer; and a patterned polyimide layer obtained by the method according to any one of the preceding claims, conformally formed on the passivation protection layer.

[0021] The wafer stacking structure described above is used for automotive power chips.

[0022] Using the method of the present invention for forming a polyimide protective layer on a wafer, the stress on the polyimide layer during development is significantly reduced. Even with a significant increase in the thickness of both the polyimide layer and the overlying photoresist, the integrity and stability of the polyimide layer are maintained after photoresist removal, thereby achieving the desired protection of the internal structure of the chip and ensuring that the device performance meets design requirements. Attached Figure Description

[0023] Some embodiments of this disclosure have been described with reference to the accompanying drawings. This description, together with the drawings, makes it apparent to those skilled in the art how some embodiments can be practiced. The drawings are for illustrative purposes and do not attempt to show structural details of the embodiments in more detail than necessary for a basic understanding of this disclosure.

[0024] Figure 1 The diagram illustrates a schematic of the existing non-photosensitive polyimide process.

[0025] Figure 2 This is a cross-sectional view of a wafer stacking structure according to some embodiments of the present invention.

[0026] Figure 3 The diagram illustrates the cracking of the polyimide layer caused by existing technology.

[0027] Figure 4 This is a flowchart of a method for forming a polyimide protective layer on a wafer according to some embodiments of the present invention.

[0028] Figure 5 This is a flowchart of a first process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention.

[0029] Figure 6 This is a flowchart of a second process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention.

[0030] Figure 7 This is a flowchart of a third process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention.

[0031] Figure 8 This is a flowchart of a fourth process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention.

[0032] Figures 9-17 The illustrations show some embodiments of the invention. Figures 4-8 A schematic diagram of the stages of forming a polyimide protective layer using any of the methods or processes described above.

[0033] It will be understood that, for the sake of brevity and clarity, the elements shown in the accompanying drawings are not necessarily drawn to scale. For example, some dimensions of elements may be exaggerated relative to others for clarity. Additionally, reference numerals may be repeated between drawings where deemed appropriate to indicate corresponding or similar elements. Detailed Implementation

[0034] Numerous specific details are set forth in the following detailed description in order to provide a thorough understanding of the subject matter of this disclosure. However, those skilled in the art will understand that the subject matter of this disclosure can be practiced without these specific details. In other instances, well-known methods, processes, and components have not been described in detail so as not to obscure the subject matter of this disclosure.

[0035] In the specification and claims of this application, the words “comprising” and “having” and their various forms are not limited to members of the list that may be associated with these words.

[0036] As used herein, the term "about" can be used to specify that the value of a quantity or parameter (e.g., the length of an element) is within a continuous range of values ​​near (and including) a given (specified) value. According to some embodiments, "about" can specify that the value of a parameter is between 80% and 120% of a given value. For example, the statement "the length of the element is approximately 1 m" is equivalent to the statement "the length of the element is between 0.8 m and 1.2 m." According to some embodiments, "about" can specify that the value of a parameter is between 90% and 110% of a given value. According to some embodiments, "about" can specify that the value of a parameter is between 95% and 105% of a given value.

[0037] As used herein, the terms “substantially” and “about” are interchangeable according to some embodiments.

[0038] In this application, ordinal numbers such as "first," "second," and "third" are used to distinguish different instances of objects with the same name. The ordinal numbers "first," "second," and "third" do not indicate a relative order of the indicated objects in time, space, sequence, or other aspects.

[0039] In this application, the term "conformal" refers to a thin film / structure prepared by deposition, etching or growth processes that maintains a contour fit with the existing surface morphology of the underlying substrate.

[0040] In this application, the term "step" refers to a three-dimensional morphological structure formed on the substrate surface by processes such as photolithography, etching, and deposition, which has a height difference from the substrate reference plane.

[0041] In this application, the term "buffer layer" refers to a layer that buffers the stress between the polyimide layer and the photoresist in the process according to an embodiment of the invention.

[0042] Polyimide is the mainstream material for chip protection layers in current wafer manufacturing and advanced packaging fields due to its excellent insulation properties, high temperature stability, chemical corrosion resistance and mechanical flexibility. According to process adaptability, it can be divided into two categories: photosensitive polyimide and non-photosensitive polyimide. The characteristics and applicable scenarios of the two are clearly different.

[0043] The core characteristic of photosensitive polyimide is that the material itself contains photosensitive groups, which can simultaneously achieve the pattern transfer function of photoresist and the insulating and protective function of polyimide. It has shorter processing steps and better thermal compatibility with silicon substrates. However, the material cost is higher than that of non-photosensitive polyimide, and the volume shrinkage rate during curing is typically about 15%-25%. Its coverage of steep steps with a height of 5μm or more is slightly lower than that of non-photosensitive polyimide of the same viscosity. This type of material is suitable for patterning scenarios requiring low to medium precision, such as surface passivation layers for consumer electronics chips, dielectric layers for redistribution layers (RDLs) in advanced packaging, and bottom fill protective layers for flip chips.

[0044] The core characteristic of non-photosensitive polyimide is that the material itself has no photosensitive groups, requiring additional photoresist for patterning. It offers greater flexibility in formulation adjustments, typically exhibits a curing shrinkage rate of less than 10%, provides superior coverage for steep morphologies with step heights exceeding 10 μm, and has a lower material cost compared to photosensitive polyimide. This type of material is suitable for applications requiring high reliability and precision, such as passivation layers for automotive electronics and aerospace-grade chips, insulating linings for through-silicon vias (TSVs), and sacrificial / support layers for microelectromechanical systems (MEMS) devices. It is also suitable for large-scale, mature process chip mass production scenarios where material cost is a concern.

[0045] This invention aims to address the defect of cracking that easily occurs in the process of non-photosensitive polyimide protective layers. In the following description, for convenience, unless otherwise explicitly stated, "polyimide" refers to "non-photosensitive polyimide".

[0046] Figure 1 The diagram illustrates a schematic of the existing non-photosensitive polyimide process.

[0047] For the preparation of non-photosensitive polyimide as a chip protective layer, the conventional process includes the following steps in sequence.

[0048] First, non-photosensitive polyimide is spin-coated onto the surface of the silicon wafer to be treated (e.g., spin-coating at approximately 1000-5000 rpm for approximately 30-60 s) to form a uniform wet film with a thickness of approximately 1-20 μm. Next, the spin-coated wafer is placed on a hot plate at, for example, approximately 130°C and baked for approximately 60-180 s to remove most of the organic solvent from the polyimide wet film.

[0049] Next, positive or negative photoresist is spin-coated onto the pre-baked polyimide layer. The spin-coating speed is typically 2000-4000 rpm, and the photoresist thickness is determined based on the subsequent etching selectivity. Subsequently, the spin-coated wafer is placed on a hot plate at approximately 90-110°C and baked for about 60-120 seconds to remove the solvent from the photoresist.

[0050] Next, the mask is exposed using ultraviolet (UV) light of the corresponding wavelength according to the target pattern, which alters the solubility of the photoresist. The exposed wafer is then sprayed or immersed in a developer solution (e.g., an alkaline solution) corresponding to the photoresist to remove the photoresist in the soluble areas and simultaneously remove the corresponding areas in the polyimide layer.

[0051] Subsequently, the remaining photoresist after development is removed using either a dry or wet process. Dry processes typically employ oxygen plasma ashing; wet processes can use organic solvents such as acetone or N-methylpyrrolidone (NMP) to strip the photoresist. Finally, the stripped wafer is placed in an oven for stepped temperature curing to form a final chip protective layer with stable insulation and temperature resistance.

[0052] The existing process described above generally carries the risk of polyimide layer cracking during the adhesive removal step. This defect is caused by multi-source stress coupling, and the probability of cracking increases significantly with the increase of polyimide layer thickness.

[0053] During dry resist stripping, oxygen plasma bombardment causes uneven cross-linking modification on the surface of the polyimide layer, creating a significant internal stress difference between the surface and inner layers. Simultaneously, the localized temperature rise during plasma treatment leads to interfacial stress between the polyimide layer and the silicon substrate, as well as residual photoresist, due to the mismatch in their coefficients of thermal expansion. In contrast, during wet resist stripping, organic solvents such as acetone and NMP penetrate the polyimide pores, generating swelling stress. The rapid evaporation of these solvents after stripping induces shrinkage stress in the film. This alternating effect of two stresses directly creates microcrack initiations within the film.

[0054] When the polyimide layer thickness is <5μm, the overall stress of the film layer can still be released through slight deformation; however, when the thickness is ≥5μm, the stress gradient inside the film layer increases significantly with the increase of thickness, and the stress cannot be completely released through uniform deformation. Microcracks will preferentially propagate at stress concentration points such as step corners, and the risk of cracking increases significantly. Ultimately, this leads to a decrease in the insulation performance and corrosion resistance failure of the polyimide protective layer, causing chip reliability failure.

[0055] According to one aspect of the present invention, a wafer stacking structure is provided.

[0056] Figure 2 This is a cross-sectional view of a wafer stacking structure according to some embodiments of the present invention.

[0057] In some embodiments, the wafer stack structure includes a substrate 210, one or more material layers 220, a passivation (PAD) layer 230, and a patterned polyimide layer 245.

[0058] One or more material layers 220 are disposed above the substrate 210. The top layer of the one or more material layers 220 may include a metal layer 225 for implementing electrical interconnect functions of the device. A PAD layer 230 is conformally formed on the metal layer 225. The PAD layer 230 may have multiple openings for subsequent packaging wiring. A patterned polyimide layer 245 may be conformally formed above the PAD layer 230. The pattern of the patterned polyimide layer 245 is substantially consistent with the pattern of the PAD layer 230. The patterned polyimide layer 245 can be described in conjunction with the following... Figures 4-8 The described methods or processes are used to form the wafer stacking structure. According to some embodiments, the wafer stacking structure can provide additional protection such as corrosion resistance, high temperature resistance, and radiation protection for special chips with high reliability requirements.

[0059] The "step" or "step difference" of the polyimide layer refers to the height difference between its surface morphology and the original morphology of the underlying PAD layer and metal layer. The PAD layer itself has an open structure, and the underlying metal layer has a naturally occurring raised morphology due to interconnect traces, together forming the basis of the lower layer's step. The polyimide layer needs to form an open pattern corresponding to the PAD layer, creating a step difference at the corresponding location, such as... Figure 2 The area shown by the dashed line.

[0060] The corners and sidewall edges of the steps are structural abrupt change points with discontinuous morphology. In conventional polyimide processes, the internal stress, interfacial stress, and swelling / shrinkage stress generated during the debonding process will be superimposed at these locations, far exceeding the inherent toughness threshold of the polyimide material, leading to cracking.

[0061] Defects caused by existing technology, such as cracking of the polyimide layer (especially at steps), are as follows: Figure 3 As shown in the image.

[0062] According to another aspect of the present invention, a method for forming a polyimide protective layer on a wafer is provided.

[0063] Figure 4 This is a flowchart of a method for forming a polyimide protective layer on a wafer according to some embodiments of the present invention.

[0064] In some examples, the method may include step S1: providing a wafer. The wafer may include a substrate, one or more material layers on the substrate, and a passivation protection layer. The top layer of the one or more material layers may include a metal layer, and the passivation protection layer may be conformally formed with the metal layer. In some embodiments, the one or more material layers may include material layers required for the functionality and / or structure of the final chip product. As an example, the one or more material layers may be formed by a deposition process and optionally a patterning process.

[0065] In some examples, the method may include step S2: forming a polyimide layer on the passivation protective layer. The polyimide layer may include a non-photosensitive polyimide.

[0066] In some examples, the method may include step S3: forming a buffer layer over the polyimide layer.

[0067] In some examples, the method may include step S4: applying photoresist over the buffer layer.

[0068] In some examples, the method may include step S5: exposing the photoresist with a mask that includes a shape associated with the shape of the metal layer.

[0069] In some examples, the method may include step S6: developing the photoresist using a first developer.

[0070] In some examples, the method may include step S7: removing the portions of the buffer layer and polyimide layer that are not covered by photoresist.

[0071] In some examples, the method may include step S8: removing the developed photoresist.

[0072] In some examples, the method may include step S9: removing the remaining buffer layer to obtain a polyimide protective layer conforming to the passivation protective layer.

[0073] In some examples, the material of the buffer layer can be a photolithography aid that can be developed using a developer different from the first developer.

[0074] In some examples, the buffer layer may include a bottom anti-reflective coating or a spin-coated carbon layer. In some examples, the thickness of the buffer layer may be determined based on the stress of the buffer layer material.

[0075] In some examples, the method may optionally further include step S10: pre-baking the buffer layer. In some examples, the pre-baking temperature of the buffer layer may be set to a temperature that does not alter the properties of the polyimide layer.

[0076] In some examples, the mask includes a shape associated with an opening for electrical connection between the metal layer and the outside.

[0077] The following will combine Figures 9-17 describe Figure 4 Further implementation details of the method.

[0078] Figure 5 This is a flowchart of a first process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention. The first process may be... Figure 4 The specific implementation of step S7 in the method is described, but the scope of the present invention is not limited thereto.

[0079] In one embodiment, the first process may include step S71: using a first developer to remove the portion of the buffer layer not covered by photoresist. In another embodiment, the first process may include step S72: using a liquid different from the first developer to remove the portion of the polyimide layer not covered by photoresist.

[0080] Figure 5The first process corresponds to the following scenario: the buffer layer can be treated with the same developer as the photoresist development process, without the need for a separate developer for the buffer layer; another liquid can be used to remove the parts of the polyimide layer that are not covered by the photoresist (as a mask).

[0081] Figure 6 This is a flowchart of a second process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention. This second process may be... Figure 4 This is another specific implementation of step S7 in the method, but the scope of the present invention is not limited thereto.

[0082] In one embodiment, the second process may include step S73: removing the portion of the buffer layer not covered by photoresist using a second liquid different from the first developer. In another embodiment, the second process may include step S74: removing the portion of the polyimide layer not covered by photoresist using a third liquid different from both the first developer and the second liquid, or using the second liquid.

[0083] Figure 6 The second process corresponds to the following process scenario: the buffer layer can be treated with a different developing solution than the photoresist developing process; and when removing the part of the polyimide layer not covered by photoresist (as a mask), a liquid different from that used for both the photoresist and the buffer layer can be used (the parts of the buffer layer and the polyimide layer not covered by photoresist are removed sequentially), or the same liquid used for the buffer layer can be used (the parts of the buffer layer and the polyimide layer not covered by photoresist are removed simultaneously).

[0084] Figure 7 This is a flowchart of a third process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention. This third process may be... Figure 4 This is another specific implementation of step S7 in the method, but the scope of the present invention is not limited thereto.

[0085] In an embodiment, the third process may correspond to the case where step S7 is performed in the photolithography process.

[0086] In an embodiment, the third process may include step S75: developing the buffer layer using a first developer. In an embodiment, step S75 may be combined with... Figure 4 The third process is performed together with step S6. In an embodiment, the third process may include step S76: developing the polyimide layer using a developer different from the first developer.

[0087] Figure 7The third process corresponds to the following process scenario: the development of photoresist, buffer layer and polyimide layer is completed in the photolithography process; the buffer layer can be treated with the same developer as the photoresist development process (using one developer to remove the corresponding areas of photoresist and buffer layer at the same time); another developer can be used to remove the part of polyimide layer that is not covered by photoresist (as a mask).

[0088] Figure 8 This is a flowchart of a fourth process associated with a method for forming a polyimide protective layer on a wafer, according to some embodiments of the present invention. This fourth process may be... Figure 4 This is another specific implementation of step S7 in the method, but the scope of the present invention is not limited thereto.

[0089] In an embodiment, the fourth process may correspond to the case where step S7 is performed in the photolithography process.

[0090] In one embodiment, the fourth process may include step S77: developing the buffer layer using a second developer that is different from the first developer. In another embodiment, the fourth process may include step S78: developing the polyimide layer using a third developer that is different from both the first and second developers, or using the second developer.

[0091] Figure 8 The fourth process corresponds to the following process scenario: the development of photoresist, buffer layer and polyimide layer is completed in the photolithography process; the buffer layer can be treated with a different developer than the photoresist development process; when removing the part of the polyimide layer not covered by photoresist (as a mask), a different developer than the one used for photoresist and buffer layer can be used (the parts of the buffer layer and polyimide layer not covered by photoresist are removed sequentially by development), or the same developer as the one used for buffer layer can be used (the parts of the buffer layer and polyimide layer not covered by photoresist are removed simultaneously by development).

[0092] The following will combine Figures 9-17 describe Figures 5-8 Further implementation details of any of the processes.

[0093] Figures 9-17 The illustrations show some embodiments of the invention. Figures 4-8 A schematic diagram of the stages of forming a polyimide protective layer using any of the methods or processes described above.

[0094] like Figure 9As shown, a wafer is first provided, which may include a substrate 210, one or more material layers 220 on the substrate 210, and a passivation protection layer 230. The top layer of the one or more material layers 220 includes a metal layer 225, and the passivation protection layer 230 is conformally formed with the metal layer 225. The passivation protection layer 230 may include one or more openings for providing electrical connections between the metal layer 225 and the outside.

[0095] Next, as Figure 10 As shown, a polyimide layer 240 is formed on the passivation protective layer 230. The polyimide layer 240 may include a non-photosensitive polyimide. The following is in conjunction with... Figures 11-17 The described process aims to pattern the polyimide layer 240 so that it has a pattern substantially consistent with the passivation protective layer 230.

[0096] Subsequently, as Figure 11 As shown, a buffer layer 250 is formed over the polyimide layer 240. The material of the buffer layer 250 can be a photolithography aid material, which can be developed using a developer different from the developer used with the photoresist. As an example, the buffer layer 250 may include a bottom anti-reflective coating or a spin-coated carbon layer.

[0097] It should be noted that the thickness of the buffer layer 250 can be determined based on the stress of the specific buffer material used, and this thickness is much smaller than the thickness of the polyimide layer 240. For example, the thickness of the buffer layer 250 can be less than about 10% of the thickness of the polyimide layer 240. For example, when the thickness of the polyimide layer 240 is about 10 μm, the thickness of the buffer layer 250 can be about 0.5 μm. Under the condition of satisfying the process requirements, it is desirable that the ratio of the thickness of the buffer layer 250 to the thickness of the polyimide layer 240 be as small as possible.

[0098] The buffer layer 250 may optionally be pre-baked. When the buffer layer 250 is pre-baked, the pre-baking temperature is set to a temperature that does not change the properties of the polyimide layer 240.

[0099] like Figure 12 As shown, photoresist 260 is applied over buffer layer 250 to pattern polyimide layer 240. The photoresist 260 is then exposed using a mask with a shape associated with the shape of metal layer 225 to obtain exposed photoresist. The mask may include a shape associated with an opening for electrical connection between metal layer 225 and the outside.

[0100] Subsequently, the photoresist 260 is developed using a developer to obtain developed photoresist 265, and the portions of the buffer layer 250 and polyimide layer 240 not covered by the developed photoresist 265 are removed. This can be achieved by development (e.g., with...) Figure 7 The third process or Figure 8 corresponds to the fourth process in [reference], but the present invention is not limited thereto) or etching (e.g., corresponding to the first process in [reference] or Figure 5 the first process in [reference] or Figure 6 the second process in [reference], but the present invention is not limited thereto). Depending on the material of the buffer layer 250, the corresponding part of the buffer layer 250 can be removed using the developer solution for the photoresist 260, or another liquid can also be used to remove the corresponding part of the buffer layer 250. The liquid used to remove the corresponding part of the polyimide layer 240 is different from the developer solution for the photoresist 260, but can be the same as or different from the liquid used to remove the buffer layer 250.

[0101] Specifically, three different liquids can be used to process the photoresist 260, the buffer layer 250, and the polyimide layer 240 respectively, successively obtaining the developed photoresist 265 as shown in Figure 13 [reference], Figure 14 the patterned buffer layer 255 in [reference], and Figure 15 the patterned polyimide layer 245 in [reference].

[0102] As an alternative, the same developer solution can also be used to process the photoresist 260 and the buffer layer 250, directly obtaining the structure as shown in Figure 14 [reference], which includes the developed photoresist 265 and the patterned buffer layer 255. Then, a different developer solution or other liquid is used to process the polyimide layer 240, obtaining the structure as shown in Figure 15 [reference], which includes the patterned polyimide layer 245.

[0103] As a further alternative, the photoresist 260 can be developed first using a developer solution, obtaining the structure as shown in Figure 13 [reference], which includes the developed photoresist 265. Then, another developer solution or other liquid is used to process the buffer layer 250 and the polyimide layer 240 simultaneously, directly obtaining the structure as shown in Figure 15 [reference], which includes the patterned buffer layer 255 and the patterned polyimide layer 245.

[0104] After that, the developed photoresist 265 is removed through a photoresist stripping process to obtain the structure as shown in Figure 16 [reference]. Finally, the patterned buffer layer 255 is removed to obtain the structure as shown in Figure 17 [reference]. Figure 17 The structure shown in [reference] is the wafer stack structure formed according to the embodiment of the present invention, corresponding to the structure shown in Figure 2 [reference].

[0105] The advantage of embodiments of the present invention lies in the addition of a buffer material between the polyimide layer and the photoresist. This buffer material not only smooths out the unevenness caused by the PAD step difference but also buffers the stress on the polyimide material during photoresist removal, thereby improving the cracking phenomenon of the polyimide layer caused by this process. Embodiments of the present invention, by introducing combinations of materials and processes with different materials and stresses, reduce the stress on the polyimide layer during the photoresist stripping process after development, thus enabling the polyimide layer to form a complete and stable morphology.

[0106] The method according to embodiments of the present invention improves the yield of manufacturing high-precision chips, thereby reducing production costs and improving the reliability and stability of chip structures.

[0107] It will be understood that, for clarity, certain features of this disclosure described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for brevity, various features of this disclosure described in the context of a single embodiment may also be provided individually, or in any suitable sub-combination, or appropriately provided in any other described embodiment of this disclosure. Unless expressly stated otherwise, any feature described in the context of an embodiment should not be considered an essential feature of that embodiment.

[0108] Although the operations of a method may be described in a specific sequence according to some embodiments, the methods of this disclosure may include some or all of the methods performed in a different order. Specifically, it should be understood that the order of operations and sub-operations of any described method may be reordered, for example, when a later operation requires the output of a previous operation as input, or when a later operation requires the product of a previous operation. The methods of this disclosure may include some or all of the described operations. Unless expressly stated otherwise, no particular operation of the disclosed methods should be considered an essential operation of the method.

[0109] Furthermore, the terms “front,” “back,” “top,” “bottom,” “above,” “below,” etc. (if any) used in the specification and claims are for descriptive purposes and are not necessarily used to describe persistent relative positions. It should be understood that such terms are interchangeable where appropriate, such that the embodiments described herein can, for example, operate in orientations other than those illustrated or otherwise described herein.

[0110] Although this disclosure has been described in conjunction with specific embodiments thereof, it will be apparent that numerous alternatives, modifications, and variations are possible and will be obvious to those skilled in the art. Therefore, this disclosure encompasses all such alternatives, modifications, and variations falling within the scope of the appended claims. It should be understood that this disclosure is not necessarily limited in its application to the details of the construction and arrangement of the components and / or methods set forth herein. Other embodiments may also be practiced, and embodiments may be implemented in various ways.

[0111] It will be understood that the wording and terminology used herein are for descriptive purposes and should not be considered restrictive. Therefore, those skilled in the art will understand that the concepts upon which this disclosure is based can serve as the basis for designing other structures, methods, and systems for carrying out the various purposes of this disclosure.

[0112] Those skilled in the art will readily understand that various modifications and changes can be applied to the embodiments of the present disclosure as described above without departing from the scope defined in and by the appended claims.

Claims

1. A method for forming a polyimide protective layer on a wafer, characterized in that, Includes the following steps: S1: A wafer is provided, the wafer including a substrate, one or more material layers on the substrate and a passivation protection layer, the top layer of the one or more material layers including a metal layer, and the passivation protection layer being conformally formed with the metal layer; S2: A polyimide layer is formed on the passivation protective layer, wherein the polyimide layer comprises a non-photosensitive polyimide; S3: A buffer layer is formed above the polyimide layer; S4: Apply photoresist over the buffer layer; S5: Expose the photoresist using a mask that includes a shape associated with the shape of the metal layer; S6: Develop the photoresist using the first developing solution; S7: Remove the portions of the buffer layer and the polyimide layer that are not covered by photoresist; S8: Remove the developed photoresist; as well as S9: Remove the remaining buffer layer to obtain the polyimide protective layer that conforms to the passivation protective layer.

2. The method according to claim 1, characterized in that, S7 includes: S71: Use the first developer to remove the portion of the buffer layer not covered by photoresist; and S72: Use a liquid different from the first developer to remove the portion of the polyimide layer not covered by photoresist.

3. The method according to claim 1, characterized in that, S7 includes: S73: Remove the portion of the buffer layer not covered by photoresist using a second liquid different from the first developer; and S74: Use a third liquid that is different from the first developer and different from the second liquid, or use the second liquid to remove the portion of the polyimide layer that is not covered by photoresist.

4. The method according to claim 1, characterized in that, S7 is performed during the photolithography process.

5. The method according to claim 4, characterized in that, S7 includes: S75: Develop the buffer layer using the first developer; and S76: Develop the polyimide layer using a developer different from the first developer.

6. The method according to claim 4, characterized in that, S7 includes: S77: Develop the buffer layer using a second developer, different from the first developer; and S78: Develop the polyimide layer using a third developer that is different from the first developer and different from the second developer, or using the second developer.

7. The method according to claim 1, characterized in that, The material of the buffer layer is a photolithography auxiliary material that can be developed using a developer different from the first developer.

8. The method according to claim 7, characterized in that, The buffer layer includes a bottom anti-reflective coating or a spin-coated carbon layer.

9. The method according to claim 1, characterized in that, The thickness of the buffer layer is determined based on the stress of the material of the buffer layer.

10. The method according to claim 1, characterized in that, Further includes: S10: Pre-bake the buffer layer.

11. The method according to claim 10, characterized in that, The pre-baking temperature of the buffer layer is set to a temperature that does not change the properties of the polyimide layer.

12. The method according to claim 1, characterized in that, The mask includes a shape associated with an opening for electrical connection between the metal layer and the outside.

13. A wafer stacking structure, characterized in that, include: Substrate; One or more material layers on the substrate, wherein the top layer of the one or more material layers includes a metal layer; A passivation protective layer is conformally formed on the metal layer; as well as A patterned polyimide layer obtained by the method according to any one of claims 1-12 is conformally formed on the passivated protective layer.

14. The wafer stacking structure according to claim 13, characterized in that, The wafer stacking structure is used for automotive power chips.

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