Electronic package structure with high thermal and electromagnetic shielding and method of manufacture

Abstract

An electronic packaging structure and manufacturing method with high thermal conductivity and electromagnetic shielding are disclosed. The electronic packaging structure includes a circuit board, a chip, an electromagnetic shielding layer, a passivation layer, a dielectric layer, a solder composite layer, a thermally conductive metal layer, and a heat sink. The chip is disposed on the upper surface of the circuit board and has a grounding via electrically connected to the grounding line of the circuit board. The electromagnetic shielding layer is disposed on the surface of the chip. The passivation layer is disposed on the electromagnetic shielding layer. The dielectric layer is disposed on the passivation layer. The solder composite layer includes a solder substrate layer and a tin layer. The solder substrate layer is disposed on the dielectric layer, and the tin layer is disposed on the solder substrate layer. The thermally conductive metal layer is disposed on the tin layer. The heat sink is disposed on the thermally conductive metal layer, and the inner tin layer of the heat sink and the thermally conductive metal layer together form an intermetallic compound layer to fix the heat sink to the solder substrate layer. Multiple solder balls are disposed on the lower surface of the circuit board.

Description

Technical Field

[0001] This invention relates to an electronic packaging structure with high thermal conductivity and electromagnetic shielding, and more particularly to an electronic packaging structure that provides a chip therein with good thermal conductivity and electromagnetic shielding. Background Technology

[0002] With advancements in semiconductor manufacturing technology, the heat generated by semiconductor chips continues to increase. Therefore, the need for heat dissipation in semiconductor chips is becoming increasingly important. Currently, the main heat dissipation pathways for semiconductor chips can be divided into two categories: first, conduction through the packaging structure to the printed circuit board and package surface; and second, transfer from the printed circuit board and package surface to the atmosphere through convection and radiation. Therefore, if heat can be quickly transferred to the printed circuit board and package surface, good heat dissipation performance can be achieved.

[0003] In addition, high-power radio frequency chips also need to deal with the problem of electromagnetic waves. External electromagnetic waves can interfere with semiconductor chips, leading to performance degradation. Therefore, it is necessary to effectively isolate electromagnetic waves to limit interference to semiconductor chips.

[0004] Existing technologies provide a metal cap around the semiconductor wafer and use a thermal interface material (TIM), such as common silicon-based thermal paste, to apply between the metal cap and the wafer to reduce contact thermal resistance. However, silicon-based thermal paste has a low thermal conductivity, typically 3–8 W / (m·K), resulting in slow heat transfer to the metal cap. Furthermore, prolonged exposure to high temperatures often causes the silicon-based thermal paste to harden, significantly impacting overall heat dissipation efficiency.

[0005] To achieve electromagnetic shielding, existing technologies use conductive adhesive to connect to the grounding terminal of the substrate. However, when the metal cover is connected to the grounding terminal of the substrate, the conductive adhesive is prone to short-circuiting due to process or environmental temperature differences, connecting to other circuits.

[0006] Therefore, how to improve the electronic packaging structure and enhance its heat dissipation and electromagnetic shielding effects to overcome the aforementioned defects has become an important issue that needs to be addressed in this technical field. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide an electronic packaging structure with high thermal conductivity and electromagnetic shielding, which improves the thermal conductivity between the chip and the heat sink on the one hand, and improves the electromagnetic shielding effect of the chip on the other hand.

[0008] To solve the aforementioned technical problems, one technical solution adopted by the present invention is to provide an electronic packaging structure with high thermal conductivity and electromagnetic shielding, comprising a circuit board, the circuit board including an upper surface, a lower surface, and at least one grounding line disposed on the upper surface; a chip having a bottom surface, a top surface, multiple side surfaces, and at least one grounding via, the at least one grounding via connecting the bottom surface to the top surface, the bottom surface of the chip being disposed on the upper surface of the circuit board, and the at least one grounding via being electrically connected to the at least one grounding line of the circuit board; and an electromagnetic shielding layer. On the top surface and the plurality of sides of the chip: a passivation layer disposed on the electromagnetic shielding layer; a dielectric layer disposed on the passivation layer; a solder composite layer including a solder substrate layer and a tin layer, the solder substrate layer being disposed on the dielectric layer and the tin layer being disposed on the solder substrate layer; a thermally conductive metal layer disposed on the tin layer; a heat sink disposed on the thermally conductive metal layer, the heat sink having an inner tin layer, wherein the thermally conductive metal layer and the inner tin layer together form an intermetallic compound layer to fix the heat sink to the solder substrate layer; and a plurality of solder balls disposed on the lower surface of the circuit board.

[0009] One of the beneficial effects of this invention is that the electronic packaging structure with high thermal conductivity and electromagnetic shielding provided by this invention can provide electromagnetic shielding for the chip by placing an electromagnetic shielding layer on the chip, connecting a thermally conductive metal layer to the top surface of the chip, and connecting it to the grounding line of the circuit board through the grounding via of the chip. Furthermore, by utilizing liquid-phase diffusion bonding, the thermally conductive metal layer and the tin layer form an intermetallic compound layer, which can effectively fix the heat sink to the solder composite layer, allowing residual heat from the chip to dissipate outwards through the heat sink. The electronic packaging structure with high thermal conductivity and electromagnetic shielding of this invention has better thermal conductivity than traditional thermal paste bonding methods.

[0010] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0011] Figure 1A This is a schematic diagram of the wafer of the present invention disposed on a temporary carrier.

[0012] Figure 1B This is a schematic diagram illustrating the formation of an electromagnetic shielding layer, a passivation layer, and a dielectric layer on a wafer according to the present invention.

[0013] Figure 1C This is a schematic diagram of the welded composite layer formed according to the present invention.

[0014] Figure 1D This is a schematic diagram illustrating the removal of the temporary carrier plate according to the present invention.

[0015] Figure 1E This is a schematic diagram of the present invention where a wafer is disposed on a circuit substrate in a flip-chip manner.

[0016] Figure 1F This is a schematic diagram illustrating the thermally conductive metal layer and the welding composite layer of the present invention.

[0017] Figure 1G This is a schematic diagram showing the heat dissipation cover placed around the chip in this invention.

[0018] Figure 2A This is a bottom view of the heat dissipation cover of the present invention.

[0019] Figure 2B For along Figure 2A Sectional view of IIB-IIB.

[0020] Figure 2C This is a cross-sectional view of the heat sink cover of the present invention having an inner tin layer and a solder resist layer.

[0021] Figure 3 This is a schematic diagram of the reflow process for the electronic packaging structure of the present invention.

[0022] Figure 4 This is a schematic diagram of the heat dissipation cover according to the second embodiment of the present invention.

[0023] Figure 5A This is a schematic diagram of the electronic packaging structure according to the second embodiment of the present invention.

[0024] Figure 5B This is a schematic diagram of the reflow process of the electronic packaging structure according to the second embodiment of the present invention.

[0025] Symbol Explanation

[0026] 10: Chips

[0027] 101: Grounding via

[0028] 11: Bottom surface

[0029] 12: Top surface

[0030] 13: Side view

[0031] 14: Conductive materials

[0032] 15: Conductive bumps

[0033] 20: Electromagnetic shielding layer

[0034] 30: Passivation layer

[0035] 40: Dielectric layer

[0036] 50: Welded composite layer

[0037] 51: Welding substrate layer

[0038] 52: Tin layer

[0039] 60: Thermally conductive metal layer

[0040] 60M: Intermetallic compound layer

[0041] 70: Heat sink

[0042] 70S: Coverage Space

[0043] 71: Top Wall

[0044] 710: Stomata

[0045] 72: Inner Tin Layer

[0046] 73: Sidewall

[0047] 74: Solder resist layer

[0048] 8: Circuit board

[0049] 81: Upper surface

[0050] 82: Lower surface

[0051] 83: Grounding line

[0052] 85: Tin Ball

[0053] 9: Temporary carrier board

[0054] B: Reflow oven

[0055] F: Bottom filling material

[0056] G: Passivating gas Detailed Implementation

[0057] The following specific embodiments illustrate the implementation methods disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0058] This invention provides a method for manufacturing an electronic packaging structure with high thermal conductivity and electromagnetic shielding, comprising the following steps:

[0059] See Figure 1AA diced wafer 10 is placed on a temporary carrier 9. The wafer 10 is formed by dicing a whole wafer (not shown) after forming a circuit layer (not shown), vias, and conductive bumps 15. Specifically, the wafer 10 has a bottom surface 11, a top surface 12, and multiple side surfaces 13. The bottom surface 11 is an active surface and has circuit components, while the top surface 12 and side surfaces 13 are passive surfaces. The wafer 10 has at least one ground via 101. The ground via 101 connects the bottom surface 11 to the top surface 12. In this embodiment, the ground via 101 can be a through-silicon via (TSV), and the interior of the ground via 101 is filled with conductive material 14, thereby penetrating the wafer 10 to create a vertical interconnect.

[0060] See Figure 1B An electromagnetic shielding layer 20 is formed on the top surface 12 and multiple side surfaces 13 of the wafer 10. In this embodiment, the electromagnetic shielding layer 20 is a transparent conductive layer, for example, it can be formed by depositing indium tin oxide (ITO) onto the surface of the wafer 10 using a sputtering deposition method. Indium tin oxide (ITO) is a mixture of 90% indium oxide (In2O3) and 10% tin oxide (SnO2). Its main characteristic is the combination of electrical conductivity and optical transparency, simultaneously possessing low resistivity and high light transmittance, thus meeting the requirements of good conductivity and light transmittance when manufactured into a thin film. The material for indium tin oxide is made by mixing indium oxide and tin oxide powders in a certain proportion, pressing them into ingots, sintering and heat treating them, and then forming a sputtering target.

[0061] However, the present invention is not limited thereto. The transparent conductive layer may be formed by sputtering indium tin oxide, indium oxide, tin oxide, tin antimony oxide, zinc oxide, zinc aluminum oxide, zinc gallium oxide, or graphene. The electromagnetic shielding layer 20 contacts the grounding via 101 of the wafer 10, and can be grounded to provide electromagnetic shielding.

[0062] Next, a passivation layer 30 is formed on the electromagnetic shielding layer 20. In this embodiment, the passivation layer 30 is an insulating protective layer formed of inorganic materials, such as silicon glass, silicon nitride, or silicon oxide. The passivation layer 30 can be formed on the wafer 10 by chemical vapor deposition (CVD). Other suitable dielectric materials and techniques can also be used to form it.

[0063] Then, a dielectric layer 40 is formed on the passivation layer 30. In this embodiment, the dielectric layer 40 is made of a polymer material, such as epoxy resin and polyimide resin (PI) sputtered together.

[0064] See Figure 1CA solder composite layer 50 is formed on the dielectric layer 40. The solder composite layer 50 includes a solder substrate layer 51 and a tin layer 52. In this embodiment, the solder substrate layer 51 can be a copper-nickel layer. Copper itself is easily oxidized, and the inert nickel plating layer can protect the copper layer and prevent copper from diffusing into the tin layer 52 during connection. Specifically, the nickel layer is used to prevent migration and diffusion between the copper layer and the tin layer. The nickel layer can act as a barrier layer and an anti-corrosion protective layer, protecting the copper layer from oxidation and preventing degradation of conductivity and solderability. In this embodiment, the step of forming the solder composite layer 50 includes first electroplating a copper-nickel layer on the dielectric layer 40, and then plating the tin layer 52 on the upper surface of the copper-nickel layer. The thickness of the tin layer 52 can be 15 μm (micrometer).

[0065] See Figure 1D Remove the temporary carrier 9. In other words, remove the wafer 10, whose composite layer 50 has been bonded, from the temporary carrier 9.

[0066] See Figure 1E A wafer 10 is placed on the upper surface 81 of a circuit substrate 8 using a flip-chip method, and a bottom filler material F is filled on the bottom surface 11 of the wafer 10, filling the gap between the bottom surface 11 of the wafer 10 and the circuit substrate 8. The bottom surface 11 of the wafer 10 is located on the upper surface 81 of the circuit substrate 8, so that the conductive bumps 15 of the wafer 10 are correspondingly connected to the lines on the upper surface 81 of the circuit substrate 8. Thus, the ground via 101 of the wafer 10 is connected to the ground line 83 of the circuit substrate 8 through the internal lines and the conductive bumps 15. In this embodiment, the electromagnetic shielding layer 20 contacts the ground via 101 of the wafer 10 and the ground line 83 of the circuit substrate 8, thereby grounding and providing electromagnetic shielding.

[0067] See Figure 1F A thermally conductive metal layer 60 is disposed on the welding composite layer 50. In this embodiment, the thermally conductive metal layer 60 is an indium sheet. The method of disposing of the thermally conductive metal layer 60 can be to preheat and attach the indium sheet as the thermally conductive metal layer 60. Pure indium has a thermal conductivity of 86 W / mk and good ductility, which can completely fill the gap between the two materials, helping to improve the overall thermal conductivity of the heat dissipation module. Indium has a melting point of 157°C. At this melting point temperature, indium can melt and bond with other metals, allowing for a lower operating temperature compared to other metals with good thermal conductivity such as gold and copper.

[0068] However, the present invention is not limited thereto; the thermally conductive metal layer may be a low-temperature alloy of indium and tin or bismuth. Thus, the structure from wafer 10 to the thermally conductive metal layer 60 can be referred to as a package.

[0069] See Figure 1G A heat sink 70 is provided on the thermally conductive metal layer 60. The heat sink 70 is preferably made of a metal material with a high thermal conductivity, such as copper or aluminum.

[0070] The heat sink 70 in this embodiment is as follows: Figures 2A to 2C As shown, the heat sink 70 includes a top wall 71 and a side wall 73, with the side wall 73 connected to the periphery of the top wall 71. The top wall 71 forms a plurality of vents 710. The heat sink 70 of this embodiment has four vents 710; however, the invention is not limited thereto. The number of vents 710 can be at least one. These vents 710 communicate with the outer surface of the thermally conductive metal layer 60. An inner tin layer 72 and a solder resist layer 74 are disposed on the inner surface of the top wall 71 of the heat sink 70. The solder resist layer 74 is located around the inner tin layer 72 and around the vents 710. The thickness of the inner tin layer 72 can be 15 μm (micrometer).

[0071] like Figure 3 As shown, the heat sink 70 is located around the chip 10 to form a covering space 70S. The sidewall 73 of the heat sink 70 abuts against the upper surface 81 of the circuit board 8.

[0072] The temperature is raised to the melting point of the thermally conductive metal layer 60, for example, the melting point of indium is 156.6°C, and then the heat sink 70 is attached. The heat sink 70 has an inner tin layer 72. The thermally conductive metal layer 60 and the inner tin layer 72, when heated, together form an intermetallic compound layer (IMC layer) 60M to fix the heat sink 70 to the solder substrate layer 51. In this embodiment, the inner tin layer 72 and the indium layer are bonded to an indium-tin alloy layer using transient liquid phase bonding (TLP) technology to connect the heat sink 70 to the solder substrate layer 51. The intermetallic compound layer 60M is an indium-tin alloy, or intermetallic compound.

[0073] Transient liquid-phase diffusion bonding technology uses welding materials with a lower melting point than the substrate for welding. When heated to the melting point of the welding material, it liquefies and forms a transient liquid at the bonding surface. During isothermal treatment, the lower-melting-point welding material diffuses into the substrate, forming an intermetallic compound and thus creating a bond. The thickness of the transient liquid also decreases accordingly. The substrate of transient liquid-phase diffusion bonding technology does not melt, allowing welding of all suitable metallic or non-metallic welding materials without compromising substrate performance. Furthermore, it produces high-quality joint surfaces, high welding precision, and minimal deformation of the substrate and welding materials.

[0074] like Figure 3As shown, the ball-mounting process involves printing multiple solder balls 85 onto the lower surface 82 of the circuit board 8, followed by a reflow soldering process to fix the multiple solder balls 85 onto the lower surface 82 of the circuit board 8.

[0075] The temperature during the reflow process can reach as high as 245°C to 260°C, which is higher than the melting point of indium (156.6°C). Therefore, the indium layer may become molten and overflow during the reflow process. To avoid the indium layer flow problem, this invention applies a passivating gas G (e.g., nitrogen) simultaneously in the reflow furnace B during the reflow process to restrict the flow of the thermally conductive metal layer 60 (indium layer).

[0076] like Figure 3 As shown, passivating gas G enters the coverage space 70S of heat sink 70 through the vent 710, creating a saturated gas pressure inside the heat sink 70 to restrict and fix the flow of the molten thermally conductive metal layer 60. The passivating gas G surrounds the thermally conductive metal layer 60, preventing the molten indium from overflowing due to the gas pressure. After the ball-mounting process is completed, the application of passivating gas G is removed. When the reflow ball-mounting process ends and the temperature returns to room temperature, the thermally conductive metal layer 60, such as the indium sheet, returns to a solid state.

[0077] Finally, the electronic packaging structure with high thermal conductivity and electromagnetic shielding of the present invention is completed, which includes a circuit board 8, a wafer 10, an electromagnetic shielding layer 20, a passivation layer 30, a dielectric layer 40, a solder composite layer 50, and a thermally conductive metal layer 60. The bottom surface 11 of the wafer 10 is disposed on the upper surface 81 of the circuit board 8, and the grounding via 101 is electrically connected to the grounding line 83 of the circuit board 8. The electromagnetic shielding layer 20 is disposed on the top surface 12 and multiple side surfaces 13 of the wafer 10, and is connected to the grounding line 83 of the circuit board 8 through the grounding via 101 and conductive bumps 15, thereby providing electromagnetic shielding. The passivation layer 30 is disposed on the electromagnetic shielding layer 20. The dielectric layer 40 is disposed on the passivation layer 30. The solder composite layer 50 includes a solder substrate layer 51 and a tin layer 52, the solder substrate layer 51 is disposed on the dielectric layer 40, and the tin layer 52 is disposed on the solder substrate layer 51. A thermally conductive metal layer 60 is disposed on the tin layer 52. A heat sink 70 is disposed on the thermally conductive metal layer 60, wherein the thermally conductive metal layer 60 and the inner tin layer 72 of the heat sink 70 together form an intermetallic compound layer 60M to fix the heat sink 70 to the solder composite layer 50. Finally, a plurality of solder balls 85 are disposed on the lower surface 82 of the circuit board 8.

[0078] [Second Embodiment]

[0079] like Figure 4 As shown, this is the second embodiment of the present invention, which differs from the previous embodiment in the shape of the heat sink 70b. In this embodiment, the heat sink 70b corresponds to the shape of the chip 10; in other words, it can be a sheet-like structure, slightly square in shape.

[0080] The temperature is raised to the melting point of the thermally conductive metal layer 60 (indium layer), and then the heat sink 70b is attached, so that the tin layer 52 and the indium layer form an indium-tin alloy layer through transient liquid phase diffusion to connect the heat sink 70b to the solder substrate layer 51.

[0081] Finally, the reflow balling process is carried out in a closed reflow oven B. A passivating gas G (e.g., nitrogen) is applied in the reflow oven B to surround the package and restrict the flow of the thermally conductive metal layer 60.

[0082] In addition, the present invention can also be performed after the reflow soldering ball-mounting process, by preheating and attaching the thermally conductive metal layer 60 (indium layer), then heating to the melting point of the thermally conductive metal layer 60 (indium layer), and then attaching the heat sink cap, which is then fixedly connected to the soldering substrate layer 51. In this process, it is not necessary to raise the temperature to the reflow temperature, and the process of applying passivating gas can be omitted.

[0083] [Beneficial Effects of the Examples]

[0084] One of the beneficial effects of the present invention is that the electronic packaging structure with high thermal conductivity and electromagnetic shielding provided by the present invention can provide the effect of electromagnetic shielding of the chip by setting the electromagnetic shielding layer on the chip, connecting the thermally conductive metal layer to the top surface of the chip, and connecting it to the ground line of the circuit board through the grounding via of the chip.

[0085] This invention uses an indium sheet as the thermally conductive metal layer and utilizes liquid-phase diffusion bonding through the intermetallic compound layer to effectively fix the heat sink to the solder composite layer, while also dissipating excess heat from the chip outwards through the heat sink. The electronic packaging structure of this invention, with its high thermal conductivity and electromagnetic shielding, offers superior thermal conductivity compared to traditional thermal paste bonding methods.

[0086] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the scope of the claims of the present invention.

Claims

1. An electronic packaging structure with high thermal conductivity and electromagnetic shielding, comprising: A circuit board includes an upper surface, a lower surface, and at least one grounding line disposed on the upper surface; A chip has a bottom surface, a top surface, multiple side surfaces, and at least one grounding via, the at least one grounding via connecting the bottom surface to the top surface, the bottom surface of the chip being disposed on the upper surface of the circuit board, and the at least one grounding via being electrically connected to the at least one grounding line of the circuit board. An electromagnetic shielding layer is disposed on the top surface and the plurality of sides of the wafer; A passivation layer is disposed on the electromagnetic shielding layer; A dielectric layer is disposed on the passivation layer; A welding composite layer includes a welding substrate layer and a tin layer, wherein the welding substrate layer is disposed on the dielectric layer and the tin layer is disposed on the welding substrate layer; A thermally conductive metal layer is disposed on the tin layer; A heat sink is disposed on the thermally conductive metal layer. The heat sink has an inner tin layer, wherein the thermally conductive metal layer and the inner tin layer together form an intermetallic compound layer to fix the heat sink to the solder substrate layer. as well as Multiple solder balls are disposed on the lower surface of the circuit board.

2. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as described in claim 1, wherein a bottom filler material is further included between the bottom surface of the chip and the circuit board.

3. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as described in claim 1, wherein the electromagnetic shielding layer is a transparent conductive layer, and the material of the transparent conductive layer is selected from the group consisting of indium tin oxide, indium oxide, tin oxide, antimony tin oxide, zinc oxide, aluminum zinc oxide, gallium zinc oxide, and graphene.

4. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as described in claim 1, wherein the passivation layer is formed of an inorganic material and is selected from the group consisting of silicon glass, silicon nitride, and silicon oxide.

5. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as claimed in claim 1, wherein the dielectric layer is made of a polymer material and is selected from the group consisting of epoxy resin and polyimide resin.

6. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as described in claim 1, wherein the solder substrate layer is a copper-nickel layer, and the tin layer is located on the upper surface of the copper-nickel layer.

7. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as described in claim 1, wherein the thermally conductive metal layer is an indium layer, and an indium-tin alloy layer is formed with the tin layer through transient liquid phase diffusion to connect the solder substrate layer and the heat sink.

8. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as described in claim 1, wherein the heat sink includes a top wall and a side wall, the top wall includes at least one vent, the at least one vent communicates with the outer surface of the heat sink and is located on the periphery of the chip, and the side wall abuts against the upper surface of the circuit board.

9. The electronic packaging structure with high thermal conductivity and electromagnetic shielding as described in claim 8, wherein the inner surface of the top wall of the heat sink further includes a solder resist layer, the solder resist layer being located around the inner tin layer and around the at least one vent.

10. A method for manufacturing an electronic packaging structure with high thermal conductivity and electromagnetic shielding, comprising the following steps: A diced wafer is placed on a temporary carrier plate. The wafer has a bottom surface, a top surface, multiple side surfaces, and at least one grounding via, which connects the bottom surface to the top surface. An electromagnetic shielding layer is formed on the top surface and the plurality of sides of the wafer; A passivation layer is formed on the electromagnetic shielding layer; A dielectric layer is formed on the passivation layer; A welding composite layer is formed on the dielectric layer, the welding composite layer including a welding substrate layer and a tin layer; Remove the temporary carrier board; The wafer is placed on the upper surface of a circuit substrate in a flip-chip manner, and a bottom filler material is filled on the bottom surface of the wafer; wherein the bottom surface of the wafer is disposed on the upper surface of the circuit substrate, and the at least one grounding via of the wafer is connected to at least one grounding line of the circuit substrate. A thermally conductive metal layer is disposed on the welded composite layer; A heat sink is provided on the thermally conductive metal layer, the heat sink having an inner tin layer; Multiple solder balls are printed on the lower surface of the circuit board; and A reflow soldering process is performed to fix the multiple solder balls to the lower surface of the circuit board, while a passivating gas is applied to restrict the flow of the thermally conductive metal layer; wherein the thermally conductive metal layer and the inner tin layer are heated together to form an intermetallic compound layer to fix the heat sink to the solder substrate layer.

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