Stacked package configuration
By setting conductive pillars between the edge of the carrier board and the electronic component placement area to form a space to accommodate the electronic components, and using a package to cover the conductive pillars and electronic components, the problem of limited carrier board space is solved, and the electrical function of the package structure and the placement area of the electronic components are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHIPBOND TECH
- Filing Date
- 2025-01-03
- Publication Date
- 2026-06-19
AI Technical Summary
Existing technologies make it difficult to effectively place multiple electronic components with different electrical functions within a limited space on the substrate, resulting in insufficient electrical functionality in the package structure.
By placing conductive pillars between the edge of the carrier board and the electronic component placement area, and placing conductive pillars only at the edge, a space is formed to accommodate the electronic components. The conductive pillars and electronic components are then encapsulated in a package, thereby achieving an electrical connection between the carrier board and the semiconductor components.
It improves the electrical functionality of the stacked package structure, increases the placement area of electronic components and the flexibility of electrical connections, and meets electrical requirements.
Smart Images
Figure CN122249095A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a stacked package structure, and more particularly to a stacked package structure that enhances electrical functionality. Background Technology
[0002] With the increasing electrical functions of electronic products and the demand for thinner and smaller designs, the size of packaging structures must be reduced. Therefore, it is a problem that existing packaging technology must solve to place multiple electronic components with different electrical functions on a carrier board with limited space. Summary of the Invention
[0003] The main objective of this invention is to provide a stacked packaging structure that allows the space between the carrier and the semiconductor components to be configured according to electrical requirements, thereby improving the electrical functionality of the stacked packaging structure.
[0004] A stacked package structure of the present invention includes a carrier plate, a plurality of conductive pillars, a semiconductor element, a plurality of electronic components, and a first package body. The carrier plate has a first surface, which includes a plurality of edges, at least one electronic component mounting area, and a conductive pillar mounting area. The conductive pillar mounting area is located only between one of the edges and the electronic component mounting area. The conductive pillars are disposed only in the conductive pillar mounting area, and the first ends of the conductive pillars are electrically connected to the carrier plate. The semiconductor element has a second surface facing the first surface, which includes a conductive pillar bonding area and a non-conductive bonding area. The conductive pillar bonding area has its second ends bonded to it to electrically connect the semiconductor element. The non-conductive pillar bonding area is located above the electronic element placement area, forming a space between the non-conductive pillar bonding area and the electronic element placement area. The electronic elements are disposed in the electronic element placement area without the conductive pillars and are located in the space. The first package fills the space between the carrier and the semiconductor element, and covers the conductive pillars and the electronic elements located in the space. The first package also supports the non-conductive pillar bonding area without the conductive pillars.
[0005] The present invention, by having the conductive pillar placement area of the carrier plate located only between the edge and the electronic component placement area, allows the conductive pillars to be placed only in the conductive pillar placement area. This enables the electronic components to be placed in the space between the electronic component placement area of the carrier plate and the non-conductive pillar bonding area of the semiconductor element according to electrical requirements, thereby improving the electrical function of the stacked package structure. Attached Figure Description
[0006] Figure 1 : A cross-sectional schematic diagram of the carrier plate of the present invention.
[0007] Figures 2A to 2B : A top view of the carrier plate of the present invention.
[0008] Figure 3 This invention is a cross-sectional schematic diagram showing the conductive pillars and electronic components mounted on a carrier plate.
[0009] Figures 4A to 4B This invention is illustrated by a top view of the conductive pillars and electronic components mounted on a carrier plate.
[0010] Figure 5A and Figure 5B This invention is a schematic diagram of sealing conductive pillars and electronic components with a first package.
[0011] Figure 6 This invention relates to a schematic diagram of bonding a semiconductor element to a conductive pillar.
[0012] Figures 7A to 8B This invention is a schematic diagram of sealing a semiconductor element with a second package and forming a heat dissipation layer.
[0013] Figures 9A to 9B This is a schematic diagram of the present invention, which uses a second package to seal a semiconductor element and form an electromagnetic shield.
[0014] [Explanation of Key Component Symbols]
[0015] 100: Stacked package construction; 110: Carrier board
[0016] 111: First surface; 111a: Edge
[0017] 111b: Electronic component placement area; 111c: Conductive post placement area
[0018] 120: Conductive post; 121: First end
[0019] 122: Second terminal; 130: Electronic component
[0020] 140: First package body; 141: Side wall
[0021] 150: Semiconductor element; 151: Second surface
[0022] 151a: Conductive post joint area; 151b: Non-conductive post joint area
[0023] 151c: Edge 152: Surface
[0024] 160: Second package 170: Heat dissipation layer
[0025] 180: Electromagnetic shielding cover A: Carrier
[0026] S: Space Detailed Implementation
[0027] Please see Figure 6 A stacked package structure 100 of the present invention includes at least a carrier plate 110, a plurality of conductive pillars 120, a semiconductor element 150, a plurality of electronic components 130, and a first package body 140. (See also...) Figure 8A and Figure 8B The stacked package configuration 100 further includes a second package 160 and a heat dissipation layer 170, or, see [link to relevant documentation]. Figure 9A and Figure 9B The stacked package structure 100 further includes the second package 160 and the electromagnetic shield 180.
[0028] Please see Figure 1 , Figure 2A , Figure 2B and Figure 6 The carrier plate 110 has a first surface 111, which includes a plurality of edges 111a, at least one electronic component mounting area 111b, and a conductive post mounting area 111c. The conductive post mounting area 111c is located only between one of the edges 111a and the electronic component mounting area 111b. The conductive posts 120 are disposed only in the conductive post mounting area 111c, and the first ends 121 of the conductive posts 120 are electrically connected to the carrier plate 110. Please refer to [link to relevant documentation]. Figure 4A or Figure 4B In this embodiment, the conductive posts 120 are only disposed along the axial direction in the conductive post placement area 111c. Please refer to [link to relevant documentation]. Figure 4A These conductive posts 120 are disposed only along the axial direction Y in the conductive post placement area 111c, or, please refer to Figure 4B These conductive posts 120 are disposed only along another axial direction X in the conductive post placement area 111c.
[0029] Please see Figure 6 The semiconductor element 150 has a second surface 151 facing the first surface 111. The second surface 151 includes a conductive pillar bonding region 151a and a non-conductive pillar bonding region 151b. The second ends 122 of the conductive pillars 120 are bonded to the conductive pillar bonding region 151a to electrically connect the semiconductor element 150. In this embodiment, the conductive pillar bonding region 151a is adjacent to the edge 151c of the second surface 151. The conductive pillar bonding region 151a is located between the non-conductive pillar bonding region 151b and the edge 151c. The conductive pillar bonding region 151a is located above the conductive pillar placement region 111c, and the non-conductive pillar bonding region 151b is located above the electronic component placement region 111b, so that a space S is formed between the non-conductive pillar bonding region 151b and the electronic component placement region 111b.
[0030] Please see Figure 6The electronic components 130 are disposed in the electronic component placement area 111b where the conductive pillars 120 are not provided and are located in the space S. The first package 140 fills between the carrier plate 110 and the semiconductor element 150, and covers the conductive pillars 120 and the electronic components 130 located in the space S. The semiconductor element 150 is supported by the first package 140 in the non-conductive pillar bonding area 151b where the conductive pillars 120 are not bonded.
[0031] Please see Figures 1 to 9B The stacked package structure 100 is manufactured by the following manufacturing method.
[0032] First, please refer to Figure 1 , Figure 2A and Figure 2B A carrier A is provided, which can be selected from wafers, circuit boards, or glass substrates, etc. The carrier A can be disposed on adhesive tape (not shown) for subsequent processes. The carrier A includes a plurality of interconnected carrier plates 110, each carrier plate 110 having a first surface 111. The first surface 111 includes edges 111a, electronic component placement areas 111b, and conductive post placement areas 111c. Please refer to [reference needed]. Figure 2A or Figure 2B The conductive post setting area 111c is located only between one of the edge 111a and the electronic component setting area 111b.
[0033] Next, please refer to Figure 3 , Figure 4A and Figure 4B The conductive pillars 120 are disposed only in the conductive pillar placement area 111c between the edge 111a and the electronic component placement area 111b, and the electronic components 130 are disposed in the electronic component placement area 111b. The conductive pillars 120 are electrically connected to the carrier plate 110 at the first end 121. The material of the conductive pillars 120 may be copper, but is not limited thereto. The electronic components 130 may be chips, filters, passive components, etc., and may be disposed according to electrical requirements. The electronic components 130 are electrically connected to the carrier plate 110.
[0034] Please see Figure 4A or Figure 4B These conductive posts 120 are disposed only along the axial direction in the conductive post placement area 111c. Please refer to [link / reference]. Figure 4A These conductive posts 120 are only disposed in the conductive post placement area 111c along the Y-axis, or, please refer to Figure 4BThe conductive posts 120 are disposed only along the axial direction X in the conductive post placement area 111c, so that the electronic component placement area 111b, which does not have the conductive posts 120, can be used to place the electronic components 130 according to electrical requirements.
[0035] Next, please refer to Figure 5A The first package 140 seals the conductive posts 120 and the electronic components 130. When the first package 140 covers the second end 122 of the conductive posts 120, the first package 140 can be ground to expose the second end 122 (see [link]). Figure 5B Alternatively, please refer to Figure 5B When the first package 140 seals the conductive posts 120 and the electronic components 130, the second end 122 is exposed.
[0036] Next, please refer to Figure 6 The semiconductor element 150 is provided and is bonded to the second ends 122 of the conductive pillars 120. In this embodiment, the semiconductor element 150 has a second surface 151, which includes a conductive pillar bonding region 151a and a non-conductive pillar bonding region 151b. The semiconductor element 150 faces the first surface 111 with the second surface 151 facing it, and the second ends 122 of the conductive pillars 120 are bonded to the conductive pillar bonding region 151a. The conductive pillars 120 and the semiconductor element 150 are electrically connected. In this embodiment, a space S is formed between the non-conductive pillar bonding area 151b and the electronic element placement area 111b. The space S is used to place the electronic elements 130 and fill the first package 140. In addition to covering the conductive pillars 120 and the electronic elements 130 located in the space S, the first package 140 can also support the non-conductive pillar bonding area 151b that is not bonded to the conductive pillars 120.
[0037] Next, please refer to Figure 7A Preferably, the semiconductor element 150 is sealed by the second package 160. In this embodiment, the second package 160 covers the surface 152 of the semiconductor element 150. Then, a heat dissipation layer 170 is formed on the second package 160. The heat dissipation layer 170 is disposed on the second package 160, and each of the stacked package structures 100 dissipates heat through the heat dissipation layer 170. Please refer to [link to documentation]. Figure 8A Next, a cutting process is performed to separate the stacked package structures 100.
[0038] Alternatively, please see Figure 7BWhen the second package 160 seals the semiconductor element 150 and covers the surface 152 of the semiconductor element 150, the second package 160 can be ground to expose the surface 152. The heat dissipation layer 170 is disposed on the surface 152 of the semiconductor element 150 so that the stacked package structure 100 dissipates heat through the heat dissipation layer 170. Next, please refer to Figure 8B The process involves cutting the stacked package structures 100 to separate them.
[0039] Alternatively, please see Figure 9A After the second package 160 is formed to seal the semiconductor element 150, a cutting process is performed to separate the stacked package structures 100, and an electromagnetic shield 180 is formed on each of the stacked package structures 100. The electromagnetic shield 180 covers the sidewalls 141 of the second package 160 and the first package 140, and is electrically connected to the carrier plate 110.
[0040] Alternatively, please see Figure 9A After the second package 160 is formed to seal the semiconductor element 150, the second package 160 can be ground to expose the surface 152. Then, a cutting process is performed to separate the stacked package structures 100, and an electromagnetic shield 180 is formed on each of the stacked package structures 100. The electromagnetic shield 180 covers the second package 160, the surface 152 of the semiconductor element 150, the sidewall 141 of the first package 140, and is electrically connected to the carrier plate 110.
[0041] The stacked package structure 100 of the present invention, by having the conductive pillar placement area 111c of the carrier 110 located only between one of the edges 111a and the electronic component placement area 111b, allows the conductive pillars 120 to be disposed only in the conductive pillar placement area 111c, thereby increasing the usable area of the electronic component placement area 111b of the carrier 110. Furthermore, the space S between the electronic component placement area 111b of the carrier 110 and the non-conductive pillar bonding area 151b of the semiconductor element 150 can be used to place the electronic components 130 in the space S according to electrical requirements, thereby improving the electrical function of the stacked package structure 100.
[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A stacked packaging structure, characterized in that... include: A carrier board has a first surface, the first surface including a plurality of edges, at least one electronic component placement area and a conductive pillar placement area, the conductive pillar placement area being located only between one of the edges and the electronic component placement area; A plurality of conductive posts are disposed only in the conductive post placement area, and the first end of the conductive posts is electrically connected to the carrier plate; A semiconductor element has a second surface facing the first surface. The second surface includes a conductive pillar bonding region and a non-conductive pillar bonding region. The second ends of the conductive pillars are bonded to the conductive pillar bonding region to electrically connect the semiconductor element. The non-conductive pillar bonding region is located above the electronic component mounting region, so that a space is formed between the non-conductive pillar bonding region and the electronic component mounting region. A plurality of electronic components are disposed in the electronic component placement area, which does not have the conductive pillars, and are located in the space; and A first package is filled between the carrier and the semiconductor element, and covers the conductive pillars and the electronic components located in the space, and the first package supports the non-conductive pillar bonding area where the conductive pillars are not bonded.
2. The stacked packaging structure as described in claim 1, characterized in that... These conductive posts are arranged only along the axial direction in the conductive post setting area.
3. The stacked packaging structure as described in claim 1 or 2, characterized in that... It also includes a second package and a heat dissipation layer, the second package sealing the semiconductor device and the heat dissipation layer being formed in the second package.
4. The stacked packaging structure as described in claim 3, characterized in that... The second package exposes the surface of the semiconductor element, and the heat dissipation layer is disposed on the surface of the semiconductor element.
5. The stacked packaging structure as described in claim 1 or 2, characterized in that... It also includes a second package and an electromagnetic shield. The second package seals the semiconductor element, and the electromagnetic shield covers the sidewalls of the second package and the first package and is electrically connected to the carrier plate.
6. The stacked packaging structure as described in claim 5, characterized in that... The second package exposes the surface of the semiconductor element, and the electromagnetic shield covers the surface of the semiconductor element.
7. The stacked packaging structure as described in claim 1, characterized in that... The second surface includes an edge, the conductive post bonding area is adjacent to the edge, the conductive post bonding area is located between the non-conductive post bonding area and the edge, and the conductive post bonding area is located above the conductive post setting area.