A signal detection device and a detection method

Abstract

This application discloses a signal detection device and method, applicable to the field of digital circuits. The signal detection device includes a detection unit whose input terminal is connected to the output terminal of a voltage divider circuit. The input terminal of the voltage divider circuit receives multiple digital signals to be detected, with each digital signal corresponding to one of the multiple input terminals. The detection unit determines the output voltage of the voltage divider circuit (i.e., the voltage at the output terminal of the voltage divider circuit) as a first voltage value, and determines the level state of each digital signal based on the first voltage value. The output voltage of the voltage divider circuit is correlated with the voltages at its multiple input terminals. The detection device connects to the voltage divider circuit through an interface, enabling the monitoring of multiple digital signals. This reduces the reliance on GPIO pins in large-scale digital signal detection by using analog signal processing, and also lowers hardware costs.

Description

A signal detection device and a detection method TECHNICAL FIELD

[0001] The present application relates to the technical field of digital circuits, and in particular to a signal detection device and a detection method. BACKGROUND

[0002] In a large-scale digital logic circuit, a large number of digital signal inputs are usually received to monitor external signals in real time.

[0003] At present, a plurality of external digital signals are monitored by a digital device with a general purpose input / output (GPIO) port, which can be a complex programmable logic device (CPLD), a system-on-a-chip (SOC), etc. By this way of monitoring external digital signals, when there is a large-scale digital signal input requirement, the digital device needs to have a large number of GPIO pins, resulting in high cost of device modification.

[0004] SUMMARY

[0005] The present application discloses a signal detection device and a detection method, which can monitor a plurality of external digital signals at a lower cost and has a low requirement for the number of GPIO pins of a digital device.

[0006] In a first aspect, the present application provides a signal detection device, which comprises a detection device, an input end of the detection device being connected with an output end of a voltage dividing circuit, a plurality of input ends of the voltage dividing circuit being used for receiving a plurality of digital signals to be detected, one digital signal in the plurality of digital signals corresponding to one input end in the plurality of input ends; wherein the detection device is used for determining that an output voltage of the voltage dividing circuit is a first voltage value, and determining a level state of each digital signal in the plurality of digital signals based on the first voltage value; wherein the output voltage of the voltage dividing circuit is a voltage at the output end of the voltage dividing circuit, and the output voltage of the voltage dividing circuit is associated with voltages at the plurality of input ends of the voltage dividing circuit.

[0007] The level state of a digital signal refers to a logic representation of a voltage level of the digital signal at a specific time point. In a digital circuit, two voltage levels are usually used to represent different logic values, for example, a high level and a low level, wherein the logic value represented by the high level is "1", and the logic value represented by the low level is "0".

[0008] In the device, the detection device is connected with the voltage dividing circuit through an interface, receives the plurality of digital signals to be detected through the voltage dividing circuit, and determines the level state of each digital signal in the plurality of digital signals according to the output voltage of the voltage dividing circuit, that is, the detection device is connected with the voltage dividing circuit through an interface, realizes the detection of the plurality of digital signals, and the mode of converting the digital signals into analog signals for processing reduces the dependence on the number of GPIO pins of the device in large-scale digital signal detection, and the hardware cost is low.

[0009] In any possible implementation manner of the first aspect, the signal detection device further includes the voltage dividing circuit.

[0010] In this implementation manner, the voltage dividing circuit can also be integrated with the detection device in the signal detection device, reducing the dependence on the GPIO pin of the device in monitoring the digital signal.

[0011] In any possible implementation manner of the first aspect, the voltage dividing circuit has different voltage dividing weights corresponding to each of the plurality of input ends.

[0012] In any possible implementation manner of the first aspect, the first input end of the voltage dividing circuit is configured to receive a first digital signal in the plurality of digital signals, the voltage dividing weight corresponding to the first input end of the voltage dividing circuit is configured to represent the contribution degree of the voltage at the first input end of the voltage dividing circuit to the output voltage of the voltage dividing circuit, the voltage at the first input end of the voltage dividing circuit is associated with the level state of the first digital signal and a reference voltage of the signal detection device, and the first input end of the voltage dividing circuit belongs to the plurality of input ends of the voltage dividing circuit.

[0013] The number of input ends of the voltage dividing circuit is greater than or equal to the number of digital signals to be detected, and each input end of the voltage dividing circuit is configured to receive a digital signal. When the number of input ends of the voltage dividing circuit is greater than the number of digital signals to be detected, the input end of the voltage dividing circuit that does not receive a digital signal can be connected to a power supply (i.e., set to high level) or connected to the ground (i.e., set to low level).

[0014] As can be seen, the output voltage of the voltage dividing circuit is different when the plurality of digital signals received by the voltage dividing circuit are in different level states, so when the output voltage of the voltage dividing circuit changes, it can be known that the level state of a digital signal in the plurality of digital signals to be detected changes.

[0015] In any possible implementation form of the first aspect, the detection apparatus comprises a first digital-to-analog converter (DAC), a first comparator and a controller, an input of the detection apparatus comprises a first input of the first comparator, an output of the first DAC is connected to a second input of the first comparator, an input of the first DAC is connected to the controller, and the controller is further connected to an output of the first comparator; wherein the controller is configured to control a magnitude of a voltage output by the first DAC, the first comparator is configured to output a first result, the first result being a comparison result of the voltage output by the first DAC and the output voltage of the voltage dividing circuit, the controller is further configured to determine, based on a change of the first result, that the output voltage of the voltage dividing circuit is a first voltage value, and determine, based on the first voltage value, a level state of each of the plurality of digital signals.

[0016] In the above implementation form, the controller can control the first DAC to change the magnitude of the voltage output by the first DAC to observe the first result output by the first comparator, and the first comparator is configured to compare the voltage output by the first DAC and the current output voltage of the voltage dividing circuit, and determine the current output voltage of the voltage dividing circuit according to the change of the first result, so that the level state of each of the plurality of digital signals received by the voltage dividing circuit can be obtained, and the dependence on the GPIO pin in the digital signal monitoring process is reduced.

[0017] In any possible implementation form of the first aspect, the controller is specifically configured to determine, based on the first voltage value, a reference voltage of the signal detection apparatus and weight information, the level state of each of the plurality of digital signals, wherein the weight information comprises a voltage dividing weight corresponding to each of the plurality of inputs of the voltage dividing circuit.

[0018] In this implementation form, the weight information is calculated based on the design parameters of the voltage dividing circuit (for example, including the resistance values of resistors), and based on the weight information, the relationship between the output voltage of the voltage dividing circuit and the voltages at the plurality of inputs of the voltage dividing circuit can be known. The voltage at each input of the voltage dividing circuit is associated with the level state of the digital signal received by the input and the reference voltage of the signal detection apparatus. Thus, in the case of knowing the output voltage of the voltage dividing circuit, the level state of the plurality of digital signals to be detected can be quickly determined in combination with the weight information and the reference voltage of the signal detection apparatus.

[0019] Exemplarily, the controller is specifically configured to obtain, based on the first voltage value and mapping information, the level state of each of the plurality of digital signals, wherein the mapping information comprises a corresponding relationship between the first voltage value and the level state of each of the plurality of digital signals.

[0020] That is, the mapping information includes a correspondence relationship between the level state of the plurality of digital signals received by the voltage dividing circuit and the output voltage of the voltage dividing circuit, that is, the output voltage of the voltage dividing circuit is different when the plurality of digital signals are in different level states, and the mapping information is associated with the weight information and the reference voltage of the signal detection device. Therefore, the controller can look up the mapping information based on the first voltage value, quickly obtain the current level state of the plurality of digital signals corresponding to the first voltage value, and realize detection of the plurality of digital signals outside.

[0021] In any possible implementation manner of the first aspect, the detection device further includes a second DAC and a second comparator, wherein a first input end of the second comparator is connected with an output end of the second DAC, the input end of the detection device further includes a second input end of the second comparator, an output end of the second comparator is connected with the controller, the controller is further connected with an input end of the second DAC, and the second input end of the second comparator is opposite to the first input end of the first comparator; wherein the controller is further configured to control the size of the voltage output by the second DAC, the second comparator is configured to output a second result, the second result is a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the second DAC, and the controller is further configured to determine that the output voltage of the voltage dividing circuit is the first voltage value according to the change of the first result and the second result.

[0022] In the above implementation manner, the controller can control the first DAC and the second DAC to change the size of the voltage output at the same time to observe the output result of the corresponding comparator, and the output voltage of the voltage dividing circuit is determined by using this successive approximation method, so that the detection efficiency of the output voltage of the voltage dividing circuit is improved, thereby facilitating improvement of the detection efficiency of the level state of the digital signal monitored outside.

[0023] In any possible implementation manner of the first aspect, the controller is further configured to: control the voltage output by the first DAC to be a second voltage value and control the voltage output by the second DAC to be a third voltage value; when it is detected that the output result of at least one of the first comparator and the second comparator changes, control the first DAC to change the size of the voltage output, and determine that the output voltage of the voltage dividing circuit is a fourth voltage value according to the change of the output result of the first comparator, the fourth voltage value being different from the first voltage value; and determine the level state of each digital signal in the plurality of digital signals according to the fourth voltage value; wherein the first voltage value is between the second voltage value and the third voltage value, the offset of the second voltage value relative to the first voltage value is a first value, the offset of the third voltage value relative to the first voltage value is a second value, the first value and the second value are both positive numbers less than a preset value, and the preset value is determined based on the reference voltage and the minimum voltage dividing weight in the weight information.

[0024] In the implementation manner, when the level state of a digital signal in the plurality of digital signals received by the voltage dividing circuit changes, the output voltage of the voltage dividing circuit changes, and the output voltages of the first DAC and the second DAC remain unchanged, which causes the output result of at least one of the first comparator and the second comparator to change, and an interrupt signal is generated, which triggers the controller to determine the current output voltage of the voltage dividing circuit, and the current level state of the plurality of digital signals is determined, the level state of the external digital signal is detected in real time without monitoring the output voltage of the voltage dividing circuit in real time, and the power consumption of the controller is reduced.

[0025] In any possible implementation manner of the first aspect, the second voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value; or the third voltage value is greater than the first voltage value, and the first voltage value is greater than the first voltage value.

[0026] In the implementation manner, the second voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value, which means that the first comparator is adjusted by using the up-bias mode and the second comparator is adjusted by using the down-bias mode. The third voltage value is greater than the first voltage value, and the first voltage value is greater than the first voltage value, which means that the first comparator is adjusted by using the down-bias mode and the second comparator is adjusted by using the up-bias mode, and the voltage adjustment means is diversified.

[0027] In any possible implementation manner of the first aspect, the detection apparatus includes an analog-to-digital converter (ADC) and a controller, the input end of the detection apparatus is an input end of the ADC, and an output end of the ADC is connected to the controller; the ADC is configured to determine that the output voltage of the voltage dividing circuit is the first voltage value, and the controller is configured to determine the level state of each digital signal in the plurality of digital signals according to the first voltage value.

[0028] In the implementation manner, the voltage dividing circuit is connected to the controller through the ADC, and the plurality of digital signals to be detected are received by the voltage dividing circuit. The processing manner of converting the digital signals into analog signals can reduce the dependence on GPIO pins in digital signal detection, and the controller can determine the level state of each digital signal in the plurality of digital signals received by the voltage dividing circuit based on the output result of the ADC, so that the level state of the plurality of digital signals is monitored in real time at a low cost.

[0029] In any possible implementation manner of the first aspect, the controller is specifically configured to determine the level state of each digital signal in the plurality of digital signals according to the first voltage value, a reference voltage of the signal detection apparatus, and weight information, and the weight information includes a voltage dividing weight corresponding to each input end of the plurality of input ends of the voltage dividing circuit.

[0030] In a second aspect, the application provides a signal detection method, which is applied to a controller in a detection device, an input of the detection device is connected with an output of a voltage dividing circuit, a plurality of inputs of the voltage dividing circuit are configured to receive a plurality of digital signals to be detected, one digital signal in the plurality of digital signals corresponds to one input in the plurality of inputs, the detection device further comprises a first digital-to-analog converter (DAC) and a first comparator, the input of the detection device comprises a first input of the first comparator, an output of the first DAC is connected with a second input of the first comparator, an input of the first DAC is connected with the controller, and the controller is further connected with an output of the first comparator, the method comprises: controlling the first DAC to output a voltage; obtaining a first result output by the first comparator, the first result is a comparison result of the voltage output by the first DAC and the voltage output by the voltage dividing circuit, the voltage output by the voltage dividing circuit is a voltage at the output of the voltage dividing circuit; determining, according to a change of the first result, that the voltage output by the voltage dividing circuit is a first voltage value, and determining, based on the first voltage value, a level state of each digital signal in the plurality of digital signals, the voltage output by the voltage dividing circuit is associated with voltages at the plurality of inputs of the voltage dividing circuit.

[0031] In the above method, based on the connection relationship among the voltage dividing circuit, the first DAC, the first comparator and the controller, the controller can control the first DAC to change the size of the output voltage to observe the first result output by the first comparator, and the first comparator is configured to compare the size of the voltage output by the first DAC and the current output voltage of the voltage dividing circuit, and determine the current output voltage of the voltage dividing circuit according to the change of the first result, and then obtain the level state of each digital signal in the plurality of digital signals received by the voltage dividing circuit, which is processed in the form of analog signal, thereby reducing the dependence on GPIO pins in the digital signal detection process, and compared with the way of directly modifying the digital device to increase the number of GPIO pins, the detection of the plurality of external digital signals can be realized at a lower cost.

[0032] In any possible implementation manner of the second aspect, each input in the plurality of inputs of the voltage dividing circuit corresponds to a different voltage dividing weight. The first input of the voltage dividing circuit is configured to receive a first digital signal in the plurality of digital signals, and the voltage dividing weight corresponding to the first input of the voltage dividing circuit is configured to represent a contribution degree of the voltage at the first input of the voltage dividing circuit to the output voltage of the voltage dividing circuit, and the voltage at the first input of the voltage dividing circuit is associated with the level state of the first digital signal and a reference voltage of the signal detection device.

[0033] In this way, the output voltage of the voltage dividing circuit is different when the plurality of digital signals received by the voltage dividing circuit are in different level states, so when the change of the output voltage of the voltage dividing circuit is detected, it can be known that the level state of the digital signal in the plurality of digital signals to be detected has changed.

[0034] In any possible implementation form of the second aspect, determining the level state of each of the plurality of digital signals based on the first voltage value comprises: determining the level state of each of the plurality of digital signals according to the first voltage value, the reference voltage of the signal detection apparatus and weight information, wherein the weight information comprises a corresponding voltage division weight of each of the plurality of inputs of the voltage division circuit.

[0035] In this implementation form, the weight information corresponds to the voltage division circuit, and based on the weight information, the relationship between the output voltage of the voltage division circuit and the voltage at the plurality of inputs of the voltage division circuit can be known, and the voltage at each input of the voltage division circuit is associated with the level state of the digital signal received by the input and the reference voltage of the signal detection apparatus. Thus, in the case of knowing the output voltage of the voltage division circuit, the level state of the plurality of digital signals to be detected can be quickly determined in combination with the weight information and the reference voltage of the signal detection apparatus.

[0036] In any possible implementation form of the second aspect, determining the level state of each of the plurality of digital signals based on the first voltage value comprises: determining the level state of each of the plurality of digital signals according to the first voltage value and mapping information, wherein the mapping information comprises a corresponding relationship between the first voltage value and the level state of each of the plurality of digital signals.

[0037] That is, through the mapping information, it can be known that the output voltage of the voltage division circuit is different when the plurality of digital signals are in different level states, and the mapping information can be obtained based on the weight information and the reference voltage of the signal detection apparatus. Therefore, in the case of determining that the output voltage of the voltage division circuit currently takes the first voltage value, the mapping information is looked up based on the first voltage value, and the current level state of the plurality of digital signals can be quickly obtained, thereby realizing the detection of the plurality of digital signals outside.

[0038] In any possible implementation form of the second aspect, the detection apparatus further comprises a second DAC and a second comparator, wherein a first input terminal of the second comparator is connected with an output terminal of the second DAC, the input terminal of the detection apparatus further comprises a second input terminal of the second comparator, an output terminal of the second comparator is connected with the controller, the controller is further connected with an input terminal of the second DAC, and the second input terminal of the second comparator is opposite to the first input terminal of the first comparator; the method further comprises: controlling the second DAC to output a voltage; obtaining a second result output by the second comparator, the second result being a comparison result of the output voltage of the voltage division circuit and the voltage output by the second DAC; and determining that the output voltage of the voltage division circuit is the first voltage value according to the change of the first result, comprising: determining that the output voltage of the voltage division circuit is the first voltage value according to the changes of the first result and the second result.

[0039] In the implementation, based on the connection relationship among the voltage dividing circuit, the first DAC, the first comparator, the second DAC, the second comparator and the controller, the controller can control the first DAC and the second DAC to change the size of the output voltage at the same time to observe the output result of the corresponding comparator, so that the current output voltage of the voltage dividing circuit can be approached successively, the detection efficiency of the output voltage of the voltage dividing circuit can be improved, and thus the detection efficiency of the level state of the digital signal monitored externally can be improved.

[0040] In any possible implementation of the second aspect, the method further includes: controlling the first DAC to output a second voltage value and the second DAC to output a third voltage value; when detecting that the output result of at least one of the first comparator and the second comparator changes, controlling the first DAC to change the size of the output voltage, and determining, according to the change of the output result of the first comparator, that the output voltage of the voltage dividing circuit is a fourth voltage value, the fourth voltage value being different from the first voltage value; determining the level state of each of the plurality of digital signals according to the fourth voltage value; and wherein the first voltage value is between the second voltage value and the third voltage value, the second voltage value is offset from the first voltage value by a first value, and the third voltage value is offset from the first voltage value by a second value, the first value and the second value are both positive numbers less than a preset value, and the preset value is determined based on the reference voltage and the minimum voltage dividing weight in the weight information.

[0041] Implementing the above implementation, the controller can support interrupt detection, after the controller determines the value of the output voltage of the current voltage dividing circuit, the output voltage of the first DAC and the second DAC remains unchanged, and the change of the output result of the first comparator and / or the second comparator is equivalent to an interrupt signal, when the interrupt signal is detected, the controller knows that the output voltage of the current voltage dividing circuit has changed, and then triggers the controller to determine the current output voltage of the voltage dividing circuit again, and thus the current level state of the plurality of digital signals can be determined, the output voltage of the voltage dividing circuit does not need to be monitored in real time, the level state of the external digital signal can be detected in real time, and the power consumption of the controller can be reduced.

[0042] In any possible implementation of the second aspect, the second voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value; or the third voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value.

[0043] In a third aspect, the present application provides a signal detection method, which is applied to a controller in a detection device, an input end of the detection device is connected with an output end of a voltage dividing circuit, a plurality of input ends of the voltage dividing circuit are used to receive a plurality of digital signals to be detected, one digital signal in the plurality of digital signals corresponds to one input end in the plurality of input ends, the detection device further comprises an analog-to-digital converter (ADC), the input end of the detection device is an input end of the ADC, an output end of the ADC is connected with the controller, and the method comprises the following steps: obtaining an output voltage of the voltage dividing circuit from the ADC, the output voltage of the voltage dividing circuit is a first voltage value, and the output voltage of the voltage dividing circuit is a voltage at the output end of the voltage dividing circuit; determining a level state of each digital signal in the plurality of digital signals according to the first voltage value, the output voltage of the voltage dividing circuit is associated with voltages at the plurality of input ends of the voltage dividing circuit, and the voltage at the first input end of the voltage dividing circuit is associated with a level state of a first digital signal received by the first input end of the voltage dividing circuit and a reference voltage of the signal detection device.

[0044] In the above method, the voltage dividing circuit is connected with the controller through the ADC, the plurality of digital signals to be detected are received through the voltage dividing circuit, the voltage dividing circuit can output an output voltage according to the voltages at the plurality of input ends of the voltage dividing circuit, the processing is performed in the mode of converting into an analog signal, and the dependence on GPIO pins in the digital signal detection process is reduced. In addition, the controller can determine the respective level states of the plurality of digital signals received by the voltage dividing circuit based on the first voltage value obtained from the ADC, and compared with the detection mode of directly modifying a digital device to increase the number of GPIO pins, the detection of the plurality of external digital signals can be realized at a lower cost.

[0045] In any possible implementation manner of the third aspect, each input end in the plurality of input ends of the voltage dividing circuit corresponds to different voltage dividing weights.

[0046] In any possible implementation manner of the third aspect, the determining of the level state of each digital signal in the plurality of digital signals according to the first voltage value comprises: determining the level state of each digital signal in the plurality of digital signals according to the first voltage value, the reference voltage of the signal detection device and weight information, and the weight information comprises the voltage dividing weight corresponding to each input end in the plurality of input ends of the voltage dividing circuit.

[0047] In any possible implementation manner of the third aspect, the determining of the level state of each digital signal in the plurality of digital signals according to the first voltage value comprises: obtaining the level state of each digital signal in the plurality of digital signals according to the first voltage value and mapping information, wherein the mapping information comprises a corresponding relationship between the first voltage value and the level state of each digital signal in the plurality of digital signals.

[0048] The beneficial effects of other features of the third aspect are described in the description of the first aspect, which will not be repeated here.

[0049] In a fourth aspect, the present application provides a device for signal detection, the device being a controller in a detection device, an input of the detection device being connected with an output of a voltage dividing circuit, a plurality of inputs of the voltage dividing circuit being configured to receive a plurality of digital signals to be detected, one digital signal of the plurality of digital signals corresponding to one input of the plurality of inputs, the detection device further comprising a first digital-to-analog converter (DAC) and a first comparator, the input of the detection device comprising a first input of the first comparator, an output of the first DAC being connected with a second input of the first comparator, an input of the first DAC being connected with the controller, the controller being further connected with an output of the first comparator, the device comprising: a processing unit configured to control the first DAC to output a voltage; an obtaining unit configured to obtain a first result output by the first comparator, the first result being a comparison result of the voltage output by the voltage dividing circuit and the voltage output by the first DAC, the voltage output by the voltage dividing circuit being a voltage at the output of the voltage dividing circuit; and the processing unit being further configured to determine, according to a change of the first result, that the voltage output by the voltage dividing circuit is a first voltage value, and determine, based on the first voltage value, a level state of each digital signal of the plurality of digital signals, the voltage output by the voltage dividing circuit being associated with voltages at the plurality of inputs of the voltage dividing circuit.

[0050] In any possible implementation form of the fourth aspect, each input of the plurality of inputs of the voltage dividing circuit corresponds to a different voltage dividing weight. The plurality of inputs of the voltage dividing circuit comprises a first input, the first input of the voltage dividing circuit being configured to receive a first digital signal of the plurality of digital signals, the voltage dividing weight corresponding to the first input of the voltage dividing circuit being configured to represent a degree of contribution of a voltage at the first input of the voltage dividing circuit to the voltage output by the voltage dividing circuit, the voltage at the first input of the voltage dividing circuit being associated with the level state of the first digital signal and a reference voltage of the signal detection device.

[0051] In any possible implementation form of the fourth aspect, the processing unit is specifically configured to determine, according to the first voltage value, the reference voltage of the signal detection device and weight information, the level state of each digital signal of the plurality of digital signals, wherein the weight information comprises the voltage dividing weight corresponding to each input of the plurality of inputs of the voltage dividing circuit.

[0052] In any possible implementation form of the fourth aspect, the processing unit is specifically configured to determine, according to the first voltage value and mapping information, the level state of each digital signal of the plurality of digital signals, wherein the mapping information comprises a corresponding relationship between the first voltage value and the level state of each digital signal of the plurality of digital signals.

[0053] In any possible implementation form of the fourth aspect, the detection apparatus further comprises a second DAC and a second comparator, wherein a first input terminal of the second comparator is connected with an output terminal of the second DAC, the input terminal of the detection apparatus further comprises a second input terminal of the second comparator, an output terminal of the second comparator is connected with the controller, the controller is further connected with an input terminal of the second DAC, the second input terminal of the second comparator is opposite to the first input terminal of the first comparator; wherein the processing unit is further configured to control the second DAC to output a voltage; the obtaining unit is further configured to obtain a second result output by the second comparator, the second result being a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the second DAC; and the processing unit is specifically configured to: determine the output voltage of the voltage dividing circuit as the first voltage value according to the change of the first result and the second result.

[0054] In any possible implementation form of the fourth aspect, the processing unit is further configured to: control the first DAC to output a voltage as a second voltage value and control the second DAC to output a voltage as a third voltage value; when it is detected that the output result of at least one of the first comparator and the second comparator changes, control the first DAC to change the size of the output voltage, and determine the output voltage of the voltage dividing circuit as a fourth voltage value according to the change of the output result of the first comparator, the fourth voltage value being different from the first voltage value; and determine the level state of each digital signal in the plurality of digital signals according to the fourth voltage value; wherein the first voltage value is between the second voltage value and the third voltage value, an offset of the second voltage value relative to the first voltage value is a first value, an offset of the third voltage value relative to the first voltage value is a second value, the first value and the second value are both positive numbers less than a preset value, and the preset value is determined based on the reference voltage and the minimum voltage dividing weight in the weight information, the weight information comprising a voltage dividing weight corresponding to each input terminal of the plurality of input terminals of the voltage dividing circuit.

[0055] In any possible implementation form of the fourth aspect, the second voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value; or the third voltage value is greater than the first voltage value, and the first voltage value is greater than the first voltage value.

[0056] In a fifth aspect, the present application provides a device for signal detection, the device being a controller in a detection device, an input of the detection device being connected with an output of a voltage dividing circuit, a plurality of inputs of the voltage dividing circuit being configured to receive a plurality of digital signals to be detected, one of the plurality of digital signals corresponding to one of the plurality of inputs, the detection device further comprising an analog-to-digital converter (ADC), the input of the detection device being an input of the ADC, an output of the ADC being connected with the controller, the device comprising: an obtaining unit configured to obtain an output voltage of the voltage dividing circuit from the ADC, the output voltage of the voltage dividing circuit being a first voltage value, the output voltage of the voltage dividing circuit being a voltage at an output of the voltage dividing circuit; and a processing unit configured to determine a level state of each of the plurality of digital signals according to the first voltage value, the output voltage of the voltage dividing circuit being associated with voltages at the plurality of inputs of the voltage dividing circuit, the voltage at a first input of the voltage dividing circuit being associated with a level state of a first digital signal received by the first input of the voltage dividing circuit and a reference voltage of the signal detection device.

[0057] In any possible implementation form of the fifth aspect, each of the plurality of inputs of the voltage dividing circuit corresponds to a different voltage dividing weight.

[0058] In any possible implementation form of the fifth aspect, the processing unit is specifically configured to determine the level state of each of the plurality of digital signals according to the first voltage value, the reference voltage of the signal detection device and weight information, the weight information comprising the voltage dividing weight corresponding to each of the plurality of inputs of the voltage dividing circuit.

[0059] In any possible implementation form of the fifth aspect, the processing unit is specifically configured to determine the level state of each of the plurality of digital signals according to the first voltage value and mapping information, the mapping information comprising a corresponding relationship between the first voltage value and the level state of each of the plurality of digital signals.

[0060] In a sixth aspect, the present application provides a device for signal detection, the device comprising a processor and a memory, wherein the memory is configured to store program instructions; the processor is configured to invoke the program instructions in the memory, so that the device executes the method in the second aspect or any possible implementation form of the second aspect, or executes the method in the third aspect or any possible implementation form of the third aspect.

[0061] In a seventh aspect, the present application provides a vehicle, the vehicle comprising the device in the first aspect or any possible implementation form of the first aspect, or comprising the device in the fourth aspect or any possible implementation form of the fourth aspect, or comprising the device in the fifth aspect or any possible implementation form of the fifth aspect, or comprising the device in the sixth aspect.

[0062] In an eighth aspect, the present application provides a computer readable storage medium, comprising computer instructions, which when executed by a processor, implement the method in the first aspect or any possible implementation of the first aspect.

[0063] In a ninth aspect, the present application provides a computer program product, which when executed by a processor, implements the method in the second aspect or any possible implementation of the second aspect, or implements the method in the third aspect or any possible implementation of the third aspect. Exemplarily, the computer program product can be a software installation package. BRIEF DESCRIPTION OF DRAWINGS

[0064] FIG. 1 is a structural schematic diagram of a signal detection device provided by an embodiment of the present application;

[0065] FIG. 2 is a circuit structure diagram of a voltage dividing circuit with four input ends provided by an embodiment of the present application;

[0066] FIG. 3 is a circuit structure diagram of a detection device provided by an embodiment of the present application;

[0067] FIG. 4 is a circuit structure diagram of another detection device provided by an embodiment of the present application;

[0068] FIG. 5A is a circuit structure diagram of another detection device provided by an embodiment of the present application;

[0069] FIG. 5B is a circuit structure diagram of another signal detection device provided by an embodiment of the present application;

[0070] FIG. 6 is a flow chart of a signal detection method provided by an embodiment of the present application;

[0071] FIG. 7 is a flow chart of another signal detection method provided by an embodiment of the present application;

[0072] FIG. 8 is a structural schematic diagram of a control device provided by an embodiment of the present application;

[0073] FIG. 9 is a structural schematic diagram of a computing device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0074] In the present solution, prefix words such as "first", "second" are used only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. For example, the ordinal words before the described objects "fields" in "first field" and "second field" do not limit the position or order between the "fields", and "first" and "second" do not limit whether the "fields" they modify are in the same message or not, nor do they limit the order of "first field" and "second field". For another example, the ordinal words before the described objects "levels" in "first level" and "second level" do not limit the priority between the "levels". For another example, the quantity of the described objects is not limited by the prefix words, and can be one or more. For example, "first device", where the quantity of "devices" can be one or more. In addition, the objects modified by different prefix words can be the same or different, for example, the described objects are "devices", then "first device" and "second device" can be the same device, the same type of device or different types of devices; for another example, the described objects are "information", then "first information" and "second information" can be information of the same content or information of different content. In summary, the use of prefix words in the embodiments of the present application to distinguish the described objects does not constitute a limitation on the described objects, and the description of the described objects should be referred to the description of the context in the claims or embodiments, and should not constitute an unnecessary limitation because of the use of such prefix words.

[0075] In the present solution, description methods such as "at least one (or at least one) of a1, a2, … and an" are used, which includes any one of a1, a2, … and an existing alone, and also includes any combination of any number of a1, a2, … and an, each of which can exist alone. For example, the description method of "at least one of a, b and c" includes the cases of a alone, b alone, c alone, a and b combination, a and c combination, b and c combination, or abc three combination.

[0076] For ease of understanding, the related terms and the like that may be involved in the present solution are introduced as follows.

[0077] (1) GPIO

[0078] GPIO refers to a general purpose input / output (general purpose input / output) port, which is a general digital signal interface. GPIO is usually associated with a pin in a microcontroller, microprocessor or other integrated circuit, and is used to transmit digital signals between external devices and chips.

[0079] (2) Analog-to-digital converter

[0080] Analog-to-digital converter (ADC) refers to an electronic element that converts an analog signal into a digital signal. For example, an ADC can convert a continuously varying analog voltage connected to a pin into a digital variable (e.g., voltage value) stored in memory.

[0081] (3) Digital-to-analog converter

[0082] Digital-to-analog converter (DAC) refers to an electronic element that converts a digital signal into an analog signal, which can also be referred to as a D / A converter. As can be seen, a DAC is the opposite of an ADC.

[0083] (4) Comparator

[0084] A comparator is a device that can compare the magnitudes of two input signals (e.g., analog voltages) at its input terminals.

[0085] Exemplarily, a comparator has two input terminals (i.e., a non-inverting input terminal and an inverting input terminal) and an output terminal, the input terminals receive analog signals, and the output terminal outputs a digital signal. When the input signal at the non-inverting input terminal is greater than the input signal at the inverting input terminal, the output terminal of the comparator outputs a digital signal indicating a high level, for example, outputs "1"; when the input signal at the non-inverting input terminal is less than the input signal at the inverting input terminal, the output terminal of the comparator outputs a digital signal indicating a low level, for example, outputs "0". In some schemes, the non-inverting input terminal can also be referred to as a positive input terminal or a non-inverting terminal, and the inverting input terminal can also be referred to as a negative input terminal or an inverting terminal.

[0086] When a large number of digital signals are currently detected by using digital devices, the number of GPIO pins possessed by the digital devices is required to be high, and when the number of digital signals to be monitored is greater than the number of GPIO pins possessed by the digital devices, the cost required for modification of the digital devices is high. In order to solve this technical problem, some signal detection devices are provided in the present scheme, which can be used for monitoring a large number of digital signals, and the number of GPIO pins possessed by the digital devices is required to be low, and the implementation cost is also low.

[0087] Here, the digital device can be the above-mentioned CPLD, SOC, microcontroller unit (MCU), etc.

[0088] Referring to FIG. 1, FIG. 1 is a structural schematic diagram of a signal detection apparatus provided by an embodiment of the present application. In FIG. 1, the signal detection apparatus comprises a detection apparatus, an input end of the detection apparatus is connected with an output end of a voltage dividing circuit, the voltage dividing circuit has a plurality of input ends, the plurality of input ends of the voltage dividing circuit are used for receiving a plurality of digital signals to be detected, one digital signal in the plurality of digital signals corresponds to one input end in the plurality of input ends; wherein the voltage dividing circuit is used for outputting an output voltage according to voltages at the plurality of input ends of the voltage dividing circuit, the detection apparatus is used for determining that the output voltage of the voltage dividing circuit is a first voltage value, and determining a level state of each digital signal in the plurality of digital signals based on the first voltage value.

[0089] The first voltage value corresponds to a current level state of the plurality of digital signals received by the plurality of input ends of the voltage dividing circuit. When a level state of one digital signal in the plurality of digital signals changes, the first voltage value also changes accordingly.

[0090] Here, the output voltage of the voltage dividing circuit is a voltage at an output end of the voltage dividing circuit. The output voltage of the voltage dividing circuit is associated with the voltages at the plurality of input ends of the voltage dividing circuit.

[0091] Taking a first input end in the plurality of input ends of the voltage dividing circuit as an example, the first input end of the voltage dividing circuit is any one input end in the plurality of input ends, assuming that the first input end of the voltage dividing circuit is used for receiving a first digital signal in the plurality of digital signals, the voltage at the first input end of the voltage dividing circuit is associated with the level state of the first digital signal and a reference voltage of the signal detection apparatus.

[0092] Exemplarily, the level state of the digital signal refers to a logic representation of a voltage level of the digital signal at a specific time point. In a digital circuit, two voltage levels are usually used to represent different logic values, for example, a high level and a low level, wherein the logic value corresponding to the high level is represented as a first logic value, the logic value corresponding to the low level is a second logic value, for example, the first logic value is "1" and the second logic value is "0".

[0093] The reference voltage of the signal detection device is used to represent the input / output (IO) power voltage corresponding to the digital signal received by the input end of the voltage dividing circuit. For example, when the level state of the digital signal is "1" to indicate a high level and "0" to indicate a low level, the voltage at the first input end of the voltage dividing circuit is associated with the level state of the first digital signal and the reference voltage of the signal detection device, which can be the product of the level state of the first digital signal and the reference voltage of the signal detection device. For example, assuming that the reference voltage of the signal detection device is "5v", when the level state of the first digital signal is "1", the voltage at the first input end of the voltage dividing circuit is "5v" at a high level; when the level state of the first digital signal is "0", the voltage at the first input end of the voltage dividing circuit is "0v" at a high level. In some schemes, the IO power voltages corresponding to the plurality of digital signals can also be different. In this case, the reference voltage of the signal detection device includes the input / output (IO) power voltage corresponding to each digital signal in the plurality of digital signals, and the voltage at the first input end of the voltage dividing circuit is associated with the level state of the first digital signal and the IO power voltage corresponding to the first digital signal.

[0094] In an implementation, the signal detection device includes the detection device and the voltage dividing circuit.

[0095] For example, the number of input ends of the voltage dividing circuit is greater than or equal to the number of digital signals to be detected. Each input end of the voltage dividing circuit is used to receive one digital signal to be detected. In this way, the demand for monitoring large-scale digital signals can be met.

[0096] For example, the voltage dividing circuit is a resistive voltage dividing network, i.e., the voltage dividing circuit includes a plurality of resistors. After the resistance values of the resistors of the voltage dividing circuit are determined, the voltage dividing weight corresponding to each input end of the voltage dividing circuit can be calculated by Ohm's law. The calculation of the voltage dividing weight has been applied for a long time and will not be described here. In this scheme, the design idea of the voltage dividing circuit is to set the resistance values of the resistors of the voltage dividing circuit such that the voltage dividing weights corresponding to each input end of the voltage dividing circuit are different. In other words, the voltage dividing weights corresponding to any two input ends of the plurality of input ends of the voltage dividing circuit are different.

[0097] For the convenience of describing the structure of the voltage dividing circuit, the voltage dividing circuit with four input terminals is taken as an example for description, but it is not limited that the voltage dividing circuit has only four input terminals. Referring to FIG. 2, which is a circuit structure diagram of a voltage dividing circuit with four input terminals according to an embodiment of the present application. The four input terminals of the voltage dividing circuit are input terminal 1, input terminal 2, input terminal 3 and input terminal 4, wherein the voltage at the input terminal 1 is represented as V1, the voltage at the input terminal 2 is represented as V2, the voltage at the input terminal 3 is represented as V3 and the voltage at the input terminal 4 is represented as V4, and the voltage at the output terminal of the voltage dividing circuit is represented as V0.

[0098] In FIG. 2, the voltage dividing circuit is composed of eight resistors, which are R1-R8. The connection relationship of the eight resistors can be: the first terminal of the resistor R1 is grounded, the second terminal of the resistor R1 is connected with the first terminal of the resistor R3 and the first terminal of the resistor R2 respectively, the second terminal of the resistor R2 is the input terminal 4 of the voltage dividing circuit, the second terminal of the resistor R3 is connected with the first terminal of the resistor R4 and the second terminal of the resistor R6 respectively, the first terminal of the resistor R6 is the input terminal 3 of the voltage dividing circuit, the second terminal of the resistor R4 is connected with the first terminal of the resistor R5 and the second terminal of the resistor R7 respectively, the first terminal of the resistor R7 is the input terminal 2 of the voltage dividing circuit, the second terminal of the resistor R5 is the output terminal of the voltage dividing circuit, the second terminal of the resistor R5 is also connected with the second terminal of the resistor R8, and the first terminal of the resistor R8 is the input terminal 1 of the voltage dividing circuit.

[0099] Here, the circuit structure of the voltage dividing circuit shown in FIG. 2 is only an example and should not be limited to the number of resistors included in the voltage dividing circuit and the connection relationship of each resistor in the voltage dividing circuit. In some schemes, the voltage dividing circuit shown in FIG. 2 can also not have the resistors R6, R7 and R8. The design of the voltage dividing circuit only needs to satisfy that the voltage dividing weights of the voltages at different input terminals of the voltage dividing circuit are different. That is, when designing the resistance values of each resistor in the voltage dividing circuit shown in FIG. 2, it is necessary to satisfy that the voltage dividing weights of any two of V1, V2, V3 and V4 are different.

[0100] Taking the first input terminal of the multiple input terminals of the voltage dividing circuit as an example, the first input terminal of the voltage dividing circuit is used to receive the first digital signal of the multiple digital signals, and the voltage dividing weight corresponding to the first input terminal of the voltage dividing circuit is used to represent the contribution degree or contribution rate of the voltage at the first input terminal of the voltage dividing circuit to the output voltage of the voltage dividing circuit.

[0101] That is, the output voltage of the voltage dividing circuit is associated with the voltage at each input terminal of the multiple input terminals of the voltage dividing circuit and the voltage dividing weight corresponding to each input terminal. In combination with FIG. 1, the voltage at the input terminal 1 is represented as V1, the voltage at the input terminal 2 is represented as V2, …, the voltage at the input terminal n is represented as Vn, and the voltage dividing weight corresponding to the input terminal 1 is represented as W1, the voltage dividing weight corresponding to the input terminal 2 is represented as W2, …, the voltage dividing weight corresponding to the input terminal n is represented as Wn. nLet n be a positive integer greater than 1, and let V0 be the output voltage of the voltage divider circuit. Then the relationship between the voltage at each input terminal of the voltage divider circuit and the output voltage of the voltage divider circuit satisfies the following formula (1): V0=w1V1+w2V2+…+w n V n Formula (1)

[0102] Among them, w i For V i The corresponding voltage divider weights, where i is a positive integer less than or equal to n. From formula (1), it can be seen that w i V represents i The contribution rate or degree of contribution to V0. For other parameters in formula (1), please refer to the description of the corresponding content above, and they will not be repeated here.

[0103] Furthermore, since the voltage at the input terminal of the voltage divider circuit is related to the level of the digital signal received at that input terminal and the reference voltage of the signal detection device, that is, the input voltage of the voltage divider circuit is related to the voltage division weight corresponding to each of the multiple input terminals of the voltage divider circuit, the level of the digital signal received at each input terminal, and the reference voltage of the signal detection device.

[0104] For example, assuming the level states of a digital signal include logic value "1" and logic value "0", where logic value "1" indicates a high level, then the voltage V at the input of the voltage divider circuit described above... i The voltage divider circuit's output voltage can be expressed as the product of the digital signal's level and the reference voltage of the signal detection device. Therefore, the output voltage can be represented by the following formula (2): V0 = w1L1V base +w2L2V base +…+w n L n V base Formula (2)

[0105] Among them, V base L represents the reference voltage of the signal detection device. i L represents the level state of the digital signal i received at input terminal i of the voltage divider circuit. i The value of w is either "0" or "1". i L represents the voltage division weight corresponding to the digital signal i in the voltage divider circuit. i V base Vi represents the voltage at input terminal i of the voltage divider circuit, where i is a positive integer less than or equal to n, and V0 represents the output voltage of the voltage divider circuit. Here, formula (2) is only used as an example. In this embodiment, the IO power supply voltage corresponding to each of the above multiple digital signals is the same, so the reference voltage of the signal detection device is the IO power supply voltage, which is expressed as V0. base.

[0106] In some schemes, it is also possible that the IO power supply voltages corresponding to the digital signals in the plurality of digital signals are different. In this case, the reference voltage of the signal detection device includes the IO power supply voltage corresponding to each digital signal in the plurality of digital signals, and the output voltage of the voltage dividing circuit can be represented by the following formula (3). V0 = w1L1V base_1 + w2L2V base_2 + … + w n L n V base_n Formula (3)

[0107] wherein V base_1 represents the IO power supply voltage corresponding to the digital signal 1, V base_2 represents the IO power supply voltage corresponding to the digital signal 2, …, V base_n represents the IO power supply voltage corresponding to the digital signal n, and the other parameters in formula (3) refer to the descriptions of the corresponding parameters in formula (2) above, which will not be repeated here.

[0108] For formula (2), in the case where the detection device can determine that the output voltage V0 of the voltage dividing circuit takes the first voltage value, since the weight information is known, the weight information includes the voltage dividing weight corresponding to each input end of the plurality of input ends of the voltage dividing circuit, i.e., the parameters {w1, w2, …, w n} are known, and the reference voltage of the signal detection device is also known, and the values of L i are either “0” or “1”, therefore the detection device can solve {L1, L 2, ..., L n} in formula (2) by formula (2), i.e., obtains the level state of each digital signal in the plurality of digital signals corresponding to the case where the output voltage V0 of the voltage dividing circuit takes the first voltage value. Similarly, {L1, L 2, ..., L n} can also be solved by formula (3).

[0109] Some possible implementation manners of the circuit structure of the detection device capable of detecting the output voltage of the voltage dividing circuit will be specifically introduced below, please refer to implementation manner 1-implementation manner 3.

[0110] Implementation manner 1:

[0111] In the implementation, the detection apparatus comprises an analog-to-digital converter (ADC) and a controller, the input end of the detection apparatus is an input end of the ADC, the input end of the ADC is connected with the output end of the voltage dividing circuit, the output end of the ADC is connected with the controller, in this case, the detection apparatus is used to determine that the output voltage of the voltage dividing circuit is the first voltage value, and determine the level state of each digital signal in the plurality of digital signals based on the first voltage value, which comprises: the ADC is used to determine that the output voltage of the voltage dividing circuit is the first voltage value, and the controller is used to determine the level state of each digital signal in the plurality of digital signals based on the first voltage value. In the implementation, the circuit structure of the control circuit can refer to FIG. 3, which is a circuit structure diagram of a detection apparatus according to an embodiment of the present application.

[0112] In FIG. 3, the ADC and the controller can be separately arranged. In some schemes, the ADC can also be integrated into the controller.

[0113] Implementation 2

[0114] In the implementation, the detection apparatus comprises a first DAC, a first comparator and a controller, the input end of the detection apparatus comprises a first input end of the first comparator, the first input end of the first comparator is connected with the output end of the voltage dividing circuit, the output end of the first comparator is connected with the controller, the controller is further connected with an input end of the first DAC, and an output end of the first DAC is connected with a second input end of the first comparator, in this case, the detection apparatus is used to determine that the output voltage of the voltage dividing circuit is the first voltage value, and determine the level state of each digital signal in the plurality of digital signals based on the first voltage value, which comprises: the controller is used to control the size of the voltage output by the first DAC, the first comparator is used to output a first result, the first result is a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the first DAC, the controller is further used to determine that the output voltage of the voltage dividing circuit is the first voltage value based on the change of the first result, and determine the level state of each digital signal in the plurality of digital signals based on the first voltage value. In some schemes, the controller is also used to determine that the output voltage of the voltage dividing circuit is the first voltage value based on the first result.

[0115] Referring to FIG. 4, which is a circuit structure diagram of a detection apparatus according to an embodiment of the present application, the circuit structure of the detection apparatus shown in FIG. 4 is an example of the circuit structure of the detection apparatus in the implementation 2, in FIG. 4, the output end of the voltage dividing circuit is connected with an inverting input end of the first comparator, the output end of the first comparator is connected with the controller, the controller is further connected with an input end of the first DAC, and an output end of the first DAC is connected with a non-inverting input end of the first comparator.

[0116] Based on the connection relationship of each device in the detection apparatus shown in FIG. 4, it can be seen that in FIG. 4, the first input end of the first comparator is the inverting input end of the first comparator, and the second input end of the first comparator is the non-inverting input end of the first comparator. In some schemes, the first input end of the first comparator can also be the non-inverting input end of the first comparator, and the second input end of the first comparator is the inverting input end of the first comparator.

[0117] In FIG. 4, the first DAC, the first comparator, and the controller can be separately and independently arranged. In some schemes, one or more of the first DAC and the first comparator can be integrated into the controller.

[0118] Implementation 3:

[0119] In this implementation, the detection apparatus includes a first DAC, a second DAC, a first comparator, a second comparator, and a controller. Compared with the circuit structure shown in the above-mentioned implementation 2, the implementation 3 adds the second DAC and the second comparator, and the connection relationship among the first DAC, the first comparator, and the controller is described in the above-mentioned implementation 2, which is not repeated here. The connection relationship between the second DAC, the second comparator, and the controller in the implementation 3 is described below.

[0120] The first input end of the second comparator is connected with the output end of the second DAC, the input end of the detection apparatus further includes the second input end of the second comparator, that is, the second input end of the second comparator is connected with the output end of the voltage dividing circuit, the output end of the second comparator is connected with the controller, the controller is further connected with the input end of the second DAC, and the second input end of the second comparator is opposite to the first input end of the first comparator; in this case, the controller is further configured to control the size of the voltage output by the second DAC, and the second comparator is configured to output a second result, the second result being the comparison result of the output voltage of the voltage dividing circuit and the voltage output by the second DAC; the controller is further configured to determine that the output voltage of the voltage dividing circuit is the first voltage value based on the change of the first result, including that the controller is further configured to determine that the output voltage of the voltage dividing circuit is the first voltage value according to the changes of the first result and the second result. In some schemes, the controller is also configured to determine that the output voltage of the voltage dividing circuit is the first voltage value according to the first result and the second result.

[0121] Here, the second input end of the second comparator being opposite to the first input end of the first comparator includes that the first input end of the first comparator is the inverting input end of the first comparator, and the second input end of the second comparator is the non-inverting input end of the second comparator; or the first input end of the first comparator is the non-inverting input end of the first comparator, and the second input end of the second comparator is the inverting input end of the second comparator.

[0122] Referring to FIG. 5A, it is a circuit structure diagram of a detection device provided by an embodiment of the present application. The circuit structure of the detection device shown in FIG. 5A is an example of the circuit structure of the detection device in the above-mentioned implementation manner 3. As can be seen from FIG. 5A, compared with FIG. 4, the newly added devices include a second DAC and a second comparator. In FIG. 5A, the connection relationship among the first DAC, the first comparator and the controller is described above with reference to the corresponding content of FIG. 4. The connection relationship among the second DAC, the second comparator and the controller is described as follows: the output end of the voltage dividing circuit is connected with the non-inverting input end of the second comparator, the output end of the second comparator is connected with the controller, the controller is further connected with the input end of the second DAC, and the output end of the second DAC is connected with the inverting input end of the second comparator. As can be seen from FIG. 5A, the first input end of the second comparator is the inverting input end of the second comparator, and the second input end of the second comparator is the non-inverting input end of the second comparator.

[0123] Based on the connection relationship among the devices in the detection device shown in FIG. 5A, it can be seen that in FIG. 5A, the first input end of the first comparator is the inverting input end of the first comparator, the second input end of the second comparator is the non-inverting input end of the second comparator, and the second input end of the second comparator is opposite to the first input end of the first comparator. In some schemes, when the first input end of the first comparator is the non-inverting input end of the first comparator, the second input end of the second comparator is the inverting input end of the second comparator, the second input end of the first comparator is the inverting input end of the first comparator, and the first input end of the second comparator is the non-inverting input end of the second comparator.

[0124] Exemplarily, in FIG. 5A, when the voltage dividing circuit adopts the circuit structure shown in FIG. 2, the circuit structure shown in FIG. 5B can be obtained. The connection mode of the voltage dividing circuit in FIG. 5B can be referred to the description of FIG. 2 above, and the internal connection mode of the detection device in FIG. 5B can be referred to the description of the corresponding content in FIG. 5A, which will not be described here.

[0125] In FIG. 5A, the first DAC, the second DAC, the first comparator, the second comparator and the controller can be separately and independently arranged. In some schemes, one or more of the first DAC, the second DAC, the first comparator and the second comparator can be integrated into the controller.

[0126] Based on the circuit structure shown in FIGS. 3-5A, it can be seen that the plurality of digital signals to be detected are received by the voltage dividing circuit, and the detection device can be connected to the voltage dividing circuit through one or two interfaces, and the detection device can determine the output voltage of the voltage dividing circuit and determine the level state of each digital signal in the plurality of digital signals to be detected according to the output voltage of the voltage dividing circuit. In this way, the monitoring of the plurality of external digital signals is realized at a lower cost, and it is not required that the number of GPIO pins possessed by the detection device should be greater than or equal to the number of digital signals to be detected, thereby reducing the requirement for the number of GPIO pins of the device. It can be seen that in the circuit structure shown in FIG. 3 or FIG. 4, the detection device is connected to the voltage dividing circuit through one interface. In the circuit structure shown in FIG. 5A, the detection device is connected to the voltage dividing circuit through two interfaces.

[0127] Compared with FIG. 4, the circuit structure using the detection device shown in FIG. 5A enables the controller to determine the output voltage of the voltage dividing circuit more quickly, so as to more quickly acquire the level state of the corresponding digital signal, which is beneficial to improve the detection efficiency of the digital signal. In addition, the circuit structure of the detection device shown in FIG. 5A can also support interrupt detection, so that the controller can timely perceive the change of the level state of the digital signal through the change of the output result of the comparator. The specific detection method is described in the corresponding content of the following embodiment of FIG. 7, which is not described here again.

[0128] The signal detection method provided by the embodiment of the present application is described below based on the foregoing circuit structure. Please refer to the description of FIG. 6 and FIG. 7 below.

[0129] Referring to FIG. 6, FIG. 6 is a flowchart of a signal detection method provided by an embodiment of the present application. The method is applied to a controller in a detection device, and the detection device is connected to a voltage dividing circuit, and a plurality of input terminals of the voltage dividing circuit are used to receive a plurality of digital signals to be detected. The detection device can be the detection device shown in FIG. 3 described above, and the controller is the controller in the detection device shown in FIG. 3.

[0130] The detection device further includes an ADC, and the connection relationship among the ADC, the controller and the voltage dividing circuit is described in the foregoing related description of FIG. 3.

[0131] The method includes but is not limited to the following steps S601-S602.

[0132] S601: Acquire the output voltage of the voltage dividing circuit from the ADC, and the output voltage of the voltage dividing circuit is a first voltage value.

[0133] Here, the multiple input terminals of the voltage divider circuit are used to receive multiple digital signals, the output terminal of the voltage divider circuit is connected to the input terminal of the ADC, and the output terminal of the ADC is connected to the controller. Obtaining the output voltage of the voltage divider circuit from the ADC includes: obtaining the output voltage of the voltage divider circuit from the output terminal of the ADC.

[0134] S602: Determine the level state of each digital signal among the multiple digital signals received by the voltage divider circuit based on the first voltage value.

[0135] In one implementation, determining the level state of each of the plurality of digital signals based on a first voltage value includes: determining the level state of each of the plurality of digital signals based on the first voltage value, the reference voltage of the signal detection device, and weight information. The weight information includes the voltage division weight corresponding to each of the plurality of input terminals of the voltage divider circuit. The voltage division weights are described in the corresponding content of the embodiment in Figure 1 above and will not be repeated here.

[0136] Here, the weight information is pre-stored locally on the controller. For example, the weight information can be pre-written into the controller by the configuration personnel, or it can be obtained by the controller during the initialization phase. In some solutions, the weight information can also be obtained by the controller when it needs to determine the level state of a digital signal.

[0137] Knowing the first voltage value, weight information, and the reference voltage of the signal detection device, for example, based on the above formula (2), the first voltage value is substituted into parameter V0, and the reference voltage of the signal detection device is substituted into parameter V. base Substitute the specific weighting values ​​into {W1, W2, ..., W...} n In the corresponding parameters of}, and {W1, W2, ..., W n} satisfies that any two parameters have different values, and L i The value of can be either "0" or "1", so the {L1, L2, ..., L} in formula (2) can be solved. n}, {L1, L2, ..., L n} This refers to the level state of each of the aforementioned digital signals when the output voltage V0 of the voltage divider circuit is the first voltage value.

[0138] In one implementation, determining the level state of each of the plurality of digital signals based on a first voltage value includes: obtaining the level state of each of the plurality of digital signals based on the first voltage value and mapping information, wherein the mapping information includes the correspondence between the first voltage value and the level state of each of the plurality of digital signals.

[0139] Exemplarily, the mapping information is obtained based on the weight information and the reference voltage of the signal detection device.

[0140] For the convenience of describing the obtaining process of the mapping information, it is assumed that there are four digital signals to be detected externally, and the voltage dividing circuit in FIG. 3 can be replaced by the voltage dividing circuit shown in FIG. 2, wherein the input end 1 is used to receive the digital signal 1, the input end 2 is used to receive the digital signal 2, the input end 3 is used to receive the digital signal 3, and the input end 4 is used to receive the digital signal 4. Based on the resistance settings of the resistors in FIG. 2, it is assumed that the relationship between the level state of the digital signal received at each input end of the voltage dividing circuit and the output voltage of the voltage dividing circuit satisfies the following formula (4):

[0141] wherein V0 represents the output voltage of the voltage dividing circuit, L j represents the level state of the digital signal j, wherein the value of j includes {1, 2, 3, 4}, V base represents the reference voltage of the signal detection device, and are both voltage dividing weights.

[0142] It is assumed that the value of V base is “5v”, and the value of L j is “0” or “1”. The value of L j is combined, and the value of L j is substituted into the above formula (4) to calculate the value of the parameter V0. In this way, the mapping information can be obtained, which can be represented as the following Table 1.

[0143] Referring to Table 1, the mapping information shown in Table 1 includes the corresponding relationship between the level state of the plurality of digital signals and the output voltage of the voltage dividing circuit. Taking the corresponding relationship “L4(0)-L3(0)-L2(0)-L1(1)-V0(0.3125)” in Table 1 as an example, it is explained that when the output voltage V0 of the voltage dividing circuit is the first voltage value “0.3125v”, the level state of the plurality of digital signals corresponding thereto is respectively: the level state of the digital signal 4 is “0”, the level state of the digital signal 3 is “0”, the level state of the digital signal 2 is “0”, and the level state of the digital signal 1 is “1”.

[0144] As can be seen from Table 1, the level states of the plurality of digital signals have multiple groups of values, each group of values including one level state of each digital signal in the plurality of digital signals, for example, {L4(0), L3(0), L2(0), L1(1)} is one group of values. When the level states of the plurality of digital signals are a first group of values, the output voltage of the voltage dividing circuit is a first target voltage value; when the level states of the plurality of digital signals are a second group of values, the output voltage of the voltage dividing circuit is a second target voltage value, wherein the first group of values is different from the second group of values, and the first target voltage value is different from the second target voltage value. In addition, when the level state of one digital signal in the plurality of digital signals changes, the output voltage of the voltage dividing circuit also changes.

[0145] Table 1 mapping information (reference voltage is 5v)

[0146] Here, Table 1 is only an example of a storage form of mapping information. In actual applications, the textual content and storage method of the correspondence described in Table 1 can also be other forms, for example, the mapping information shown in Table 1 can include the correspondence between the voltage at each input terminal of the voltage dividing circuit and the output voltage of the voltage dividing circuit, and the correspondence between the level state of the plurality of digital signals and the voltage at each input terminal of the voltage dividing circuit.

[0147] For example, when the first voltage value is "0.3125v", the mapping information shown in Table 1 is searched based on the first voltage value "0.3125v", and it is obtained that the level state of the plurality of digital signals corresponding to the first voltage value "0.3125v" includes: the level state of digital signal 1 is "1", the level state of digital signal 2 is "0", the level state of digital signal 3 is "0", and the level state of digital signal 4 is "0".

[0148] For example, the controller can periodically execute the above S601 and S602, so that the external plurality of digital signals can be periodically detected. In some schemes, the controller can also execute the above S601 and S602 in real time, so that the external plurality of digital signals can be detected in real time.

[0149] In the embodiment of FIG. 6, the plurality of digital signals to be detected are received by the voltage dividing circuit, and the controller is connected to the voltage dividing circuit through the ADC. In this way, the conversion to an analog signal can reduce the need for GPIO pins of the device, and the controller can determine the level state of each digital signal in the plurality of digital signals currently received by the voltage dividing circuit based on the output result of the ADC, so that the level state of the plurality of digital signals can be monitored in real time.

[0150] Referring to FIG. 7, FIG. 7 is a flowchart of another signal detection method according to an embodiment of the present application. The method can be applied to a controller in a detection device, the detection device being connected with a voltage dividing circuit, and a plurality of inputs of the voltage dividing circuit being configured to receive a plurality of digital signals to be detected.

[0151] In one implementation, the detection device is the detection device shown in FIG. 4, and the controller is the controller in the detection device shown in FIG. 4. In this case, the detection device further includes a first DAC and a first comparator. The connection relationship between the components in the detection device and the voltage dividing circuit is described above with reference to FIG. 4.

[0152] In another implementation, the detection device is the detection device shown in FIG. 5A, and the controller is the controller in the detection device shown in FIG. 5A. In this case, the detection device further includes a first DAC, a first comparator, a second DAC and a second comparator. The connection relationship between the components in the detection device and the voltage dividing circuit is described above with reference to FIG. 5A.

[0153] The method shown in FIG. 7 includes but is not limited to the following steps:

[0154] S701: Control the first DAC to output a voltage, and obtain a first result output by the first comparator.

[0155] The first result is a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the first DAC.

[0156] For example, the controller controls the first DAC to output the voltage, including: the controller sends a control instruction to the first DAC, the control instruction indicating that the voltage output by the first DAC is a target voltage value. The target voltage value belongs to the voltage range interval (0, reference voltage of the signal detection device). The target voltage value is used to compare with the output voltage of the current voltage dividing circuit.

[0157] For example, the controller can select an arbitrary voltage value in the voltage range interval (0, reference voltage of the signal detection device) as the target voltage value. Alternatively, the controller has the mapping information stored locally, and the controller can determine the target voltage value based on some possible output voltages of the voltage dividing circuit in the mapping information, but the target voltage value still belongs to the voltage range interval (0, reference voltage of the signal detection device). For example, the target voltage value can be less than a certain voltage value in the mapping information, or greater than a certain voltage value in the mapping information.

[0158] For the first comparator, assuming that the output terminal of the first DAC is connected to the non-inverting input terminal of the first comparator and the output terminal of the voltage dividing circuit is connected to the inverting input terminal of the first comparator, when the voltage outputted by the first DAC is greater than the output voltage of the voltage dividing circuit, the first result takes the first target value, for example, the first target value is "1"; when the voltage outputted by the first DAC is less than the output voltage of the voltage dividing circuit, the first result takes the second target value, for example, the second target value is "0". In this way, the detection device knows the size relationship between the output voltage of the voltage dividing circuit and the target voltage value according to the first result.

[0159] S702: determining that the output voltage of the voltage dividing circuit is the first voltage value according to the change of the first result.

[0160] In an implementation manner, the determining that the output voltage of the voltage dividing circuit is the first voltage value according to the change of the first result comprises: the controller can control the size of the voltage outputted by the first DAC, and determine that the output voltage of the voltage dividing circuit is the first voltage value according to the change of the first result and the mapping information. The mapping information comprises the values of the output voltage of the voltage dividing circuit in different level states of the plurality of digital signals.

[0161] In this way, the controller controls the first DAC to output different voltages to observe the change of the output result of the first comparator, and this kind of successive approximation method can determine the output voltage of the voltage dividing circuit.

[0162] In some schemes, the controller can also determine that the output voltage of the voltage dividing circuit is the first voltage value according to the change of the first result, the weight information and the reference voltage of the signal detection device.

[0163] In combination with FIG. 4, the following takes a specific example to illustrate the process of determining the output voltage of the voltage dividing circuit by the controller:

[0164] Suppose the voltage range is (0, 5v), the controller first controls the first DAC to output a voltage of a first target voltage value (for example, 0.35v), in which case the first result output by the first comparator is "1", indicating that the output voltage of the voltage dividing circuit is less than 0.35v; then, the controller controls the first DAC to output a voltage of a second target voltage value (for example, 0.25v), in which case the first result output by the first comparator is "0", indicating that the output voltage of the voltage dividing circuit is greater than 0.25v. As can be seen, the first result output by the first comparator is different in the two cases, and it can be determined that the output voltage of the voltage dividing circuit is in the voltage range (0.25v, 0.35v). Further, in combination with some possible output voltages of the voltage dividing circuit in the mapping information shown in Table 1, it can be seen that the only voltage value in the voltage range (0.25v, 0.35v) in Table 1 is 0.3125v, so it is determined that the output voltage of the voltage dividing circuit is 0.3125v, i.e., the first voltage value is 0.3125v. In this scheme, the controller determines the output voltage of the voltage dividing circuit by default, without changing the output voltage of the voltage dividing circuit.

[0165] Here, the control of the controller on the first DAC is affected by the output result of the first comparator. For example, the controller can adjust the voltage output by the first DAC according to the first result output by the first comparator. When the first result is "1", the controller can control the first DAC to decrease the output voltage (i.e., the target voltage value is decreased); when the first result is "0", the controller can control the first DAC to increase the output voltage (i.e., the target voltage value is increased). In this way, the voltage output by the first DAC can gradually approach the output voltage of the voltage dividing circuit.

[0166] When applied to the circuit structure shown in FIG. 5A, the controller can determine the output voltage of the voltage dividing circuit by controlling any one of the first DAC and the second DAC. When the controller selects to control the voltage output by the second DAC, the controller needs to determine the output voltage of the voltage dividing circuit according to the change of the output result of the second comparator.

[0167] In some schemes, when applied to the circuit structure shown in FIG. 5A, the controller can also determine the output voltage of the voltage dividing circuit by controlling the first DAC and the second DAC. That is, the controller is also configured to control the voltage output by the second DAC, and to obtain a second result output by the second comparator, the second result being a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the second DAC. The above-mentioned determining the output voltage of the voltage dividing circuit as a first voltage value according to the change of the first result includes: determining the output voltage of the voltage dividing circuit as the first voltage value according to the changes of the first result and the second result.

[0168] Exemplarily, the output voltage of the voltage dividing circuit can also be determined as the first voltage value according to the changes of the first result and the second result and mapping information including the values of the output voltage of the voltage dividing circuit in different level states of the plurality of digital signals.

[0169] With reference to FIG. 5A, the process of determining the output voltage of the voltage dividing circuit by the controller is described below with a specific example:

[0170] Suppose the voltage range is (0, 5v), the controller controls the first DAC to output a voltage of a first target voltage value (e.g. 0.35v) and controls the second DAC to output a voltage of a second target voltage value (e.g. 0.25v), in this case, the first result output by the first comparator is “1” and the second result output by the second comparator is also “1”, which indicates that the output voltage of the voltage dividing circuit is less than 0.35v and the output voltage of the voltage dividing circuit is greater than 0.25v, i.e. the output voltage of the voltage dividing circuit is in the voltage range (0.25v, 0.35v), further, in combination with the mapping information shown in Table 1, it can be seen that the voltage value in the voltage range (0.25v, 0.35v) in Table 1 is only 0.3125v, so it is determined that the output voltage of the current voltage dividing circuit is 0.3125v, i.e. the first voltage value is 0.3125v.

[0171] With the circuit shown in FIG. 5A, the controller can simultaneously control the first DAC and the second DAC to change the size of the output voltage to observe the output result of the corresponding comparator, which can improve the detection efficiency of the output voltage of the voltage dividing circuit, thereby facilitating the improvement of the detection efficiency of the level state of the externally monitored digital signal.

[0172] S703: Determine the level state of each digital signal in the plurality of digital signals received by the voltage dividing circuit according to the first voltage value. For details, please refer to the description of S602 in the embodiment of FIG. 6, which will not be repeated here for the sake of brevity.

[0173] When the above method is applied to the circuit structure shown in FIG. 4, the controller determines the output voltage of the voltage dividing circuit as the first voltage value, i.e. the controller completes the determination of the output voltage of the voltage dividing circuit once, and based on the first voltage value, the controller can know the current level state of each digital signal in the plurality of digital signals to be detected. If real-time detection of the level state of the digital signal is desired, the controller needs to execute steps S701-S702 to determine the current output voltage of the voltage dividing circuit in real time or periodically.

[0174] In some possible embodiments, the circuit structure shown in FIG. 5A can also support interrupt detection. After the controller determines the output voltage of the voltage dividing circuit each time, the controller can optionally perform the following steps S704-S707. In this way, when the controller detects an interrupt signal, the controller can re-determine the current output voltage of the voltage dividing circuit, so that the level state of the external digital signal can be detected in real time without real-time monitoring, and the power consumption of the controller can be reduced.

[0175] S704: determining a second voltage value and a third voltage value according to the first voltage value and a preset offset.

[0176] The preset offset is a positive number less than a preset value, and the preset value is determined based on a reference voltage of the signal detection apparatus and a minimum voltage dividing weight in the weight information.

[0177] For example, when the IO power supply voltage corresponding to each of the plurality of digital signals is the same, the output voltage of the voltage dividing circuit satisfies the formula (2), and the preset value can be the product of the reference voltage of the signal detection apparatus and the minimum voltage dividing weight, i.e., the minimum value of w i V base i is a positive integer less than or equal to n. In some schemes, the preset value can also be half of the product of the reference voltage of the signal detection apparatus and the minimum voltage dividing weight.

[0178] For example, when the IO power supply voltage corresponding to each of the plurality of digital signals is different, the output voltage of the voltage dividing circuit satisfies the formula (3), and the preset value can be the minimum value of w i V base_i i is a positive integer less than or equal to n. In some schemes, the preset value can also be half of the minimum value of w

[0179] The first voltage value is between the second voltage value and the third voltage value, the second voltage value is used to adjust the output of the first DAC, and the third voltage value is used to adjust the output of the second DAC.

[0180] Exemplarily, the first voltage value is between the second voltage value and the third voltage value, including:

[0181] Case 1: the second voltage value > the first voltage value > the third voltage value; or,

[0182] Case 2: the second voltage value < the first voltage value < the third voltage value.

[0183] For case 1, it is explained that the first comparator adopts up bias, and the second comparator adopts down bias. For case 2, it is explained that the first comparator adopts down bias, and the second comparator adopts up bias.

[0184] In one implementation, the second voltage value is the sum of the first voltage value and a preset offset, and the third voltage value is the difference between the first voltage value and the preset offset; or, the second voltage value is the difference between the first voltage value and the preset offset, and the third voltage value is the sum of the first voltage value and the preset offset.

[0185] In another implementation, the preset offset includes a first value and a second value, the first value and the second value are different, and the first value and the second value are less than the preset value, and the determination of the second voltage value and the third voltage value satisfies any one of the following conditions:

[0186] The second voltage value is the sum of the first voltage value and the first value, and the third voltage value is the difference between the first voltage value and the second value; or,

[0187] The second voltage value is the difference between the first voltage value and the first value, and the third voltage value is the sum of the first voltage value and the second value.

[0188] S705: Control the voltage output by the first DAC to be the second voltage value and control the voltage output by the second DAC to be the third voltage value.

[0189] S706: When it is detected that the output result of at least one of the first comparator and the second comparator changes, control the first DAC to change the magnitude of the voltage output, and determine the output voltage of the voltage dividing circuit to be a fourth voltage value according to the change of the output result of the first comparator.

[0190] The fourth voltage value is different from the first voltage value, which means that the level state of at least one of the plurality of digital signals received by the voltage dividing circuit changes. In this way, by detecting the output results of the first comparator and the second comparator, it can be determined whether the level state of the digital signal externally connected to the voltage dividing circuit changes.

[0191] It can be understood that the condition of "detecting that the output result of at least one of the first comparator and the second comparator changes" is equivalent to an interrupt signal, triggering the controller to re-determine the current output voltage of the voltage dividing circuit.

[0192] Exemplarily, the change of the output result of the comparator includes that the output result of the comparator jumps from "1" to "0", or the output result of the comparator jumps from "0" to "1".

[0193] In FIG. 5A, the voltage dividing circuit is specifically shown in FIG. 2, i.e. the detection of four digital signals is implemented, for the convenience of description, the output voltage of the voltage dividing circuit is denoted as V0, the output voltage of the first DAC is denoted as V1, the output voltage of the second DAC is denoted as V2, the output result of the first comparator is denoted as B1, the output result of the second comparator is denoted as B2, in addition, assuming that the reference voltage of the signal detection device is 5v, the relationship between the level state of the digital signal received at each input terminal of the voltage dividing circuit and V0 satisfies the above formula (4), the above preset value is for example assuming that the preset offset is taken as 0.3, assuming that the controller determines that the current V0=0.625v (i.e. the first voltage value is 0.625) through the above steps, the control logic of the controller in the interrupt detection is described below in combination with FIG. 5A:

[0194] (1) V1=V0+0.3 and V2=V0-0.3

[0195] assuming that the current V0=0.625v, V1=0.925v (i.e. the second voltage value is 0.625) and V2=0.325v (i.e. the third voltage value is 0.325) are determined based on the preset offset, in this case, V1>V0, V0>V2, so B1=B2=1;

[0196] assuming that V0 changes from 0.625v to 0.3125 due to the change of the level state of the digital signal, and the current V1=0.925v, V2=0.325v, in this case, V1>V0, V0<V2, so B1=1 but B2=0, it can be seen that only the value of B2 jumps from "1" to "0", i.e. the change of the output result of the second comparator is detected, which triggers the controller to determine the output voltage of the current voltage dividing circuit again.

[0197] assuming that V0 changes from 0.625v to 1.25v due to the change of the level state of the digital signal, and the current V1=0.925v, V2=0.325v, in this case, V1<V0, V0>V2, so B1=0 but B2=1, it can be seen that only the value of B1 jumps from "1" to "0", i.e. the change of the output result of the first comparator is detected, which triggers the controller to determine the output voltage of the current voltage dividing circuit again.

[0198] (2) V1=V0-0.3 and V2=V0+0.3

[0199] assuming that the current V0=0.625v, V1=0.325v (i.e. the second voltage value is 0.325) and V2=0.925v (i.e. the third voltage value is 0.925) are determined based on the preset offset, in this case, V1<V0, V0<V2, so B1=B2=0;

[0200] If the level state of the digital signal changes, causing V0 to change from 0.625v to 0v, and the current V1 = 0.325v and V2 = 0.925v, in this case, V1 > V0 and V0 < V2, so B1 = 1 but B2 = 0. As can be seen, only the value of B1 jumps from "0" to "1", that is, the output result of the first comparator changes, which will trigger the controller to determine the output voltage of the current voltage dividing circuit again.

[0201] If the level state of the digital signal changes, causing V0 to change from 0.625v to 1.25v, and the current V1 = 0.325v and V2 = 0.925v, in this case, V1 < V0 and V0 > V2, so B1 = 0 but B2 = 1. As can be seen, only the value of B2 jumps from "0" to "1", that is, the output result of the second comparator changes, which will trigger the controller to determine the output voltage of the current voltage dividing circuit again.

[0202] Similarly, when V0 changes from 0.625v to other values of V0 in Table 1, it will also cause the output result of one of the first comparator and the second comparator to change, which will not be exemplified one by one here. In addition, the above is an example of determining V1 and V2 when V0 = 0.625v. V0 can also be other values of V0 in Table 1.

[0203] In some schemes, when the first voltage value is the minimum output voltage of the voltage dividing circuit in the mapping information, one of the second voltage value and the third voltage value can be set as the minimum output voltage of the voltage dividing circuit, and the other voltage value can be set as the sum of the first voltage value and a preset offset. When the first voltage value is the maximum output voltage of the voltage dividing circuit in the mapping information, one of the second voltage value and the third voltage value can be set as the maximum output voltage of the voltage dividing circuit, and the other voltage value can be set as the difference between the first voltage value and the preset offset.

[0204] Taking the minimum output voltage 0v of the voltage dividing circuit in Table 1 as the first voltage value and the preset offset as 0.3 as an example, the control logic of the controller is still described in combination with the above Figure 5A:

[0205] (1) V1 = V0 min + 0.3. V2 = V0 min

[0206] If the level state of the digital signal changes, causing V0 to change from 0.625v to 0v, and the current V1 = 0.325v and V2 = 0.925v, in this case, V1 > V0 and V0 < V2, so B1 = 1 but B2 = 0. As can be seen, only the value of B1 jumps from "0" to "1", that is, the output result of the first comparator changes, which will trigger the controller to determine the output voltage of the current voltage dividing circuit again.

[0207] If the level state of the digital signal changes, V0 changes from 0v to 0.3125v, and the current V1 is 0.3v and V2 is 0v, in this case, V1 < V0 and V0 > V2, so B1 = 0 and B2 = 1. As can be seen, the value of B1 jumps from "1" to "0", and the value of B2 jumps from "0" to "1", that is, the output results of both the first comparator and the second comparator change, which triggers the controller to re-determine the output voltage of the current voltage dividing circuit.

[0208] (2) V1 = V0 min , V2 = V0 min + 0.3

[0209] If the level state of the digital signal changes, V0 changes from 0v to 0.3125v, and the current V1 is 0.3v and V2 is 0v, in this case, V1 < V0 and V0 > V2, so B1 = 0 and B2 = 1. As can be seen, the value of B1 jumps from "1" to "0", and the value of B2 jumps from "0" to "1", that is, the output results of both the first comparator and the second comparator change, which triggers the controller to re-determine the output voltage of the current voltage dividing circuit.

[0210] If the level state of the digital signal changes, V0 changes from 0v to 0.3125v, and the current V1 is 0.3v and V2 is 0v, in this case, V1 < V0 and V0 > V2, so B1 = 0 and B2 = 1. As can be seen, the value of B1 jumps from "1" to "0", and the value of B2 jumps from "0" to "1", that is, the output results of both the first comparator and the second comparator change, which triggers the controller to re-determine the output voltage of the current voltage dividing circuit.

[0211] In the above scheme, the control re-determining the output voltage of the current voltage dividing circuit includes: controlling the first DAC to change the size of the output voltage, and determining the output voltage of the voltage dividing circuit as the fourth voltage value according to the change of the output result of the first comparator. This process can be referred to the related description of S701-S702, which will not be repeated here.

[0212] In some schemes, when it is detected that the output result of at least one of the first comparator and the second comparator changes, the controller re-determines the output voltage of the current voltage dividing circuit, which can also be: controlling the second DAC to change the size of the output voltage, and determining the output voltage of the voltage dividing circuit as the fourth voltage value according to the change of the output result of the second comparator; or, respectively controlling the first DAC and the second DAC to change the size of the output voltage, and determining the output voltage of the voltage dividing circuit as the fourth voltage value according to the change of the output result of the first comparator and the second comparator. This implementation can be referred to the related description of S701-S702, which will not be repeated here.

[0213] S707: Determine the level state of each digital signal in the plurality of digital signals received by the voltage dividing circuit according to the fourth voltage value. For details, refer to the description of S602 in the embodiment of FIG. 6. For the sake of brevity of the description, details are not described herein again.

[0214] In the embodiment of FIG. 7, the plurality of digital signals to be detected are received by the voltage dividing circuit, and a detection device is constructed based on a DAC, a comparator and a controller. The voltage dividing circuit is connected to the DAC in the detection device, and the controller changes the output voltage of the DAC to observe the output result of the comparator. According to the change of the output result of the comparator, the output voltage of the voltage dividing circuit at present can be determined, so that the level state of each digital signal in the plurality of digital signals to be detected can be obtained according to the output voltage of the voltage dividing circuit. This analog implementation manner reduces the dependence on GPIO pins of devices, and can realize real-time monitoring of the level state of the plurality of digital signals at a lower cost. In addition, the detection device also supports interrupt detection. Thus, when the controller detects an interrupt signal, it indicates that the level state of the external digital signal has changed, and the output voltage of the voltage dividing circuit at present is determined again to obtain the latest level state of the monitored digital signal. It is not necessary to detect the output voltage of the voltage dividing circuit in real time, which is beneficial to reduce the power consumption of the controller.

[0215] Referring to FIG. 8, FIG. 8 is a structural schematic diagram of a control device provided in an embodiment of the present application. The control device 30 includes an obtaining unit 310 and a processing unit 312. The control device 30 can be implemented in a manner of hardware, software or a combination of software and hardware.

[0216] In an implementation manner, the control device 30 can be the controller in the above-mentioned FIG. 3 or the implementation manner 1. In this case, the obtaining unit 310 is configured to obtain the output voltage of the voltage dividing circuit from the ADC, and the output voltage of the voltage dividing circuit is a first voltage value. The processing unit 312 is configured to determine the level state of each digital signal in the plurality of digital signals received by the voltage dividing circuit according to the first voltage value.

[0217] In the implementation manner, the control device 30 can be used to implement the method described in the embodiment of FIG. 6. In the embodiment of FIG. 6, the obtaining unit 310 can be used to perform S601, and the processing unit 312 can be used to perform S602.

[0218] In another implementation, the control device 30 can be the controller in FIG. 4 or FIG. 5A, or the controller in the above-mentioned implementation 2 or implementation 3, in which case the processing unit 312 is configured to control the magnitude of the voltage output by the first DAC, and the obtaining unit 310 is configured to obtain a first result output by the first comparator, the first result being a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the first DAC; the processing unit 312 is further configured to determine, according to a change in the first result, that the output voltage of the voltage dividing circuit is a first voltage value, and determine, based on the first voltage value, the level state of each of the plurality of digital signals.

[0219] In this implementation, the control device 30 can be used to implement the method described in the embodiment of FIG. 7. In the embodiment of FIG. 7, the obtaining unit 310 can be configured to perform S701, and the processing unit 312 can be configured to perform S702-S703. Optionally, the processing unit 312 can be further configured to perform S704-S707.

[0220] It should be understood that the division of the units in the control device 30 above is only a logical division, and in actual implementation, all or part of the units can be integrated into one physical entity, or can be physically separated. In addition, the units in the device can be implemented in the form of processor calling software; for example, the device includes a processor, the processor is connected with a memory, the memory stores instructions, and the processor calls the instructions stored in the memory to implement any one of the above methods or to implement the functions of the units of the device, wherein the processor is, for example, a general processor such as a central processing unit (CPU) or a microprocessor, and the memory is a memory in the device or a memory outside the device. Alternatively, the units in the device can be implemented in the form of hardware circuit, and the functions of part or all of the units can be implemented through the design of the hardware circuit, which can be understood as one or more processors; for example, in one implementation, the hardware circuit is an application-specific integrated circuit (ASIC), and the functions of part or all of the units are implemented through the design of the logical relationship between the elements in the circuit; for example, in another implementation, the hardware circuit is a programmable logic device (PLD), and a field programmable gate array (FPGA) is taken as an example, which can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured through a configuration file, so as to implement the functions of part or all of the units. All the units of the above device can be implemented in the form of processor calling software, or all the units can be implemented in the form of hardware circuit, or part of the units are implemented in the form of processor calling software, and the remaining part is implemented in the form of hardware circuit.

[0221] In embodiments of the present application, the processor is a circuit with signal processing capability. In one implementation, the processor can be a circuit with instruction reading and running capability, such as a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU) (which can be understood as a microprocessor), a digital signal processor (DSP), etc. In another implementation, the processor can implement certain functions through a logical relationship of hardware circuit, which is fixed or reconfigurable. For example, the processor is a hardware circuit implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the processor loads a configuration document to implement the configuration of the hardware circuit. It can be understood that the processor loads instructions to implement the functions of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc.

[0222] It can be seen that each unit in the above apparatus can be one or more processors (or processing circuits) configured to implement the above methods, such as a CPU, a GPU, an NPU, a TPU, a DPU, a microprocessor, a DSP, an ASIC, an FPGA, or a combination of at least two of these processor forms.

[0223] In addition, each unit in the above apparatus can be integrated together or can be independently implemented. In one implementation, the units are integrated together to form a system-on-a-chip (SOC). The SOC can include at least one processor for implementing any of the above methods or functions of the units of the apparatus. The at least one processor can be of different types, such as a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, etc.

[0224] Referring to FIG. 9, FIG. 9 is a structural schematic diagram of a computing device according to an embodiment of the present application. As shown in FIG. 9, the computing device 40 includes a processor 401, a communication interface 402, a memory 403 and a bus 404. The processor 401, the memory 403 and the communication interface 402 communicate through the bus 404. It should be understood that the number of processors and memories in the computing device 40 is not limited by the present application.

[0225] In an implementation manner, the computing device 40 can be the aforementioned signal detection apparatus, the detection apparatus or a controller in the detection apparatus.

[0226] The bus 404 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one line is shown in FIG. 9, but it does not mean that there is only one bus or one type of bus. The bus 404 can include a channel for transmitting information between various components (for example, the memory 403, the processor 401, the communication interface 402) of the computing device 40.

[0227] The processor 401 can refer to the related description of the processor in the above embodiments, which will not be repeated here.

[0228] The memory 403 is configured to provide a storage space in which data such as an operating system and a computer program can be stored. The memory 403 can be one or a combination of a random access memory (RAM), an erasable programmable read-only memory (EPROM), a read-only memory (ROM) or a compact disc read memory (CD-ROM). The memory 403 can exist independently or be integrated into the processor 401.

[0229] The communication interface 402 can be configured to provide information input or output for the processor 401. Alternatively, the communication interface 402 can be configured to receive data sent by an external device and / or send data to the external device. The communication interface 402 can be a wired link interface such as an Ethernet cable, or a wireless link (such as Wi-Fi, Bluetooth, universal wireless transmission, etc.) interface. Alternatively, the communication interface 402 can further include a transmitter (such as a radio frequency transmitter, an antenna, etc.) coupled with the interface, or a receiver, etc.

[0230] The processor 401 in the computing device 40 is configured to read a computer program stored in the memory 403, and execute the foregoing method, such as the method described in FIG. 6 or FIG. 7.

[0231] In a possible design, the computing device 40 can be one or more modules in an execution subject that executes the method shown in FIG. 6, and the processor 401 can be configured to read one or more computer programs stored in the memory, and execute the following operations:

[0232] The output voltage of the voltage dividing circuit is obtained from the ADC by the obtaining unit 310, and the output voltage of the voltage dividing circuit is a first voltage value;

[0233] The level state of each digital signal in the plurality of digital signals received by the voltage dividing circuit is determined according to the first voltage value.

[0234] In a possible design, the computing device 40 can be one or more modules in an execution subject that executes the method shown in FIG. 7, and the processor 401 can be configured to read one or more computer programs stored in the memory, and execute the following operations:

[0235] The magnitude of the voltage output by the first DAC is controlled;

[0236] The first result output by the first comparator is obtained by the obtaining unit 310, and the first result is a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the first DAC;

[0237] The output voltage of the voltage dividing circuit is determined to be the first voltage value according to the change of the first result, and the level state of each digital signal in the plurality of digital signals is determined based on the first voltage value.

[0238] In the embodiments described above, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments. In addition, in each embodiment of the present application, the terms and / or descriptions of each embodiment are consistent and can be mutually referred to, unless otherwise specified and logically conflicted, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0239] It should be noted that all or part of the steps in the various methods of the above embodiments can be completed by programs instructing relevant hardware, and the programs can be stored in a computer readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage, magnetic tape storage, or any other medium that can be used to carry or store data which is readable by a computer.

[0240] The technical solutions of the present application, in essence or the part that contributes, or all or part of the technical solutions can be embodied in the form of a software product. The computer program product is stored in a storage medium and includes a plurality of instructions for causing a device (which can be a personal computer, a server, or a network device, a robot, a single-chip microcomputer, a chip, a robot, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.

Claims

1. A signal detection device, characterized by, The signal detection apparatus comprises a detection device, an input end of the detection device is connected with an output end of a voltage dividing circuit, a plurality of input ends of the voltage dividing circuit are used for receiving a plurality of digital signals to be detected, one digital signal in the plurality of digital signals corresponds to one input end in the plurality of input ends; The detection device is used for determining that an output voltage of the voltage dividing circuit is a first voltage value, and determining a level state of each digital signal in the plurality of digital signals based on the first voltage value, wherein the output voltage of the voltage dividing circuit is a voltage at an output end of the voltage dividing circuit, and the output voltage of the voltage dividing circuit is associated with voltages at the plurality of input ends of the voltage dividing circuit.

2. The apparatus of claim 1, wherein, The signal detection apparatus further comprises the voltage dividing circuit.

3. The apparatus of claim 1 or 2, wherein, The voltage dividing weight corresponding to each input end in the plurality of input ends of the voltage dividing circuit is different.

4. The device according to any of claims 1-3, characterized in that The plurality of input ends of the voltage dividing circuit comprises a first input end, the first input end of the voltage dividing circuit is used for receiving a first digital signal in the plurality of digital signals, The voltage dividing weight corresponding to the first input end of the voltage dividing circuit is used for characterizing a degree of contribution of a voltage at the first input end of the voltage dividing circuit to the output voltage of the voltage dividing circuit, and the voltage at the first input end of the voltage dividing circuit is associated with the level state of the first digital signal and a reference voltage of the signal detection apparatus.

5. The apparatus of claim 4, wherein, The detection device comprises a first digital-to-analog converter (DAC), a first comparator and a controller, an input end of the detection device comprises a first input end of the first comparator, an output end of the first DAC is connected with a second input end of the first comparator, an input end of the first DAC is connected with the controller, and the controller is further connected with an output end of the first comparator; The controller is used for controlling a size of a voltage output by the first DAC, the first comparator is used for outputting a first result, the first result is a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the first DAC, and the controller is further used for determining that the output voltage of the voltage dividing circuit is the first voltage value based on a change condition of the first result, and determining the level state of each digital signal in the plurality of digital signals based on the first voltage value.

6. The apparatus of claim 5, wherein, The controller is specifically used for: determining the level state of each digital signal in the plurality of digital signals based on the first voltage value, a reference voltage of the signal detection apparatus and weight information, wherein the weight information comprises the voltage dividing weight corresponding to each input end in the plurality of input ends of the voltage dividing circuit.

7. The device of any one of claims 5 or 6, wherein, The detection device further comprises a second DAC and a second comparator, wherein a first input end of the second comparator is connected with an output end of the second DAC, an input end of the detection device further comprises a second input end of the second comparator, an output end of the second comparator is connected with the controller, the controller is further connected with an input end of the second DAC, and the second input end of the second comparator is opposite to the first input end of the first comparator. The controller is further configured to control a magnitude of a voltage output by the second DAC, and the second comparator is configured to output a second result, which is a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the second DAC, and the controller is further configured to determine the output voltage of the voltage dividing circuit as the first voltage value according to changes of the first result and the second result.

8. The apparatus of claim 7, wherein, The controller is further configured to: control the first DAC to output a voltage of a second voltage value and control the second DAC to output a voltage of a third voltage value; when detecting that an output result of at least one of the first comparator and the second comparator changes, control the first DAC to change the magnitude of the output voltage, and determine the output voltage of the voltage dividing circuit as a fourth voltage value according to a change of the output result of the first comparator, the fourth voltage value being different from the first voltage value; determine a level state of each of the plurality of digital signals according to the fourth voltage value; wherein the first voltage value is between the second voltage value and the third voltage value, an offset of the second voltage value relative to the first voltage value is a first value, and an offset of the third voltage value relative to the first voltage value is a second value, the first value and the second value are both positive numbers less than a preset value, and the preset value is determined based on the reference voltage and a minimum voltage dividing weight in weight information, the weight information including a voltage dividing weight corresponding to each of a plurality of input terminals of the voltage dividing circuit.

9. The apparatus of claim 8, wherein: the second voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value; or the third voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value. The detection apparatus includes an analog-to-digital converter (ADC) and a controller, an input terminal of the detection apparatus is an input terminal of the ADC, and an output terminal of the ADC is connected to the controller.

10. The apparatus of claim 4, wherein, The ADC is configured to determine the output voltage of the voltage dividing circuit as the first voltage value, and the controller is configured to determine the level state of each of the plurality of digital signals according to the first voltage value. The controller is specifically configured to:

11. The apparatus of claim 10, wherein, determine the level state of each of the plurality of digital signals according to the first voltage value, a reference voltage of the signal detection apparatus, and weight information, the weight information including a voltage dividing weight corresponding to each of the plurality of digital signals in the voltage dividing circuit. ​ 12. A signal detection method, characterized by, The method is applied to a controller of a detection device, an input end of the detection device is connected with an output end of a voltage dividing circuit, a plurality of input ends of the voltage dividing circuit are used to receive a plurality of digital signals to be detected, one digital signal in the plurality of digital signals corresponds to one input end in the plurality of input ends, the detection device further comprises a first digital-to-analog converter (DAC) and a first comparator, the input end of the detection device comprises a first input end of the first comparator, an output end of the first DAC is connected with a second input end of the first comparator, an input end of the first DAC is connected with the controller, the controller is further connected with an output end of the first comparator, and the method comprises: controlling a first DAC to output a voltage; obtaining a first result output by a first comparator, the first result being a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the first DAC, the output voltage of the voltage dividing circuit being a voltage at the output end of the voltage dividing circuit; determining, according to a change of the first result, that the output voltage of the voltage dividing circuit is a first voltage value, and determining, based on the first voltage value, a level state of each digital signal in the plurality of digital signals, the output voltage of the voltage dividing circuit being associated with voltages at the plurality of input ends of the voltage dividing circuit.

13. The method of claim 12, wherein, Each input end in the plurality of input ends of the voltage dividing circuit corresponds to different voltage dividing weights.

14. The method according to claim 12 or 13, characterized in that, The plurality of input ends of the voltage dividing circuit comprises a first input end, the first input end of the voltage dividing circuit is used to receive a first digital signal in the plurality of digital signals, the voltage dividing weight corresponding to the first input end of the voltage dividing circuit is used to represent a contribution degree of the voltage at the first input end of the voltage dividing circuit to the output voltage of the voltage dividing circuit, the voltage at the first input end of the voltage dividing circuit being associated with the level state of the first digital signal and a reference voltage of the signal detection device.

15. The method of claim 14, wherein, The determination of the level state of each digital signal in the plurality of digital signals based on the first voltage value comprises: determining, according to the first voltage value, the reference voltage of the signal detection device and weight information, the level state of each digital signal in the plurality of digital signals, wherein the weight information comprises the voltage dividing weight corresponding to each input end in the plurality of input ends of the voltage dividing circuit.

16. The method of claim 14, wherein, The determination of the level state of each digital signal in the plurality of digital signals based on the first voltage value comprises: obtaining, according to the first voltage value and mapping information, the level state of each digital signal in the plurality of digital signals, wherein the mapping information comprises a corresponding relationship between the first voltage value and the level state of each digital signal in the plurality of digital signals. ​ 17. The method according to any one of claims 12-16, characterized by, The detection device further comprises a second DAC and a second comparator, wherein a first input end of the second comparator is connected with an output end of the second DAC, the input end of the detection device further comprises a second input end of the second comparator, an output end of the second comparator is connected with the controller, the controller is further connected with an input end of the second DAC, the second input end of the second comparator is opposite to the first input end of the first comparator; the method further comprises: controlling the second DAC to output a voltage; obtaining a second result output by the second comparator, the second result being a comparison result of the output voltage of the voltage dividing circuit and the voltage output by the second DAC; the determining of the output voltage of the voltage dividing circuit as the first voltage value according to the change of the first result comprises: determining the output voltage of the voltage dividing circuit as the first voltage value according to the changes of the first result and the second result.

18. The method of claim 17, wherein, The method further comprises: controlling the first DAC to output a second voltage value and controlling the second DAC to output a third voltage value; when it is detected that the output result of at least one of the first comparator and the second comparator changes, controlling the first DAC to change the size of the output voltage, and determining the output voltage of the voltage dividing circuit as a fourth voltage value according to the change of the output result of the first comparator, the fourth voltage value being different from the first voltage value; determining the level state of each digital signal in the plurality of digital signals according to the fourth voltage value; wherein the first voltage value is between the second voltage value and the third voltage value, the offset of the second voltage value relative to the first voltage value is a first value, the offset of the third voltage value relative to the first voltage value is a second value, the first value and the second value are both positive numbers less than a preset value, the preset value is determined based on a reference voltage of the signal detection device and a minimum voltage dividing weight in weight information, the weight information comprises a voltage dividing weight corresponding to each input end of the plurality of input ends of the voltage dividing circuit.

19. The method of claim 18, wherein: the second voltage value is greater than the first voltage value, and the first voltage value is greater than the third voltage value; or the third voltage value is greater than the first voltage value, and the first voltage value is greater than the first voltage value.

20. A signal detection method, characterized by, The method is applied to a controller in a detection device, an input end of the detection device is connected with an output end of a voltage dividing circuit, a plurality of input ends of the voltage dividing circuit are used for receiving a plurality of digital signals to be detected, one digital signal in the plurality of digital signals corresponds to one input end in the plurality of input ends, the detection device further comprises an analog-to-digital converter (ADC), the input end of the detection device is an input end of the ADC, an output end of the ADC is connected with the controller, and the method comprises: obtaining an output voltage of the voltage dividing circuit from the ADC, the output voltage of the voltage dividing circuit being a first voltage value, the output voltage of the voltage dividing circuit being a voltage at an output terminal of the voltage dividing circuit; determining a level state of each of the plurality of digital signals according to the first voltage value, the output voltage of the voltage dividing circuit being associated with voltages at a plurality of input terminals of the voltage dividing circuit, the voltage at the first input terminal of the voltage dividing circuit being associated with the level state of the first digital signal received by the first input terminal of the voltage dividing circuit and a reference voltage of the signal detection apparatus.

21. The method of claim 20, wherein, each of the plurality of input terminals of the voltage dividing circuit corresponds to a different voltage dividing weight.

22. The method according to any one of claims 19-21, characterized by, The determining of the level state of each of the plurality of digital signals according to the first voltage value comprises: determining the level state of each of the plurality of digital signals according to the first voltage value, the reference voltage of the signal detection apparatus and weight information, the weight information comprising the voltage dividing weight corresponding to each of the plurality of input terminals of the voltage dividing circuit.

23. An apparatus for detecting a signal, the apparatus comprising: The apparatus comprises an obtaining unit and a processing unit, the obtaining unit and the processing unit being configured to perform the method of any one of claims 12-19, or perform the method of any one of claims 20-22.

24. A vehicle characterized by comprising: The vehicle comprises the apparatus of any one of claims 1-11, or the apparatus of claim 23.

25. A computer readable storage medium, characterized in that, The computer readable storage medium stores program instructions for implementing the method of any one of claims 12-19, or the method of any one of claims 20-22.

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