Error condition monitoring in storage systems
By adding new read commands and a local controller to the storage controller to monitor error parameters of the NAND memory, the problem of high bit error rate in NAND memory was solved, resulting in more efficient storage performance and energy saving.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2024-09-12
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, NAND flash memory has a high bit error rate, which leads to complex ECC schemes that increase die area and cost. At the same time, periodic refresh operations consume I/O bandwidth and power budget, and there is a lack of effective solutions for monitoring and adaptive operation of the storage system.
Add new read commands to the storage controller to collect page error parameters, such as parity weights and RBER, without using the I/O bus. Detect errors via a local LDPC parity calculator and perform adaptive memory control operations based on the error parameters, such as background data reads, read reference voltage adjustments, and internal data migrations.
It reduces I/O bus data traffic between the storage controller and storage devices, saving power budget and communication bandwidth, and improving storage performance, such as memory access and background data retrieval.