Gamma voltage generation circuit and source driver circuit

Abstract

An embodiment discloses a gamma voltage generation circuit and a source drive circuit including the gamma voltage generation circuit. The gamma voltage generation circuit includes: a first voltage distribution section that outputs a plurality of voltages with different voltage levels; a plurality of amplifiers that output the voltages output from the first voltage distribution section as gamma reference voltages; a second voltage distribution section that includes a plurality of reference nodes and a plurality of distribution nodes, wherein the plurality of reference nodes output the gamma reference voltages and the plurality of distribution nodes output a plurality of gamma distribution voltages through resistors connected between the plurality of reference nodes; and a connection circuit that short-circuits the reference nodes whose gamma reference voltages change with adjacent distribution nodes.

Description

Technical Field

[0001] The embodiments involve a gamma voltage generation circuit and a source drive circuit. Background Technology

[0002] There are known flat panel display devices such as liquid crystal display (LCD), organic light-emitting diode display (OLED), electroluminescence display (ELD), field emission display (FED), plasma display panel (PDP), and electrophoresis display (EPD).

[0003] The display device may include: a display panel configured with pixels for displaying an input image; and a display panel driving circuit for writing data to the pixels of the display panel. The display panel driving circuit may include: a data driving circuit for supplying data signals of source data to the data lines of the display panel; and a gate driving circuit for supplying gate signals to the gate lines of the display panel.

[0004] The display panel driving circuit may include a gamma voltage generation circuit that supplies gamma voltage to the data driving circuit. Since the gamma voltage output from the gamma voltage generation circuit is generated by driving an amplifier and a voltage divider circuit, the connected gamma voltage will change as the data voltage changes, resulting in a longer settling time until the amplifier reaches the gamma voltage level again. Summary of the Invention

[0005] The problem the invention aims to solve

[0006] The embodiments provide a gamma voltage generation circuit and a source drive circuit that can improve settling time.

[0007] The problems of this invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] means for solving problems

[0009] A gamma voltage generation circuit according to a feature of the present invention includes: a first voltage distribution unit that outputs a plurality of voltages with different voltage levels; a plurality of amplifiers that output the voltages output from the first voltage distribution unit as gamma reference voltages; a second voltage distribution unit that includes a plurality of reference nodes and a plurality of distribution nodes, the plurality of reference nodes outputting the gamma reference voltages, the plurality of distribution nodes outputting a plurality of gamma distribution voltages through resistors connected between the plurality of reference nodes; and a connection circuit that short-circuits the reference node whose gamma reference voltage changes with the adjacent distribution node.

[0010] The connection circuit may include: a switching circuit comprising a plurality of switches forming a path that bypasses a resistor disposed between the reference node and the distribution node, thereby short-circuiting the reference node and the distribution node adjacent to the reference node; and a sensing circuit that senses voltage changes in the plurality of amplifiers to turn on the plurality of switches.

[0011] The sensing circuit may include a plurality of sensing units, which are respectively connected to the plurality of amplifiers to sense changes in the control voltage of the amplifiers. The switching circuit may include a switch array connected to the plurality of sensing units. The switch array may include a high-potential connection switch and a low-potential connection switch. The high-potential connection switch is connected to a first distribution node with a voltage higher than the reference node, and the low-potential connection switch is connected to a second distribution node with a voltage lower than the reference node.

[0012] The low-potential connection switch connected to the first sensing unit among the plurality of sensing units and the high-potential connection switch connected to the second sensing unit adjacent to the first sensing unit can be connected to the same distribution node.

[0013] The plurality of sensing units may include: a first sensor for sensing a change in a first control voltage applied to a first output transistor of the amplifier; a second sensor for sensing a change in a second control voltage applied to a second output transistor of the amplifier; and a switch control unit for outputting a signal for driving a plurality of switches based on the output signal of the first sensor or the second sensor.

[0014] If the first control voltage applied to the first output transistor drops below a predetermined voltage level, the first sensor can apply an output signal to the switch control unit.

[0015] If the second control voltage of the second output transistor rises above a predetermined voltage level, the second sensor can apply an output signal to the switch control unit.

[0016] If an output signal is applied from the first sensor or the second sensor, the switch control unit can output a conduction signal to the high-potential connection switch and the low-potential connection switch.

[0017] The sensing circuit may include: a sensing unit for sensing voltage changes in the plurality of amplifiers; and a switch control unit for selectively applying a conduction signal to the plurality of switches based on the voltage change level sensed in the sensing unit.

[0018] A source drive circuit according to a feature of the present invention includes: a data drive unit for converting source data into a data voltage based on a gamma voltage; and a gamma voltage generation unit for generating the gamma voltage; the gamma voltage generation unit includes: a first voltage distribution unit for outputting a plurality of voltages with different voltage levels; a plurality of amplifiers for outputting the voltage output from the first voltage distribution unit as a gamma reference voltage; a second voltage distribution unit including a plurality of reference nodes and a plurality of distribution nodes, the plurality of reference nodes outputting the gamma reference voltage, the plurality of distribution nodes outputting a plurality of gamma distribution voltages through resistors connected between the plurality of reference nodes; and a connection circuit for connecting the reference nodes that output gamma reference voltages with varying voltage levels to adjacent distribution nodes.

[0019] The effects of the invention

[0020] According to the embodiments, the settling time for the gamma voltage to return to the reference level can be improved, which results in high-speed driving of the display (e.g., 120Hz).

[0021] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. Attached Figure Description

[0022] Figure 1 A block diagram illustrating a display device according to an embodiment of the present invention.

[0023] Figure 2 A block diagram illustrating the circuit configuration of the data drive unit is provided.

[0024] Figure 3 A block diagram illustrating a gamma voltage generating unit according to an embodiment of the present invention.

[0025] Figure 4 The circuit diagram illustrates a gamma voltage generation unit according to an embodiment of the present invention.

[0026] Figure 5 This diagram illustrates the structure of an amplifier, sensing circuit, and switching circuit according to an embodiment of the present invention.

[0027] Figure 6 The waveforms of the amplifier's output voltage, the amplifier's first control voltage, the first sensing signal, and the second sensing signal are shown when the data voltage is low.

[0028] Figure 7 The waveforms of the amplifier's output voltage, the amplifier's first control voltage, the first sensing signal, and the second sensing signal are shown when the data voltage is high.

[0029] Figure 8 This diagram illustrates a state in which switches connected to the first to third sensing units are turned on, thereby connecting the first to seventh nodes, according to an embodiment of the present invention.

[0030] Figure 9 This diagram illustrates a state in which the switches connected to the first and second sensing units of an embodiment of the present invention are turned on, thereby connecting the first to the fifth nodes.

[0031] Figure 10 A circuit diagram illustrating the gamma voltage generation unit of another embodiment of the present invention is provided. Detailed Implementation

[0032] The advantages and features of the present invention, as well as the methods of implementing them, will become clear with reference to the accompanying drawings and detailed embodiments described below. The present invention is not limited to the embodiments disclosed below, but will be implemented in various forms that differ from each other. These embodiments are provided only to make the disclosure of the invention more complete and to fully inform those skilled in the art of the scope of the invention; the invention is defined only by the scope of the claims.

[0033] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the accompanying drawings are illustrative for the purpose of illustrating embodiments of the present invention, and therefore the present invention is not limited to the items shown in the drawings. Throughout the specification, the same reference numerals substantially refer to the same constituent elements. Furthermore, in describing the present invention, detailed descriptions of related prior art will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the spirit of the invention.

[0034] In this specification, when terms such as "provided with," "may include," "have," or "consist of" are used, other parts may be added unless "only" is used. When a constituent element is referred to in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0035] When interpreting constituent elements, even if there is no separate explicit statement, it is interpreted as including the range of error.

[0036] In describing the positional relationship and connection between two constituent elements, terms such as “on top of”, “above”, “below”, “next to”, “connected or coupled with”, and “crossing or intersecting” can be used. Unless “adjacent” or “direct” is mentioned, one or more other constituent elements may be inserted between the constituent elements.

[0037] When using phrases like "after," "next to," "before," or "before" to describe temporal sequence, the sequence may be discontinuous on the timeline unless "immediately adjacent" or "directly" is used.

[0038] To distinguish the constituent elements, terms such as "first," "second," etc., may be used, but the function or structure of these constituent elements is not limited by the ordinal number or name attached to the constituent element.

[0039] The following embodiments can be combined or integrated with each other in part or in whole, and can be technically linked and driven in various ways. Each embodiment can be implemented independently of each other, or it can be implemented together in a related manner.

[0040] In the following embodiments, the transistor is a three-electrode device including a gate, a source, and a drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, the current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. The source and drain of the transistor are not fixed. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0041] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 A block diagram illustrating a display device according to an embodiment of the present invention.

[0043] Reference Figure 1 The display device in embodiments of the present invention may include a display panel 100 and a display panel driving circuit, wherein the display panel driving circuit is used to write source data to the pixels of the display panel 100. Source data can be interpreted as pixel data.

[0044] The substrate of the display panel 100 can be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited to these. The display panel 100 can be a rectangular panel with a length in a first direction, a width in a second direction, and a thickness in a third direction, but is not limited to these. Figure 1 In this context, X, Y, and Z can represent the first direction, the second direction, and the third direction, respectively.

[0045] In the case of a liquid crystal display device, a backlight unit (BLU) may be arranged below the display panel 100. In the case of a self-emissive display device, such as an electroluminescent display device, a separate light source such as a backlight unit is not required.

[0046] The display area AA of the display panel 100 may include a pixel array for displaying an input image. The pixel array may include a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 connected to the data lines 102 and the gate lines 103.

[0047] For color display, each pixel 101 can be divided into red sub-pixels, green sub-pixels, and blue sub-pixels. Each pixel may further include a white sub-pixel. In a liquid crystal display device, a pixel may include a liquid crystal cell. In an electroluminescent display device, a pixel may include a light-emitting element such as an OLED (organic light-emitting diode). Each sub-pixel may include pixel circuitry for driving the liquid crystal cell or the light-emitting element.

[0048] Under the control of the timing controller 130, the display panel driving circuit writes source data of the input image to the pixels of the display panel 100. The display panel driving circuit may include a source driving circuit and a gate driving unit 120 that convert the source data into a data voltage. The source driving circuit may include a gamma voltage generation unit 200 and a data driving unit 110.

[0049] The display panel driving circuit may further include a touch sensor driving section for driving the touch sensor. Figure 1 The touch sensor driver unit is omitted in this paper. In mobile terminals or wearable terminals, the timing controller 130, the data driver unit 110, the touch sensor driver unit, etc., can be integrated into a single driver IC.

[0050] The data drive unit 110 receives the source data of the input image received in digital signal form from the timing controller 130, and outputs a data voltage. The data drive unit 110 uses a DA converter (Digital to Analog Converter) to convert the source data of the input image into a gamma-compensated voltage and outputs a data voltage.

[0051] The gamma voltage generation unit 200 can generate a plurality of gamma voltages with different voltage levels and provide them to the data driving unit 110. The gamma voltage can be interpreted as including a gamma reference voltage, a gamma tab voltage, and a gamma distribution voltage. For light-emitting elements, different colors may have different luminous efficiencies. Based on this color-dependent luminous efficiency characteristic, the gamma voltage can be separated into independent voltages for each color according to the color of the sub-pixel. The gamma voltage generation unit 200 can be included within the data driving unit 110 to form a source driving circuit.

[0052] The gamma voltage generated by the gamma voltage generation unit 200 is supplied to the data driving unit 110. The gamma voltage is divided in the data driving unit 110 into grayscale voltages corresponding to each grayscale level of the source data and can be supplied to the DA converter. The DA converter converts the source data, which is a digital signal, into an analog data voltage by using multiple transistors to output grayscale voltages corresponding to the grayscale values ​​of the source data. The data voltages output from the DA converter are output to the data line 102 through output buffers in each data output channel of the data driving unit 110.

[0053] The circuitry of the gate driving unit 120 can be configured in a non-display area NA other than the display area AA in the display panel 100, or at least a portion of the circuitry of the gate driving unit 120 can be configured in the display area AA. The gate driving unit 120 can be integrated into a separate gate driving IC and thus electrically connected to the gate line 103 of the display panel 100.

[0054] Under the control of the timing controller 130, the gate driving unit 120 sequentially outputs the pulses of the gate signal to the gate line. The gate driving unit 120 can use a shift register to shift the pulses of the gate signal and sequentially supply the pulses of the gate signal to the gate line 103.

[0055] The timing controller 130 receives source data of the input image and timing signals synchronized with that data from an external host system 10. The timing signals may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a master clock, etc. Since the vertical and horizontal periods can be determined by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) can be omitted. The vertical synchronization signal (Vsync) has a period of one frame. The horizontal synchronization signal (Hsync) and the data enable signal (DE) have a period of one horizontal period (1H).

[0056] The timing controller 130 controls the operation timing of the display panel drive circuits 110 and 120 based on the timing signals (Vsync, Hsync, DE) received from the host system 10.

[0057] The host system 10 can scale the image signal from the video source according to the resolution of the display panel 100 and transmit it to the timing controller 130 along with timing signals. In a mobile system, the host system 10 can be implemented by an AP (Application Processor). The host system 10 can transmit the source data of the input image to the driver IC via MIPI (Mobile Industry Processor Interface). The host system 10 can be electrically connected to the driver IC via a flexible printed circuit, such as an FPC (Flexible Printed Circuit). The driver IC can be bonded to the display panel 100 in a COG (Chip on Glass) process. The driver IC can be a COF (Chip on Film) mounted on a flexible circuit film. The COF can be bonded to data pads disposed in the non-display area of ​​the display panel 100 in a bonding process, thereby electrically connecting to the data lines on the display panel 100.

[0058] Figure 2 A block diagram illustrating the circuit configuration of the data drive unit is provided. Figure 3 A block diagram illustrating a gamma voltage generating unit according to an embodiment of the present invention.

[0059] Reference Figure 2 and Figure 3 The data driving unit 110 may include a receiving unit 111, a logic control unit 112, a shift register 113, a first latch 114, a second latch 115, a DA converter 117, and an output buffer 118.

[0060] The receiving unit 111 can receive data DATA serially received from the timing controller 130, recover the clock from the data DATA, and use the recovered clock to sample the source data of the control data and input image from the data DATA and provide it to the logic control unit 112. The timing controller 130 can convert the clock and data into differential signals and transmit them to the data driving unit 110 through the serial interface.

[0061] The logic control unit 112 rearranges the pixel data supplied from the receiving unit 111 in units of sub-pixels. The logic control unit 112 can supply start pulses and clocks to the shift register 113 using the recovered clock and control data, and control the output timing of the first latch unit 114, the second latch unit 115, and the output buffer 118.

[0062] Shift register 113, first latch 114, and second latch 115 convert serial data into parallel data. Shift register 113 shifts the clock and outputs it to the channel of first latch 114 upon receiving a start pulse. First latch 114, in response to clock signals sequentially input from shift register 113, samples the source data input from receiving unit 111 via logic control unit 112. When source data is latched on all channels, the latched data can be simultaneously output to the channel of second latch 115. Second latch 115 latches the data simultaneously received from first latch 114 and, in response to the output enable signal from logic control unit 112, simultaneously outputs the latched data to DA converter 117.

[0063] The gamma voltage generation unit 200 can supply a plurality of gamma voltages to the DA conversion unit 117. A grayscale voltage generation unit can be disposed between the gamma voltage generation unit 200 and the DA conversion unit 117. The grayscale voltage generation unit divides the plurality of gamma voltages to generate grayscale voltages corresponding to each grayscale of the source data and supplies them to the DA conversion unit 117.

[0064] The DA converter 117 can select a grayscale voltage corresponding to the grayscale value of the source data input from the second latch 115 and output it as a data voltage Vdata. The data voltage Vdata can be output through the output buffer 118 and applied to the data line 102 of the display panel 100.

[0065] The lower the grayscale of the source data, the lower the data voltage Vdata output by the DA converter 117 is likely to be. Conversely, the higher the grayscale of the source data, the higher the data voltage Vdata is likely to be. Therefore, the data voltage can change instantaneously according to the grayscale value of the pixel, and at the output node of the gamma voltage generation unit 200 connected to the DA converter 117, the gamma voltage can also change with the data voltage. The amplifier of the gamma voltage generation unit 200 can receive the output voltage and restore it to the original gamma voltage level, but this takes a considerable amount of time, resulting in an increased settling time. Therefore, high-speed driving of the display may be difficult.

[0066] Reference Figure 3The gamma voltage generation unit 200 may include: an amplification unit 220, including a plurality of amplifiers that output gamma voltages; a second voltage distribution unit 250, which divides the gamma reference voltage into a plurality of gamma distribution voltages; a sensing circuit 230, which senses the control voltage of the amplifiers; and a switching circuit 240, which selectively turns on the switch connected to the second voltage distribution unit 250 according to the control signal of the sensing circuit 230.

[0067] According to an embodiment, the sensing circuit 230 senses changes in the gamma reference voltage output from a plurality of amplifiers to detect amplifiers whose gamma reference voltage (output voltage) has changed, and can adjust the switching circuit 240 so that the changed gamma reference voltage can be quickly restored to its original voltage level.

[0068] Figure 4 The circuit diagram illustrates a gamma voltage generation unit according to an embodiment of the present invention.

[0069] Reference Figure 4 The gamma voltage generation unit 200 includes: a first voltage distribution unit 210 that outputs a plurality of voltages with different voltage levels; a plurality of amplifiers AMP1 to ANPn connected to the first voltage distribution unit 210; a second voltage distribution unit 250 connected to the plurality of amplifiers AMP1 to ANPn; and connection circuits 230 and 240 that connect a reference node whose gamma reference voltage changes to an adjacent distribution node.

[0070] A high-potential reference voltage GVDD, a low-potential reference voltage GVSS, and an amplifier drive voltage are applied to the gamma voltage generation unit 200. When the brightness is adjusted using the host system, the voltage levels of the high-potential reference voltage GVDD and the low-potential reference voltage GVSS can be changed. For example, when the brightness dims according to the user interface or the ambient illuminance, the low-potential reference voltage may increase.

[0071] The gamma voltage generation unit 200 can output 2n+1 gamma voltages (n being a natural number) with different voltage levels. A gamma voltage can be defined as including the gamma reference voltage output from a plurality of amplifiers AMP1 to ANPn and the gamma distribution voltage output from the distribution node DN located between resistors in the second voltage distribution unit 250. In the gamma voltage generation unit 200, the gamma voltages output through adjacent output nodes have a predetermined voltage difference.

[0072] The first voltage distribution unit 210 includes a plurality of resistors connected in series. The first voltage distribution unit 210 divides the high-potential reference voltage GVDD between the high-potential reference voltage GVDD and the low-potential reference voltage GVSS, thereby generating n input voltages G1 to Gn with different voltage levels through the distribution node.

[0073] The multiple amplifiers AMP1 to ANPn can be interpreted as buffers or voltage followers composed of operational amplifiers. Each amplifier includes a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal.

[0074] Multiple amplifiers AMP1 to AMPn can output the input voltages G1 to Gn, which are input to the non-inverting input terminal (+), as a gamma reference voltage. The inverting input terminal (-) and output terminal of the amplifier can be connected to the output node of the second voltage distribution unit 250 that outputs the gamma reference voltage.

[0075] The second voltage distribution unit 250 includes a plurality of resistors connected in series. The second voltage distribution unit 250 can divide the gamma reference voltage between the first gamma voltage V1 and the (2n+1)th gamma voltage V2n+1.

[0076] The dynamic range of the data voltage Vdata output in each channel of the data driving unit can be determined as the voltage range between the first gamma voltage V1 and the (2n+1)th gamma voltage V2n+1. However, this embodiment is not limited to this. For example, the first gamma voltage V1 to the (2n+1)th gamma voltage V2n+1 can be divided to generate grayscale voltages corresponding to each grayscale level of the source data and supplied to the DA conversion unit 117.

[0077] The output nodes RN and DN of the second voltage distribution unit 250 may include: a plurality of reference nodes RN that output a plurality of gamma reference voltages; and a plurality of distribution nodes DN that output a plurality of gamma distribution voltages through resistors connected between the plurality of reference nodes. The reference nodes RN and distribution nodes DN may be defined for the purpose of distinguishing their positions, and both may be defined as output nodes or output terminals.

[0078] The second voltage distribution unit 250 may include a first output node to the 2n+1th output nodes OTN1 to OTN2n+1 for outputting gamma voltage. The second output node OTN2, the fourth output node OTN4, the sixth output node OTN6 to the 2nth output node OTN2n may be the reference node RN for outputting the gamma reference voltage. The first output node OTN1, the third output node OTN3, the fifth output node OTN5, the 2n-1th output node OTN2n-1, and the 2n+1th output node OTN2n+1 may be the distribution node DN for outputting the gamma distribution voltage.

[0079] Connection circuits 230 and 240 can connect the output nodes of the second voltage distribution unit 250, whose gamma voltage changes, to each other during the connection process with the DA converter 117, as the source data changes. The DA converter 117 converts the source data, which is a digital signal, into an analog data voltage by using a plurality of transistors to select the gamma voltage corresponding to the grayscale value of the source data. Therefore, the DA converter 117 can connect the corresponding gamma voltage according to the grayscale value of the source data. However, when a high-level gamma voltage is connected when the output data voltage is low, the connected gamma voltage may drop instantaneously.

[0080] Conversely, if a relatively low gamma voltage is connected when the output data voltage is high, the connected gamma voltage may spike momentarily. The amplifier can receive the output gamma voltage and perform feedback control, but there is a problem that adjusting the gamma voltage to the same level as the input voltage takes a considerable amount of time.

[0081] The connection circuits 230 and 240 according to the embodiment have the following advantages: during the connection with the DA conversion unit 117, the output nodes of the second voltage distribution unit 250, whose gamma voltage changes, are connected to each other to short-circuit them, thereby reducing the setup time.

[0082] The connection circuits 230 and 240 may include: a sensing circuit 230 for sensing changes in the output voltage of the amplifier; and a switching circuit 240 including a plurality of switches SW1 to SWn that selectively short-circuit the output nodes.

[0083] The sensing circuit 230 may include a plurality of sensing units SP1 to SPn, which are respectively connected to a plurality of amplifiers AMP1 to AMPn. The first sensing unit SP1 may be connected to the first amplifier AMP1 to sense changes in the output voltage, the second sensing unit SP2 may be connected to the second amplifier AMP2 to sense changes in the output voltage, and the nth sensing unit SPn may be connected to the nth amplifier AMPn to sense changes in the output voltage.

[0084] The switching circuit 240 may include a switch array connected to each sensing unit. The switch array may include: a high-potential connection switch connected to a first distribution node with a voltage higher than the reference node; and a low-potential connection switch connected to a second distribution node with a voltage lower than the reference node. For example, one sensing unit may be connected to two switches. However, this embodiment is not limited to this. For example, the switching circuit 240 may include three or more switches connected to one sensing unit.

[0085] The first switch SW1 can connect the second output node OTN2 of the output second gamma voltage V2 to the first output node OTN1 of the output first gamma voltage V1. The first switch SW1 can be a high-potential connection switch.

[0086] The second switch SW2 can connect the second output node OTN2 of the output second gamma voltage V2 to the third output node OTN3 of the output third gamma voltage V3. The second switch SW2 can be a low-potential connection switch.

[0087] The second output node OTN2 can be connected to the first output node OTN1 via the first switch SW1, and can be connected to the third output node OTN3 via the second switch SW2.

[0088] The second output node OTN2 can be a reference node that outputs a gamma reference voltage, and the first output node OTN1 can be a first voltage divider node with a voltage higher than the reference node or a high-potential voltage divider node. The third output node OTN3 can be a second voltage divider node with a voltage lower than the reference node or a low-potential voltage divider node. Therefore, a pair of switches connected to one sensing unit can connect the reference node to the adjacent first and second voltage divider nodes.

[0089] The third switch SW3 can connect the fourth output node OTN4 of the output fourth gamma voltage V4 to the third output node OTN3 of the output third gamma voltage V3.

[0090] The fourth switch SW4 can connect the fourth output node OTN4 to the fifth output node OTN5 that outputs the fifth gamma voltage V5.

[0091] The third output node OTN3 can be connected to the second output node OTN2 using the second switch SW2, and can be connected to the fourth output node OTN4 using the third switch SW3.

[0092] The fifth switch SW5 can connect the sixth output node OTN6 of the sixth gamma voltage V6 output from the third amplifier AMP3 to the fifth output node OTN5 of the fifth gamma voltage V5.

[0093] The sixth switch SW6 can connect the sixth output node OTN6 to the seventh output node OTN7 that outputs the seventh gamma voltage V7.

[0094] The fifth output node OTN5 can be connected to the fourth output node OTN4 using the fourth switch SW4, and can be connected to the sixth output node OTN6 using the fifth switch SW5.

[0095] Figure 5 This diagram illustrates the structure of an amplifier, sensing circuit, and switching circuit according to an embodiment of the present invention.

[0096] Reference Figure 5 An amplifier may include multiple transistors and capacitors. Figure 5 The connection circuit connected to the second amplifier is shown.

[0097] The amplifier may include a voltage follower structure, which includes an input stage 221, a current adding stage 222, and an output stage 223. The operational amplifier can differentially amplify the difference between the input voltage VIN and the output voltage VOUT to generate an output voltage VOUT that quickly tracks the input voltage VIN.

[0098] The input stage 221 can monitor the difference between the input voltage VIN input to the non-inverting terminal and the output voltage VOUT fed back to the inverting terminal to adjust the control currents I1 to I4 provided by the current adding stage 222.

[0099] The current adder stage 222 can work with the input stage 221 to amplify the current based on the difference between the input voltage VIN and the output voltage VOUT, thereby generating control currents I1 to I4 for the input stage 221, and can generate output currents and control voltages HIP and HIN adjusted according to the control currents I1 to I4 to provide to the output stage 223.

[0100] Among the control currents I1 to I4 generated from the current adder stage 222, the currents I1 and I2 flowing from the current adder stage 222 to the input stage 221 are sink currents, and the control currents I3 and I4 flowing from the input stage 221 to the current adder stage 222 are source currents.

[0101] The output stage 223 can perform pull-up and pull-down actions based on the control voltages HIP and HIN provided by the current adder stage 222, thereby outputting an output voltage VOUT that tracks the input voltage VIN through the output terminal.

[0102] The input stage 221 may include: a first input section composed of PMOS transistors PM1 and PM2, a second input section composed of NMOS transistors NM1 and NM2, a first bias circuit composed of PMOS transistor PM3, and a second bias circuit composed of NMOS transistor NM3.

[0103] The PMOS transistors PM1 and PM2 in the first input section are controlled by the input voltage VIN and the output voltage VOUT, respectively, and can adjust the source currents I3 and I4 provided from the current adder stage 222 according to the input voltage VIN and the output voltage VOUT.

[0104] The NMOS transistors NM1 and NM2 in the second input section are controlled by the input voltage VIN and the output voltage VOUT, respectively, and can adjust the absorption currents I1 and I2 provided from the current adder stage 222 according to the input voltage VIN and the output voltage VOUT.

[0105] The PMOS transistor PM3 in the first bias circuit can be connected between the supply line of the first power supply (high potential power supply) AVDDH and the first input section. Under the control of the bias voltage VB1, it provides bias current to the PMOS transistors PM1 and PM2 in the first input section.

[0106] The NMOS transistor NM3 of the second bias circuit can be connected between the second input section and the second power supply (low potential power supply) AVSS supply line, and is controlled by the second bias voltage VB2, thereby providing bias current to the NMOS transistors NM1 and NM2 of the second input section.

[0107] The current adder stage 222 may include: a first current mirror composed of PMOS transistors PM4 and PM5; a first cascode circuit composed of PMOS transistors PM6 and PM7; a second current mirror composed of NMOS transistors NM4 and NM5; a second cascode circuit composed of NMOS transistors NM6 and NM7; a third bias circuit composed of PMOS and NMOS transistors PM8 and NM8; and a fourth bias circuit composed of PMOS and NMOS transistors PM9 and NM9. The third and fourth bias circuits can be defined as floating bias circuits.

[0108] The first current-mirror PMOS transistors PM4 and PM5 are connected to the second input NMOS transistors NM1 and NM2 of the input stage 221, and are connected in a current-mirror configuration between the supply line of the first power supply AVDDH and the first cascode circuit. The gate electrodes of the first current-mirror PMOS transistors PM4 and PM5 are connected to the output node N3 of the first cascode circuit. The first current-mirror PMOS transistors PM4 and PM5 can provide sink currents I1 and I2 to the first input NMOS transistors NM1 and NM2 through the output nodes N2 and N1, provide output current through the first cascode circuit, and provide output current to the capacitor C1 of the output stage 223 through the output node.

[0109] The PMOS transistors PM6 and PM7 of the first common source common gate circuit can be connected between the first current mirror and the third and fourth bias circuits, and are controlled by the third bias voltage VB3, thereby providing the first control voltage HIP to the output stage 223 through the output node N7.

[0110] The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5, which are current mirrors, are connected to the first input PMOS transistors PM1 and PM2 of the input stage 221, and are connected in a current mirror configuration between the supply line of the second cascode circuit and the second power supply VSS. The gate electrodes of the second current mirror NMOS transistors NM4 and NM5 are connected to the output node N5 of the second cascode circuit. The second current mirror NMOS transistors NM4 and NM5 provide source currents I3 and I4 to the PMOS transistors PM1 and PM2 of the second input stage through the output node, provide output current through the second cascode circuit, and can also provide output current to the capacitor C2 of the output stage 223 through the output node N6.

[0111] The NMOS transistors NM6 and NM7 of the second common-source common-gate circuit can be connected between the third and fourth bias circuits and the second current mirror, and are controlled by the fourth bias voltage VB3, thereby providing the second control voltage HIN to the output stage 223 through the output node N8.

[0112] The PMOS transistor PM8 and NMOS transistor NM8 of the third bias circuit can be connected between the PMOS transistor PM6 of the first cascode circuit and the NMOS transistor NM6 of the second cascode circuit, and are controlled by the fifth bias voltage VB5 and the sixth bias voltage VB6, respectively, thereby providing bias current flowing from the output node N3 of the first cascode circuit to the output node N5 of the second cascode circuit.

[0113] The PMOS transistor PM9 and NMOS transistor NM9 of the fourth bias circuit are connected between the PMOS transistor PM7 of the first cascode circuit and the NMOS transistor NM7 of the second cascode circuit, and are controlled by the seventh bias voltage VB7 and the eighth bias voltage VB8, respectively, thereby providing bias current from the output node N7 of the first cascode circuit to the output node N8 of the second cascode circuit.

[0114] The output stage 223 may include a pull-up PMOS transistor PM10, a pull-down NMOS transistor NM10, and capacitors C1 and C2. The pull-up PMOS transistor PM10 may be defined as the first output transistor, and the pull-down NMOS transistor NM10 may be defined as the second output transistor.

[0115] The pull-up PMOS transistor PM10 is controlled by a first control voltage HIP provided from the first output node N7 of the current adder stage 222 and is connected between the first power supply line AVDDH and the output terminal. The pull-up PMOS transistor PM10 performs a pull-up action according to the control of the first control voltage HIP, thereby increasing the output voltage VOUT.

[0116] The pull-down NMOS transistor NM10 is controlled by a second control voltage HIN provided from the second output node N8 of the current adder stage 222 and is connected between the output terminal and the second power supply line VSS. The pull-down NMOS transistor NM10 performs a pull-down action according to the control of the second control voltage HIN, thereby reducing the output voltage VOUT.

[0117] The capacitor section may include: a first capacitor C1 connected between the third output node N4 of the current adder stage 222 and the output terminal; and a second capacitor C2 connected between the fourth output node N6 of the current adder stage 222 and the output terminal. The capacitor section can stabilize the output voltage VOUT as it rises or falls, preventing oscillation.

[0118] The current adder stage 222 can provide output current to the first capacitor C1 through the third output node N4 connected in mirror to the first current, and can provide output current to the second capacitor C2 through the fourth output node N6 connected in mirror to the second current.

[0119] The sensing circuit 230 may include: a first sensor 231, which applies a first output signal SOR when the first control voltage HIP applied to the pull-up PMOS transistor PM10 meets a predetermined level; a second sensor 232, which applies a second output signal SOF when the second control voltage HIN applied to the pull-down NMOS transistor NM10 meets a predetermined level; and a switch control unit 233, which outputs a control signal that turns on the switch connected to the output terminal when the first output signal SOR or the second output signal SOF is applied.

[0120] The first sensor 231 can apply an output signal when the first control voltage HIP is at a predetermined level. Therefore, when the first control voltage HIP drops to the predetermined level, the first output signal SOR is transmitted; when the first control voltage HIP is higher than the predetermined level, the first output signal SOR may not be transmitted. The first output signal SOR can be a high signal, but embodiments of the present invention are not limited thereto. The first sensor 231 can be a Schmitt trigger, but is not limited thereto.

[0121] The second sensor 232 can apply an output signal only when the second control voltage HIN is above a predetermined level. Therefore, when the second control voltage HIN rises to the predetermined level, the second output signal SOF is transmitted; when it falls below the predetermined level again, the second output signal SOF may not be transmitted. The second output signal SOF can be a high signal, but embodiments of the present invention are not limited thereto. The second sensor 232 can be a Schmitt trigger, but is not limited thereto.

[0122] When the first output signal SOR or the second output signal SOF is applied, the switch control unit 233 can apply a turn-on signal to both of the pairs of switches connected to the reference node of the gamma voltage of the output amplifier. The switch control unit 233 can be an OR gate, but various other logic circuits can also be used.

[0123] The third switch SW3 connects the fourth output node OTN4, which is connected to the amplifier's output terminal, to the adjacent third output node OTN3. The fourth switch SW4 connects the fourth output node OTN4 to the adjacent fifth output node OTN5. Therefore, if both the third switch SW3 and the fourth switch SW4 are turned on simultaneously, the third output node OTN3, the fourth output node OTN4, and the fifth output node OTN5 can be connected to each other.

[0124] Figure 6 The waveforms of the amplifier's output voltage, the amplifier's first control voltage, the first sensing signal, and the second sensing signal are shown when the data voltage is low. Figure 7 The waveforms of the amplifier's output voltage, the amplifier's first control voltage, the first sensing signal, and the second sensing signal are shown when the data voltage is high.

[0125] Reference Figure 5 and Figure 6 When connected to the relatively high-voltage fourth output node OTN4 under low data voltage conditions, the gamma voltage of the fourth output node OTN4 decreases, causing the amplifier's input voltage to be greater than its output voltage. Therefore, the second amplifier AMP2 can reduce the first control voltage HIP of the pull-up PMOS transistor PM10 to increase the source current (t1). As the source current increases, the output voltage may become higher.

[0126] When the first control voltage HIP decreases below a predetermined level, the first sensor 231 can generate a first output signal SOR(t2). For example, the predetermined level can be set to generate the first output signal SOR when it drops below 90%, 70%, or 50% of the reference first control voltage HIP, but it can also be adjusted to various other levels.

[0127] When the first output signal SOR is applied, the switch control unit 233 can apply a conduction signal to the third switch SW3 and the fourth switch SW4. Therefore, the third output node OTN3, the fourth output node OTN4, and the fifth output node OTN5 can be connected to each other. The second amplifier AMP2 can be connected to these three output nodes to perform feedback control. Therefore, the voltages of all three output nodes can rise. At this time, if any one of these output nodes reaches the input voltage first, the feedback control for that node can be stopped.

[0128] When the first control voltage HIP is higher than a predetermined level, the first sensor 231 can output a low signal again (t3). In this case, the second control voltage HIN remains unchanged, and the second voltage can continue to output a low signal. Therefore, since both the first sensor 231 and the second sensor 232 output low signals, the switch control unit 233 can output a switch-off signal. Therefore, the second amplifier AMP2 can disconnect from the third output node OTN3 and the fifth output node OTN5, and only receive the output voltage of the fourth output node OTN4, causing the voltage to rise until it reaches the input voltage.

[0129] Reference Figure 5 and Figure 7 When connected to the relatively low-voltage fourth output node OTN4 while the data voltage is high, the output voltage of the fourth output node OTN4 increases and can become greater than the input voltage. Therefore, the amplifier can increase the second control voltage HIN to reduce the output voltage (t5).

[0130] When the second control voltage HIN rises above a predetermined level, the second sensor 232 can generate a second output signal SOF(t6). For example, the predetermined level can be adjusted to generate the second output signal SOF when it rises to 10%, 30%, or 50% or more of the reference second control voltage HIN, but it can also be set to various other levels.

[0131] When the second output signal SOF is applied, the switch control unit 233 can apply a turn-on signal to the third switch SW3 and the fourth switch SW4. Therefore, the third output node OTN3, the fourth output node OTN4, and the fifth output node OTN5 can be connected to each other. Therefore, the second amplifier AMP2 can be connected to these three output nodes to perform feedback control. Therefore, the voltages of all three output nodes may drop. At this time, if any one of these nodes reaches its input voltage first, the feedback control for that node can be stopped.

[0132] When the second control voltage HIN falls below a predetermined level, the second sensor 232 can output a low signal again (t7). In this case, the first control voltage HIP remains unchanged, and the first sensor 231 can continue to output a low signal. Therefore, since both the first sensor 231 and the second sensor 232 output low signals, the switch control unit 233 can output a switch-off signal. Consequently, the second amplifier AMP2 again only receives the output voltage of the fourth output node OTN4, causing the voltage to drop until it matches the input voltage.

[0133] According to an embodiment, when changes in data voltage cause changes in gamma voltage, adjacent output nodes can be connected to cause multiple gamma voltages to rise or fall simultaneously. Therefore, when gamma voltage changes, the gamma voltage can be quickly adjusted to the input voltage level.

[0134] Figure 8 The diagram illustrates a state in which switches connected to the first to third sensing units are turned on, thereby connecting the first to seventh output nodes, according to an embodiment of the present invention.

[0135] Reference Figure 6 and Figure 8 When the grayscale change increases, causing the data voltage to change significantly from low voltage to high voltage or from high voltage to low voltage, not only will the gamma voltage connected to the DA converter 117 change, but the adjacent gamma voltages will also change.

[0136] For example, when the data voltage of the DA converter is low and connected to the relatively high-voltage fourth output node OTN4, the first control voltage HIP of the pull-up PMOS transistor of the second amplifier AMP2 will become lower than a preset level, thereby turning on the third switch SW3 and the fourth switch SW4. At this time, the gamma voltages of the second output node OTN2 and the sixth output node OTN6, which are connected to the fourth output node OTN4 through resistors, will also change. At this time, the voltage changes of the second output node OTN2 and the sixth output node OTN6 may be less than the voltage changes of the fourth output node OTN4 connected to the DA converter 117.

[0137] Therefore, the first control voltage HIP of the pull-up PMOS transistor of the first amplifier AMP1 will become lower than the preset level, thereby turning on the first switch SW1 and the second switch SW2. Additionally, the first control voltage HIP of the pull-up PMOS transistor of the third amplifier AMP3 will become lower than the preset level, thereby turning on the fifth switch SW5 and the sixth switch SW6. As a result, the first output node to the seventh output nodes OTN1 to OTN7 can be connected. Therefore, due to the short circuit between the first resistor to the sixth resistor R1 to R6, the overall resistance within the second voltage distribution section 250 decreases, increasing the current applied to the second voltage distribution section 250, and thus the voltage of the fourth output node OTN4 may rise.

[0138] The first amplifier AMP1 can be connected to the first output node OTN1, the second output node OTN2, and the third output node OTN3 to perform feedback control. Therefore, the voltages of the first output node OTN1, the second output node OTN2, and the third output node OTN3 may rise simultaneously.

[0139] The second amplifier AMP2 can be connected to the third output node OTN3, the fourth output node OTN4, and the fifth output node OTN5 to perform feedback control. Therefore, the voltages of the third output node OTN3, the fourth output node OTN4, and the fifth output node OTN5 may rise simultaneously.

[0140] The third amplifier AMP3 can be connected to the fifth output node OTN5, the sixth output node OTN6, and the seventh output node OTN7 to perform feedback control. Therefore, the voltages of the fifth output node OTN5, the sixth output node OTN6, and the seventh output node OTN7 may rise simultaneously.

[0141] According to the embodiment, the output voltage of the third output node OTN3 can be increased due to the first amplifier AMP1 and the second amplifier AMP2, and the output voltage of the fifth output node OTN5 can be increased due to the second amplifier AMP2 and the third amplifier AMP3.

[0142] Furthermore, since the first output node to the seventh output nodes OTN1~OTN7 are short-circuited, the output voltage controlled by the feedback of the first amplifier AMP1 can also be transmitted to the fourth output node OTN4. Because the input voltage G1 of the first amplifier AMP1 is higher than the input voltage G2 of the second amplifier AMP2, the feedback current can be maximized. Therefore, the high output voltage of the first amplifier AMP1 is applied to the fourth output node OTN4, allowing the voltage to rise rapidly. Additionally, the third amplifier AMP3 can also apply an output voltage to the fourth output node OTN4.

[0143] According to the embodiment, since adjacent amplifiers work together to restore the voltage of the fourth output node OTN4, the voltage can be charged more quickly, thereby reducing the settling time. Therefore, the voltage profile can be adjusted from SC1 to SC2, and the settling time can be reduced from t4 to t4' (refer to...). Figure 6 The measurement results confirmed that the settling time decreased from 0.511 μs to 0.459 μs.

[0144] When the first control voltage HIP of the pull-up PMOS transistor in the first amplifier AMP1 becomes higher than a set level, the switch is turned off, allowing it to again only receive the gamma voltage from the second output node OTN2. Similarly, when the first control voltage HIP of the pull-up PMOS transistor in the second amplifier AMP2 becomes higher than a set level, the switch is turned off, allowing it to again only receive the gamma voltage from the fourth output node OTN4. Likewise, when the first control voltage HIP of the pull-up PMOS transistor in the third amplifier AMP3 becomes higher than a set level, the switch is turned off, allowing it to again only receive the gamma voltage from the sixth output node OTN6. Since the voltage changes at the second and sixth output nodes OTN2 and OTN6 are smaller than the voltage change at the fourth output node OTN4 connected to the DA converter 117, the switches connected to the first and third amplifiers AMP1 and AMP3 can turn off faster than the switch connected to the second amplifier AMP2. However, this is not a limitation; the switches connected to the first and third amplifiers AMP1 and AMP3 can turn off more slowly than the switch connected to the second amplifier AMP2. That is, the switches connected to multiple amplifiers can be turned off at different times.

[0145] According to the embodiment, as the amplitude of the data voltage change increases, in addition to the amplifier that performs feedback control on the gamma voltage connected to the DA converter 117, adjacent amplifiers also change their output voltage together, thereby enabling joint adjustment of the output voltage. When the sensor's set level is lowered, more amplifiers can participate in adjusting the gamma voltage that changes when the data voltage is connected.

[0146] The example above illustrates the connection of the DA converter 117 to the gamma voltage when the data voltage is relatively low. However, conversely, the DA converter 117 can also be connected to the gamma voltage when the data voltage is relatively high. When the data voltage is relatively high, if connected to the fourth output node OTN4 where the voltage is relatively low, the second control voltage HIN of the pull-down NMOS transistor of the second amplifier AMP2 will become higher than a preset level, thereby turning on the third switch SW3 and the fourth switch SW4.

[0147] At this time, the gamma voltages of the second output node OTN2 and the sixth output node OTN6, which are connected to the fourth output node OTN4 via resistors, may also rise. Therefore, the second control voltage HIN of the pull-down NMOS transistors of the first amplifier AMP1 and the third amplifier AMP3 becomes higher than a preset level, thereby turning on the first switch SW1, the second switch SW2, the fifth switch SW5, and the sixth switch SW6. Thus, the first output node to the seventh output nodes OTN1 to OTN7 can be connected.

[0148] As a result, due to the short circuit between the first resistor and the sixth resistor R1 to R6, the overall resistance within the second voltage distribution section 250 is reduced, thereby facilitating the discharge of the voltage at the fourth output node OTN4.

[0149] The first amplifier AMP1 can be connected to the first output node OTN1, the second output node OTN2, and the third output node OTN3 to perform feedback control. Therefore, the voltages of the first output node OTN1, the second output node OTN2, and the third output node OTN3 may all drop.

[0150] The second amplifier AMP2 can be connected to the third output node OTN3, the fourth output node OTN4, and the fifth output node OTN5 to perform feedback control. Therefore, the voltages of the third output node OTN3, the fourth output node OTN4, and the fifth output node OTN5 may all drop.

[0151] The third amplifier AMP3 can be connected to the fifth output node OTN5, the sixth output node OTN6, and the seventh output node OTN7 to perform feedback control. Therefore, the voltages of the fifth output node OTN5, the sixth output node OTN6, and the seventh output node OTN7 may all drop.

[0152] According to the embodiment, since the first output node to the seventh output nodes OTN1-OTN7 are short-circuited, the output voltage controlled by the feedback of the third amplifier AMP3 can also be transmitted to the fourth output node OTN4. Because the input voltage G3 of the third amplifier AMP3 is lower than the input voltage G2 of the second amplifier AMP2, the current draw may be maximum. Therefore, if the third amplifier AMP3 is connected to the fourth output node OTN4, the voltage can drop rapidly. Additionally, the first amplifier AMP1 is also connected to the fourth output node OTN4, causing a voltage drop.

[0153] According to the embodiment, since adjacent amplifiers work together to reduce the voltage at the fourth output node OTN4, the voltage can be reduced more quickly, thereby reducing the settling time. Therefore, the voltage profile can be adjusted from SC3 to SC4, and the settling time can be reduced from t8 to t8' (refer to...). Figure 7 The measurement results confirmed that the settling time decreased from 0.506 μs to 0.451 μs.

[0154] Figure 9 This diagram illustrates a state in which the switches connected to the first sensing unit SP1 and the second sensing unit SP2 are turned on, thereby connecting the first node to the fifth node, according to an embodiment of the present invention.

[0155] Reference Figure 9 The gamma voltage connected to the DA converter 117 may not be the gamma reference voltage output from the reference node, but rather the gamma distribution voltage output from the voltage divider node.

[0156] For example, if the third output node OTN3 is connected to the DA converter 117, and the data voltage does not differ significantly from the voltage of the third output node OTN3, the gamma voltage change at the second output node OTN2 and the fourth output node OTN4 may be small. In this case, the set level of the sensing unit cannot be met, and the first switch SW1 to the fourth switch SW4 can remain in the off state.

[0157] However, if the data voltage differs significantly from the voltage of the third output node OTN3, the gamma voltage changes at the second output node OTN2 and the fourth output node OTN4 may be large. In this case, the first sensing unit SP1 and the second sensing unit SP2 can sense changes in the first control voltage HIP or the second control voltage HIN, thereby turning on the first switch SW1 to the fourth switch SW4. At this time, the gamma voltage of the relatively far-away sixth output node OTN6 will not change significantly, so the fifth switch SW5 and the sixth switch SW6 can remain off.

[0158] When connected to the third output node OTN3 under low data voltage conditions, the first amplifier AMP1 can receive the gamma voltage from the third output node OTN3 and increase the source current, thereby increasing the output voltage. Similarly, the second amplifier AMP2 can receive the gamma voltage from the fifth output node OTN5 and increase the source current, thus increasing the output voltage. Therefore, the gamma voltage of the third output node OTN3, located between the second output node OTN2 of the first amplifier AMP1 and the fourth output node OTN4 of the second amplifier AMP2, can be quickly restored to the input voltage, thereby reducing the settling time.

[0159] Figure 10 A circuit diagram of a gamma voltage generating unit according to another embodiment of the present invention is shown.

[0160] Reference Figure 10 According to an embodiment, the gamma voltage generation unit 200 includes: a first voltage distribution unit 210 that outputs a plurality of voltages with different voltage levels; a plurality of amplifiers AMP1 to ANPn connected to the first voltage distribution unit 210; a second voltage distribution unit 250 connected to the plurality of amplifiers AMP1 to ANPn; and connection circuits 230 and 240 for connecting nodes in the output nodes of the second voltage distribution unit 250 where the output voltage changes.

[0161] The connection circuits 230 and 240 may include: a sensing circuit 230 for sensing the control voltage of a plurality of amplifiers AMP1 to ANPn; and a switching circuit 240 for controlling a plurality of switches that connect adjacent nodes of the second voltage distribution section 250.

[0162] The sensing circuit 230 can sense the first control voltage HIP and the second control voltage HIN of a plurality of amplifiers AMP1 to AMPn. For example, when the DA converter 117 is connected to the fourth output node OTN4, which outputs a relatively high gamma voltage, in a state of low data voltage, the sensing circuit 230 can sense at which amplifier the gamma voltage has changed. For example, when the first control voltage HIP of the first amplifier to the third amplifier AMP1 to AMP3 changes, the switching circuit 240 can turn on the first switch to the sixth switch SW1 to SW6.

[0163] With this configuration, instead of the sensing section being connected separately to each amplifier to control the switch, a single sensing circuit 230 can sense the voltage changes of multiple amplifiers AMP1 to ANPn. Furthermore, since each switch can be switched individually, it has the advantage of selectively turning the switches on / off to minimize the settling time.

[0164] As the contents of the specification describing the problem to be solved, the means to solve the problem, and the effect are not used to limit the essential features of the claims, the scope of the claims is not limited by the matters described in the specification.

[0165] Although embodiments of the present invention have been described in more detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in this invention are not intended to limit the technical spirit of the present invention, but are intended to illustrate that the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it must be understood that the embodiments described above are exemplary and not restrictive in all respects.

Claims

1. A gamma voltage generating circuit, wherein, include: The first voltage distribution section outputs a plurality of voltages with different voltage levels; Multiple amplifiers output the voltage from the first voltage distribution unit as a gamma reference voltage. The second voltage distribution unit includes a plurality of reference nodes and a plurality of distribution nodes. The plurality of reference nodes output the gamma reference voltage, and the plurality of distribution nodes output a plurality of gamma distribution voltages through resistors connected between the plurality of reference nodes. as well as Connect the circuit by short-circuiting the reference node where the gamma reference voltage changes with the adjacent distribution node.

2. The gamma voltage generating circuit according to claim 1, wherein, The connection circuit includes: A switching circuit includes a plurality of switches forming a path that bypasses a resistor disposed between the reference node and the distribution node, thereby short-circuiting the reference node and the distribution node adjacent to the reference node; and A sensing circuit senses the voltage changes of the plurality of amplifiers and turns on the plurality of switches accordingly.

3. The gamma voltage generating circuit according to claim 2, wherein, The sensing circuit includes a plurality of sensing units, each of which is connected to a plurality of amplifiers to sense changes in the control voltage of the amplifiers. The switching circuit includes a switch array that is connected to the plurality of sensing portions respectively. The switch array includes a high-potential connection switch and a low-potential connection switch. The high-potential connection switch is connected to a first distribution node with a voltage higher than that of the reference node, and the low-potential connection switch is connected to a second distribution node with a voltage lower than that of the reference node.

4. The gamma voltage generating circuit according to claim 3, wherein, The low-potential connection switch connected to the first sensing unit among the plurality of sensing units and the high-potential connection switch connected to the second sensing unit adjacent to the first sensing unit are connected to the same distribution node.

5. The gamma voltage generating circuit according to claim 3, wherein, The plurality of sensing units include: A first sensor is used to sense changes in a first control voltage applied to the first output transistor of the amplifier. A second sensor is used to sense changes in a second control voltage applied to the second output transistor of the amplifier; and The switch control unit outputs a signal for driving a plurality of switches based on the output signal of the first sensor or the second sensor.

6. The gamma voltage generating circuit according to claim 5, wherein, If the first control voltage applied to the first output transistor drops below a predetermined voltage level, the first sensor applies an output signal to the switch control unit.

7. The gamma voltage generating circuit according to claim 6, wherein, If the second control voltage of the second output transistor rises above a predetermined voltage level, the second sensor applies an output signal to the switch control unit.

8. The gamma voltage generating circuit according to claim 6, wherein, If an output signal is applied from the first sensor or the second sensor, the switch control unit outputs a conduction signal to the high-potential connection switch and the low-potential connection switch.

9. The gamma voltage generating circuit according to claim 2, wherein, The sensing circuit includes: A sensing unit is used to sense voltage changes in the plurality of amplifiers; and The switch control unit selectively applies a turn-on signal to a plurality of switches based on the voltage change level sensed in the sensing unit.

10. A source drive circuit, wherein, include: The data drive unit converts source data into data voltage based on gamma voltage; as well as A gamma voltage generating unit generates the gamma voltage; The gamma voltage generating unit includes: The first voltage distribution section outputs a plurality of voltages with different voltage levels; Multiple amplifiers output the voltage from the first voltage distribution unit as a gamma reference voltage; A second voltage distribution unit includes a plurality of reference nodes and a plurality of distribution nodes. The plurality of reference nodes output the gamma reference voltage, and the plurality of distribution nodes output a plurality of gamma distribution voltages through resistors connected between the plurality of reference nodes. Connect the circuit by short-circuiting the reference node where the gamma reference voltage changes with the adjacent distribution node.

11. The source drive circuit according to claim 10, wherein, The connection circuit includes: A switching circuit includes a plurality of switches forming a path that bypasses a resistor disposed between the reference node and the distribution node, thereby short-circuiting the reference node with an adjacent distribution node; and A sensing circuit senses the voltage changes of the plurality of amplifiers and turns on the plurality of switches accordingly.

12. The source drive circuit according to claim 11, wherein, The sensing circuit includes a plurality of sensing units, each of which is connected to a plurality of amplifiers to sense changes in the control voltage of the amplifiers. The switching circuit includes a switch array that is connected to the plurality of sensing portions respectively. The switch array includes a high-potential connection switch and a low-potential connection switch. The high-potential connection switch is connected to a first distribution node with a voltage higher than that of the reference node, and the low-potential connection switch is connected to a second distribution node with a voltage lower than that of the reference node.

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