Optical semiconductor element, optical semiconductor element array, and method for manufacturing optical semiconductor element

Abstract

A semiconductor element comprises: a semiconductor substrate; a first semiconductor layer doped with a first conductivity type; an active layer that emits light; a second semiconductor layer doped with a second conductivity type; and a passivation film having electrical insulation properties. A first electrode pad and a second electrode pad are stacked on the upper surface of the passivation film, and the first electrode pad is electrically connected to the second semiconductor layer via an opening in the passivation film. One of the end faces surrounding the active layer of the semiconductor element has a light-emitting surface. The semiconductor element includes a waveguide extending from the light-emitting surface toward the end face opposite to the light-emitting surface and encompassing the active layer. The semiconductor element has an electrode contact region extending from its upper surface to a depth reaching the first semiconductor layer or the semiconductor substrate. In the electrode contact region, the second electrode pad is connected to the first semiconductor layer or the semiconductor substrate via an electrode formed on a positively tapered surface having a height difference in a direction parallel to the waveguide.

Description

Technical Field

[0001] This invention relates to optical semiconductor elements, optical semiconductor element arrays, and methods for manufacturing optical semiconductor elements. Background Technology

[0002] Patent Document 1 describes the structure of an optical semiconductor element comprising: a first conductive buffer layer formed in an island shape on a semi-insulating semiconductor substrate; a mesa-shaped structure consisting of an active layer, a second conductive cladding layer, and a second conductive electrode layer formed on the first conductive buffer layer; a high-resistivity semiconductor buried layer embedded in the upper surface of the mesa-shaped structure except for a portion of the first conductive buffer layer; a first electrode connected to the upper surface of the mesa-shaped structure; and a second electrode extending from the first conductive buffer layer exposed in a trench formed in the high-resistivity semiconductor buried layer to the upper surface of the high-resistivity semiconductor buried layer.

[0003] Patent Document 2 discloses an optical semiconductor element. This element has a first terraced structure and a second terraced structure on a first conductivity type semiconductor layer disposed on a semiconductor substrate. The first terraced structure includes a first noodle-like structure comprising a stacked structure of a semiconductor active layer and a second conductivity type semiconductor layer of the opposite conductivity type to the first conductivity type, and a high-resistance semiconductor layer embedded in the side of the first noodle-like structure, and has an inclined side. The second terraced structure includes a second noodle-like structure parallel to and independent of the first noodle-like structure, having the same stacked structure as the first noodle-like structure, and a high-resistance semiconductor layer embedded in the side of the second noodle-like structure, and also has an inclined side. The optical semiconductor element includes: a first electrode located on the flat surface of the first terraced structure and connected to the second conductivity type semiconductor layer of the first terraced structure; and a second electrode connected to the first conductivity type semiconductor layer exposed between the first and second terraced structures and extending to the flat portion of the second terraced structure.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 3230785

[0007] Patent Document 2: Japanese Patent No. 5691741 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] However, in the aforementioned prior art, when constructing a flip-chip mounted laser array, two spacer electrodes are arranged in the laser array's alignment direction. Furthermore, even when the two spacer electrodes are arranged perpendicular to the laser array's alignment direction, the wiring leading out from the n-type electrodes still faces the laser array's alignment direction, thus reducing the integration density of the optical semiconductor device. Moreover, the waveguide's buried layer is not doped, thus raising concerns about heat dissipation during integration.

[0010] Therefore, the following technology is pursued: by arranging two flip-chip mounted electrodes and lead-out electrodes connected to the electrodes from the semiconductor layer on the substrate side of the active layer in a manner perpendicular to the arrangement direction of the laser array, the integration of the laser array can be improved with a simple process.

[0011] The present invention was made in view of the above circumstances, and its object is to provide an optical semiconductor element, an optical semiconductor element array, and a method for manufacturing a semiconductor element that can improve the integration of a laser array with an easy process.

[0012] Solution for solving the problem

[0013] To solve the aforementioned problems and achieve the aforementioned objectives, the optical semiconductor element of the present invention is characterized by comprising: a semiconductor substrate; a first semiconductor layer stacked on the semiconductor substrate and subjected to a first conductivity type doping; an active layer disposed on the first semiconductor layer and emitting light; a second semiconductor layer disposed on top of the first semiconductor layer and the active layer and subjected to a second conductivity type doping; and a passivation film disposed on the second semiconductor layer and having electrical insulation properties, wherein the optical semiconductor element has a first electrode pad and a second electrode pad stacked on the upper surface of the passivation film, and the first electrode pad is subjected to... The optical semiconductor element is electrically connected to the second semiconductor layer through an opening in the passivation film. One of the end faces surrounding the active layer has a light emitting surface. The optical semiconductor element has a waveguide extending from the emitting surface toward the end face opposite to the emitting surface and includes the active layer. The optical semiconductor element is provided with an electrode contact region extending from the upper surface to the depth of the first semiconductor layer or the semiconductor substrate. In the electrode contact region, the second electrode pad is connected to the semiconductor substrate or the first semiconductor layer through an electrode formed on a positive tapered surface with a height difference in a direction parallel to the waveguide.

[0014] One aspect of the present invention relates to an optical semiconductor element, characterized in that, in the above-described invention, the upper surface of the first electrode pad and the upper surface of the second electrode pad are located on approximately the same plane.

[0015] One aspect of the present invention relates to an optical semiconductor element, characterized in that, in the above-described invention, when viewed from above, the end of the upper surface is provided with metal wiring extending from the first electrode pad and the second electrode pad.

[0016] One aspect of the present invention relates to an optical semiconductor element, characterized in that, in the above-described invention, the optical semiconductor element comprises a thyristor structure formed by alternately stacking layers of different conductivity types of semiconductor layers in a direction other than the vertical direction of the waveguide.

[0017] One aspect of the present invention relates to an optical semiconductor element array, which is formed by arranging a plurality of optical semiconductor elements as described above. The optical semiconductor element array is characterized by having an electrically separated trench extending from the upper surface of the passivation film to the depth of the first semiconductor layer or the semiconductor substrate. The optical semiconductor element array has a plurality of optical semiconductor elements arranged in a state where the second semiconductor layer is electrically separated by the electrically separated trench.

[0018] One aspect of the present invention relates to an optical semiconductor element array, characterized in that, in the above-described invention, the first semiconductor layer is electrically separated by the electro-separation tank.

[0019] One aspect of the present invention relates to an optical semiconductor element array, characterized in that, in the above-described invention, the electro-separation groove is connected to the electrode contact area when viewed from above.

[0020] One aspect of the present invention relates to an optical semiconductor element array, characterized in that, in the above-described invention, the depth from the upper surface to the electrode contact region is approximately equal to the depth from the upper surface to the electro-separation trench.

[0021] One aspect of the present invention relates to a method for manufacturing an optical semiconductor element, the optical semiconductor element comprising: a first semiconductor layer formed on a semiconductor substrate and subjected to a first conductivity type doping; an active layer forming a light-emitting portion formed on the first semiconductor layer; a second semiconductor layer formed on top of the first semiconductor layer and the active layer and subjected to a second conductivity type doping; and a passivation film formed on the second semiconductor layer and having electrical insulation properties, wherein the optical semiconductor element has a first electrode pad and a second electrode pad electrically connected to the second semiconductor layer formed on the upper surface of the passivation film, the optical semiconductor element having a light-emitting surface formed on one of the end faces surrounding the active layer, and a waveguide extending toward the end face opposite to the light-emitting surface and including the active layer, the method for manufacturing the optical semiconductor element being characterized in that an electrode contact region is formed extending from the upper surface to a depth reaching the first semiconductor layer or the semiconductor substrate, and the second electrode pad is formed to be connected to the semiconductor substrate or the first semiconductor layer in the electrode contact region by an electrode formed on a positively tapered surface having a height difference in a direction parallel to the waveguide.

[0022] Invention Effects

[0023] According to the present invention, the integration density of laser arrays can be improved with a simple process. Attached Figure Description

[0024] Figure 1 This is an illustrative and schematic top view of a semiconductor element according to an embodiment of the present invention.

[0025] Figure 2 It is along Figure 1 A cross-sectional view of the semiconductor element along line II-II.

[0026] Figure 3 It is along Figure 1 The cross-sectional view of the semiconductor element along line III-III is shown.

[0027] Figure 4 It is along Figure 1 A cross-sectional view of a semiconductor element along line VI-VI.

[0028] Figure 5 It is along Figure 1 A cross-sectional view of the semiconductor element along the VV line.

[0029] Figure 6 This is an exemplary and schematic top view showing a wafer formed from a semiconductor element portion according to an embodiment of the present invention. Detailed Implementation

[0030] The embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that in all the drawings of the following embodiments, the same or corresponding parts are labeled with the same reference numerals. The structure of the embodiments shown below, as well as the effects and results (effects) brought about by that structure, are examples. The present invention can also be implemented with structures other than those disclosed in the following embodiments. Furthermore, according to the present invention, at least one of various effects obtained through the structure and derived effects can be obtained. In this specification, ordinal numbers are assigned for the convenience of distinguishing directions, components, parts, etc., and do not indicate priority or order.

[0031] In addition, in each diagram, arrow X represents the X direction, arrow Y represents the Y direction, and arrow Z represents the Z direction. The X, Y, and Z directions intersect and are orthogonal to each other. Furthermore, hereinafter, the X direction will be referred to as the short side direction or width direction, the Y direction as the long side direction or extension direction, and the Z direction as the stacking direction or height direction. Also, each diagram is an illustrative diagram for explanation purposes, and the scale or ratio may not necessarily match the actual object.

[0032] First, an optical semiconductor element according to one embodiment of the present invention will be described. Figure 1 A top view of the optical device of this embodiment is shown. Figure 2 , Figure 3 , Figure 4 ,as well as Figure 5 Show along Figure 1 The cross-sectional views of lines II-II, III-III, IV-IV, and VV.

[0033] like Figures 1-5As shown, an optical semiconductor element 1A according to an embodiment of the present invention includes: a semiconductor substrate 30; a first semiconductor layer, which is stacked on the semiconductor substrate 30 and is composed of a lower cladding layer 31 that has been doped with, for example, n-type as a first conductivity type; an active layer 34 disposed on the lower cladding layer 31 and emitting light; a second semiconductor layer disposed on the upper layer of the lower cladding layer 31 and the active layer 34, and including an upper cladding layer 35 that has been doped with, for example, p-type as a second conductivity type and a contact layer 36; and a passivation film 12 disposed on the contact layer 36 and having electrical insulation properties. The optical semiconductor element 1A has a first electrode pad, i.e., a p-side electrode pad 10, which is electrically connected to the p-side electrode 11 as a first electrode, and a second electrode pad, i.e., a p-side electrode pad 10, which is electrically connected to the p-side electrode 11 as a first electrode, and a p-side electrode pad 10, which is electrically connected to the p-side electrode 11 as a second electrode, stacked on the upper surface of the passivation film 12. The second electrode pad, i.e., the n-side electrode pad 20, is electrically connected to the n-side electrode 21 of the electrode, and the p-side electrode pad 10 is electrically connected to the contact layer 36 via the connection hole 12a provided in the passivation film 12. The optical semiconductor element 1A has a light emitting surface surrounding one of the end faces of the active layer 34. The optical semiconductor element 1A has a waveguide L extending from the emitting surface toward the end face opposite to the emitting surface and including the active layer 34. The semiconductor element 1A is provided with an electrode contact region, i.e., the n-side electrode contact region 2, which extends from the upper surface to the depth of the lower cladding 31, which is the first semiconductor layer, or the semiconductor substrate 30. In the n-side electrode contact region 2, the n-side electrode pad 20 is formed by the n-side electrode 21 formed on a positive tapered surface with a height difference in a direction parallel to the active layer 34 constituting the waveguide L.

[0034] In addition, one embodiment of the present invention is an optical semiconductor element array 1 in which a plurality of the above-mentioned optical semiconductor elements 1A are arranged. It is provided with an electrical separation trench 40 extending from the upper surface of the passivation film 12 to the depth of the lower cladding layer 31 or the semiconductor substrate 30, which is the first semiconductor layer. The optical semiconductor element array 1 is arranged with a plurality of optical semiconductor elements 1A in a state where the lower cladding layer 31 is electrically separated by the electrical separation trench 40.

[0035] like Figure 2 , Figure 3 ,as well as Figure 4As shown, the optical semiconductor device 1A of this embodiment has the following structure: a lower cladding layer 31, which is composed of a stacked structure of an n-type InP layer and an n-type InGaAsP layer and also serves as a buffer layer, is stacked on a semiconductor substrate 30 made of n-type InP; an active layer 34, which contains n-type InGaAsP; an upper cladding layer 35, which is composed of p-type InP; and a contact layer 36, which is composed of p-type InGaAsP. That is, it has a thyristor structure obtained by alternately stacking layers of different conductivity types of semiconductor layers in the direction other than the vertical direction (X direction) of the waveguide L. It should be noted that a diffraction grating layer composed of a p-type InGaAsP layer may also be provided in the upper cladding layer 35 along the long side direction (Y direction) of the optical semiconductor device 1A and along the active layer 34. The upper cladding layer 35, the active layer 34, and the lower cladding layer 31 containing the diffraction grating layer are processed into a mesa shape.

[0036] The mesa structure including the active layer 34 has a structure in which a lower barrier layer 32 composed of p-type InP constituting the second semiconductor layer and an upper barrier layer 33 composed of n-type InP are embedded. The lower barrier layer 32 and the upper barrier layer 33 function as current blocking layers. That is, the active layer 34, which is processed into a mesa shape, functions as an optical waveguide and has an embedded waveguide structure (BH waveguide structure). A main protrusion is formed in the form of a mesa structure including the active layer 34. On the contact layer 36 of the main protrusion, a p-side electrode 11 connected to the contact layer 36 is provided in a connection hole 12a, which is an opening, and a p-side electrode pad 10 is provided at a position led out along the array arrangement direction (X direction).

[0037] In addition, such as Figures 1-4 As shown in the top view, a laser emission surface is provided on one of the end faces surrounding the upper surface. A waveguide L is provided on the main protrusion containing the active layer 34, facing the end face opposite to the emission surface. An electrostatic separation trench 40 is formed along a direction parallel to the waveguide L (Y direction) to reach the lower cladding 31 or the semiconductor substrate 30. An n-side electrode 21 is formed at a position where a portion of the bottom surface of the electrostatic separation trench 40 extends along the array arrangement direction (X direction).

[0038] like Figure 1 as well as Figure 5 As shown, regarding the p-side electrode pad 10 and the n-side electrode pad 20, their upper surfaces are at approximately the same height from the active layer 34. That is, the upper surfaces of the p-side electrode pad 10 and the n-side electrode pad 20 are formed to be on approximately the same plane. The main protrusion constitutes the light-emitting part that emits laser light through current injection.

[0039] Furthermore, an n-side electrode contact region 2 is provided on the upper surface, reaching the depth of the lower cladding 31 or semiconductor substrate 30, which serves as the first semiconductor layer. Within the n-side electrode contact region 2, a contact region 21a is formed at a position extending perpendicularly to the array arrangement direction (X direction) along the Y direction, electrically connecting the lower cladding 31 or semiconductor substrate 30 to the n-side electrode 21. That is, the n-side electrode pad 20 and the n-side electrode 21 extending along the Y direction are electrically connected to the lower cladding 31 or semiconductor substrate 30 within the contact region 21a. The n-side electrode pad 20 from the n-side electrode contact region 2 has a structure connected to the contact region 21a by an n-side electrode 21 formed on a positively tapered surface having a height difference in the direction parallel to the active layer 34 constituting the waveguide L (Y direction).

[0040] Furthermore, the electrical separation trench 40 electrically separates at least the lower barrier layer 32, which serves as a second semiconductor layer, and the upper cladding layer 35 between adjacent opto-semiconductor elements 1A. That is, the depth of the electrical separation trench 40 can be either etched to the middle of the lower cladding layer 31 or etched to the depth reaching the semiconductor substrate 30. When the lower layer of the lower cladding layer 31 further includes a semi-insulating layer (not shown), by setting the depth of the electrical separation trench 40 to the semi-insulating layer and setting the contact depth of the n-side electrode 21 to the lower cladding layer 31, electrical separation of the n-side region can also be achieved.

[0041] Furthermore, if the semiconductor substrate 30 is a semi-insulating substrate, or a semiconductor substrate made of a different conductivity type (e.g., p-type) than the lower cladding layer 31 which serves as the first semiconductor layer, the electrical separation trench 40 may be formed to the lower cladding layer 31 or even deeper. In this case, the lower cladding layer 31 of the first semiconductor layer and the lower barrier layer 32 and upper cladding layer 35 of the second semiconductor layer of adjacent optical semiconductor elements 1A in the laser array are separated, thus breaking unnecessary current paths and improving carrier injection efficiency, which is therefore more preferable.

[0042] (Manufacturing method of opto-semiconductor devices)

[0043] Next, an example of a method for manufacturing an optical semiconductor device configured as described above will be described. Specifically, a lower cladding layer 31 comprising an n-type InP layer, an active layer 34 comprising a GaInAsP layer, an upper cladding layer 35 comprising a p-type InP layer, and a diffraction grating layer comprising a GaInAsP layer are sequentially crystallized and grown on a semiconductor substrate 30 made of InP.

[0044] Next, an insulating layer, for example made of silicon nitride (SiN), is grown on the substrate to which the diffraction grating layer is formed. Then, a photoresist film is formed on the grown insulating layer. Next, a diffraction grating pattern is formed on the photoresist film using an electron beam patterning apparatus, the insulating layer is etched, and the diffraction grating pattern is transferred. After removing the photoresist film, a diffraction grating is formed by etching the diffraction grating layer, for example, using a dry etching apparatus. Then, after removing the insulating layer, the layer with the embedded diffraction grating layer is crystallized and grown.

[0045] After patterning the resist film in the form of a mesa region of the residual active layer 34, the insulating layer outside the mesa region of the active layer is removed by etching. After removing the residual resist film, the active layer 34 is etched into a mesa shape.

[0046] Next, a buried structure with an active layer mesa is formed by sequentially crystallizing and growing a lower barrier layer 32 made of p-type InP and an upper barrier layer 33 made of n-type InP. Thus, the active layer 34 is processed into a mesa shape to form a buried waveguide structure that functions as an optical waveguide. Next, after removing the insulating layer, a top cladding layer 35 made of p-type InP and a contact layer 36 comprising a stacked structure of p-type GaInAsP layers are sequentially crystallized and grown.

[0047] Next, a resist film is formed on the contact layer 36 after crystal growth and patterned into the shape of an electrostatic separation tank 40. Then, the contact layer 36, the upper cladding layer 35, the upper barrier layer 33, and a portion of the lower barrier layer 32 are removed by etching, thereby forming the electrostatic separation tank 40 and creating the n-side electrode contact region 2. At this time, by selecting an anisotropic etchant such as hydrochloric acid (HCl), a conical surface with a height difference from the bottom of the n-side electrode contact region 2 towards the contact layer 36 is formed.

[0048] Next, after forming an insulating film of, for example, SiN over the entire surface, a resist film is formed on the insulating film, and the surface to which the p-side electrode 11 and the n-side electrode 21 are connected is patterned. Then, the insulating film is etched using the patterned resist film as a mask, and the resist film is removed.

[0049] Next, by means of, for example, vapor deposition stripping, a p-side electrode 11 comprising a stacked structure of Au / AuZn is formed on the contact layer 36 along the waveguide. Next, by means of, for example, vapor deposition stripping, an n-side electrode 21 comprising a stacked structure of AuGe / Ni / Au is formed in the n-side electrode contact region 2.

[0050] Next, gold (Au) is plated onto the upper layers of the p-side electrode 11 and the n-side electrode 21, thereby forming the p-side electrode pad 10 and the n-side electrode pad 20 together. Here, as... Figure 1As shown, in order to integrally form the p-side electrode pad 10 and the n-side electrode pad 20 through a plating process, raised patterns 10a and 20a are formed so that the p-side electrode pad 10 and the n-side electrode pad 20 are continuous in other optical semiconductor elements 1A adjacent to the arrangement direction (Y direction). Raised pattern 10a is composed of metal wiring extending from the p-side electrode pad 10, and raised pattern 20a is composed of metal wiring extending from the n-side electrode pad 20. That is, in the stage before the optical semiconductor elements 1A are separated and cut, the raised patterns 10a and 20a are used to make the p-side electrode pad 10 and the n-side electrode pad 20 continuous, thereby enabling the plating process.

[0051] Next, the semiconductor substrate 30 is ground to a predetermined thickness. Then, a heat treatment at, for example, 400°C is performed. This establishes an ohmic connection between the p-side electrode 11 and the contact layer 36, which is the semiconductor layer connected to the p-side electrode 11. Additionally, an ohmic connection is established between the n-side electrode 21 and the lower cladding layer 31, which is the semiconductor layer connected to the n-side electrode 21, or the semiconductor substrate 30.

[0052] Figure 6 This is a top view showing a semiconductor wafer 100 with the optical semiconductor element 1A arranged in a predetermined direction as described above. Figure 6 As shown, the surface of the semiconductor wafer 100 is a (100) plane, and the long side direction (Y direction) of the plurality of optical semiconductor elements 1A is a crystallization direction of <011>, and the arrangement direction perpendicular to the long side direction (X direction) is set as a crystallization direction of <01-1>. The semiconductor wafer 100 on which the plurality of optical semiconductor elements 1A are formed is cleaved to form end faces, and a low-reflection coating is applied on the output side, while a high-reflection coating is applied on the opposite side, thereby forming Figure 1 The optical semiconductor element 1A shown is shown.

[0053] According to one embodiment of the present invention described above, two flip-chip mounted p-side electrode pads 10 and n-side electrode pads 20, and an lead-out electrode for connecting the lower cladding 31 of the semiconductor layer (which is the active layer 34 on the side of the semiconductor substrate 30) to the n-side electrode 21 can be arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the laser array, thus enabling the integration density of the laser array to be improved with a simple process.

[0054] The present invention has been specifically described above with respect to one embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be made based on the technical concept of the present invention. Components constructed by appropriately combining the above-described constituent elements are also included in the present invention. Furthermore, further effects and modifications can be readily derived by those skilled in the art. Therefore, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the values ​​or materials given in the above-described embodiment are merely examples, and different values ​​or materials may be used as needed. The present invention is not limited to the description and drawings that constitute a part of the disclosure of the present invention as described in this embodiment.

[0055] Industrial availability

[0056] This invention can be applied to optical semiconductor devices, optical semiconductor device arrays, and methods for manufacturing optical semiconductor devices.

[0057] Explanation of reference numerals in the attached figures:

[0058] 1 Optical semiconductor element array

[0059] 1A Optoelectronic Semiconductor Component

[0060] 2 n-side electrode contact area

[0061] 10p side electrode pad

[0062] 10a, 20a convex patterns

[0063] 11 p-side electrode

[0064] 12 Passivation film

[0065] 12a Connecting hole

[0066] 20 n-side electrode pad

[0067] 21 n-side electrode

[0068] 21a Contact Area

[0069] 30 Semiconductor substrate

[0070] 31 lower cladding

[0071] 32 Lower barrier layer

[0072] 33 Upper barrier layer

[0073] 34 Active layer

[0074] 35 Upper cladding

[0075] 36 Contact Layer

[0076] 40 Electrostatic Separation Tank

[0077] 100 Semiconductor Wafers

[0078] L-waveguide.

Claims

1. An optical semiconductor element, characterized in that, The optical semiconductor element comprises: substrate; A first semiconductor layer is stacked on the substrate and is doped with a first conductivity type. An active layer is disposed on the first semiconductor layer and emits light; The second semiconductor layer is disposed on top of the first semiconductor layer and the active layer, and is doped with a second conductivity type. as well as A passivation film, disposed on the second semiconductor layer, has electrical insulating properties. The optical semiconductor element has a first electrode pad and a second electrode pad stacked on the upper surface of the passivation film, and the first electrode pad is electrically connected to the second semiconductor layer through an opening in the passivation film. The optical semiconductor element has a light-emitting surface on one of the end faces surrounding the active layer. The optical semiconductor element includes a waveguide extending from the emitting surface toward an end face opposite to the emitting surface and containing the active layer. The optical semiconductor element is provided with an electrode contact region extending from the upper surface to the depth of the first semiconductor layer or the substrate. In the electrode contact area, the second electrode pad is connected to the substrate or the first semiconductor layer by an electrode formed on a positively tapered surface having a height difference in a direction parallel to the waveguide.

2. The optical semiconductor element according to claim 1, characterized in that, The upper surface of the first electrode pad and the upper surface of the second electrode pad are located on approximately the same plane.

3. The optical semiconductor element according to claim 2, characterized in that, Viewed from above, metal wiring extending from the first electrode pad and the second electrode pad is provided at the end of the upper surface.

4. The optical semiconductor element according to any one of claims 1 to 3, characterized in that, The optical semiconductor element has a thyristor structure obtained by alternately stacking semiconductor layers of different conductivity types in a direction other than the vertical direction of the waveguide.

5. An array of optical semiconductor elements, formed by arranging a plurality of optical semiconductor elements as described in claim 1, characterized in that, The optical semiconductor element array is provided with an electrical separation trench extending from the upper surface of the passivation film to the depth of the first semiconductor layer or the substrate. The optical semiconductor element array has multiple optical semiconductor elements arranged in a state where the second semiconductor layer has been electrically separated by the electrical separation tank.

6. The optical semiconductor element array according to claim 5, characterized in that, The first semiconductor layer was electrically separated by the electro-separation tank.

7. The optical semiconductor element array according to claim 5, characterized in that, Viewed from above, the electro-separation tank is in contact with the electrode contact area.

8. The optical semiconductor element array according to claim 5, characterized in that, The depth from the upper surface to the electrode contact area is approximately equal to the depth from the upper surface to the electro-separation tank.

9. A method for manufacturing an optical semiconductor device, The optical semiconductor element comprises: a first semiconductor layer formed on a substrate and doped with a first conductivity type; an active layer forming a light-emitting portion formed on the first semiconductor layer; a second semiconductor layer formed on top of the first semiconductor layer and the active layer and doped with a second conductivity type; and a passivation film formed on the second semiconductor layer and having electrical insulation properties. The optical semiconductor element has a first electrode pad and a second electrode pad electrically connected to the second semiconductor layer formed on the upper surface of the passivation film. The optical semiconductor element has a light-emitting surface formed on one of its end faces surrounding the active layer, and a waveguide extending toward the end face opposite to the light-emitting surface and including the active layer. The method for manufacturing the optical semiconductor element is characterized in that, An electrode contact region is formed extending from the upper surface to the depth of the first semiconductor layer or the substrate, and the second electrode pad is formed in the electrode contact region by an electrode formed on a positive tapered surface having a height difference in a direction parallel to the waveguide, thereby connecting to the substrate or the first semiconductor layer.

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