Fan control methods, devices and controllers, dual rotor fans, products and equipment

Abstract

This application discloses a fan control method, device, controller, dual-rotor fan, product, and equipment, relating to the field of heat dissipation technology. The method includes: with both the first and second rotors of the dual-rotor fan in serial communication control mode, sending firmware upgrade commands to the first and second rotors respectively via a serial communication bus, causing the first rotor to enter firmware upgrade mode and stop rotating, while the second rotor enters clock signal speed regulation mode and continues operation; during the firmware upgrade mode of the first rotor, outputting a speed regulation clock signal to the second rotor via the clock signal line of the serial communication bus to adjust the speed of the second rotor; and sending firmware upgrade data to the first rotor via the data signal line of the serial communication bus, so that the first rotor can perform a firmware upgrade based on the firmware upgrade data. This application allows for effective speed regulation of the other rotor even while one rotor of the dual-rotor fan is undergoing a firmware upgrade.

Description

Technical Field

[0001] This application relates to the field of heat dissipation technology, and more specifically, to a fan control method, device and controller, dual rotor fan, product and equipment. Background Technology

[0002] Dual-rotor fans are widely used in cooling systems due to their high heat dissipation efficiency. To achieve precise control and status monitoring, existing technologies often construct an I2C (Inter-Integrated Circuit) bus by multiplexing traditional PWM (Pulse Width Modulation) or TACH (Tachometer) signal lines, enabling the fan controller to interact with each rotor. However, during operations such as firmware upgrades on one rotor that occupy the serial communication bus for extended periods, the controller cannot send speed control commands to the other rotor in a timely manner because I²C communication uses a polling mechanism and the bus is exclusively used for firmware data transmission. This causes the second rotor to lose its real-time speed control capability during the upgrade, while the first rotor typically stops rotating. The overall cooling capacity of the fan decreases significantly, potentially leading to localized overheating or even system crashes.

[0003] Therefore, how to effectively control the speed of the other rotor in a dual-rotor fan while one rotor is undergoing a firmware upgrade, in order to maintain the system's heat dissipation stability, is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a fan control method, device and controller, dual-rotor fan, product and equipment that can still effectively regulate the speed of the other rotor while one rotor of the dual-rotor fan is undergoing a firmware upgrade, so as to maintain the system's heat dissipation stability.

[0005] To achieve the above objectives, this application provides a fan control method applied to a controller, the method comprising: When both the first and second rotors of the dual-rotor fan are in serial communication control mode, firmware upgrade commands are sent to the first and second rotors respectively via the serial communication bus, so that the first rotor enters firmware upgrade mode and stops rotating, and the second rotor enters clock signal speed regulation mode and continues to run. During the firmware upgrade mode of the first rotor, a speed regulation clock signal is output to the second rotor through the clock signal line of the serial communication bus to regulate the speed of the second rotor. Firmware upgrade data is sent to the first rotor via the data signal line of the serial communication bus so that the first rotor can perform firmware upgrade based on the firmware upgrade data.

[0006] To achieve the above objectives, this application provides a fan control method applied to one of the target rotors of a dual-rotor fan, the method comprising: In serial communication control mode, the receiver receives firmware upgrade commands sent by the controller via the serial communication bus; Enter firmware upgrade mode or clock signal speed adjustment mode according to the firmware upgrade instruction; In firmware upgrade mode, the rotation stops, firmware upgrade data is received through the data signal line of the serial communication bus, and firmware upgrade is performed based on the firmware upgrade data. In clock signal speed control mode, it continues to run, receiving the speed control clock signal through the clock signal line of the serial communication bus, and adjusting its own speed based on the speed control clock signal.

[0007] To achieve the above objectives, this application provides a fan control device applied to a controller, the device comprising: The first mode switching module is used to send firmware upgrade commands to the first rotor and the second rotor respectively via the serial communication bus when both the first rotor and the second rotor of the dual rotor fan are in serial communication control mode, so that the first rotor enters firmware upgrade mode and stops rotating, and the second rotor enters clock signal speed regulation mode and continues to run. The first adjustment module is used to output a speed regulation clock signal to the second rotor through the clock signal line of the serial communication bus during the firmware upgrade mode of the first rotor, so as to adjust the speed of the second rotor. The first upgrade module is used to send firmware upgrade data to the first rotor through the data signal line of the serial communication bus, so that the first rotor can perform firmware upgrade based on the firmware upgrade data.

[0008] To achieve the above objectives, this application provides a fan control device applied to one of the target rotors of a dual-rotor fan, the device comprising: The first receiving module is used to receive firmware upgrade instructions sent by the controller through the serial communication bus in the serial communication control mode. The second mode switching module is used to enter the firmware upgrade mode or the clock signal speed regulation mode according to the firmware upgrade instruction or its own rotor identifier. The second upgrade module is used to stop rotation in firmware upgrade mode, receive firmware upgrade data through the data signal line of the serial communication bus, and perform firmware upgrade based on the firmware upgrade data. The second adjustment module is used to continue operating in clock signal speed regulation mode. It receives the speed regulation clock signal through the clock signal line of the serial communication bus and adjusts its own speed based on the speed regulation clock signal.

[0009] To achieve the above objectives, this application provides a controller, comprising: Memory, used to store computer programs; A processor is used to execute computer programs to implement the fan control method described above on the controller side.

[0010] To achieve the above objectives, this application provides a dual-rotor fan, comprising: Memory, used to store computer programs; A processor is used to execute computer programs to implement the steps of the fan control method for the dual-rotor fan side as described above.

[0011] To achieve the above objectives, this application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the fan control method described above.

[0012] To achieve the above objectives, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the fan control method described above.

[0013] To achieve the above objectives, this application provides an electronic device including a controller as described above and / or a dual-rotor fan as described above.

[0014] The fan control method provided in this application, under the premise that both the first rotor and the second rotor are in serial communication control mode, the controller sends firmware upgrade commands to both rotors through the bus, causing the first rotor to enter firmware upgrade mode and stop rotating, while simultaneously causing the second rotor to switch to clock signal speed regulation mode and continue running. In this state, the controller can continuously send firmware upgrade data to the first rotor through the bus data signal line to complete its firmware update; on the other hand, it can simultaneously output a speed regulation clock signal to the second rotor through the clock signal line of the same bus to regulate its speed. Since the firmware upgrade data and the speed regulation signal are transmitted independently through the data signal line and the clock signal line respectively, they do not conflict with each other. Therefore, even if the first rotor occupies the data signal line for a long time during the firmware upgrade process, the controller can still regulate the speed of the second rotor in real time through the clock signal line. This parallel utilization of different physical lines in the serial communication bus allows firmware upgrade and speed regulation to be performed synchronously on the same bus, thereby ensuring the smooth completion of the upgrade operation while maintaining the effective heat dissipation capacity of the fan system. This application also discloses a fan control device, a controller, a dual-rotor fan, a computer-readable storage medium, a computer program product, and an electronic device, which can achieve the above-mentioned technical effects.

[0015] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0016] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the control method for a dual-rotor fan in PWM control mode in the existing scheme; Figure 2 This is a schematic diagram of the control method for a dual-rotor fan in the I2C control mode in the existing scheme; Figure 3 This is a flowchart illustrating a fan control method according to an exemplary embodiment; Figure 4 A flowchart illustrating another fan control method according to an exemplary embodiment; Figure 5 Architecture diagram of the application embodiments provided in this application; Figure 6 The waveform of the clock signal CLK_R generated by the fan controller I2C module in CLK-PWM speed control mode in the application embodiment provided in this application; Figure 7 A flowchart illustrating how a fan controller controls a dual-rotor fan in an application embodiment provided in this application; Figure 8 This is a structural diagram of a fan control device according to an exemplary embodiment; Figure 9 This is a structural diagram illustrating another fan control device according to an exemplary embodiment; Figure 10 This is a structural diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0019] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0020] Taking the dual-rotor fan control system commonly used in server systems as an example, the PWM signal emitted by the fan controller is split into two paths and enters the front and rear rotors respectively. The front and rear rotors are fed back their actual speeds through TACH1 and TACH2 respectively. The front and rear rotors of the same fan are controlled by the same control unit.

[0021] Figure 1 In the existing control method for dual-rotor fans in PWM control mode, the fan controller can only regulate the fan speed. The speed control unit in the fan controller calculates the target duty cycle based on the target speed and uses a timer module to generate a PWM signal with the target duty cycle, which is then sent to the fan. The fan adjusts its speed according to the PWM duty cycle and uses the frequency of the TACH signal to provide feedback on the actual fan speed. The timer module in the fan controller then measures the frequency of the TACH signal, and the speed control unit calculates the actual fan speed. Each timer module in the fan controller corresponds to one fan.

[0022] After switching from PWM control mode to I2C control mode, as follows Figure 2 As shown, this describes the control method for a dual-rotor fan in I2C control mode in the existing scheme. The fan controller's I2C module uses signal selectors to connect to the IN rotor (first rotor) and OUT rotor (second rotor) respectively. The fan controller communicates with each rotor sequentially via I2C through polling. During speed regulation, the speed regulation unit in the fan controller calculates the target duty cycle based on the target speed, sends the target duty cycle to the fan through the I2C module, and reads the actual fan speed. During fan data read / write, the data read / write unit in the fan controller reads and writes data with each fan through the I2C module.

[0023] As can be seen, in scenarios where dual-rotor fans undergo firmware upgrades or other long-duration bus operations in I2C control mode, the communication time between the fan controller and the rotor undergoing firmware upgrades increases significantly. Prolonged bus occupation leads to increased communication latency between the fan controller and the other rotor. When one rotor of a dual-rotor fan is undergoing an online firmware upgrade, the rotor being upgraded will stop rotating, and the I2C bus occupation prevents timely control of the other rotor, posing a risk to system heat dissipation. Therefore, the fan control method provided in this application allows the fan controller to still regulate the speed of the other rotor even when one rotor of a dual-rotor fan is using the I2C bus for firmware data transmission, reducing the risk to system heat dissipation.

[0024] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] The embodiments of this application provide a fan control method, and the method is described in detail below in conjunction with the execution flow of the fan control method.

[0026] See Figure 3 A flowchart illustrating a fan control method according to an exemplary embodiment is shown below. Figure 3 As shown, it includes: S101: When the first and second rotors of the dual-rotor fan are both in serial communication control mode, a firmware upgrade command is sent to the first and second rotors respectively through the serial communication bus, so that the first rotor enters firmware upgrade mode and stops rotating, and the second rotor enters clock signal speed regulation mode and continues to run. In this embodiment, the execution entity is the controller.

[0027] A dual-rotor fan refers to a fan device that integrates two independent drive units within a single fan body, including a first rotor and a second rotor, each of which can be controlled to start, stop, and adjust speed independently. Serial communication control mode refers to the operating state where the first and second rotors receive digital instructions from the controller via the same serial communication bus (e.g., I2C) to execute corresponding operations. This bus contains at least one data signal line (DAT) and one clock signal line (CLK). Firmware upgrade instructions are specific control commands generated by the controller and sent via the serial communication bus to instruct the target rotor to enter the firmware update process. Clock signal speed regulation mode means that the second rotor no longer relies on conventional data instructions for speed adjustment, but instead obtains speed regulation information by parsing the timing signals carried on the CLK line.

[0028] In this step, the controller first confirms that both the first and second rotors have entered serial communication control mode, meaning both can respond to digital commands on the bus. Then, the controller sends a first firmware upgrade command to the first rotor via the DAT line. Upon receiving the command, the first rotor immediately stops supplying power to the motor drive circuit and enters firmware upgrade mode. Simultaneously, the controller sends a second firmware upgrade command to the second rotor via the DAT line. Upon receiving this command, the second rotor switches to clock signal speed control mode and maintains motor operation. For example, in a server cooling system, when a new version of the control logic needs to be upgraded to the IN-side rotor (as the first rotor), the OUT-side rotor (as the second rotor) can continue operating to maintain airflow.

[0029] As can be seen, this step enables the firmware upgrade process for a single rotor to be initiated without interrupting the operation of the entire fan, while preserving the ability for the other rotor to continue operation and subsequent speed adjustment, thus avoiding a sudden drop in the system's heat dissipation capacity due to the upgrade.

[0030] As a feasible implementation, before sending the firmware upgrade command to the first rotor and the second rotor via the serial communication bus, the method further includes: sending a mode switching command to the first rotor and the second rotor of the dual rotor fan to switch the control mode of the first rotor and the second rotor from the pulse width modulation mode to the serial communication control mode.

[0031] Among them, pulse width modulation mode refers to the traditional control method in which the rotor adjusts its speed by receiving an externally applied pulse width modulation signal. This signal is usually composed of a square wave output by the controller, and its duty cycle determines the target speed.

[0032] In practical implementation, in the initial state of the system, the first and second rotors may be in PWM mode, controlled by independent PWM signal lines. When a firmware upgrade is required, the controller first sends a mode switching command to both rotors via the serial communication bus. Upon receiving this command, each rotor disables its PWM signal response logic, activates its internal serial communication interface, and enters serial communication control mode, thus gaining the ability to receive subsequent firmware upgrade commands. For example, during the server's power-on initialization phase, the fans operate in PWM mode by default; when the remote management module triggers the firmware update process, it first sends a mode switching command, causing both rotors to enter a programmable state.

[0033] As can be seen, this implementation method achieves a smooth transition from traditional analog control to digital communication control, enabling fan hardware that originally only supported PWM input to be compatible with the firmware upgrade and parallel speed regulation mechanism proposed in this application, thereby improving the compatibility and applicability of the solution.

[0034] S102: During the firmware upgrade mode of the first rotor, a speed regulation clock signal is output to the second rotor through the clock signal line of the serial communication bus to regulate the speed of the second rotor. The speed control clock signal refers to the electrical signal with specific timing characteristics applied by the controller on the CLK line. Its frequency, period, or encoding mode is interpreted by the second rotor as a speed adjustment command. CLK is the physical line used for synchronous data transmission in the serial communication bus, and in this embodiment, it is multiplexed as the speed control command channel.

[0035] In this step, after the first rotor has entered firmware upgrade mode and stopped rotating, the controller no longer sends regular speed control commands to the second rotor via the DAT line. Instead, it controls the level change of the CLK line to output a speed control clock signal. The second rotor has an internal speed control decoding module that can monitor the signal characteristics on the CLK line in real time and adjust its motor drive current or voltage accordingly to change the speed.

[0036] As can be seen, this step utilizes the CLK line to independently transmit speed regulation information, so that the speed regulation of the second rotor does not need to occupy the DAT line resources, thus allowing it to be executed in parallel with the firmware upgrade process that is currently underway on the first rotor, effectively avoiding speed regulation delays or failures caused by bus monopoly.

[0037] As a feasible implementation, a speed-regulating clock signal is output to the second rotor via the clock signal line of the serial communication bus to adjust the rotational speed of the second rotor. This includes: determining the target rotational speed of the second rotor and converting the target rotational speed into a corresponding target pulse width modulation duty cycle; mapping the target pulse width modulation duty cycle to a clock signal duty cycle within a preset range; generating a speed-regulating clock signal based on the clock signal duty cycle and outputting it to the second rotor via the clock signal line of the serial communication bus, so that the second rotor can deduce the target pulse width modulation duty cycle based on the received clock signal duty cycle and adjust its own rotational speed based on the target pulse width modulation duty cycle.

[0038] The target speed refers to the desired operating speed of the second rotor calculated by the controller based on system heat dissipation requirements (such as temperature and load). The target pulse width modulation duty cycle is the duty cycle value corresponding to the target speed in traditional PWM control. The clock signal duty cycle refers to the ratio of the high-level time on CLK to the entire cycle, and is used as the carrier of speed regulation information.

[0039] In practice, the controller first determines the target speed of the second rotor based on the current thermal management strategy, and then converts it into an equivalent target PWM duty cycle. Since the CLK line typically has fixed electrical characteristics in serial communication, directly using the original PWM duty cycle may exceed the physically permissible range; therefore, it needs to be mapped to a preset clock signal duty cycle range. The mapped value is used to generate a speed-regulating clock signal with the corresponding duty cycle and is output through the CLK line. The second rotor has an internal decoding unit that can measure the duty cycle of the CLK signal and, based on the same mapping relationship, deduce the original PWM duty cycle, thereby driving the motor to reach the target speed.

[0040] As can be seen, this implementation method, through the duty cycle mapping mechanism, not only retains compatibility with traditional PWM control logic, but also adapts to the physical limitations of the serial communication bus, so that the second rotor can achieve precise speed regulation based on the CLK line without modifying the underlying drive algorithm.

[0041] As a feasible implementation method, converting the target rotational speed into a corresponding target pulse width modulation duty cycle includes: using the ratio of the target rotational speed to the rated rotational speed of the second rotor as the target pulse width modulation duty cycle.

[0042] Rated speed refers to the maximum stable speed that the second rotor can reach under 100% PWM duty cycle (i.e., full power input), which is usually determined by the design of the motor and fan blades.

[0043] In practice, the controller uses a linear proportional relationship to convert the target speed into a PWM duty cycle. Specifically, the target PWM duty cycle is equal to the target speed divided by the rated speed. For example, if the rated speed of the second rotor is 10,000 RPM (revolutions per minute), and the current required target speed is 7,000 RPM, then the target PWM duty cycle is 7000 / 10000 = 0.7, or 70%.

[0044] As a feasible implementation method, mapping the target pulse width modulation duty cycle to a clock signal duty cycle within a preset range includes: mapping the target pulse width modulation duty cycle to the corresponding clock signal duty cycle according to a predefined linear mapping relationship; wherein, the linear mapping relationship is: DutyR=DutyP / K+C; DutyR is the clock signal duty cycle, DutyP is the target pulse width modulation duty cycle, K is a mapping coefficient greater than 1, and C is a preset offset constant.

[0045] S103: Send firmware upgrade data to the first rotor via the data signal line of the serial communication bus so that the first rotor can perform firmware upgrade based on the firmware upgrade data.

[0046] Firmware upgrade data refers to new version code, configuration parameters, or verification information used to update the embedded program inside the first rotor. DAT is the physical line in the serial communication bus used to transmit data.

[0047] In this step, after the first rotor enters firmware upgrade mode, it activates its internal bootloader, which is responsible for receiving and processing data from the DAT line. The controller sends firmware upgrade data in frames according to a preset protocol via the DAT line, for example, in 128-byte data packets, each containing address information, payload, and checksum. After receiving the data, the first rotor first performs an integrity check. If the check passes, it writes the data to a designated area of ​​non-volatile memory. The entire process is performed while the first rotor is stopped to prevent program execution conflicts or write errors.

[0048] As can be seen, this step ensures the integrity and security of the upgrade process by using a dedicated DAT line to transmit firmware data; at the same time, since the speed regulation of the second rotor has been handled by the CLK line, the DAT line can be exclusively used by the first rotor, avoiding data packet loss or upgrade failure caused by multi-task contention.

[0049] As a possible implementation, it further includes: receiving the actual rotational speed fed back by the second rotor through the rotational speed feedback signal line; comparing the actual rotational speed with the target rotational speed; and adjusting the duty cycle of the clock signal according to the comparison result so that the actual rotational speed of the second rotor approaches the target rotational speed.

[0050] The speed feedback signal line is a dedicated signal line derived from the second rotor to report its current operating status to the controller. It typically outputs a periodic pulse signal (such as a TACH signal), the frequency of which is proportional to the actual rotor speed. The actual speed refers to the true rotational speed of the second rotor under the current driving conditions, which can be obtained by measuring the pulse frequency on the speed feedback signal line and converting it using the number of pole pairs.

[0051] In practical implementation, while outputting the speed regulation clock signal through the CLK (Clock Line), the controller continuously monitors the actual speed returned by the second rotor via the speed feedback signal line. The controller has an internal closed-loop adjustment module that compares the actual speed with the target speed, calculates the deviation, and dynamically adjusts the duty cycle of the clock signal output on the CLK line using proportional (P), proportional-integral (PI), or other control algorithms. For example, if the target speed is 6000 RPM, but the feedback shows an actual speed of only 5500 RPM, the controller appropriately increases the clock signal duty cycle to enhance the motor drive strength and increase the speed; conversely, it decreases the duty cycle to avoid overshoot.

[0052] As can be seen, this embodiment introduces closed-loop control based on actual speed feedback, which significantly improves the speed accuracy and anti-interference capability of the second rotor in clock signal speed regulation mode, ensuring that the heat dissipation performance always meets the system requirements.

[0053] As a possible implementation, it further includes: after the first rotor completes the firmware upgrade, sending a mode recovery command to the first rotor and the second rotor via a serial communication bus, so that the first rotor and the second rotor are restored to the serial communication control mode or the pulse width modulation mode.

[0054] The mode recovery command is a control command generated by the controller after the firmware upgrade process is completed and sent via the serial communication bus. It is used to instruct each rotor to exit the temporary operating state (such as firmware upgrade mode or clock signal speed control mode) and switch back to the normal operating mode. The normal operating mode can be either serial communication control mode or pulse width modulation mode, depending on the system configuration or user policy.

[0055] In practice, after the first rotor successfully completes firmware writing, verification, and restart, the controller confirms the upgrade is complete and then broadcasts a mode recovery command to both the first and second rotors via DAT. Upon receiving this command, the first rotor exits the firmware upgrade mode and reactivates the normal control logic; the second rotor exits the clock signal speed control mode and reverts to the original control method. If the system defaults to serial communication, it returns to the serial communication control mode; if the system is configured for traditional PWM control, it switches back to PWM mode and begins listening for external PWM signals.

[0056] As can be seen, this implementation method achieves complete closed-loop management of the upgrade process, ensuring that the system automatically recovers to the expected normal operating state after the firmware update is completed, avoiding control abnormalities or functional loss due to the rotor remaining in temporary mode, and improving the automation level and operational reliability of the system.

[0057] The fan control method provided in this application, under the premise that both the first rotor and the second rotor are in serial communication control mode, sends firmware upgrade commands to both rotors via the bus, causing the first rotor to enter firmware upgrade mode and stop rotating, while simultaneously causing the second rotor to switch to clock signal speed regulation mode and continue running. In this state, the controller can continuously send firmware upgrade data to the first rotor via the bus's data signal line to complete its firmware update; simultaneously, it can output a speed regulation clock signal to the second rotor via the same bus's clock signal line to adjust its speed. Since the firmware upgrade data and the speed regulation signal are transmitted independently via the data signal line and clock signal line respectively, they do not conflict with each other. Therefore, even if the first rotor occupies the data signal line for a long time during firmware upgrade, the controller can still regulate the speed of the second rotor in real time via the clock signal line. This parallel utilization of different physical lines in the serial communication bus allows firmware upgrade and speed regulation to be performed synchronously on the same bus, thereby ensuring the smooth completion of the upgrade operation while maintaining the effective heat dissipation capacity of the fan system.

[0058] Based on the above embodiments, as a preferred embodiment, it further includes: S1: While the first rotor is in firmware upgrade mode, monitor the system operating status and determine whether there are any preset critical events; The system operating status includes, but is not limited to, processor temperature, power supply voltage, internal airflow pressure of the chassis, or external alarm signals received by the management controller. Preset critical events refer to sudden situations that may jeopardize system stability, such as a processor temperature rising by more than 10°C within one second, a main power supply voltage dropping below a threshold, or a "high-temperature emergency cooling" command issued by the remote management module. The controller has a built-in event monitoring module that periodically samples sensor data or listens for system bus messages and matches them against a preset event rule base.

[0059] S2: If a critical event occurs, the speed regulation priority of the second rotor is increased, and a high-priority speed regulation clock signal is output to the second rotor through the clock signal line of the serial communication bus so that the second rotor can immediately increase its speed to the emergency speed level. Speed ​​regulation priority refers to the scheduling weight used by the controller when generating the CLK signal. In normal mode, the speed of the second rotor is slowly adjusted by the thermal management algorithm; while in high-priority mode, the controller ignores the original target speed and directly sets the CLK signal duty cycle to the maximum allowable value of the corresponding "emergency speed level". The high-priority speed regulation clock signal can be identified by specific encoding (such as continuous high-frequency pulses) or abrupt changes in duty cycle, and the second rotor will immediately accelerate after recognizing it.

[0060] S3: After the critical event is resolved, restore the original speed regulation strategy of the second rotor.

[0061] Critical event resolution refers to the system returning to a safe operating state (e.g., the temperature dropping below 80°C for 5 seconds) or receiving an event clearing command. The original speed control strategy refers to the closed-loop speed control logic based on temperature feedback or the preset speed curve that was being executed before the event occurred.

[0062] In this step, the controller continuously monitors the event status. Once the event is confirmed to be resolved, it stops outputting the high-priority CLK signal, resumes the target speed dynamically calculated based on the thermal load, and re-outputs the corresponding normal speed control clock signal through the CLK line. The second rotor then smoothly slows down to the normal operating range.

[0063] As can be seen, this embodiment, by introducing an event-driven dynamic priority speed adjustment mechanism, enables the system to maintain its proactive defense capability against sudden thermal events during the upgrade process. Since the existing CLK line is reused throughout the process, no new hardware is required or the upgrade data flow on the DAT line is interrupted, thus significantly improving system reliability without increasing costs.

[0064] This application discloses a fan control method, specifically: See Figure 4 A flowchart illustrating another fan control method according to an exemplary embodiment, such as... Figure 4 As shown, it includes: S201: In serial communication control mode, receive firmware upgrade instructions sent by the controller through the serial communication bus; The execution subject of this embodiment is one of the target rotors of the dual-rotor fan, namely one of the first rotor and the second rotor.

[0065] In this step, the communication interface module inside the rotor continuously listens for firmware upgrade commands on the DAT line.

[0066] As a feasible implementation, in the serial communication control mode, before receiving the firmware upgrade instruction sent by the controller through the serial communication bus, the method further includes: receiving the mode switching instruction sent by the controller to switch the control mode from pulse width modulation mode to serial communication control mode.

[0067] In practice, after initial power-on, the rotor operates in PWM mode by default, listening to the dedicated PWM input pin. When the controller needs to perform firmware upgrades or advanced management operations, it first sends a mode switching command via DAT. After receiving the command and verifying its validity, the rotor disables the sampling logic for the PWM pin, activates the serial communication interface module, and sets its own state to serial communication control mode, thereby gaining the ability to parse subsequent firmware upgrade commands.

[0068] S202: Enter firmware upgrade mode or clock signal speed adjustment mode according to the firmware upgrade instruction. In this step, after parsing the firmware upgrade command, the rotor further reads the mode indication field in the command. If the field indicates that the rotor is the upgrade target, it enters the firmware upgrade mode; if the field indicates that the rotor is not the upgrade target but needs to continue running, it switches to the clock signal speed control mode.

[0069] S203: In firmware upgrade mode, stop rotating, receive firmware upgrade data through the data signal line of the serial communication bus, and perform firmware upgrade based on the firmware upgrade data; In this step, once the rotor enters firmware upgrade mode, the power supply to the motor drive circuit is immediately cut off or the PWM output is disabled, causing the fan blades to stop rotating, ensuring that the firmware writing process is not disturbed by operation. Subsequently, the rotor activates its internal bootloader, which is responsible for receiving firmware upgrade data frame by frame from the controller via DAT. Each frame typically contains address information, payload, and a checksum. The rotor performs integrity verification on the received data; if the verification passes, it writes it to a designated area of ​​non-volatile memory; if the verification fails, it returns an error response to the controller, requesting retransmission.

[0070] S204: In clock signal speed control mode, it continues to run, receives the speed control clock signal through the clock signal line of the serial communication bus, and adjusts its own speed based on the speed control clock signal.

[0071] In this step, after the rotor enters the clock signal speed control mode, the motor continues to run, and the CLK monitoring module is activated. This module measures the signal characteristics on the CLK line in real time and adjusts the motor drive current or voltage accordingly to change the speed.

[0072] As a feasible implementation method, adjusting one's own rotational speed based on a speed regulation clock signal includes: mapping the clock signal duty cycle of the speed regulation clock signal to a target pulse width modulation duty cycle; determining the corresponding target rotational speed based on the target pulse width modulation duty cycle; and adjusting one's own rotational speed based on the target rotational speed.

[0073] In practical implementation, in clock signal speed control mode, the rotor measures the duty cycle of the CLK signal through an internal timer or edge detection circuit. Then, using a pre-stored mapping relationship, this duty cycle is converted into an equivalent target PWM duty cycle. Based on this duty cycle and the motor's own characteristics, the target speed is determined, and the drive circuit is adjusted to make the actual speed approach the target speed.

[0074] As a feasible implementation method, mapping the clock signal duty cycle of the speed-regulating clock signal to the target pulse width modulation duty cycle includes: mapping the clock signal duty cycle of the speed-regulating clock signal to the corresponding target pulse width modulation duty cycle according to a predefined linear inverse mapping relationship; wherein, the linear inverse mapping relationship is: DutyP=(DutyR-C)×K; DutyP is the target pulse width modulation duty cycle, DutyR is the clock signal duty cycle, K is a mapping coefficient greater than 1, and C is a preset offset constant.

[0075] As a feasible implementation method, the target rotational speed is determined based on the target pulse width modulation duty cycle, including: using the product of the target pulse width modulation duty cycle and the rated rotational speed of the target rotor itself as the target rotational speed.

[0076] As a feasible implementation method, it also includes: in clock signal speed regulation mode, feeding back its actual speed to the controller through a speed feedback signal line.

[0077] In practice, the rotor runs continuously in clock signal speed control mode and synchronously sends speed pulses to the controller via the TACH line.

[0078] As a possible implementation, it also includes: receiving a mode recovery command sent by the controller via a serial communication bus, and restoring to the serial communication control mode or pulse width modulation mode.

[0079] In practice, once the firmware upgrade process is complete, the controller sends a mode recovery command via the DAT line. Upon receiving this command, the rotor exits the temporary mode (such as firmware upgrade mode or clock signal speed control mode) and switches back to serial communication control mode or PWM mode according to the target mode field in the command. If switching to PWM mode, monitoring of the PWM input pin is re-enabled, and the serial communication interface is disabled to reduce power consumption.

[0080] Therefore, this embodiment, based on the physical structure characteristics of the serial communication bus, uses the data signal line (DAT) and the clock signal line (CLK) for different purposes: upon receiving a firmware upgrade command from the controller, each rotor in the dual-rotor fan autonomously enters a different operating mode according to its own role. The rotor targeted for upgrade stops rotating and receives firmware upgrade data via the DAT line to complete a safe and reliable program update; while the other rotor switches to clock signal speed control mode, continues to run, and parses the speed control clock signal via the CLK line to dynamically adjust its own speed. Since the tasks of the two rotors depend on independent signal lines in the bus, there is no resource contention between them, thus enabling parallel operation of firmware upgrade and real-time speed control on the same serial communication bus.

[0081] The following describes an application embodiment provided by this application, such as... Figure 5 As shown, firmware upgrades on the OUT rotor are taken as an example. The OUT rotor operates in I2C mode. Its two signal lines are used for I2C communication. The signal paths to the CLK and DAT interfaces of the fan controller's I2C module are continuous, while the signal paths to the PWM and TACH2 interfaces of the fan controller's timer module are disconnected (indicated by dashed lines). The signal selector DAT is connected to DAT2. The fan controller's I2C module transmits firmware data to the OUT rotor via the clock signal CLK_R and the data signal DAT2. The motor does not operate during the firmware upgrade process, therefore, OUT rotor speed control is unnecessary.

[0082] Because the front and rear rotors of the dual-rotor fan share the PWM (CLK) signal line, the CLK_R clock signal from the fan controller's I2C module is also sent to the IN rotor. However, the IN rotor operates in a special PWM speed control mode (called CLK-PWM speed control mode). The difference between this mode and the traditional PWM mode is that the signal path from the IN rotor to the PWM interface of the fan controller's timer module is open (indicated by a dashed line). The speed control of the IN rotor is based on the duty cycle of the CLK_R clock signal, not the PWM signal from the timer module. The signal path from the IN rotor to the TACH1 interface of the fan controller's timer module is active, while the signal path to the DAT interface of the fan controller's I2C module is open (indicated by a dashed line). The speed measurement of the IN rotor is still performed by the timer module.

[0083] In summary, when the fan controller performs a firmware upgrade on one of the rotors of the dual-rotor fan, the other rotor (the working rotor) operates in CLK-PWM speed control mode. The fan speed control unit controls the duty cycle of the CLK_R signal generated by the I2C module to regulate the target speed of the working rotor, and obtains the actual speed of the working rotor by measuring the TACH signal through the timer module.

[0084] In traditional PWM mode, the duty cycle of the PWM signal generated by the fan controller's timer module ranges from 0% to 100%, corresponding to a target fan speed that is 0% to 100% of the rated speed. That is, the target speed duty cycle is: DutyP = SpeedInRef / SpeedInMax = SpeedOutRef / SpeedOutMax; where SpeedInRef and SpeedOutRef are the target speeds of the IN and OUT rotors, respectively, and SpeedInMax and SpeedOutMax are the rated speeds of the IN and OUT rotors, respectively.

[0085] The waveform of the clock signal CLK_R generated by the fan controller I2C module in CLK-PWM speed control mode is as follows: Figure 6As shown. The period Tr of the CLK_R signal is determined by the rate of I2C communication between the OUT rotor and the IN rotor. The duty cycle of the CLK_R signal is used to transmit the target speed information to the IN rotor. Considering the requirements of I2C communication on the duty cycle of the clock signal, in order to avoid I2C communication abnormalities caused by the duty cycle of the CLK_R signal being too large or too small, it is necessary to limit the range of variation of the duty cycle of the CLK_R signal. Taking [30%, 50%] as an example, the duty cycle of the CLK_R signal is defined as: DutyR = DutyP / 5 + 30%. Therefore, the high-level time of the CLK_R signal is: TRH = DutyR Tr. Figure 6 The diagram illustrates the process of the target rotational speed duty cycle changing from DutyP1 to DutyP2, corresponding to the CLK_R signal duty cycle changing from DutyR1 to DutyR2, and the high-level time changing from Trh1=DutyR1. Tr becomes Trh2=DutyR2 Tr.

[0086] like Figure 7 The flowchart shown illustrates the hybrid fan control method for controlling a dual-rotor fan, taking firmware upgrade of the OUT rotor as an example. The fan controller first switches the control modes of both the IN and OUT rotors to I2C mode. The fan controller then sends a firmware upgrade command to the OUT rotor via the I2C module. Upon receiving the command, the OUT rotor enters firmware upgrade mode, while the IN rotor enters CLK-PWM speed control mode.

[0087] During the OUT rotor firmware upgrade process, the fan controller sends firmware data to the OUT rotor via the I2C module. The fan controller's speed control unit sets the target speed of the IN rotor according to the system's cooling requirements and adjusts the duty cycle (DutyR) of the I2C module's clock signal CLK_R. The IN rotor measures the CLK_R signal to obtain the duty cycle (DutyR), calculates the target speed duty cycle (DutyP), obtains the target speed of the IN rotor, controls the IN rotor's speed, and feeds back the actual speed (TACH1) to the fan controller. The fan controller uses a timer module to measure the TACH1 frequency to obtain the actual speed of the IN rotor.

[0088] The following describes a fan control device provided in an embodiment of this application. The fan control device described below and the fan control method on the controller side described above can be referred to each other.

[0089] See Figure 8 A structural diagram of a fan control device according to an exemplary embodiment is shown, as follows: Figure 8 As shown, it includes: The first mode switching module 801 is used to send firmware upgrade commands to the first rotor and the second rotor respectively via a serial communication bus when both the first rotor and the second rotor of the dual rotor fan are in serial communication control mode, so that the first rotor enters firmware upgrade mode and stops rotating, and the second rotor enters clock signal speed regulation mode and continues to run. The first adjustment module 802 is used to output a speed adjustment clock signal to the second rotor through the clock signal line of the serial communication bus during the firmware upgrade mode of the first rotor, so as to adjust the speed of the second rotor. The first upgrade module 803 is used to send firmware upgrade data to the first rotor through the data signal line of the serial communication bus, so that the first rotor can perform firmware upgrade based on the firmware upgrade data.

[0090] The fan control device provided in this application embodiment, under the premise that both the first rotor and the second rotor are in serial communication control mode, the controller sends firmware upgrade commands to both rotors through the bus, causing the first rotor to enter firmware upgrade mode and stop rotating, while simultaneously causing the second rotor to switch to clock signal speed regulation mode and continue running. In this state, the controller can continuously send firmware upgrade data to the first rotor through the bus data signal line to complete its firmware update; on the other hand, it can simultaneously output a speed regulation clock signal to the second rotor through the clock signal line of the same bus to regulate its speed. Since the firmware upgrade data and the speed regulation signal are transmitted independently through the data signal line and the clock signal line respectively, they do not conflict with each other. Therefore, even if the first rotor occupies the data signal line for a long time during the firmware upgrade process, the controller can still regulate the speed of the second rotor in real time through the clock signal line. This parallel utilization of different physical lines in the serial communication bus allows firmware upgrade and speed regulation to be performed synchronously on the same bus, thereby ensuring the smooth completion of the upgrade operation while maintaining the effective heat dissipation capacity of the fan system.

[0091] Based on the above embodiments, as a preferred embodiment, the first adjustment module 802 includes: The first conversion unit is used to determine the target speed of the second rotor and convert the target speed into the corresponding target pulse width modulation duty cycle. The first mapping unit is used to map the target pulse width modulation duty cycle to a clock signal duty cycle within a preset range; The output unit is used to generate a speed regulation clock signal based on the clock signal duty cycle and output it to the second rotor through the clock signal line of the serial communication bus, so that the second rotor can deduce the target pulse width modulation duty cycle according to the received clock signal duty cycle and adjust its own speed based on the target pulse width modulation duty cycle.

[0092] Based on the above embodiments, as a preferred implementation, the first conversion unit is specifically used to: use the ratio of the target rotational speed to the rated rotational speed of the second rotor as the target pulse width modulation duty cycle.

[0093] Based on the above embodiments, as a preferred implementation, the first mapping unit is specifically used to: map the target pulse width modulation duty cycle to the corresponding clock signal duty cycle according to a predefined linear mapping relationship; The linear mapping relationship is: DutyR = DutyP / K + C; DutyR is the clock signal duty cycle, DutyP is the target pulse width modulation duty cycle, K is a mapping coefficient greater than 1, and C is a preset offset constant.

[0094] Based on the above embodiments, as a preferred embodiment, it further includes: The second receiving module is used to receive the actual rotational speed fed back by the second rotor through the rotational speed feedback signal line; The comparison module is used to compare the actual rotational speed with the target rotational speed and adjust the clock signal duty cycle according to the comparison result so that the actual rotational speed of the second rotor approaches the target rotational speed.

[0095] Based on the above embodiments, as a preferred embodiment, it further includes: The third mode switching module is used to send mode switching commands to the first and second rotors of the dual-rotor fan to switch the control mode of the first and second rotors from pulse width modulation mode to serial communication control mode.

[0096] Based on the above embodiments, as a preferred embodiment, it further includes: The first mode recovery module is used to send mode recovery commands to the first rotor and the second rotor via a serial communication bus after the first rotor completes the firmware upgrade, so that the first rotor and the second rotor can be restored to the serial communication control mode or the pulse width modulation mode.

[0097] The following describes a fan control device provided in an embodiment of this application. The fan control device described below and the fan control method for the dual-rotor fan side described above can be referred to each other.

[0098] See Figure 9 A structural diagram of a fan control device according to an exemplary embodiment is shown, as follows: Figure 9 As shown, it includes: The first receiving module 901 is used to receive firmware upgrade instructions sent by the controller through the serial communication bus in the serial communication control mode. The second mode switching module 902 is used to enter the firmware upgrade mode or the clock signal speed regulation mode according to the firmware upgrade instruction or its own rotor identifier. The second upgrade module 903 is used to stop rotation in firmware upgrade mode, receive firmware upgrade data through the data signal line of the serial communication bus, and perform firmware upgrade based on the firmware upgrade data. The second adjustment module 904 is used to continue operating in clock signal speed regulation mode, receive speed regulation clock signal through the clock signal line of the serial communication bus, and adjust its own speed based on the speed regulation clock signal.

[0099] Therefore, this embodiment, based on the physical structure characteristics of the serial communication bus, uses the data signal line (DAT) and the clock signal line (CLK) for different purposes: upon receiving a firmware upgrade command from the controller, each rotor in the dual-rotor fan autonomously enters a different operating mode according to its own role. The rotor targeted for upgrade stops rotating and receives firmware upgrade data via the DAT line to complete a safe and reliable program update; while the other rotor switches to clock signal speed control mode, continues to run, and parses the speed control clock signal via the CLK line to dynamically adjust its own speed. Since the tasks of the two rotors depend on independent signal lines in the bus, there is no resource contention between them, thus enabling parallel operation of firmware upgrade and real-time speed control on the same serial communication bus.

[0100] Based on the above embodiments, as a preferred embodiment, the second adjustment module 904 includes: The second mapping unit is used to map the clock signal duty cycle of the speed regulation clock signal to the target pulse width modulation duty cycle. The adjustment unit is used to determine the corresponding target rotational speed based on the target pulse width modulation duty cycle, and adjust its own rotational speed based on the target rotational speed.

[0101] Based on the above embodiments, as a preferred implementation, the second mapping unit is specifically used to: map the clock signal duty cycle of the speed regulation clock signal to the corresponding target pulse width modulation duty cycle according to a predefined linear inverse mapping relationship; The linear inverse mapping relationship is: DutyP=(DutyR-C)×K; DutyP is the target pulse width modulation duty cycle, DutyR is the clock signal duty cycle, K is a mapping coefficient greater than 1, and C is a preset offset constant.

[0102] Based on the above embodiments, as a preferred implementation, the adjustment unit is specifically used to: take the product of the target pulse width modulation duty cycle and the rated speed of the target rotor itself as the target speed.

[0103] Based on the above embodiments, as a preferred embodiment, it further includes: The feedback module is used to feed back its actual speed to the controller via a speed feedback signal line in clock signal speed control mode.

[0104] Based on the above embodiments, as a preferred embodiment, it further includes: The fourth mode switching module is used to receive mode switching instructions sent by the controller to switch the control mode from pulse width modulation mode to serial communication control mode.

[0105] Based on the above embodiments, as a preferred embodiment, it further includes: The second mode recovery module is used to receive the mode recovery command sent by the controller through the serial communication bus and restore to the serial communication control mode or pulse width modulation mode.

[0106] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0107] Embodiments of this application also provide an electronic device, including a controller and / or a dual-rotor fan. The internal structure of the controller and the dual-rotor fan is as follows: Figure 10 As shown, it includes: Communication interface 1 enables information exchange with other devices, such as network devices; Processor 2 is connected to communication interface 1 to enable information exchange with other devices and, when running a computer program, executes the fan control method provided by one or more of the above-mentioned technical solutions. The computer program is stored on memory 3.

[0108] Of course, in practical applications, the various components in an electronic device are coupled together through bus system 4. It can be understood that bus system 4 is used to achieve communication and connection between these components. In addition to the data bus, bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 10 The general will label all buses as Bus System 4.

[0109] The memory 3 in this embodiment is used to store various types of data to support the operation of the electronic device. Examples of such data include any computer program used to operate on the electronic device.

[0110] It is understood that memory 3 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 3 described in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0111] The methods disclosed in the embodiments of this application can be applied to processor 2, or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 2 or by instructions in the form of software. The processor 2 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the aforementioned method in combination with its hardware.

[0112] When processor 2 executes the program, it implements the corresponding processes in the various methods of the embodiments of this application. For the sake of brevity, these will not be described in detail here.

[0113] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described fan control method embodiments when it is run.

[0114] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0115] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by processor 2, implements the steps in any of the above-described fan control method embodiments.

[0116] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by processor 2, implements the steps in any of the above-described fan control method embodiments.

[0117] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0118] The foregoing has provided a detailed description of a fan control system, method, apparatus, device, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A fan control method, characterized in that, Applied to a controller, the method includes: When both the first and second rotors of the dual-rotor fan are in serial communication control mode, firmware upgrade commands are sent to the first and second rotors respectively via the serial communication bus, so that the first rotor enters firmware upgrade mode and stops rotating, and the second rotor enters clock signal speed regulation mode and continues to run. During the firmware upgrade mode of the first rotor, a speed regulation clock signal is output to the second rotor through the clock signal line of the serial communication bus to regulate the speed of the second rotor. Firmware upgrade data is sent to the first rotor via the data signal line of the serial communication bus so that the first rotor can perform firmware upgrade based on the firmware upgrade data.

2. The fan control method according to claim 1, characterized in that, Outputting a speed-regulating clock signal to the second rotor via the clock signal line of the serial communication bus to adjust the speed of the second rotor includes: Determine the target rotational speed of the second rotor and convert the target rotational speed into a corresponding target pulse width modulation duty cycle; The target pulse width modulation duty cycle is mapped to a clock signal duty cycle within a preset range; A speed-regulating clock signal is generated based on the clock signal duty cycle and output to the second rotor through the clock signal line of the serial communication bus, so that the second rotor can deduce the target pulse width modulation duty cycle based on the received clock signal duty cycle and adjust its own speed based on the target pulse width modulation duty cycle.

3. The fan control method according to claim 2, characterized in that, Converting the target rotational speed into the corresponding target pulse width modulation duty cycle includes: The ratio of the target rotational speed to the rated rotational speed of the second rotor is used as the target pulse width modulation duty cycle.

4. The fan control method according to claim 2, characterized in that, Mapping the target pulse width modulation duty cycle to a clock signal duty cycle within a preset range includes: Based on a predefined linear mapping relationship, the target pulse width modulation duty cycle is mapped to the corresponding clock signal duty cycle; Wherein, the linear mapping relationship is: DutyR=DutyP / K+C; DutyR is the clock signal duty cycle, DutyP is the target pulse width modulation duty cycle, K is a mapping coefficient greater than 1, and C is a preset offset constant.

5. The fan control method according to claim 2, characterized in that, Also includes: Receive the actual rotational speed fed back by the second rotor through the rotational speed feedback signal line; The actual rotational speed is compared with the target rotational speed, and the duty cycle of the clock signal is adjusted according to the comparison result so that the actual rotational speed of the second rotor approaches the target rotational speed.

6. The fan control method according to claim 1, characterized in that, Before sending firmware upgrade commands to the first rotor and the second rotor via the serial communication bus, the process also includes: A mode switching command is sent to the first and second rotors of the dual-rotor fan to switch the control mode of the first and second rotors from pulse width modulation mode to serial communication control mode.

7. The fan control method according to claim 1, characterized in that, Also includes: After the first rotor completes the firmware upgrade, a mode recovery command is sent to the first rotor and the second rotor through the serial communication bus to restore the first rotor and the second rotor to the serial communication control mode or the pulse width modulation mode.

8. A fan control method, characterized in that, The method, applied to one of the target rotors of a dual-rotor fan, includes: In serial communication control mode, the receiver receives firmware upgrade commands sent by the controller via the serial communication bus; Enter firmware upgrade mode or clock signal speed adjustment mode according to the firmware upgrade instruction; In the firmware upgrade mode, rotation stops, firmware upgrade data is received via the data signal line of the serial communication bus, and firmware upgrade is performed based on the firmware upgrade data. In the clock signal speed control mode, it continues to operate, receives the speed control clock signal through the clock signal line of the serial communication bus, and adjusts its own speed based on the speed control clock signal.

9. The fan control method according to claim 8, characterized in that, Adjusting its own rotational speed based on the speed-regulating clock signal includes: The clock signal duty cycle of the speed regulation clock signal is mapped to the target pulse width modulation duty cycle; The target rotational speed is determined based on the target pulse width modulation duty cycle, and the rotational speed is adjusted based on the target rotational speed.

10. The fan control method according to claim 9, characterized in that, Mapping the clock signal duty cycle of the speed-regulating clock signal to the target pulse width modulation duty cycle includes: According to a predefined linear inverse mapping relationship, the clock signal duty cycle of the speed regulation clock signal is mapped to the corresponding target pulse width modulation duty cycle; Wherein, the linear inverse mapping relationship is: DutyP=(DutyR-C)×K; DutyP is the target pulse width modulation duty cycle, DutyR is the clock signal duty cycle, K is a mapping coefficient greater than 1, and C is a preset offset constant.

11. The fan control method according to claim 9, characterized in that, Determining the corresponding target rotational speed based on the target pulse width modulation duty cycle includes: The target speed is the product of the target pulse width modulation duty cycle and the rated speed of the target rotor itself.

12. The fan control method according to claim 8, characterized in that, Also includes: In the clock signal speed control mode, the actual speed is fed back to the controller via the speed feedback signal line.

13. The fan control method according to claim 8, characterized in that, In serial communication control mode, before receiving the firmware upgrade command sent by the controller via the serial communication bus, the following steps are also included: The controller receives a mode switching command to switch the control mode from pulse width modulation mode to serial communication control mode.

14. The fan control method according to claim 8, characterized in that, Also includes: The controller receives a mode recovery command sent via the serial communication bus and restores the mode to either serial communication control mode or pulse width modulation mode.

15. A fan control device, characterized in that, Applied to a controller, the device includes: The first mode switching module is used to send firmware upgrade commands to the first rotor and the second rotor respectively via a serial communication bus when both the first rotor and the second rotor of the dual rotor fan are in serial communication control mode, so that the first rotor enters firmware upgrade mode and stops rotating, and the second rotor enters clock signal speed regulation mode and continues to run. The first adjustment module is used to output a speed adjustment clock signal to the second rotor through the clock signal line of the serial communication bus during the firmware upgrade mode of the first rotor, so as to adjust the speed of the second rotor. The first upgrade module is used to send firmware upgrade data to the first rotor through the data signal line of the serial communication bus, so that the first rotor can perform firmware upgrade based on the firmware upgrade data.

16. A fan control device, characterized in that, The device, applied to one of the target rotors of a dual-rotor fan, includes: The first receiving module is used to receive firmware upgrade instructions sent by the controller through the serial communication bus in the serial communication control mode. The second mode switching module is used to enter the firmware upgrade mode or the clock signal speed regulation mode according to the firmware upgrade instruction or its own rotor identifier. The second upgrade module is used to stop rotation in the firmware upgrade mode, receive firmware upgrade data through the data signal line of the serial communication bus, and perform firmware upgrade based on the firmware upgrade data. The second adjustment module is used to continue operating in the clock signal speed regulation mode, receive the speed regulation clock signal through the clock signal line of the serial communication bus, and adjust its own speed based on the speed regulation clock signal.

17. A controller, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the fan control method as described in any one of claims 1 to 7.

18. A dual-rotor fan, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the fan control method as described in any one of claims 8 to 14.

19. A computer program product, characterized in that, Includes a computer program, which, when executed, implements the steps of the fan control method as described in any one of claims 1 to 14.

20. An electronic device, characterized in that, Includes the controller as described in claim 17 and / or the dual-rotor fan as described in claim 18.

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