A dimming mode detection circuit and a lighting system

Abstract

The application provides a dimming mode detection circuit and a lighting system, comprising a voltage detection module, a current detection module and a mode judgment module. The voltage detection module collects the bus voltage output by the thyristor dimmer to generate a first detection signal representing the voltage edge feature; the current detection module collects the bleeder current flowing through the bleeder current module to generate a second detection signal representing the duration feature that the bleeder current is lower than the preset current threshold; the mode judgment module outputs a mode judgment signal according to the first detection signal and the second detection signal to control the working state of the bleeder current module and the output driving strategy of the LED constant current driving module. By jointly analyzing the voltage signal and the current signal, the misjudgment caused by the power grid noise when simply relying on voltage detection is effectively avoided, the accuracy and anti-interference ability of dimming mode recognition are significantly improved, and thus the subsequent circuit can reliably and efficiently work under various power grid environments.

Description

Technical Field

[0001] This application relates to the field of lighting control technology, and more specifically, to a dimming mode detection circuit and a lighting system. Background Technology

[0002] LED lighting has been widely used to replace traditional incandescent and fluorescent lamps due to its high efficiency and energy saving. In LED lighting systems compatible with SCR dimmers, common dimming modes include leading-edge (or front-edge) dimming, trailing-edge (or rear-edge) dimming, and no dimming. Since SCR dimmers require a certain holding current to maintain conduction, such systems typically have a bleed current module. After the dimmer is turned on, if the main circuit current is insufficient, the bleed current circuit provides additional current to maintain the SCR's conduction. Different dimming modes correspond to different bleed current requirements; therefore, accurate and reliable detection of the current dimming mode is crucial.

[0003] In existing technologies, common dimming mode detection methods mainly rely on detecting the bus voltage waveform, such as determining the dimming mode by detecting the presence of continuous fast rising and falling edges in the bus voltage. However, in environments with unstable grid voltage, distortion, or noise (such as voltage spikes caused by low load power factor), this detection method relying solely on voltage signals is prone to misjudgment. For example, voltage noise in the absence of dimming mode may be misidentified as a dimming signal; and when the follow-up dimmer is switched off at a large conduction angle, the voltage falling edge slope is small, which may prevent the detection of fast falling edges, thus misjudging it as the absence of dimming mode, leading to errors in subsequent discharge current control and affecting the normal operation and dimming performance of the system. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a dimming mode detection circuit and a lighting system to overcome the problems in the prior art.

[0005] In a first aspect, embodiments of this application provide a dimming mode detection circuit for controlling the dimming mode of an LED lighting circuit; including: The voltage detection module is used to acquire the bus voltage output by the thyristor dimmer and generate a first detection signal that characterizes the voltage edge features. The current detection module is used to collect the discharge current flowing through the discharge current module and generate a second detection signal to characterize whether dimming behavior is performed. The mode determination module is used to output a mode determination signal based on the first detection signal and the second detection signal, so as to control the working state of the discharge current module and the output driving strategy of the LED constant current drive module.

[0006] In some technical solutions of this application, the dimming mode detection circuit further includes: The detection cycle counting module is used to count the cycles of the AC power supply and output a detection end signal; The mode determination module is used to output the mode determination signal based on the first detection signal and the second detection signal at the time of reception when the detection end signal is received.

[0007] In some technical solutions of this application, the above-mentioned mode determination module is used to output a pre-cut dimming mode signal when both the first detection signal and the second detection signal are valid; When the first detection signal is invalid and the second detection signal is valid, the back-cut dimming mode signal is output; When the second detection signal is invalid, a no-dimming mode signal is output.

[0008] In some technical solutions of this application, the voltage detection module includes: The first comparison module is used to compare the bus voltage with a preset first voltage threshold and output a first enable signal; The rising edge detection module is used to detect the fast rising edge of the bus voltage during the first enabling period corresponding to the first enabling signal, and output a pulse signal when the fast rising edge is detected. The first detection count determination module is used to perform continuous statistics on the pulse signal and output the corresponding first detection signal based on the first statistical result.

[0009] In some technical solutions of this application, the aforementioned current detection module includes: The second comparison module is used to compare the sampled voltage, which characterizes the magnitude of the discharge current, and the second voltage threshold, and outputs a second enable signal; The third comparison module is used to compare the bus voltage with the third voltage threshold and output a third enable signal; The time comparison module is used to time the duration during which the discharge current is lower than a preset current threshold during the target enable period when the second enable signal and the third enable signal are simultaneously valid. The second detection count determination module is used to perform continuous statistics on the timing results and output the corresponding second detection signal based on the second statistical results.

[0010] In some technical solutions of this application, the aforementioned time comparison module is used to perform timing based on a reference clock signal to measure the duration during which the discharge current is lower than a preset current threshold. The duration is compared with a preset time threshold, and a valid duration determination signal is output when the duration exceeds the preset time threshold. The second detection count determination module is used to perform continuous statistics on the duration determination signal. When a valid duration determination signal is received within a consecutive preset number of AC half-wave cycles, the second detection signal is set to a valid state.

[0011] In some technical solutions of this application, the first comparison module mentioned above includes a first comparator; The rising edge detection module includes an RC filter circuit and an edge detection comparator; The first detection count determination module includes a first counter and a first latch.

[0012] In some technical solutions of this application, the second comparison module includes a second comparator; The third comparison module includes a third comparator; The time comparison module includes a first digital timer and a fifth comparator; The second detection count determination module includes a second counter and a second latch.

[0013] In some technical solutions of this application, the dimming mode detection circuit further includes a sampling resistor connected in series in the discharge circuit, wherein the sampling voltage is the voltage drop across the sampling resistor.

[0014] Secondly, embodiments of this application provide a lighting system, including: a silicon controlled rectifier dimmer, a current discharge module, an LED constant current drive module; and a dimming mode detection circuit as described in any one of the above.

[0015] The technical solutions provided by the embodiments of this application may include the following beneficial effects: This application provides a dimming mode detection circuit for controlling the dimming mode of an LED lighting circuit; it includes: a voltage detection module for acquiring the bus voltage output by a silicon controlled rectifier (SCR) dimmer and generating a first detection signal characterizing the voltage edge characteristics; a current detection module for acquiring the discharge current flowing through a discharge current module and generating a second detection signal characterizing whether dimming behavior is performed; and a mode judgment module for outputting a mode judgment signal based on the first detection signal and the second detection signal, so as to control the operating state of the discharge current module and the output driving strategy of the LED constant current drive module.

[0016] This application determines the operating mode of the thyristor dimmer by simultaneously acquiring the bus voltage and the discharge current, and based on the joint logic judgment of the two. Since the discharge current signal is not easily affected by noise interference such as glitches and distortions in the grid voltage, it can effectively overcome the problem of false triggering or missed detection caused by abnormal voltage signals when the grid environment is unstable, and significantly improve the accuracy and reliability of mode detection.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a dimming mode detection circuit provided in an embodiment of this application is shown; Figure 2 This illustration shows a schematic diagram of a pre-cut dimmer detection waveform provided in an embodiment of this application; Figure 3 This illustration shows a schematic diagram of a post-cut dimmer detection waveform provided in an embodiment of this application; Figure 4 A schematic diagram of a Lead mode implementation provided in an embodiment of this application is shown; Figure 5 This illustration shows a schematic diagram of a Trail mode implementation provided in an embodiment of this application; Figure 6 This illustration shows a schematic diagram of a time comparison module provided in an embodiment of this application; Figure 7 A schematic diagram of another dimming mode detection circuit provided in an embodiment of this application is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0021] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0023] LED lighting has been widely used to replace traditional incandescent and fluorescent lamps due to its high efficiency and energy saving. In LED lighting systems compatible with SCR dimmers, common dimming modes include leading-edge (or front-edge) dimming, trailing-edge (or rear-edge) dimming, and no dimming. Since SCR dimmers require a certain holding current to maintain conduction, such systems typically have a bleed current module. After the dimmer is turned on, if the main circuit current is insufficient, the bleed current circuit provides additional current to maintain the SCR's conduction. Different dimming modes correspond to different bleed current requirements; therefore, accurate and reliable detection of the current dimming mode is crucial.

[0024] In existing technologies, common dimming mode detection methods mainly rely on detecting the bus voltage waveform, such as determining the dimming mode by detecting the presence of continuous fast rising and falling edges in the bus voltage. However, in environments with unstable grid voltage, distortion, or noise (such as voltage spikes caused by low load power factor), this detection method relying solely on voltage signals is prone to misjudgment. For example, voltage noise in the absence of dimming mode may be misidentified as a dimming signal; and when the follow-up dimmer is switched off at a large conduction angle, the voltage falling edge slope is small, which may prevent the detection of fast falling edges, thus misjudging it as the absence of dimming mode, leading to errors in subsequent discharge current control and affecting the normal operation and dimming performance of the system.

[0025] Based on this, this application provides a dimming mode detection circuit and a lighting system, which are described below through embodiments. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] like Figure 1As shown in the illustration, this application provides a dimming mode detection circuit, mainly used to control the dimming mode of LED lighting circuits, and is particularly suitable for LED lighting systems (including a SCR dimmer, a discharge current module, and an LED constant current drive module) that work in conjunction with a SCR dimmer. In practical applications, the SCR dimmer achieves dimming by phase chopping the AC input voltage. Depending on the position of the chopping, it is mainly divided into leading-edge dimming mode (also known as front-edge dimming) and trailing-edge dimming mode (also known as rear-edge dimming). In addition, there is also a no-dimming mode without a dimmer connected. Different dimming modes have different requirements on the system's operating state, especially on the discharge current required to maintain the normal conduction of the SCR. Therefore, accurately and reliably identifying the current dimming mode is the key to achieving good dimming performance and stable system operation.

[0027] The dimming mode detection circuit in this embodiment differs from traditional circuits that rely solely on the analysis of the bus voltage waveform (e.g., detecting the rapid rising or falling edge of the voltage). Instead, it introduces synchronous detection and analysis of the discharge current signal based on the analysis of the bus voltage (VBUS), and performs joint logical judgment on the detection results of the two signals, thereby greatly improving the anti-interference capability and accuracy of pattern recognition.

[0028] Specifically, the dimming mode detection circuit comprises several main functional parts: a voltage detection module, a current detection module, and a mode determination module. The voltage detection module is responsible for acquiring the bus voltage signal after being chopped by the SCR dimmer, and its purpose is to extract features from this voltage signal that can characterize the presence of a fast voltage rise edge.

[0029] The current detection module is responsible for acquiring the discharge current signal flowing through the discharge current module. The function of the discharge current module is to provide an additional current path when the main power circuit current is insufficient to keep the thyristor conducting. The key feature of the current detection module is analyzing the duration characteristics of the discharge current below a certain preset threshold, which is closely related to the dimmer's operating characteristics.

[0030] The mode determination module is the decision-making center of the entire circuit. It receives a first detection signal from the voltage detection module (which characterizes the validity of the voltage edge characteristics) and a second detection signal from the current detection module (which characterizes whether dimming behavior is performed and is related to the validity of the low-level duration characteristic of the discharge current). Based on different combinations of these two signals, the mode determination module can accurately determine whether the system is currently in a pre-dim dimming mode, a post-dim dimming mode, or a no-dim mode, and outputs the corresponding mode determination signal.

[0031] Specifically, the system judges and outputs the following preset logic: When the first detection signal is confirmed as valid (e.g., high level) and the second detection signal is also confirmed as valid, the mode judgment module determines that the system is operating in the pre-cut dimming mode. In this mode, the SCR dimmer is chopped at the beginning of the AC half-wave, causing the bus voltage to have a rapid rising edge at the beginning of each half-wave (captured by the voltage detection module). At the same time, in order to maintain the SCR's conduction at a relatively small conduction angle, the bleed current module provides bleed current for a specific period of time, and its current waveform will exhibit a characteristic duration below a threshold (captured by the current detection module). Both characteristics are present simultaneously, so the corresponding pre-cut dimming mode signal is output.

[0032] When the first detection signal is confirmed as invalid (e.g., low level), but the second detection signal is confirmed as valid, the mode determination module determines that the system is operating in the back-cut dimming mode. In this mode, the SCR dimmer is chopped at the end of the AC half-wave, so the leading edge of the bus voltage waveform is a natural, slow AC rising edge, without any abnormal "fast rising edge" (hence the first detection signal is invalid). However, the back-cut dimming mechanism causes the discharge current to be below a threshold after the SCR is turned off until the next half-wave's natural zero-crossing point, and the duration of this low current state is very distinct and stable (hence the second detection signal is valid). Therefore, the back-cut mode can be accurately identified and the corresponding back-cut dimming mode signal can be output based solely on the validity of the second detection signal.

[0033] When the second detection signal is confirmed to be invalid (either the first detection signal is valid or invalid), the mode determination module determines that the system is in a no-dimming mode. This means that no SCR dimmer is connected. At this time, the bus voltage is a complete sine wave without any abnormal fast edges; the bleed current module may not need to operate, and the aforementioned low current duration characteristic cannot be met. Since neither characteristic appears, a no-dimming mode signal is output.

[0034] This final judgment signal is used to simultaneously control two key subsequent execution units: first, to control the discharge current module to switch to the optimal operating state that matches the currently identified dimming mode, in order to optimize efficiency and reliability; and second, to guide the LED constant current drive module to adjust its output drive strategy, thereby achieving precise and stable control of the LED light source brightness.

[0035] In an optional implementation, to further ensure the stability and reliability of the detection results and avoid misjudgments due to occasional power grid noise or interference, the dimming mode detection circuit may also include a detection cycle counting module. This module counts the cycles of the AC power supply and outputs a detection end signal (DET_END) after completing a pre-set second number of consecutive detection cycles. The mode determination module, upon receiving this detection end signal, makes a final, locked mode determination based on the now stable states of the first and second detection signals and outputs the result. This design ensures that the determination is based on a continuous and reliable set of observation data, rather than a momentary fluctuation.

[0036] In practical implementation, the detection cycle counting module can specifically include a second digital counter and its related control logic. The clock input of this second digital counter can be connected to a shaped signal that reflects the zero-crossing or periodic characteristics of the AC power supply, for example, to a clock signal obtained by processing the bus voltage signal, which generates one pulse per AC half-wave. Whenever a new AC half-wave cycle is detected, the counter increments. Its count value is compared with a preset second quantity stored in a register or set by circuit parameters. When the count value reaches this second quantity, the overflow / final value output of the second counter triggers a valid detection end signal and typically resets the counter to prepare for the next detection cycle. The specific value of the second quantity can be set according to the system's trade-off between detection speed and reliability; for example, it can be set to 8, 16, or 32 consecutive AC half-wave cycles.

[0037] In an alternative implementation, such as Figure 4 As shown, the voltage detection module can be further divided into three cooperating sub-modules: a first comparison module, a rising edge detection module, and a first detection count determination module. These three sub-modules are connected in sequence to jointly complete the task of extracting and confirming the stable voltage edge characteristics from the original bus voltage signal.

[0038] The core component of the first comparison module can be a voltage comparator. This module continuously monitors the bus voltage output by the SCR dimmer and compares it with a pre-set first voltage threshold. This first voltage threshold has a specific purpose: it needs to be higher than the unstable noise amplitude that may occur near the zero-crossing point of the grid voltage and in the low-voltage region. When the bus voltage is below this threshold, the first comparison module outputs an invalid first enable signal (represented by COMP1), which is equivalent to shutting down subsequent detection channels, thereby actively shielding the voltage waveform from distortion and interference that may exist in the low-amplitude region, preventing malfunctions. Only when the bus voltage rises and exceeds the first voltage threshold does the first comparison module output a valid first enable signal. This valid signal defines a first enable period, indicating that the bus voltage has entered a relatively stable and clean safe region, allowing for precise fast rising edge searching within this time window.

[0039] The rising edge detection module (output denoted by Vpluse) is activated only during the first enable period. Its task is to capture abnormally high rising edges in the bus voltage, a typical characteristic when the pre-cut dimmer is turned on. For example, an RC filter circuit is used in conjunction with a voltage comparator (fourth comparator). The RC circuit delays the input bus voltage, while the fourth comparator simultaneously receives both the original bus voltage and the voltage after the RC delay. During normal AC voltage rising edges or slow changes, the voltage difference before and after the RC circuit is small, and the fourth comparator output remains constant. However, when the pre-cut dimmer suddenly turns on, causing a rapid rising edge in the bus voltage that is much faster than the RC circuit's time constant, the undelayed voltage will momentarily be much higher than the delayed voltage, resulting in a significant voltage difference across the comparator. This causes its output state to flip, generating a clear pulse signal. This pulse signal is the characteristic of detecting a single rapid rising edge.

[0040] The first detection count determination module receives pulse signals generated by the rising edge detection module during the enable period of one AC half-cycle. Drawing conclusions based solely on a single pulse makes it highly susceptible to being misled by occasional power grid spikes. Therefore, the core logic of this module is to perform continuous statistics. Internally, it typically includes a first counter and a first latch. The first counter accumulates the received valid pulses, but its counting rule is designed so that only pulses occurring within consecutive AC half-wave cycles are effectively accumulated. If no pulse occurs in a cycle during continuous counting (indicating that no fast rising edge was detected in that cycle), the counter may be reset. Only when fast rising edge pulses are successfully detected within a third preset number (e.g., 2, 4, or 8) consecutive AC half-wave cycles does the first detection count determination module consider the voltage fast rising edge characteristic to be stable and repetitive, rather than accidental. At this point, it outputs a stable, locked-in first detection signal. This continuous statistical judgment is one of the key mechanisms enabling this circuit to resist occasional interference and improve detection reliability.

[0041] In implementation, the first counter can be constructed by cascading multiple flip-flops. For example, multiple D flip-flops or JK flip-flops can be connected in series, with the output of the previous stage flip-flop serving as the clock or data input of the next stage, thus forming an asynchronous counter; alternatively, all flip-flops can share the same system clock, and the current counting state can be decoded and fed back as the input for the next counting state through combinational logic, thus forming a synchronous counter. The number of bits in the counter (i.e., the number of flip-flops) determines its maximum count value, which is directly related to the number of consecutive confirmation cycles required (i.e., the third number mentioned above). For example, to achieve judgment within 8 consecutive cycles, a 3-bit binary counter (composed of 3 flip-flops) can meet the basic requirements.

[0042] In an alternative implementation, such as Figure 5 As shown, the current detection module consists of four main parts: a second comparison module, a third comparison module, a time comparison module, and a second detection count judgment module. Together, they form a complete logical path from current sampling to feature confirmation.

[0043] The second comparison module receives a sampled voltage, which directly and linearly represents the actual current flowing through the discharge current module (e.g., obtained through a sampling resistor connected in series in the discharge circuit, the voltage drop across which is the sampled voltage). The core of the second comparison module is a voltage comparator that compares this sampled voltage with a preset second voltage threshold (corresponding to a preset current threshold) in real time. When the discharge current is large, causing the sampled voltage to exceed the second voltage threshold, the second comparison module outputs an invalid second enable signal (represented by COMP2), indicating that the discharge current has not reached zero-crossing. Only when the discharge current decreases, causing the sampled voltage to fall below the second voltage threshold, does the second comparison module output a valid second enable signal. The second enable signal identifies the start and end of the time period when the discharge current is below the preset current threshold, providing a fundamental basis for subsequent duration measurement.

[0044] The third comparison module contains a voltage comparator, but its inputs are the bus voltage and a preset third voltage threshold. It compares the real-time bus voltage with the third voltage threshold. The purpose of setting the third voltage threshold is to allow precise current duration measurement only when the bus voltage is sufficiently high and the waveform is relatively stable. When the bus voltage is higher than the third voltage threshold, it outputs a valid third enable signal (represented by COMP3), indicating that the current voltage is within a permissible timing window. This design cleverly utilizes the system's own operating characteristics: the permissible time period is in the zero-crossing region during the periods when the SCR dimmer may operate and the discharge current is active. By introducing this condition, abnormal fluctuations in the current signal caused by noise that may occur in the AC voltage zero-crossing or extremely low voltage regions can be effectively shielded, thereby greatly enhancing the anti-interference capability of the detection circuit.

[0045] The time comparison module is controlled by the outputs of the second and third comparison modules. This module is used only during the period when the second and third enable signals are simultaneously valid (i.e., the overlapping period when the discharge current is below the threshold and the bus voltage is in a stable window, referred to as the target enable period) to perform timing based on the reference clock signal to measure the duration of the discharge current being below the preset current threshold; it compares the duration with the preset time threshold, and outputs a valid duration determination signal when the duration exceeds the preset time threshold.

[0046] In specific implementation, such as Figure 6The time comparison module shown includes a first digital timer and a fifth comparator. The first digital timer is the foundation for implementing duration quantization. It is typically composed of a counter driven by a high-frequency reference clock (CLK). The start and stop of its counting operation are strictly controlled: an AND gate logic or similar enable control circuit will only open when the second and third enable signals are simultaneously valid, allowing the reference clock pulse to enter the first digital timer and begin its accumulation count. If either of these two signals becomes invalid, the counting will immediately stop.

[0047] The fifth comparator is responsible for performing the crucial threshold decision. It is not a digital comparator that processes analog voltage signals. One set of its inputs receives the digital value representing the measured duration output by the first digital timer; the other set of inputs is connected to a register storing a preset time threshold value. This time threshold is a fixed or configurable value set according to system characteristics (such as the typical low-level duration of the discharge current in the back-cut dimming mode). The fifth comparator performs a real-time or periodic comparison of these two digital values. The fifth comparator outputs a valid duration determination signal only if the digital value output by the timer (the measured duration) is greater than the time threshold value in the register. This indicates that the low-level state of the discharge current has lasted long enough within the current detection cycle to meet the time characteristics required for back-cut modes, etc.

[0048] The second detection count judgment module works similarly to the first detection count judgment module in the voltage detection path, aiming to filter out single, accidental events through statistical regularity. This module receives duration judgment signals from the time comparison module, which may be scattered across various AC cycles. The core logic is: only if a valid duration judgment signal is received in each cycle within a continuous, preset number of AC half-wave cycles is the characteristic of "the discharge current being below the threshold for a long period of time" considered stable and reliable. When this continuity condition is met, the second detection count judgment module will output a stable, latched, valid second detection signal. If, during this continuous statistical process, any cycle fails to meet the duration condition, the statistical sequence will be interrupted and reset.

[0049] In an optional implementation, upon receiving the detection end signal indicating the end of the detection process, the pattern determination module samples and latches the first and second detection signals, which are now in a stable state. It then decodes these signals according to preset logic rules and finally outputs a definite, mutually exclusive pattern control signal. To achieve this function, the pattern determination module can primarily consist of digital logic circuits, including flip-flops for signal latching and basic gate circuits (such as AND gates and NOT gates) for performing logical operations.

[0050] In an alternative implementation, such as Figure 7 As shown, in specific implementation, the mode judgment module only starts the final decision procedure after the detection end signal output by the detection cycle counting module takes effect, marking the completion of the preset detection cycle. At this time, it reads and latches the first detection signal from the voltage detection path (which can be called the Lead signal internally) and the second detection signal from the current detection path (which can be called the Trail signal internally).

[0051] If both the Lead and Trail signals are at a logic high level at the end of the detection, the system is determined to be operating in leading-edge dimming mode, as shown in the waveform diagram below. Figure 2 As shown, Iin represents the system's input current during dimmer detection, with the lower step being the discharge current and the higher step being the current of the LED constant current drive module. At this time, the module outputs a specific set of coded signals to characterize this mode. For example, the output representing the leading-edge dimming mode is set to logic 1 (Lead_mode=1), while the outputs representing the trailing-edge dimming mode and no dimming mode are both set to logic 0 (Trail_mode=0, Nodim_mode=0).

[0052] If, at the end of the detection, the Lead signal is at a logic low level and the Trail signal is at a logic high level, the system is determined to be operating in trailing edge dimming mode. The corresponding output encoding changes accordingly. For example, the output representing trailing edge dimming mode is set to logic 1 (Trail_mode=1), while the outputs representing the other two modes are set to logic 0 (Lead_mode=0, Nodim_mode=0). The specific waveform diagram is shown below. Figure 3 As shown, Iin represents the system input current during dimmer detection, with the lower step being the discharge current and the higher step being the current of the LED constant current drive module. CNT enable indicates that COMP3 is active (active low).

[0053] If both the Lead and Trail signals are at a low logic level at the end of the detection, the system is determined to be in no dimming mode. In this case, the output encoding will change accordingly, setting only the no dimming mode indicator to logic 1 (Nodim_mode=1), and the other two ends to logic 0 (Lead_mode=0, Trail_mode=0).

[0054] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0055] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A dimming mode detection circuit, characterized in that, Used to control the dimming modes of LED lighting circuits; including: The voltage detection module is used to acquire the bus voltage output by the thyristor dimmer and generate a first detection signal that characterizes the voltage edge features. The current detection module is used to collect the discharge current flowing through the discharge current module and generate a second detection signal to characterize whether dimming behavior is performed. The mode determination module is used to output a mode determination signal based on the first detection signal and the second detection signal, so as to control the working state of the discharge current module and the output driving strategy of the LED constant current drive module. The current detection module includes: The second comparison module is used to compare the sampled voltage, which characterizes the magnitude of the discharge current, and the second voltage threshold, and outputs a second enable signal; The third comparison module is used to compare the bus voltage with the third voltage threshold and output a third enable signal; The time comparison module is used to time the duration during which the discharge current is lower than a preset current threshold during the target enable period when the second enable signal and the third enable signal are simultaneously valid. The second detection count determination module is used to perform continuous statistics on the timing results and output the corresponding second detection signal based on the second statistical results; The time comparison module is used to perform timing based on a reference clock signal to measure the duration during which the discharge current is lower than a preset current threshold. The duration is compared with a preset time threshold, and a valid duration determination signal is output when the duration exceeds the preset time threshold. The second detection count determination module is used to perform continuous statistics on the duration determination signal. When a valid duration determination signal is received within a preset first number of AC half-wave cycles, the second detection signal is set to a valid state.

2. The dimming mode detection circuit according to claim 1, characterized in that, Also includes: The detection cycle counting module is used to count the cycles of the AC power supply and output a detection end signal; The mode determination module is used to output the mode determination signal based on the first detection signal and the second detection signal at the time of reception when the detection end signal is received.

3. The dimming mode detection circuit according to claim 1, characterized in that, The mode determination module is used to output a pre-cut dimming mode signal when both the first detection signal and the second detection signal are valid. When the first detection signal is invalid and the second detection signal is valid, the back-cut dimming mode signal is output; When the second detection signal is invalid, a no-dimming mode signal is output.

4. The dimming mode detection circuit according to claim 1, characterized in that, The voltage detection module includes: The first comparison module is used to compare the bus voltage with a preset first voltage threshold and output a first enable signal; The rising edge detection module is used to detect the fast rising edge of the bus voltage during the first enabling period corresponding to the first enabling signal, and output a pulse signal when the fast rising edge is detected. The first detection count determination module is used to perform continuous statistics on the pulse signal and output the corresponding first detection signal based on the first statistical result.

5. The dimming mode detection circuit according to claim 4, characterized in that, The first comparison module includes a first comparator; The rising edge detection module includes an RC filter circuit and an edge detection comparator; The first detection count determination module includes a first counter and a first latch.

6. The dimming mode detection circuit according to claim 1, characterized in that, The second comparison module includes a second comparator; The third comparison module includes a third comparator; The time comparison module includes a first digital timer and a fifth comparator; The second detection count determination module includes a second counter and a second latch.

7. The dimming mode detection circuit according to claim 6, characterized in that, It also includes a sampling resistor connected in series in the discharge circuit, wherein the sampling voltage is the voltage drop across the sampling resistor.

8. A lighting system, characterized in that, include: Thyristor dimmer, bleed current module, LED constant current drive module; And the dimming mode detection circuit as described in any one of claims 1 to 7.

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