A fetch control method and system based on RISC-V architecture

Abstract

The present application belongs to the technical field of chip design, and particularly relates to a fetch control method and system based on RISC-V architecture. Through the design of splicing and cutting modules, cross-cache line instruction efficient splicing is realized, fetch bubbles caused by pipeline suspension are effectively avoided, the overhead of cross-block fetching is reduced, and the fetch throughput is improved. Through the age vector-based directional flushing mechanism, the prefetch instruction transactions on the prediction error path are accurately flushed, the pipeline flushing accuracy is improved, and the repeated fetch rate caused by full flushing is reduced. Through the missing queue module, a dedicated reserved entry is configured for the main fetch transaction, the pre-fetch request resource preemption is isolated, the main fetch missing problem under high pre-fetch pressure is alleviated, and the pipeline blocking and deadlock hazards caused by resource competition are avoided.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology, specifically relating to an instruction fetch control method and system based on RISC-V architecture. Background Technology

[0002] A processor's instruction fetch module typically includes a branch prediction module, a fetch target queue module, an instruction translation back buffer module, an instruction cache module, a miss queue module, and an instruction buffer module. When the processor supports mixed encoding of compressed and regular instructions, 32-bit instructions may cross fetch block boundaries or cache line boundaries. Using traditional methods, to fill in missing half-word alignment data for cross-block instructions, the instruction fetch pipeline often needs to pause and re-access the instruction cache module, introducing additional latency.

[0003] Meanwhile, while prefetching requests improve the hit rate, they also consume table entries in the missing queue module. When the prefetching intensity is high, the primary fetching of missing requests may fail to allocate entries and cause fetching blockage. Furthermore, when branch prediction correction or front-end consistency verification fails, simply using a full flush strategy will unnecessarily clear older in-transit requests and backfilled data, resulting in duplicate missing data and performance degradation.

[0004] For the reasons mentioned above, it is necessary to propose a technical solution that can reduce the overhead of cross-block instruction processing, ensure the handling of missing master fetch instructions under prefetch pressure, and perform targeted flushing of pipeline and missing queue modules in redirection scenarios. Summary of the Invention

[0005] The purpose of this invention is to provide an instruction fetch control method and system based on RISC-V architecture to solve the problems of high overhead of cross-block instruction fetch, lack of master instruction fetch under pre-fetch pressure, and insufficient accuracy during directional flushing.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: An instruction fetch control system based on RISC-V architecture includes the following modules: The instruction fetch target queue module is used to respond to instruction fetch requests, schedule and output the instruction fetch target address.

[0007] The instruction translation backup buffer module is used to complete the virtual address to physical address mapping of the target address and provide three distinguishable results: hit, missing, and exception.

[0008] The instruction cache module determines cache hits based on the physical address output by the instruction translation back buffer module. When a hit occurs, it provides instruction fetch block data; when a miss occurs, it provides miss information and sends it to the miss queue module.

[0009] The splicing and cutting module is used to provide the ability to splice cache line data when there is a requirement for half-word alignment when the cache line output by the instruction cache module has cross-line instruction fetching; and to perform instruction window cutting in fixed steps under the constraints of cache line configuration parameters.

[0010] The missing queue module is used to take over missing transactions when the physical address of the instruction cache module is missing. It implements functions such as missing entry storage, entry allocation / merging, cache line address matching, waiter set management, issuing queue requests, backfill reception and write control, and bypass output. It adopts an entry reservation constraint strategy to reserve dedicated entries for missing master instruction fetches.

[0011] The pre-decoding module is used to pre-decode the instruction window cut by the splicing and cutting module, compare the pre-decoding result with the target address of the branch prediction module, and generate a redirection request and redirection target when an error is detected.

[0012] The directional flushing module is used to generate a comparison benchmark and execute an age vector-based flushing strategy in redirection scenarios. It implements the logic for benchmark selection, age comparison, pipeline-level flushing control, missing queue flushing triggering, half-word alignment flushing, and full flushing coordination.

[0013] The instruction fetch pipeline control module interacts with the instruction fetch target queue module to obtain instruction fetch transaction information and selects to advance the current transaction if it is hit or handle the missing one. At the same time, it combines the missing queue module to implement allocation, merging, pause and replay control for missing transactions. It also combines the redirection request to generate a redirection target and trigger a targeted flush.

[0014] Preferably, the specific operations for table entry allocation / merging in the missing queue module are as follows: The missing queue module matches missing requests issued by the instruction fetch pipeline control module, which include cache line alignment address, instruction fetch type, transaction identifier, and age vector, using the cache line alignment address as the key, and merges missing requests with the same address.

[0015] Preferably, the alignment of half-characters in the splicing and cutting module is as follows: The splicing and cutting module determines whether to save the last half-word of the previous fetch block based on the candidate half-word data, half-word boundary judgment information, and transaction identifier information latched by the fetch pipeline control module. If it saves the half-word, when the splicing conditions are met, the half-word alignment position is set to valid, and splicing is performed across cache lines.

[0016] Preferably, the splicing of cached row data in the splicing and cutting module must simultaneously meet the following conditions: Cross-block instructions are uncompressed instructions; the last two bytes of the cache line mark the beginning of a valid instruction; the absence of a predicted jump control flow instruction before the instruction stream causes the instruction fetch block to terminate prematurely.

[0017] Preferably, the cutting operation in the instruction window of the splicing and cutting module is as follows: Under the constraints of block boundary and length configuration parameters provided by the instruction fetch pipeline control module, the cutting window, offset and valid candidate information are generated, and the continuous byte data stream is cut into instructions with half-word alignment.

[0018] Preferably, the age vector in the directional flushing module is: The transaction identifier and optional ring position information provided by the instruction fetch pipeline control module are mapped to an age vector.

[0019] Preferably, after comparing the pre-decoding result with the target address of the branch prediction module, the method further includes: When an anomaly is detected, the output includes the redirection request, error type, error location index, and redirection target, along with a benchmark identifier for directional flushing.

[0020] Preferably, the age vector-based flushing strategy operation in the directional flushing module is as follows: The missing queue module compares the time-series age of entries and internal waiters based on the comparison benchmark identifier, selectively deletes younger entries or younger waiters within entries, and updates the age identifier; for the splicing and cutting module, it performs transaction age matching verification on residual data that does not meet the cross-cache row splicing legality requirements, and sets the half-word alignment validity flag of transactions belonging to the flush path to invalid.

[0021] Preferably, the instruction cache module provides missing information when an instruction is missing: When the instruction cache module is missing the instruction fetch block corresponding to the target address, it returns a missing indication and triggers the missing queue module to establish a missing transaction. At the same time, the instruction cache module also receives the backfill request and backfill data returned by the missing queue module and writes the backfill data into the cache array.

[0022] An instruction fetch control method based on RISC-V architecture, comprising: When the instruction fetch queue module receives an instruction fetch request, it extracts the target address, and the instruction fetch pipeline control module latches the attribute information of the target address.

[0023] The target address is in the instruction translation back buffer module, which completes the virtual address to physical address mapping; if the mapping is normal, the instruction cache module is accessed.

[0024] In the instruction cache module, a cache hit is determined based on the physical address output by the instruction translation back buffer module. If a cache hit occurs, the missing transaction is sent to the missing queue module; if a cache hit occurs, the transaction is entered into the splicing and splitting module.

[0025] In the splicing and cutting module, when there is cross-line instruction fetching in the cache line output by the instruction cache module, the cache line data is spliced ​​according to the half-word alignment. Under the constraints of the cache line configuration parameters, the instruction window is cut in a fixed step to generate a continuous target address window sequence, which is then entered into the pre-decoding module.

[0026] In the missing queue module, the front-end request is received, the missing transaction is allocated table entries, and a read request is sent to the underlying storage. After the data is backfilled, it is written to the instruction cache module.

[0027] In the pre-decoding module, the target address is pre-decoded, and the pre-decoding result is compared with the target address of the branch prediction module. If it is normal, resources are pre-allocated for the target address to complete the instruction fetching. If it is abnormal, the module enters the directional flushing module.

[0028] In the directional flushing module, pipeline transactions are flushed based on age vectors.

[0029] Compared with the prior art, the technical solution provided by this invention has the following advantages: The design of the splicing and cutting module enables efficient splicing of instructions across cache lines, effectively avoiding fetch bubbles caused by pipeline pauses, reducing the overhead of cross-block fetching, and improving fetch throughput.

[0030] The design incorporates an age-vector-based directional flushing mechanism to precisely flush prefetch transactions on incorrect prediction paths, thereby improving pipeline flushing accuracy and reducing the duplicate fetch rate caused by full flushing.

[0031] The missing queue module is designed with a reserved table entry dedicated to the primary fetch transaction configuration. This isolates prefetch request resource preemption, alleviates the primary fetch missing problem under high prefetch pressure, and avoids pipeline blockage and deadlock risks caused by resource contention. Detailed Implementation

[0032] This invention provides an instruction fetching control system. To further understand the content of this invention, the following detailed description is provided in conjunction with embodiments.

[0033] An instruction fetch control system based on RISC-V architecture includes the following modules: The instruction fetch target queue module is used to respond to instruction fetch requests, schedule and output the instruction fetch target address.

[0034] The instruction fetch target queue module is used to receive and cache various instruction fetch requests from the front end, and output the instruction fetch target address in an orderly manner according to the instruction fetch priority scheduling strategy (prioritizing the main instruction fetch service); at the same time, it responds to control signals such as flushing, redirection, and back pressure to complete queue clearing, address redirection, request pause and replay, so as to realize the orderly queuing, distribution and timing control of instruction fetch transactions.

[0035] The instruction translation backup buffer module is used to complete the virtual address to physical address mapping of the target address and provide three distinguishable results: hit, missing, and exception.

[0036] The instruction translation backup buffer module is used to complete the translation of the target address from the virtual address to the physical address, and to provide distinguishable results to the instruction fetch control in three cases: hit, missing, and exception.

[0037] The instruction translation backup buffer module searches based on the virtual address query request and access attributes given by the instruction fetch pipeline control module.

[0038] When a hit occurs, the physical address and attribute information are returned.

[0039] When a missing value occurs, return a missing value indication and wait for page table traversal or address translation to complete and backfill information.

[0040] When a permission or page-related exception is detected, an exception indication and corresponding exception information are returned.

[0041] After missing information is filled in, the instruction translation backup buffer module outputs a transaction wake-up indication to trigger the corresponding transaction to be replayed and restored on the instruction fetch pipeline control module side, thereby avoiding pipeline consistency disruption due to multi-cycle translation.

[0042] Specifically, the instruction translation backup buffer module and the instruction fetch pipeline control module cooperate through a handshake mechanism to achieve multi-cycle access, pause and replay.

[0043] The instruction cache module determines cache hits based on the physical address output by the instruction translation back buffer module. When a hit occurs, it provides instruction fetch block data; when a miss occurs, it provides miss information and sends it to the miss queue module.

[0044] Preferably, the instruction cache module provides missing information when an instruction is missing: When the instruction cache module is missing the instruction fetch block corresponding to the target address, it returns a missing indication and triggers the missing queue module to establish a missing transaction. At the same time, the instruction cache module also receives the backfill request and backfill data returned by the missing queue module and writes the backfill data into the cache array.

[0045] The instruction cache module includes a tag array, a data array, hit determination logic, and replacement / consistency management and backfill control logic. It is used to provide instruction fetch block data when a hit occurs and to provide missing information when a missing instruction occurs, so as to enter the missing instruction processing flow.

[0046] The instruction cache module accesses the instruction based on the physical address, access request, and access control information provided by the instruction fetch pipeline control module.

[0047] When a hit is achieved, the hit indicator and the corresponding fetch block data are returned.

[0048] When missing, a missing indication is returned to trigger the missing queue module to establish a missing transaction.

[0049] At the same time, the instruction cache module also receives the backfill request and backfill data returned by the missing queue module, and writes the backfill data into the cache array so that subsequent accesses can hit the cache.

[0050] Specifically, prefetch access can reduce the priority of data array access or only access the tag array to ensure master fetch bandwidth and reduce critical path latency.

[0051] The splicing and cutting module is used to provide the ability to splice cache line data when there is a requirement for half-word alignment when the cache line output by the instruction cache module has cross-line instruction fetching; and to perform instruction window cutting in fixed steps under the constraints of cache line configuration parameters.

[0052] The splicing and slicing module provides continuous splicing capability when half-word alignment is required across fetch block boundaries, supporting the correct construction of decoding windows for 16-bit / 32-bit mixed-length instructions. It also organizes the fetch block data into a unified windowed input and generates a sequence of instruction code windows for pre-decoding at fixed steps.

[0053] The splicing and cutting module includes a half-word data register, a valid flag register, an identifier register, and age information of the half-word, along with logic for determining the validity of half-word alignment and logic for clearing half-word flushing association.

[0054] In terms of data sources, it supports two types of instruction fetch block inputs: hit data from the instruction cache module and bypass data from the missing queue module. At the same time, it combines the half-word alignment bit data given by the half-word data register and the control signal of the half-word alignment bit given by the valid flag register to complete the alignment and splicing selection.

[0055] The cutting window, offset, and valid candidate information are generated under the constraints of block boundary and length configuration parameters (such as cache line size) provided by the instruction fetch pipeline control module.

[0056] Preferably, the alignment of half-characters in the splicing and cutting module is as follows: The splicing and cutting module determines whether to save the last half-word of the previous fetch block based on the candidate half-word data, half-word boundary judgment information, and transaction identifier information latched by the fetch pipeline control module. If saved, the half-word alignment position is set to valid, and when the splicing conditions are met, cross-cache line splicing is performed.

[0057] The splicing and segmentation module determines whether to save the last half-word alignment bit of the previous instruction fetch block based on the candidate data for the last half-word alignment bit, the segmentation / pre-decoding boundary judgment information, and the transaction identifier information provided by the instruction fetch pipeline control module. If the last half-word alignment bit of the previous instruction fetch block is a low-order 16-bit segment of a 32-bit instruction, belongs to a valid instruction segment, is not truncated by the predicted termination mask, and is not marked as an invalid transaction path by directional flushing, then the half-word alignment bit data is saved and the half-word alignment bit is marked as valid. If any of the conditions for instruction segment validity, mask constraints, or path flushing verification are not met, then the half-word alignment bit data is discarded and the half-word alignment bit is marked as invalid.

[0058] Cross-block concatenation is achieved by combining half-word alignment and cache line data concatenation conditions.

[0059] Preferably, the splicing of cached row data in the splicing and cutting module must simultaneously meet the following conditions: Cross-block instructions are uncompressed instructions; the last two bytes of the cache line mark the beginning of a valid instruction; the absence of a predicted jump control flow instruction before the instruction stream causes the instruction fetch block to terminate prematurely.

[0060] If the following conditions are met, the half-word alignment bit at the end of the fetch block is saved to the half-word data register for subsequent cross-block concatenation: First, the cross-block instruction is an uncompressed instruction; Second, the last two bytes of the fetch block have a half-word alignment bit and are in a valid state, the half-word boundary is valid, the half-word candidate data is valid, and the transaction identifier matches the continuous instruction flow; Third, there is no predictive jump-type control flow instruction that causes the predictive block to terminate prematurely before the instruction, and the subsequent fetch block satisfies the instruction flow continuity and no branch path jump with the previous fetch block.

[0061] When the above conditions are met, the instruction fetch pipeline control module controls the writing of half-word data registers, and records the transaction identifier and age vector identifier corresponding to the last half-word alignment bit. When the next instruction fetch block arrives, the splicing is performed.

[0062] If the above conditions are not met, the fetch pipeline control module clears the valid flag of the last two bytes of data. Furthermore, when a subsequent flush or redirection causes the fetch block to no longer be in a valid path, the fetch pipeline control module invalidates the half-word alignment position to prevent half-word data from being reused by invalid transactions and erroneous paths.

[0063] Preferably, the cutting operation in the instruction window of the splicing and cutting module is as follows: Under the constraints of block boundary and length configuration parameters provided by the instruction fetch pipeline control module, the cutting window, offset and valid candidate information are generated, and the continuous byte data stream is cut into instructions with half-word alignment.

[0064] When half-word alignment is valid, the concatenation and splitting module concatenates the half-word data with the current fetch block data across cache lines to construct a continuous data stream. The splitting step is half-word alignment, the splitting window width is 4 bytes, and it is allowed to form a half-word alignment window when the data at the end of the data stream is less than 4 bytes. The first splitting window is composed of the last two bytes of the previous fetch block and the first two bytes of the current fetch block concatenated, and subsequent windows slide sequentially to complete the splitting with half-word alignment steps.

[0065] When the half-word alignment is invalid, the current fetch block is directly cut.

[0066] The segmented window sequence is sent to the pre-decoding module for instruction category identification; the window offset and candidate valid information are synchronously fed back to the instruction fetch pipeline control module to generate instruction valid vector and instruction mask vector, providing instruction validity identifier and position information for the downstream instruction submission stage, supporting ordered instruction packaging and invalid instruction masking.

[0067] Specifically, when control flow instructions (such as branch instructions, jump instructions, etc.) are separated by cache lines or fetch block boundaries, the branch prediction module does not predict jumps for the control flow instruction within the current prediction block. Instead, it assigns the prediction of the control flow instruction to the next prediction block. Consequently, the next prediction block can use the half-bytes remaining in the current fetch block and concatenate them with its own starting data to reconstruct the complete control flow instruction. This eliminates the need to pause the fetch pipeline or repeatedly access the instruction cache to fill in missing instruction bytes, effectively reducing pipeline pause overhead and cache access overhead for cross-line fetching.

[0068] The missing queue module is used to take over missing transactions when the physical address of the instruction cache module is missing. It implements functions such as missing entry storage, entry allocation / merging, cache line address matching, waiter set management, issuing queue requests, backfill reception and write control, and bypass output. It adopts an entry reservation constraint strategy to reserve dedicated entries for missing master instruction fetches.

[0069] The missing queue module is used to take over the missing transaction, initiate a read request to the lower-level cache / storage layer when the physical address of the instruction fetch target is missing in the instruction cache module, and complete the write and bypass recovery after the backfill arrives, thereby shortening the missing recovery latency.

[0070] The missing queue module includes an entry storage array, entry allocation / reclaim logic, cache line address matching logic, waiter set management logic, request queue and interface logic, backfill reception and write control logic, bypass output logic, and flushing processing logic.

[0071] The table entries include reserved entries and regular entries, and both the total number of entries and the number of reserved entries are configurable parameters. To ensure that the primary fetch instruction can still proceed when resources are scarce, the missing queue module employs a reservation constraint strategy, allowing the primary fetch instruction to prioritize the use of reserved entries when a missing instruction is missing, while prohibiting the use of reserved entries for prefetch instructions. The missing queue module creates or reuses entries based on the missing allocation / merging requests provided by the value pipeline control module.

[0072] Preferably, the specific operations for table entry allocation / merging in the missing queue module are as follows: The missing queue module matches missing requests issued by the instruction fetch pipeline control module, which include cache line alignment address, instruction fetch type, transaction identifier, and age vector, using the cache line alignment address as the key, and merges missing requests with the same address.

[0073] The missing allocation / merge request includes the cache line alignment address, master fetch / prefetch type, transaction identifier, and age vector identifier. Missing data merging is achieved by matching cache line addresses, allowing multiple transactions waiting for the cache line to be filled to share the same filled data.

[0074] When the lower-level cache returns backfilled data, the missing queue module writes the backfilled data to the instruction cache module and provides it to the instruction fetch pipeline control module in a bypass manner. The instruction fetch pipeline control module preferably supports conflict checking bypass and backfill bypass mechanisms. When the data is ready, it directly obtains the data from the missing queue module or the backfill path, without waiting for the instruction cache module to complete the write-back and then reread, and can continue to perform instruction splitting, pre-decoding and pipeline commit operations.

[0075] When a front-end directional flush occurs, the missing queue module deletes young entries based on the comparison benchmark identifier, or deletes young waiters within an entry and updates the oldest waiter identifier, thereby releasing resources and avoiding erroneous path wake-ups.

[0076] When a backend flush or reset occurs, the missing queue module performs a full flush to restore consistency and eliminate residual transactions.

[0077] The pre-decoding module is used to pre-decode the instruction window cut by the splicing and cutting module, compare the pre-decoding result with the target address of the branch prediction module, and generate a redirection request and redirection target when an error is detected.

[0078] The pre-decoding module is used to determine the consistency between the predicted information and the pre-decoding result, and generates a redirection request and redirection target when an error is detected, so that the front end returns to the correct path to continue fetching instructions.

[0079] By using the pre-decoded fields and target address, and combined with the prediction information provided by the branch prediction module (including whether to predict a jump, the prediction termination position / mask, and the prediction target address, etc.), the comparison judgment and anomaly detection are completed under the location of the transaction identifier and target value address information provided by the instruction fetch pipeline control module.

[0080] When a match is found, cache resources are pre-allocated based on the verified target address. A fetch control system based on a RISC-V architecture also includes an instruction buffer module, which outputs instruction packet information when the instruction buffer module is ready. If the instruction buffer module is not ready, the fetch pipeline control module pauses or replays the current fetch transaction to prevent instruction buffer overflow, until the instruction buffer module is ready to complete the fetch process.

[0081] Preferably, after comparing the pre-decoding result with the target address of the branch prediction module, the method further includes: When an anomaly is detected, the output includes the redirection request, error type, error location index, and redirection target, along with a benchmark identifier for directional flushing.

[0082] Anomalies include jump prediction errors for detection instructions, jump prediction errors for jumps with return instructions, target address inconsistencies, and non-control flow prediction errors.

[0083] When an anomaly is detected, the system outputs a redirection request, error type, error location index, and redirection target address. It can also provide a comparison benchmark identifier for directional flushing (or generate it by the instruction fetch pipeline control module) so that the directional flushing module can clear the young path state according to age.

[0084] In particular, the forecast information can be updated by the branch forecast module during the flow process, and the updated forecast information is used as the final decision-making basis, thereby improving the timeliness of forecast correction.

[0085] The directional flushing module is used to generate a comparison benchmark and execute an age vector-based flushing strategy in redirection scenarios. It implements the logic for benchmark selection, age comparison, pipeline-level flushing control, missing queue flushing triggering, half-word alignment flushing, and full flushing coordination.

[0086] Preferably, the age vector in the directional flushing module is: The transaction identifier and optional ring position information provided by the instruction fetch pipeline control module are mapped to an age vector.

[0087] The age vector provides a unified age identifier and comparison capability to support control logic that relies on the sequence of transactions, such as targeted flushing and missing merge waiter management. The age vector is generated from the transaction identifier and optional loop position information provided by the instruction fetch pipeline control module.

[0088] The directional flushing module is used to generate a benchmark in redirection scenarios and drive an age vector-based flushing strategy to preserve older, valid states and remove younger, erroneous states as much as possible when correcting the path.

[0089] Preferably, the age vector-based flushing strategy operation in the directional flushing module is as follows: The missing queue module compares the time-series age of entries and internal waiters based on the comparison benchmark identifier, selectively deletes younger entries or younger waiters within entries, and updates the age identifier; for the splicing and cutting module, it performs transaction age matching verification on residual data that does not meet the cross-cache row splicing legality requirements, and sets the half-word alignment validity flag of transactions belonging to the flush path to invalid.

[0090] The directional flushing module includes comparison benchmark selection logic, age comparison logic, pipeline-level flushing control logic, missing queue module flushing trigger interface, splicing and cutting module half-word data coordination logic, and full flushing coordination logic.

[0091] Based on the redirection information, and combined with the redirection point identifier and age vector generation identifier provided by the branch prediction module, a benchmark identifier for comparison is formed.

[0092] Based on the benchmark identifier for comparison, the pipeline implements hierarchical control over each stage of the instruction fetching pipeline, including flushing young transactions, retaining old transactions, and updating the matching transaction age vector information. Simultaneously, it triggers the missing queue module to perform front-end targeted flushing to remove invalid young missing transactions. This module also collaborates with the splicing and control module to simultaneously invalidate the half-word alignment position of the corresponding young transactions during flushing, preventing illegal data splicing across invalid paths.

[0093] When a backend flush or reset occurs, a full flush is triggered and all modules are coordinated to clear the data consistently.

[0094] The instruction fetch pipeline control module interacts with the instruction fetch queue to obtain instruction fetch transaction information and selects whether to advance the current transaction if it hits or handle missing transactions. Simultaneously, it combines data from the missing transaction queue module to perform allocation, merging, pause, and replay control on missing transactions; and, in conjunction with redirection requests, it generates redirection targets and triggers targeted flushing.

[0095] The instruction fetch pipeline control module is used to coordinate the timing and control of front-end instruction fetch transactions between address translation, cache access, missing data handling, pre-decoding, and instruction packet submission.

[0096] The instruction fetch pipeline control module interacts with the instruction fetch target queue module to obtain and latch instruction fetch transaction information. The transaction information includes at least the target address, the next target address, prediction information, transaction identifier, and age vector.

[0097] The instruction fetch pipeline control module combines the translation hit / missing / abnormal information from the instruction translation backup buffer module to select the hit-progress or missing-processing path for the current transaction.

[0098] The instruction fetch pipeline control module combines the allocation results, merging results, bypass data and backfill instructions from the missing queue module to perform allocation, merging, pause and replay control on missing transactions.

[0099] The instruction fetch pipeline control module combines the pre-decoding information with the instruction fetch target queue and the prediction termination information output by the branch prediction module to generate an instruction mask vector. This vector limits the range of instructions that can be submitted to the instruction buffer within the current prediction block, preventing invalid instructions after the prediction termination point from being incorrectly submitted to the downstream pipeline.

[0100] In terms of interface driving, the instruction fetch pipeline control module initiates a translation request to the instruction translation backup buffer module; it initiates an access request to the instruction cache module; and when the instruction cache module is missing, it initiates allocation / merging and conflict checking related requests to the missing queue module.

[0101] On the data path, the instruction fetch pipeline control module organizes the data from the instruction cache module hit or missing queue module bypass into instruction fetch block input, and sends it to the splicing and cutting module in conjunction with half-word alignment bits; it also provides pre-decoding related information to the pre-decoding module; at the same time, it provides the reference identifier and control information for comparison to the directional flushing module, and finally returns the ready / backpressure and transaction progress status to the branch prediction module, thereby realizing the closed-loop progress of the instruction fetch transaction.

[0102] An instruction fetch control method based on RISC-V architecture, comprising: S1. The instruction fetch queue module receives the instruction fetch request, extracts the target address, and the instruction fetch pipeline control module latches the attribute information of the target address.

[0103] The instruction fetch pipeline control module receives the main instruction fetch request and prefetch request from the branch prediction module, and latches the pipeline status and control parameters such as the target address of the starting instruction fetch block, the target address of the next instruction fetch block, the transaction identifier, the age vector, the cache line alignment address, the half-word candidate data, and the boundary judgment information. At the same time, it sends the above-mentioned required parameters to the instruction cache module, the splicing and cutting module, and the missing queue module, so that each module can complete logical processing such as hit determination, cross-block splicing, and missing table entry allocation.

[0104] An age vector is generated based on the transaction identifier and optional ring position information provided by the instruction fetch pipeline control module. This vector is used to provide a unified age transaction identifier to support the accurate flushing of the directional flushing module. In the missing queue module, it is used to compare the ages, maintain priorities, and control the flushing and filtering of multiple queued transactions aggregated at the same missing address.

[0105] S2. The target address is in the instruction translation back buffer module, which completes the mapping from virtual address to physical address; if the mapping is normal, execute S3.

[0106] The instruction translation backup buffer module is used to complete the conversion from instruction fetch virtual address to physical address, and performs the lookup based on the virtual address query request and access attributes given by the instruction fetch pipeline control module.

[0107] When a virtual address is missing, a missing information indication is returned and the system waits for fill-in information. After the missing information is filled in, the instruction translation backup buffer module further issues a wake-up indication to trigger the corresponding transaction to resume work in the instruction fetch pipeline control module, thereby avoiding pipeline consistency disruption caused by multi-cycle translation.

[0108] When an abnormal virtual address is detected, an abnormal indication and corresponding abnormal information are returned. The instruction fetch pipeline control module associates the abnormal information with the transaction and enters it into the instruction buffer module.

[0109] When a virtual address is hit, the physical address and attribute information are returned, and the instruction cache module is accessed.

[0110] S3. In the instruction cache module, a cache hit is determined based on the physical address output by the instruction translation backup buffer module. If a cache hit occurs, the missing transaction S5 will be executed; if a cache hit occurs, S4 will be executed.

[0111] The instruction cache module performs cache access based on the target address access request issued by the instruction fetch pipeline control module and the access control information. When a hit occurs, it outputs the instruction fetch block data to which the target address belongs. When a miss occurs, it provides missing information and enters the missing queue module.

[0112] When a hit occurs, a hit indication and corresponding cache line data are returned to the instruction fetch pipeline control module. If the current instruction fetch block is within a single cache line and the cache line data is complete, it is directly output to the pre-decoding module for pre-decoding. If the instruction fetch block crosses cache line boundaries and involves cross-line instruction fetching, the cache line data is sent to the concatenation and splitting module to perform cross-cache line data concatenation, and then output to the pre-decoding module after concatenation.

[0113] When an access is missing, the instruction cache module returns a missing indication to trigger the missing queue module to establish a missing transaction. At the same time, the instruction cache module also receives a backfill request and backfill cache line data from the missing queue module, and writes the backfill data into the internal cache array of the instruction cache module to complete the cache line filling, thereby enabling subsequent accesses to the same address to be hit normally.

[0114] S4. In the splicing and cutting module, when there is cross-line instruction fetching in the cache line output by the instruction cache module, the cache line data is spliced ​​according to the half-word alignment. Under the constraints of the cache line configuration parameters, the instruction window is cut in a fixed step to generate a continuous target address window sequence, and then S6 is executed.

[0115] When splicing cache line data and cutting instruction windows, the splicing and cutting module checks whether there are 32-bit uncompressed instructions that cross cache lines at the end of the instruction fetch block.

[0116] If the splicing conditions are met, the last two bytes of the current instruction fetch block are temporarily stored inside the splicing and cutting module, and the transaction identifier and age vector information corresponding to the last half word are recorded. The instruction is then spliced ​​in combination with the half word alignment.

[0117] If the above conditions are not met, the half-word alignment position of the last two bytes of data will be invalid.

[0118] When the half-word alignment is valid, the fetch pipeline control module concatenates the last two bytes of data retained from the previous fetch block with the cached line data returned by the current fetch block to form a continuous byte data stream. For example, if the current fetch block data width is 64 bytes, the concatenation will form a 66-byte continuous data stream.

[0119] The instruction fetch pipeline control module performs instruction code segmentation with half-word alignment for both the concatenated continuous byte data stream and the complete single-byte data stream that does not require cross-block concatenation.

[0120] When the half-word alignment valid flag is invalid, the fetch pipeline control module only processes the data returned by the current fetch block and does not perform cross-block splicing.

[0121] S5. In the missing queue module, receive the front-end request, allocate table entries for missing transactions, and simultaneously send a read request to the underlying storage. After the data is backfilled, write it to the instruction cache module and execute S4.

[0122] When the instruction cache module misses an instruction, the missing queue module searches for it using the cache line aligned address as the key. The instruction fetch pipeline control module initiates an interaction request to the missing queue module according to the following rules, carrying information such as the cache line aligned physical address, transaction identifier, and age vector.

[0123] If there is a matching entry in the missing queue for the current missing data, that is, a missing request has been issued for the same address, and the missing entry has been registered and is in a pending state waiting for a response from the lower-level storage and has not yet completed data backfilling, then the current missing request can be merged into an existing valid entry for unified scheduling and processing. There is no need to repeatedly allocate missing entries or repeatedly initiate memory access requests.

[0124] Specifically, if a valid missing entry already exists at the same address, the current missing request is merged into the waiter set corresponding to that entry. The age vector carried by the current request is compared sequentially with the oldest waiter identifier already stored in the entry. If the current transaction is earlier in the time sequence and older, the oldest waiter identifier of the entry is updated to the age vector and transaction identifier corresponding to the current transaction; otherwise, the original identifier remains unchanged.

[0125] If there is no matching entry to be processed in the missing address queue, or the transaction merge constraint is not met, or the cached row addresses corresponding to the cross-row double missing are independent of each other, a new entry allocation request is initiated to request the allocation of an independent missing entry for the current missing transaction.

[0126] Specifically, if no matching existing entry is found, the missing queue module allocates a new missing entry, registers the age vector of the current transaction and initializes it as the oldest waiter identifier of that entry, and simultaneously initiates a data read request to the lower-level cache or storage layer.

[0127] Specifically, when a single instruction fetch covers two cached rows and both rows experience cache misses, table entry allocation and miss request management are performed for transactions with two missing rows. One of the following two implementation methods is preferred: The first method is atomic double allocation, in which the instruction fetch pipeline control module uses the cache line alignment address as the matching key and simultaneously sends two cache line entry allocation requests to the missing queue module in the same cycle. If the missing queue module cannot process the two line requests together, it must allocate two entries at the same time, or the overall application fails and the queue is full, to avoid only filling a single cache line, which would cause the splicing process to stop due to incomplete cross-line data.

[0128] The second method is a step-by-step allocation method. The instruction fetch pipeline control module uses the cache line alignment address as the matching key to prioritize the allocation of table entries for the starting cache line. Subsequently, it retryes the allocation of adjacent cache lines during idle periods. If the allocation fails, the pipeline replay mechanism is triggered to fill in the missing requests required for cross-line instruction fetching.

[0129] Specifically, the total number of entries in the missing queue module is a configurable parameter N, and there are also a configurable parameter R reserved entries. Primary fetching means that missing requests can preferentially use reserved entries; if there are insufficient reserved entries, other non-reserved free entries can be used. Prefetching, on the other hand, only allows the use of non-reserved free entries and cannot occupy reserved entries.

[0130] This resource isolation constraint ensures that even when prefetch pressure is high, missing primary fetch requests can still be allocated to entries, effectively reducing pipeline congestion. An example configuration could be N=8 total entries and R=2 reserved entries; this example does not limit the scope of this solution.

[0131] S6. In the pre-decoding module, pre-decode the target address and compare the pre-decoding result with the target address of the branch prediction module. If normal, pre-allocate resources for the target address to complete instruction fetching. If abnormal, execute S7.

[0132] The instruction fetch pipeline control module generates pre-decoding information for each instruction code window obtained from the segmentation. This includes whether it is a compressed instruction, a branch instruction, a direct jump instruction, an indirect jump instruction, a return instruction, a call instruction, and a return / call composite identifier. If the pre-decoding determines that the current instruction is a branch instruction or a direct jump instruction, the instruction fetch pipeline control module further calculates the jump target address and performs a consistency comparison and verification between the pre-decoded target address and the predicted target address given by the branch prediction module.

[0133] The instruction fetch pipeline control module compares the pre-decoding result with the prediction result from the branch prediction module, and detects at least the following four types of prediction errors: errors where the pre-decoding determines it to be a jump instruction but predicts it not to jump; errors where the pre-decoding determines it to be a jump instruction with a return but predicts it not to jump; errors where the predicted branch or jump target address does not match the target address calculated by the pre-decoding; and errors where the pre-decoding determines it to be a non-control flow instruction but predicts a jump.

[0134] If the verification result is normal and consistent, resources are pre-allocated for the target address to complete the instruction fetching.

[0135] If the address comparison is abnormal or there is a prediction error, the process enters the directional flushing module to perform pipeline directional flushing and redirection operations.

[0136] S7. In the directional flushing module, flushing is performed on pipeline transactions based on the age vector.

[0137] When a prediction error is detected, the instruction fetch pipeline control module generates a redirection signal and outputs the redirection target address and type information. At the same time, it performs age-based targeted flushing on the instruction fetch pipeline and the missing queue module.

[0138] For the missing queue module, an age vector-based flushing mechanism is used: When the branch prediction module generates a redirection and outputs the redirection point transaction identifier, the missing queue module uses the redirection point transaction identifier as the flush comparison benchmark to perform a targeted flush operation, uniformly clearing missing entries and waiting transactions that are younger than the comparison benchmark time sequence.

[0139] If a missing entry corresponds to only a single waiter transaction: if the waiter transaction identifier is a younger transaction than the flushing benchmark identifier, the missing entry is directly cleared; if it is an older transaction, the missing entry is retained without processing.

[0140] If a missing entry has multiple waiter transactions attached: the missing queue deletes all waiters in the set that are younger than the comparison base identifier; if the waiter set is empty after deletion, the missing entry is reclaimed and cleared; if there are still remaining waiters, the oldest waiter identifier recorded in the entry is updated to the oldest transaction identifier in the remaining set.

[0141] For production lines, fixed-point flushing based on age vectors is employed: The indexing pipeline matches and compares the age of each level of pipeline transaction identifier.

[0142] When a pipeline level transaction identifier matches a redirection point transaction identifier, the instruction fetch pipeline control module updates the pipeline level prediction information to the latest correction result from the branch prediction module, and flushes all younger pipeline level transactions after that level, while retaining older pipeline levels to continue to proceed normally.

[0143] If the match occurs during the instruction commit phase, the instruction fetch pipeline uses the instruction mask corrected by the branch prediction module to complete the subsequent instruction commit or resource allocation to the instruction buffer.

[0144] For the splicing and cutting modules, an age vector-based flushing method is used: If the path identifier corresponding to the remaining half-word data belongs to the young transaction path that was flushed this time, the remaining valid flags will be cleared simultaneously to ensure pipeline data consistency.

[0145] The following application example describes this solution: Application Example 1: Cross-block splicing, cutting, and submission process in the finger retrieval pipeline This embodiment provides an instruction fetch control method suitable for mixed-length instructions. This method can be used with processors that support compressed instructions; this embodiment is preferably adapted to RISC-CV processors, but is not limited thereto.

[0146] In a specific implementation, the instruction fetch frontend is configured with a multi-level instruction fetch pipeline. The pipeline levels can be named IF0, IF1, IF2, and IF3. The number of pipeline levels and the functional division of each level can be flexibly adjusted, as long as the splicing, pre-decoding, and consistency verification described in this article can be achieved.

[0147] During the IF0 phase, the instruction fetch pipeline control module receives a main fetch request or prefetch request from the instruction fetch target queue, and simultaneously initiates a virtual address to physical address mapping query to the instruction translation back buffer module. It also initiates an array access request to the instruction cache module. If the current instruction fetch spans two cache line boundaries, the instruction fetch pipeline control module can trigger accesses to adjacent cache lines in parallel, such as through atomic double allocation or step-by-step allocation, or employ an equivalent double-line access strategy.

[0148] In the IF1 phase, the instruction fetch pipeline control module receives the physical address or exception information returned by the instruction translation back buffer module, completes the instruction cache module's tag array comparison, and determines the cache hit status. When the instruction cache module hits, the instruction fetch pipeline control module receives data read from the instruction cache module's data array and concatenates the read results from multiple memory banks into a fetch block data. The fetch block data is preferably a continuous byte data of the cache line width, such as 64 bytes. When the instruction cache module misses, the instruction fetch pipeline control module generates an allocation or merge request for the missing queue module, carrying the cache line-aligned physical address, transaction identifier, and age vector.

[0149] In the IF2 stage, the fetch pipeline control module generates a half-word alignment bit. The fetch pipeline control module checks the validity of the last half-word alignment bit of the previous fetch block. If the last half-word alignment bit belongs to the high 16 bits of a valid 32-bit instruction and is not covered by the prediction block termination mask, the fetch pipeline control module saves the half-word alignment bit and sets a valid flag. Subsequently, the fetch pipeline control module concatenates the remaining half-word alignment bit with the current fetch block data to form a continuous byte stream. The width of the continuous byte stream is preferably "cache line width plus half-word alignment bit", for example, 66 bytes. The fetch pipeline control module steps by half-word alignment bits and segments the instruction code in 4-byte windows. The fetch pipeline control module outputs the instruction code window sequence and generates the corresponding instruction validity vector and pre-decoding information. If the remaining half-word alignment bit is invalid or the continuity condition is not met, the half-word alignment bit is invalid, and the fetch pipeline control module only segments the current fetch block data.

[0150] In the IF3 stage, the instruction fetch pipeline control module performs a consistency check on the control flow information obtained from pre-decoding. The module compares the branch or jump target address calculated by pre-decoding with the predicted target address provided by the branch prediction module. Simultaneously, the module performs a consistency check on whether the instruction is a control flow instruction and whether a jump is predicted. If the consistency check passes, the module pre-allocates resources to the target address based on the instruction mask vector. If the consistency check fails, the module generates a redirection and outputs the redirection target, while simultaneously triggering a directional flush based on the age vector.

[0151] Application Example 2: Miss merging and bypass forwarding mechanism for a missing queue module with master fetch reservation This embodiment, based on the instruction fetch pipeline of Embodiment 1, provides a missing queue management mechanism. This mechanism is used to handle instruction cache module missing requests, merge multiple missing requests for the same cache line, and provide bypass data to the instruction fetch pipeline.

[0152] The number of entries N in the missing queue module is a configurable parameter. The missing queue module sets R reserved entries for primary fetching of missing requests. The reservation policy is constrained as follows: primary fetching of missing requests can use any free entries, including reserved entries; prefetching of missing requests cannot occupy reserved entries. An example configuration could be N=8 and R=2, but this example does not constitute a limitation.

[0153] When an instruction cache miss occurs, the instruction fetch pipeline control module sends a miss request to the miss queue module. The miss request carries the cache line alignment physical address, transaction identifier, and an optional age vector. The miss queue module matches the cache line address as the key. If an existing entry is matched, the miss queue module performs a dynamic merge. The miss queue module adds the new waiter to the waiter set and maintains the identifier of the oldest transaction in the waiter set. The oldest identifier can be used for subsequent wake-up sorting and for quick determination of targeted flushing. If an existing entry is not matched, the miss queue module allocates a new entry and initiates a read request to the lower-level cache or memory.

[0154] When backfilled data is returned from the next lower level, the missing queue module performs backfilling processing. The missing queue module writes the backfilled data to the instruction cache module and updates the status of the corresponding entries. Simultaneously, the missing queue module provides bypass data to the instruction fetch pipeline control module. Bypass methods include conflict checking bypass and backfilling bypass. Conflict checking bypass is used when the instruction fetch pipeline control module requests cached line data; if the missing queue module already holds ready data, it returns directly. Backfilling bypass is used simultaneously with or in adjacent cycles to provide backfilled data directly to the instruction fetch pipeline control module. When a bypass hits, the instruction fetch pipeline control module selects the bypass data as the instruction fetch data source and continues to complete concatenation, splitting, pre-decoding, and submission.

[0155] Application Example 3: Age Vector-Based Instruction Fetch Pipeline and Missing Queue Module Directed Flushing Implementation This embodiment provides a directional flushing control method. This method handles redirections triggered by a branch prediction module or pre-decoding consistency check. The method uses transaction identifiers or age vectors as the basis for comparison and employs circular comparison logic to handle wraparound.

[0156] When the branch prediction module issues a redirection, or when the instruction fetch pipeline control module determines a prediction error during the consistency check phase, the system generates a redirection baseline identifier F. F can be equivalently mapped to an age vector. The directional flushing control module compares each stage of the instruction fetch pipeline with F as the baseline. Pipeline stages younger than F are flushed. Pipeline stages matching F are updated with corrected prediction information and instruction masks. Pipeline stages older than F are retained and continue to advance.

[0157] The targeted flush control module sends a front-end targeted flush request along with F to the missing queue module. The missing queue module performs selective deletion on the entries and the waiter set. Entries younger than F are cleared. Waits younger than F within an entry are deleted. If the waiter set is empty after deletion, the entry is cleared. If the waiter set is not empty, the oldest waiter identifier is updated to the oldest among the remaining waiters. Entries that have been backfilled but only correspond to young waiters are also cleared under this rule, thus preventing erroneous paths from continuing to occupy resources.

[0158] The logic for preserving residual half-word alignment is consistent with the logic for targeted flushing. If the transaction to which the residual data belongs is younger than F, the residual validity flag is cleared. If the transaction to which the residual data belongs is older than F, it can be retained. Whether to retain it or not can be determined by the implementation strategy, but it should be ensured that cross-path splicing does not occur.

[0159] Application Example 4: Parallel Allocation of Instruction Buffers and Low-Latency Pass-Through Implementation The instruction buffer module employs a multi-entry, multi-memory array architecture. The number of entries and the number of entries per entry are configurable parameters. An example structure has 8 entries and 16 entries per entry, but this example is not intended to be limiting. The instruction buffer module maintains an entry allocation pointer and an entry allocation pointer. The entry allocation pointer is used to select the target entry sequence when writing multiple instructions. The entry allocation pointer is used to locate a free entry within the selected entry. Pointer updates can employ a circular shift algorithm or an equivalent ring allocation algorithm to achieve parallel routing and writing of multiple instructions within a single cycle.

[0160] When the instruction buffer module is detected to be empty and a valid output is generated in the IF3 phase of the current cycle, the instruction pass-through issue path can be enabled. The pass-through path directly bypasses the oldest instructions and outputs them to the back-end decoder stage. The number of pass-through instructions is a configurable parameter. The pass-through issue operation can be performed in parallel with the write operation to the instruction buffer, or the instruction buffer write process can be selectively skipped when the pass-through condition is met. The specific scheduling strategy can be flexibly configured according to the implementation performance and timing goals, but the overall system must strictly ensure that the original instruction dispatch order and exception handling semantics are not violated.

[0161] Application Example 5: Implementation of Blocking, Injecting, and Full Flushing for Front-End Anomalies and Bus Errors This embodiment provides an exception and error handling process. Exception sources include, but are not limited to, exceptions to the instruction translation back buffer module, instruction fetch permission exceptions, page faults, and bus errors returned when the miss queue module initiates a read from the lower-level cache or memory.

[0162] When an anomaly or bus error is detected, the instruction fetch front end immediately blocks error propagation. This blocking includes stopping the use of untrusted data for cross-block concatenation and pre-decoding, stopping the writing of untrusted data to the instruction buffer module, and stopping the submission of normal instruction packets to the instruction buffer module. Subsequently, the instruction fetch front end generates exception injection information. This exception injection information can be sent to the instruction buffer module as a placeholder instruction table entry or an equivalent exception table entry, carrying the exception cause code and exception flags, so that the back end can handle the exception according to the architecture.

[0163] In the exception handling path, the instruction fetch frontend triggers a full flush. This full flush operation comprehensively covers the status of all in-transit transactions in the instruction fetch pipeline, all entries in the missing queue module and their associated waiter sets, as well as the remaining half-word storage status, achieving a complete clearing of all error states of the instruction fetch frontend. During the full flush, the instruction fetch frontend synchronously stops receiving new requests from the instruction fetch target queue to avoid new requests interfering with the exception handling process. After the backend exception handling program completes execution and sends a recovery or reset signal back to the instruction fetch frontend, the instruction fetch frontend releases the blocking and flushing state and restarts the normal instruction fetch process.

[0164] Application Example 6: Implementation of Early Wake-up and Forwarding Timing Based on Missing Queue Module Backfilling Bypass This embodiment presents a miss recovery timing scheme based on missing queue module bypass. This timing scheme is used to reduce recovery latency when the instruction fetch request is missing from the instruction cache module. The timing scheme uses symbols such as T0 and Tn to represent relative periods, and the specific waiting period is determined by the latency of the lower-level cache and interconnect.

[0165] During cycle T0 to T2, a master instruction fetch request misses in the instruction cache module. The instruction fetch pipeline control module sends an allocation request to the missing queue module and preferentially uses the master instruction fetch reserved entry. The missing queue module records the cache line's aligned physical address and transaction identifier, and records the transaction's age vector. The missing queue module then sends a read request to the lower-level cache.

[0166] During cycle Tn, the missing queue module receives backfill data and marks it as ready. The missing queue module can perform early wake-up, which involves sending a wake-up instruction to the instruction fetch pipeline control module before the backfill instruction buffer module completes. Early wake-up carries a transaction identifier so that the instruction fetch pipeline control module can align the replay objects.

[0167] In cycle Tn+1, the instruction fetch pipeline control module receives a wake-up instruction and replays the corresponding transaction into the instruction fetch pipeline. Simultaneously, the missing queue module initiates a refill request to the instruction buffer module. The replay transaction reaches the read phase in a subsequent cycle. The instruction fetch pipeline control module performs an address conflict check and confirms that the missing queue module already holds ready data. The missing queue module forwards the refill data to the instruction fetch pipeline control module via a bypass channel. Based on this, the instruction fetch pipeline control module completes the splicing, segmentation, and pre-decoding, and continues to submit instruction packets to the instruction buffer module.

Claims

1. An instruction fetch control system based on RISC-V architecture, characterized in that, Includes the following modules: The instruction fetch target queue module is used to respond to instruction fetch requests, schedule and output the instruction fetch target address; The instruction translation backup buffer module is used to complete the virtual address to physical address mapping of the target address and provide three distinguishable results: hit, missing, and exception. The instruction cache module determines cache hits based on the physical address output by the instruction translation back buffer module. When a hit occurs, it provides fetch block data; when a miss occurs, it provides missing information and sends it to the missing queue module. The splicing and cutting module is used to provide the ability to splice cache line data when there is a requirement for half-word alignment when the cache line output by the instruction cache module has cross-line instruction fetching; and to perform instruction window cutting in fixed steps under the constraints of cache line configuration parameters. The missing queue module is used to take over missing transactions when the physical address of the instruction cache module is missing. It implements functions such as missing entry storage, entry allocation / merging, cache line address matching, waiter set management, issuing queue requests, backfill reception and write control, and bypass output. It adopts an entry reservation constraint strategy to reserve dedicated entries for missing master instruction fetch. The pre-decoding module is used to pre-decode the instruction window cut by the splicing and cutting module, compare the pre-decoding result with the target address of the branch prediction module, and generate a redirection request and redirection target when an error is detected. The directional flushing module is used to generate a comparison benchmark and execute an age vector-based flushing strategy in a redirection scenario. It implements the logic for benchmark selection, age comparison, pipeline-level flushing control, missing queue flushing triggering, half-word alignment flushing, and full flushing coordination. The instruction fetch pipeline control module interacts with the instruction fetch target queue module to obtain instruction fetch transaction information and selects whether to advance the current transaction if it hits or handle missing transactions. At the same time, it combines the information from the missing queue module to implement allocation, merging, pause, and replay control for missing transactions. Combined with the redirection request, a redirection target is generated and a targeted flush is triggered.

2. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... The specific operations for assigning / merging entries in the missing queue module are as follows: The missing queue module matches missing requests issued by the instruction fetch pipeline control module, which include cache line alignment address, instruction fetch type, transaction identifier, and age vector, using the cache line alignment address as the key, and merges missing requests with the same address.

3. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... The alignment of half-characters in the splicing and cutting module is as follows: The splicing and cutting module determines whether to save the last half-word of the previous fetch block based on the candidate half-word data, half-word boundary judgment information, and transaction identifier information latched by the fetch pipeline control module. If saved, the half-word alignment position is set to valid, and when the splicing conditions are met, cross-cache line splicing is performed.

4. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... The concatenation of cached row data in the concatenation and splitting module must simultaneously meet the following conditions: Cross-block instructions are uncompressed instructions; the last two bytes of the cache line mark the beginning of a valid instruction; the absence of a predicted jump control flow instruction before the instruction stream causes the instruction fetch block to terminate prematurely.

5. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... The cutting operation in the command window of the splicing and cutting module is as follows: Under the constraints of block boundary and length configuration parameters provided by the instruction fetch pipeline control module, the cutting window, offset and valid candidate information are generated, and the continuous byte data stream is cut into instructions with half-word alignment.

6. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... The age vector in the directional flushing module is: The transaction identifier and optional ring position information provided by the instruction fetch pipeline control module are mapped to an age vector.

7. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... In the pre-decoding module, after comparing the pre-decoding result with the target address of the branch prediction module, the following steps are also included: When an anomaly is detected, the output includes the redirection request, error type, error location index, and redirection target, along with a benchmark identifier for directional flushing.

8. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... The age vector-based flushing strategy operation in the targeted flushing module is as follows: The missing queue module compares the time-series age of entries and their internal waiters based on the comparison benchmark identifier, selectively deletes younger entries or younger waiters within entries, and updates the age identifier. For the splicing and cutting module, perform transaction age matching verification on residual data that does not meet the splicing legality requirements across cache lines, and set the half-word alignment valid flag of the transaction belonging to the flush path to invalid.

9. The instruction fetch control system based on RISC-V architecture according to claim 1, characterized in that... The instruction cache module provides missing information when an instruction is missing: When the instruction cache module is missing the instruction fetch block corresponding to the target address, it returns a missing indication and triggers the missing queue module to establish a missing transaction. At the same time, the instruction cache module also receives the backfill request and backfill data returned by the missing queue module, and writes the backfill data into the cache array.

10. A method for instruction fetch control based on RISC-V architecture, characterized in that, include: S1. The instruction fetch queue module receives the instruction fetch request, extracts the target address, and the instruction fetch pipeline control module latches the attribute information of the target address. S2. The target address is in the instruction translation back buffer module, which completes the mapping from virtual address to physical address; if the mapping is normal, proceed to S3. S3. In the instruction cache module, a cache hit is determined based on the physical address output by the instruction translation back buffer module. If a cache hit occurs, the missing transaction is executed in S5; if a cache hit occurs, S4 is executed. S4. In the splicing and cutting module, when there is cross-line instruction fetching in the cache line output by the instruction cache module, the cache line data is spliced ​​according to the half-word alignment. Under the constraints of the cache line configuration parameters, the instruction window is cut in a fixed step to generate a continuous target address window sequence, and then S6 is executed. S5. In the missing queue module, receive the front-end request, allocate table entries for missing transactions, and simultaneously send a read request to the underlying storage. After the data is backfilled, write it to the instruction cache module and execute S4. S6. In the pre-decoding module, perform target address pre-decoding and compare the pre-decoding result with the target address of the branch prediction module; If all goes well, pre-allocate resources for the target address to complete the instruction fetch; If an exception occurs, execute S7; S7. In the directional flushing module, flushing is performed on pipeline transactions based on the age vector.