Processor and interrupt control method and apparatus

Abstract

The application discloses a kind of involving computer technical field processor and interruption control method, device.The device includes: hardware interruption control circuit when receiving high priority new hardware interruption request, determine the hardware interruption processing program being executed and the estimated completion time of new hardware interruption processing program, according to task time limit demand generation control signal.Software and hardware interruption association processing circuit is predicted to hardware interruption request in future preset time period, in the software interruption request generated, select target software interruption request corresponding to hardware interruption prediction information same processing task and by same processing core execution, and send to corresponding processing core.Resource regulation circuit adjusts the hardware operating parameter of processor according to the control signal forwarded by processing core cluster.The application can solve the problem of large task processing delay in related technology, can effectively improve the real-time processing performance of processor, meet the user demand of high real-time application scenario.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a processor and its interrupt control method and apparatus. Background Technology

[0002] With the increasing application of RISC-V (Reduced Instruction Set Computer-V) based processors in high real-time scenarios such as industrial control, electronics, and data storage controllers, higher requirements are being placed on the real-time response performance of their interrupt control systems.

[0003] The RISC-V processors of related technologies process the same real-time task through two independent paths: software interrupts and hardware interrupts. The real-time task processing latency is relatively high, making it difficult to meet the needs of high real-time application scenarios. Summary of the Invention

[0004] This invention provides a processor and its interrupt control method and apparatus, which effectively improve the real-time processing performance of the processor, reduce the processing latency of real-time tasks, and enable real-time tasks of different priorities to simultaneously meet the corresponding time limit requirements, thus meeting the user needs of high real-time application scenarios.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In one aspect, the present invention provides an interruption control device, comprising: The hardware interrupt control circuit is connected to the hardware interrupt controller and the processing core cluster. When it receives a new hardware interrupt request from the hardware interrupt controller, it determines the estimated completion time of the current hardware interrupt handler and the new hardware interrupt handler corresponding to the new hardware interrupt request, and generates program execution control signals according to the task time limit requirements. The hardware and software interrupt association processing circuit is connected to the processing core cluster. It predicts hardware interrupt requests within a preset time period in the future. Among the generated software interrupt requests, it selects the target software interrupt request that corresponds to the same processing task as the hardware interrupt prediction information and is executed by the same processing core, and sends at least one target software interrupt request to the corresponding processing core. The resource regulation circuit is connected to the processing core cluster, receives program execution control signals sent by the processing core cluster, and adjusts the processor's hardware operating parameters according to the program execution control signals. Among them, the new hardware interrupt request has a higher priority than the current hardware interrupt request. The program execution control signal is used to control the execution order of the new hardware interrupt request and the current hardware interrupt request, and to enable the resource adjustment circuit.

[0006] Another aspect of the present invention provides an interrupt control method applicable to the above-mentioned interrupt control device, comprising: When a new hardware interrupt request is received from the hardware interrupt controller, the estimated completion time of the currently executing hardware interrupt handler and the new hardware interrupt handler corresponding to the new hardware interrupt request are determined, and program execution control signals are generated according to the task time limit requirements. Predict hardware interrupt requests within a preset time period in the future, select the target software interrupt request from the generated software interrupt requests that corresponds to the hardware interrupt prediction information, is executed by the same processing core, and send the target software interrupt request to the processing core. It receives program execution control signals sent by the processing core cluster and adjusts the processor's hardware operating parameters according to the program execution control signals; Among them, the new hardware interrupt request has a higher priority than the current hardware interrupt request. The program execution control signal is used to control the execution order of the new hardware interrupt request and the current hardware interrupt request, and to enable the resource adjustment circuit.

[0007] The present invention also provides a processor employing a reduced instruction set computer architecture, including the aforementioned interrupt control device.

[0008] The advantages of the technical solution provided by this invention are as follows: During the hardware interrupt handling process, when a new hardware interrupt request with a higher priority is received after priority arbitration by the hardware interrupt controller, the hardware interrupt control circuit first predicts the time required for the current hardware interrupt handler and the new hardware interrupt handler to complete their respective tasks. It then generates a program execution control signal based on the task time limit requirements. This ensures that the execution order of the current interrupt and the new interrupt depends not only on their priorities but also on the combined influence of their estimated completion times and time limit constraints. This reduces the possibility that the current hardware interrupt handler may exceed its completion time limit due to repeated preemption by higher-priority interrupts. The software and hardware interrupt association processing circuit predicts future hardware interrupt requests and selects target software interrupt requests from the generated software interrupt requests that belong to the same processing task as the predicted hardware interrupt information and are processed by the same processing core. This ensures that the software interrupt service and hardware interrupt service corresponding to the same processing task are executed sequentially on the same processing core, reducing the waiting time between software and hardware interrupts. This achieves joint processing of software and hardware interrupts within the same process, improving the interrupt process processing speed and effectively reducing the processing latency of real-time tasks. After receiving the program execution control signal forwarded by the processing core cluster, the resource regulation circuit adjusts the processor's hardware operating parameters. This increases the likelihood of interrupt handlers completing on time without software intervention, meeting the real-time requirements of more tasks while increasing power consumption. It maximizes the guarantee that the real-time performance of multiple real-time tasks meets requirements, ensuring the overall real-time performance and security of the RISC-V processor. Furthermore, this invention also provides a corresponding method and processor for interrupt control, which offer significant advantages. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the present invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of the hardware framework applicable to the interrupt control methods of related technologies; Figure 2 This is a flowchart illustrating the interruption control method for related technologies. Figure 3 A schematic diagram of the structural framework of the interrupt control device provided by the present invention in an exemplary embodiment; Figure 4 A schematic diagram of the hardware framework applicable to the interrupt control method provided by the present invention; Figure 5 A schematic diagram of the structural framework of the hardware interrupt control circuit provided by the present invention in an exemplary embodiment; Figure 6 A schematic diagram of the structural framework of the hardware and software interrupt association processing circuit provided by the present invention in an exemplary embodiment; Figure 7 A schematic diagram of the structural framework of the resource regulation circuit provided by the present invention in an exemplary embodiment; Figure 8 A flowchart illustrating an interrupt control method provided by the present invention; Figure 9 This is a schematic diagram of the processor provided by the present invention in an exemplary embodiment. Detailed Implementation

[0011] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. In this specification and the aforementioned drawings, the terms "first," "second," "third," "fourth," etc., are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. The term "exemplary" means "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0012] In applications with high real-time requirements, such as industrial automation control, automotive electronics and autonomous driving, communication network equipment and solid-state drive controllers, the timeliness of external event response and task switching directly affects data processing capabilities and operational stability. Therefore, the response speed and processing efficiency of the interrupt control system to interrupt requests directly affect whether the task can be completed within the specified time limit.

[0013] The related RISC-V CPU (Central Processing Unit) includes multiple processing cores, such as RISC-V Cores. Figure 1 As shown, its interrupt control system includes a software interrupt controller and a hardware interrupt controller. The software interrupt controller generates inter-core interrupts and timer interrupts. Inter-core interrupts are triggered by other cores or the core itself (i.e., software writes to specified registers) to synchronize data or wake up processes. Timer interrupts are periodic interrupts generated when the real-time counter exceeds the comparator register value. Interrupt requests are directly notified to the target core via private signal lines within the processor core, without priority arbitration. After detecting the software interrupt, the RISC-V core jumps to the corresponding interrupt handler function entry point (memory address) to execute the interrupt. The hardware interrupt controller's processing flow is as follows:Figure 2 As shown, it receives physical interrupt signals from external interfaces of the processor, such as the IIC (Inter-Integrated Circuit) interface, DMA (Direct Memory Access) interface, and EMAC (Ethernet Media Access Controller) interface. Each interface generates more than one interrupt. Interrupt response order is determined by preset priority, and interrupt requests are sent to the corresponding processing cores. In real-time task processing, for the same real-time task, software interrupts and hardware interrupts are handled by two independent paths, with the processing of the two types of interrupts separated. When the hardware interrupt corresponding to the same task is completed, if the related software interrupt has not yet been executed, the task must wait for the software interrupt to complete before it can finish processing. This results in an extension of task processing time and reduces the processor's real-time responsiveness.

[0014] Furthermore, in the actual operation of the hardware interrupt controller, when a hardware interrupt is being executed by the processor core, if a new hardware interrupt request with a higher priority is generated simultaneously by an external interface, the hardware interrupt controller will pause the execution of the current interrupt handler, save its context, and execute the higher-priority interrupt handler. The paused interrupt handler will resume execution after the higher-priority interrupt has finished processing. For example, the priority sequence of interface_0 is 4, the priority sequence of interface_1 is 2, the priority sequence of interface_2 is 3, and the priority sequence of interface_3 is 1. The smaller the sequence value, the higher the priority. If interrupts from interface 0 and interface 2 arrive simultaneously, the hardware interrupt controller will prioritize processing the interrupt handler corresponding to interface 2 according to its priority order, while that handler is still executing (not yet finished). When an interrupt is triggered by interface 1, the hardware interrupt controller pauses / suspends the interrupt handler for interface 2, prioritizing the interrupt handler for interface 1. Once the interrupt handler for interface 1 finishes, the paused interrupt handler for interface 2 is executed. However, if a higher-priority interface (e.g., interface 1) generates an interrupt, the interrupt handler for interface 2 will be paused / suspended again until no higher-priority interrupt occurs. This process prioritizes processor core resources for handling the highest-priority interrupt. However, the currently executing interrupt handler may also correspond to a real-time task with time constraints. Its execution may be interrupted due to processor core resources being preempted by higher-priority interrupts, extending the processing time of that task and potentially causing it to fail within the specified timeframe, thus leading to the failure of the more critical task.

[0015] As can be seen from the above, the interrupt control method of the relevant technology separates the software interrupts and hardware interrupts associated with the same real-time task, resulting in an increase in the overall processing delay of the real-time task. It is also difficult to meet the completion time limits of multiple interrupt tasks with different priorities at the same time, which limits the task processing capability of the processor in real-time application scenarios.

[0016] Therefore, this invention, by adding a software / hardware interrupt association processing circuit, a hardware interrupt control circuit, and a resource adjustment circuit inside the processor, achieves joint processing of software and hardware interrupts for the same process, improving the processing speed and real-time performance of the task process. Simultaneously, it comprehensively analyzes the real-time performance of multiple interrupt-corresponding processes, ensuring that the real-time performance of multiple processes meets requirements to the greatest extent possible. It also comprehensively manages and controls hardware interrupts and synchronously designs resource adjustment circuits. While increasing power consumption, it satisfies the real-time performance requirements of more processes, thereby ensuring the overall real-time performance and security of the RISC-V CPU. After introducing the technical solution of this invention, various non-limiting embodiments of this invention will be described in detail below with reference to the accompanying drawings and specific implementation details.

[0017] Please see first. Figure 3 According to the interrupt control device provided by the present invention, it can be deployed inside a processor employing a reduced instruction set computer architecture. In some embodiments of the device, it may include the following: The interrupt control device in this embodiment includes a hardware interrupt control circuit 31, a hardware / software interrupt association processing circuit 32, and a resource adjustment circuit 33. The input terminal of the hardware interrupt control circuit 31 is connected to the hardware interrupt controller, and its output terminal is connected to the processing core cluster. The inputs and outputs of the hardware / software interrupt association processing circuit 32 and the resource adjustment circuit 33 are both connected to the processing core cluster. The hardware interrupt control circuit 31 is configured to: when receiving a new hardware interrupt request sent by the hardware interrupt controller, determine the estimated completion time of the currently executing hardware interrupt handler and the new hardware interrupt handler corresponding to the new hardware interrupt request, and generate a program execution control signal according to the task time limit requirements. The hardware / software interrupt association processing circuit 32 is configured to: predict hardware interrupt requests within a preset time period in the future, select target software interrupt requests that correspond to the same processing task as the hardware interrupt prediction information and are executed by the same processing core from the generated software interrupt requests, and send at least one target software interrupt request to the corresponding processing core. The resource adjustment circuit 33 is configured to: receive the program execution control signal sent by the processing core cluster and adjust the processor's hardware operating parameters according to the program execution control signal. The hardware interrupt control circuit 31, the software and hardware interrupt association processing circuit 32, and the resource adjustment circuit 33 can be written in any suitable hardware description language, and obtained through logic synthesis and physical implementation to achieve the corresponding functions.

[0018] In this embodiment, as Figure 4As shown, the hardware interrupt controller is a hardware component within the processor used to receive interrupt request signals initiated by external devices and arbitrate and distribute them according to priority. The processing core cluster is a group of processor cores connected to the software interrupt controller, and each core can independently execute instruction streams. The program execution control signal is a signal generated by the hardware interrupt control circuit 31, which is sent to the processing core cluster to control the execution order of new hardware interrupt requests and current hardware interrupt requests, and to enable the resource adjustment circuit 33. A new hardware interrupt request is a hardware interrupt request recently received by the hardware interrupt controller and, after priority arbitration, has a higher priority than the currently processed hardware interrupt request. The current hardware interrupt request is the hardware interrupt request for which the processing core is currently executing its interrupt handler. The priority is a value pre-assigned to each hardware interrupt request; the smaller the value, the higher the priority. In actual products, the hardware interrupt control circuit 31 and the hardware interrupt controller can be connected via an internal bus. The hardware interrupt controller sorts the received external interrupt request signals by priority and sends the highest priority interrupt request to the hardware interrupt control circuit 31. The hardware interrupt control circuit 31 can, for example, obtain the completion status information of the interrupt handler currently being executed by each processing core through configuration registers. The hardware interrupt control circuit 31 operates as follows: When a new hardware interrupt request is received from the hardware interrupt controller, the hardware interrupt control circuit 31 first obtains the completion status of the currently executing hardware interrupt handler, including the number of instructions executed and the actual time consumed by each instruction. Simultaneously, the hardware interrupt control circuit 31 also obtains the instruction content of the new hardware interrupt handler corresponding to the new hardware interrupt request. A hardware interrupt handler is a sequence of instructions stored in memory, executed sequentially by the processing core. Its starting address is the address of the first instruction in memory, and its ending address is the address of the last instruction. Each hardware interrupt handler is assigned a task time limit by the operating system, which is the maximum allowed time from start to finish. The hardware interrupt control circuit 31 estimates the remaining completion time of the currently executed hardware interrupt handler based on the instructions already executed, and simultaneously estimates the execution time of the new hardware interrupt handler. Then, based on the estimated completion time and task time limit of each interrupt handler, it generates a program execution control signal through comparison and judgment logic. Because the hardware interrupt control circuit 31 considers the estimated completion time and time limit constraints of both the current interrupt and the new interrupt when generating the program execution control signal, the execution order of the interrupt program depends not only on the priority but also on the actual situation of whether the two interrupts can be completed on time. This reduces the possibility that the current hardware interrupt handler may exceed its completion time limit due to repeated preemption by high-priority interrupts.

[0019] In this embodiment, the hardware interrupt prediction information is the prediction result of the software / hardware interrupt association processing circuit 32 for the processing cores that will initiate hardware interrupt requests within a preset future time period. The preset future time period is a pre-configured time length, such as 4 milliseconds. The same processing task refers to a holistic task consisting of software and hardware operations triggered by the same external event and logically completed sequentially or collaboratively. The software interrupt request is an inter-core interrupt request or a timer interrupt request generated by the software interrupt controller. The target software interrupt request is the software interrupt request selected by the software / hardware interrupt association processing circuit 32 that needs to be sent to the corresponding processing core. In actual products, the software / hardware interrupt association processing circuit 32 can be connected to the software interrupt controller and the processing core cluster via internal signal lines. The software interrupt controller maintains a software interrupt request queue to temporarily store generated but not yet sent software interrupt requests. The software / hardware interrupt association processing circuit 32 reads the target core identifier and task identifier of each software interrupt request from the software interrupt request queue and performs filtering and matching based on the hardware interrupt prediction information. The hardware / software interrupt association processing circuit 32 operates as follows: First, it predicts which processing cores will execute hardware interrupt handlers within a preset time period. After obtaining the hardware interrupt prediction information, the circuit checks the software interrupt requests already generated in the software interrupt controller. It selects software interrupt requests that belong to the same processing task and are processed by the same processing core as the hardware interrupt prediction information as target software interrupt requests. Then, the selected target software interrupt requests are sequentially distributed to the corresponding processing cores. By actively filtering software interrupt requests from the generated software interrupt requests that belong to the same processing task and are processed by the same processing core as the predicted hardware interrupts, the hardware / software interrupt service and hardware interrupt service corresponding to the same processing task are executed sequentially on the same processing core, reducing the mutual waiting time caused by software interrupts and hardware interrupts being processed by different paths.

[0020] In this embodiment, the processor's hardware operating parameters refer to adjustable parameters that affect the speed at which the processing core executes software interrupt routines. These parameters include at least the processing core's operating frequency, operating voltage, memory access bandwidth, and the object to which the software interrupt routine is executed. In practical applications, the resource adjustment circuit 33 may contain a set of control and configuration registers, through which the aforementioned hardware operating parameters can be read, written, and adjusted. The workflow of the resource adjustment circuit 33 is as follows: When the processing core cluster receives the program execution control signal generated by the hardware interrupt control circuit 31, the processing core cluster forwards the signal to the resource adjustment circuit 33. The resource adjustment circuit 33 parses the received program execution control signal. If it finds that the signal contains a resource adjustment enable bit, it adjusts the operating parameters of the corresponding processing core according to the adjustment object specified in the signal. After receiving the program execution control signal forwarded by the processing core cluster, the resource adjustment circuit 33 directly adjusts the processor's hardware operating parameters, increasing the likelihood of the current interrupt handler or new interrupt handler completing on time without software intervention.

[0021] In the technical solution provided in this embodiment, during the hardware interrupt handling process, when a new hardware interrupt request with a higher priority is received after priority arbitration by the hardware interrupt controller, the hardware interrupt control circuit 31 first predicts the time required for the current hardware interrupt handler and the new hardware interrupt handler to complete their respective tasks, and generates a program execution control signal based on the task time limit requirements. This ensures that the execution order of the current interrupt and the new interrupt depends not only on their priorities but also on the combined influence of their estimated completion times and time limit constraints, thereby reducing the possibility that the current hardware interrupt handler may exceed its completion time limit due to repeated preemption by higher-priority interrupts. The software and hardware interrupt association processing circuit 32 predicts future hardware interrupt requests and selects target software interrupt requests from the generated software interrupt requests that belong to the same processing task as the predicted hardware interrupt information and are processed by the same processing core for distribution. This ensures that the software interrupt service and hardware interrupt service corresponding to the same processing task are executed sequentially on the same processing core, reducing the waiting time between software interrupts and hardware interrupts, realizing the joint processing of software interrupts and hardware interrupts in the same process, improving the interrupt process processing speed, and effectively reducing the processing latency of real-time tasks. After receiving the program execution control signal forwarded by the processing core cluster, the resource adjustment circuit 33 adjusts the hardware operating parameters of the processor. Without software intervention, it increases the possibility of interrupt handlers completing on time. While increasing power consumption, it meets the real-time requirements of more tasks and ensures that the real-time performance of multiple real-time tasks meets the requirements to the greatest extent possible, thus ensuring the overall real-time performance and security of the RISC-V processor.

[0022] Based on the above embodiments, this embodiment further defines the program execution control signal generation process of the hardware interrupt control circuit 31, which may include the following: When a new hardware interrupt request with a higher priority than the currently executing hardware interrupt request is received from the hardware interrupt controller, the remaining instruction completion time is estimated based on the total number of instructions in the current hardware interrupt handler and the information on completed instructions; the corresponding task completion time is estimated based on the different execution order of the new hardware interrupt request; and a program execution control signal is generated based on the remaining instruction completion time, the completion time of each task, and the time limit requirements of the current hardware interrupt request and the new hardware interrupt request.

[0023] In this embodiment, the hardware interrupt control circuit 31 receives the trigger signal of a new hardware interrupt request from the hardware interrupt controller. When the hardware interrupt controller determines that the priority value of the newly arrived external interrupt request is less than the priority value of the interrupt request currently being executed by the processing core, it determines that the priority of the new interrupt request is higher. The hardware interrupt controller can send the identifier and priority information of the new hardware interrupt request to the hardware interrupt control circuit 31 through the bus.

[0024] The total number of instructions in the current hardware interrupt handler can be obtained by analyzing the program body using compiler tools when the program is loaded into memory. This information can be stored, for example, in the interrupt vector table or in the metadata field of the program header. The hardware interrupt control circuit 31 can obtain the total number of instructions by reading these fields. The completed instruction information of the current hardware interrupt handler includes the number of instructions that the processing core has executed from the start of the program to the current moment, as well as the time consumed by each executed instruction. The time consumed can be determined, for example, by the number of clock cycles. This information can be obtained through the performance monitoring counter inside the processing core. The hardware interrupt control circuit 31 subtracts the number of completed instructions from the total number of instructions to obtain the remaining number of instructions, and then multiplies it by the average execution time of the completed instructions to obtain the estimated value of the remaining instruction completion time. Different execution orders of new hardware interrupt requests refer to the execution order of the new hardware interrupt request and the current hardware interrupt request. One execution order could be to immediately pause the current hardware interrupt handler and directly execute the new hardware interrupt handler. Another execution order could be to wait for the current hardware interrupt handler to complete before executing the new hardware interrupt handler. The hardware interrupt control circuit 31 calculates the total time required for a new hardware interrupt handler to complete execution from start to finish under different execution sequences. During calculation, the hardware interrupt control circuit 31 obtains the total number of instructions in the new hardware interrupt handler and estimates it by referring to the actual average execution time of similar instructions in currently executing hardware interrupt handlers. The task time limit requirement is the completion time limit value issued by the operating system to the hardware interrupt control circuit 31 through the interrupt controller when a hardware interrupt is triggered. The current hardware interrupt request and the new hardware interrupt request each have independent task time limit requirements. The remaining instruction completion time calculated by the hardware interrupt control circuit 31 in the previous step, and the completion time of each task obtained in the second step, are compared with the respective task time limit requirements of the current hardware interrupt request and the new hardware interrupt request. Based on the comparison results, the program execution control signal that can meet the time limit requirements of each hardware interrupt request is determined.

[0025] As can be seen from the above, this embodiment estimates the remaining instruction completion time of the current hardware interrupt handler and the task completion time of the new hardware interrupt request under different execution orders, and generates program execution control signals in combination with task time limit requirements. This enables the hardware interrupt control circuit 31 to determine the interrupt execution order based on quantified execution time data rather than fixed priority rules, thereby realizing the comparison and dynamic scheduling of the completion time limits of interrupt handlers with different priorities, reducing interrupt processing timeouts caused by unconditional preemption, and improving the speed and security of real-time task processing.

[0026] Based on the above embodiments, this embodiment further defines how the hardware interrupt control circuit 31 generates different types of program execution control signals, which may include the following: Based on the completion time of the first task in the first execution scenario of the new hardware interrupt request, determine the estimated duration of the first task corresponding to the first execution scenario; based on the remaining instruction completion time and the completion time of the second task in the second execution scenario, determine the estimated duration of the second task corresponding to the second execution scenario; if the estimated duration of the first task is greater than the maximum completion time of the new hardware interrupt request, generate a first type of program execution control signal and send it to the processing core cluster; if the estimated duration of the first task is less than the maximum completion time of the new hardware interrupt request, and the estimated duration of the second task is greater than the maximum completion time of the new hardware interrupt request, generate a second type of program execution control signal and send it to the processing core cluster; if the estimated duration of the first task is less than the maximum completion time of the new hardware interrupt request, and the estimated duration of the second task is less than the maximum completion time of the new hardware interrupt request, generate a third type of program execution control signal.

[0027] In the first execution scenario, the task execution process of the current hardware interrupt request is terminated, and a new hardware interrupt request is executed directly. In this scenario, the time required for the new hardware interrupt handler to complete execution is the first task completion time. The hardware interrupt control circuit 31 directly uses this first task completion time as the first task estimated duration corresponding to the first execution scenario. In the second execution scenario, after the task execution of the current hardware interrupt request is completed, a new hardware interrupt request is executed. In this scenario, the new hardware interrupt handler needs to wait for the current hardware interrupt handler to complete execution. Therefore, the second task estimated duration corresponding to the second execution scenario is equal to the first task estimated duration plus the remaining instruction completion time. The maximum completion time is a time limit pre-configured by the operating system for each hardware interrupt request. The maximum completion time of the new hardware interrupt request is stored in the time limit register inside the hardware interrupt control circuit 31, which is written by the operating system via the data bus during power-on initialization. The first type of program execution control signal is a control signal that continues the execution of the current hardware interrupt handler, transfers the execution of the new hardware interrupt handler corresponding to the new hardware interrupt request to other processing cores, and enables the resource adjustment circuit 33; the second type of program execution control signal is a control signal that suspends the execution of the current hardware interrupt handler, executes the new hardware interrupt request, and enables the resource adjustment circuit 33; the third type of program execution control signal is a control signal that continues the execution of the current hardware interrupt handler, and executes the new hardware interrupt request after the current hardware interrupt handler has been completed.

[0028] In this embodiment, when the estimated duration of the first task exceeds the maximum completion time of the new hardware interrupt request, it means that even if the current hardware interrupt handler is immediately paused and the processing cores are allowed to execute the new hardware interrupt handler at full capacity, the completion time of the new hardware interrupt handler will still exceed its time limit requirement. In this case, the hardware interrupt control circuit 31 generates a first type of program execution control signal. This signal instructs the processing core cluster to continue executing the current hardware interrupt handler, transfer the new hardware interrupt handler to other processing cores for execution, and simultaneously sends an enable signal to the resource adjustment circuit 33. The resource adjustment circuit 33 attempts to shorten the execution time of the current interrupt handler by adjusting the hardware operating parameters. Since the new hardware interrupt request is transferred to other idle or lightly loaded processing cores for independent execution, while the current processing core continues to execute the original interrupt routine, the two are processed in parallel, which can maximize the chances of both interrupts completing on time. When the estimated duration of the first task is less than or equal to the maximum completion time of the new hardware interrupt request, but the estimated duration of the second task is greater than the maximum completion time of the new hardware interrupt request, it means that if the current hardware interrupt handler is immediately paused, the new hardware interrupt request can be completed on time; however, if the current interrupt is waited for to complete before processing the new interrupt, the new interrupt will time out. In this case, the hardware interrupt control circuit 31 generates a second type of program execution control signal. This signal instructs the processing core cluster to pause the execution of the current hardware interrupt handler and prioritize the execution of the new hardware interrupt handler. At the same time, it sends an enable signal to the resource adjustment circuit 33 to shorten the processing time by increasing the operating frequency or access bandwidth of the processing core, so as to ensure that the new interrupt is completed on time and to minimize the delay caused by the current interrupt being paused. When the estimated duration of the first task is less than or equal to the maximum completion time of the new hardware interrupt request, and the estimated duration of the second task is also less than or equal to the maximum completion time of the new hardware interrupt request, it means that the new hardware interrupt request can meet its time limit requirements regardless of whether the current interrupt is waited for to complete. In this situation, the hardware interrupt control circuit 31 generates a third type of program execution control signal, which instructs the processing core cluster to continue executing the current hardware interrupt handler, and to execute a new hardware interrupt handler after the current hardware interrupt handler has been completed. The resource regulation circuit 33 is not enabled to avoid unnecessary power consumption increases.

[0029] As can be seen from the above, this embodiment generates a first type of program execution control signal to continue executing the current interrupt and transfer the new interrupt when the estimated duration of the first task exceeds the maximum completion time of the new hardware interrupt request; generates a second type of program execution control signal to pause the current interrupt when the estimated duration of the first task does not exceed the time limit but the estimated duration of the second task exceeds the time limit; and generates a third type of program execution control signal for sequential execution when neither of the two time limits are exceeded. This allows the hardware interrupt control circuit 31 to select different interrupt execution paths based on the comparison results between the actual estimated completion time of the current interrupt and the new interrupt and their respective time limit requirements. This avoids the current interrupt timeout caused by the unconditional preemption of the current interrupt by a high-priority interrupt, while ensuring that the new interrupt is completed within the time limit.

[0030] Based on the above embodiments, this embodiment further defines the internal structure of the hardware interrupt control circuit 31 as a first hardware interrupt handling prediction circuit, a second hardware interrupt handling prediction circuit, and a signal trigger generation circuit, such as... Figure 5 As shown, it may include the following: The first hardware interrupt handling prediction circuit, upon receiving a new hardware interrupt request from the hardware interrupt controller with a priority higher than the currently executing hardware interrupt request, estimates the remaining instruction completion time based on the total number of instructions in the current hardware interrupt handler and the information on completed instructions. The second hardware interrupt handling prediction circuit estimates the corresponding task completion time based on the different execution order of the new hardware interrupt request. The signal trigger generation circuit, connected to the outputs of the first and second hardware interrupt handling prediction circuits respectively, generates program execution control signals based on the remaining instruction completion time, the completion time of each task, and the time limit requirements of the current hardware interrupt request and the new hardware interrupt request.

[0031] In this embodiment, the function of the first hardware interrupt handling prediction circuit is to estimate the remaining execution time of the currently executing hardware interrupt handler. Its trigger condition is when the hardware interrupt controller sends a new hardware interrupt request with a higher priority to the hardware interrupt control circuit 31. The remaining instruction completion time can be represented as T_Cur, which is a real-time changing value continuously calculated during the current interrupt handling process. When a new high-priority hardware interrupt request arrives, the value of T_Cur at that moment is cached and used for subsequent processing. The total number of available instructions and the information on completed instructions are obtained from the performance monitoring unit inside the processing core. The total number of available instructions is an integer value representing the number of instructions to be executed in the current interrupt handler. The information on completed instructions includes the number of instructions that have been executed and the number of clock cycles from issuance to retirement for each completed instruction. The first hardware interrupt handling prediction circuit calculates the estimated value of the remaining instruction completion time by multiplying the number of remaining unexecuted instructions by the average number of execution cycles of completed instructions, and outputs this value to the signal trigger generation circuit. The function of the second hardware interrupt handling prediction circuit is to estimate the total time required for the new hardware interrupt handler to execute from start to finish under different execution orders for a new hardware interrupt request, and then output these two task completion times to the signal trigger generation circuit. The two inputs of the signal trigger generation circuit are physically connected to the outputs of the first and second hardware interrupt handling prediction circuits, respectively, receiving the remaining instruction completion time and the completion time of each task. The task time limit requirement is the maximum allowed execution time corresponding to the current hardware interrupt request and the new hardware interrupt request, obtained from the operating system. The signal trigger generation circuit compares the received prediction values ​​with the task time limit requirements and generates a program execution control signal based on the comparison result.

[0032] As can be seen from the above, this embodiment uses a cascaded structure of the first hardware interrupt handling prediction circuit, the second hardware interrupt handling prediction circuit, and the signal trigger generation circuit to enable the hardware interrupt control circuit 31 to sequentially complete the calculation of the remaining time of the current interrupt, the prediction of the time of the new interrupt in multiple scenarios, and the generation of the time limit comparison signal. The three circuits transmit the predicted time data and time limit requirements through physical signal lines, thereby reducing the circuit delay of interrupt scheduling control and improving the hardware execution speed of interrupt response control.

[0033] Based on the above embodiments, this embodiment further defines the internal structure of the first hardware interrupt handling estimation circuit as including a current instruction count statistics circuit, an instruction completion data statistics circuit, a remaining duration estimation circuit, and a first duration register, which may include the following: The current instruction count statistics circuit, upon starting the execution of the current hardware interrupt request, determines the total number of first-type instructions and the total number of second-type instructions contained in the current hardware interrupt handler based on the start and end addresses of the current hardware interrupt handler. The instruction completion data statistics circuit counts the number of first-type and second-type instructions completed at the current moment and their corresponding time consumption. The remaining time estimation circuit, connected to the outputs of the current instruction count statistics circuit and the instruction completion data statistics circuit, calculates the time consumption of each individual instruction for both types of instructions, and counts the remaining number of instructions for each type of instruction. Based on the individual instruction time consumption, the remaining number of instructions, and the weight fluctuation factor for each type of instruction, the remaining instruction completion time is calculated. The first time register, connected to the output of the remaining time estimation circuit, stores the remaining instruction completion time.

[0034] The first category of instructions includes store instructions and load instructions. The opcode field (lower 7 bits) of a store instruction is fixed at 7'b0100011, used to write data from the processing core to memory. The opcode field (lower 7 bits) of a load instruction is fixed at 7'b0000011, used to read data from memory into the processing core. The second category of instructions includes other instructions that are not store or load instructions, such as arithmetic and logical operation instructions and branch / jump instructions. The number of clock cycles consumed by these two categories of instructions differs significantly during execution; the execution time of the first category of instructions is usually much longer than that of the second category. Therefore, separate statistics can provide more accurate prediction precision. The total number of instructions in the first category and the total number of instructions in the second category are the respective totals after classification and statistics. The current instruction count circuit outputs these two totals to the remaining time prediction circuit.

[0035] In this embodiment, the start and end addresses of the current hardware interrupt handler are provided by the hardware interrupt controller when distributing the hardware interrupt and can be stored in the start and end address registers inside the first hardware interrupt handling prediction circuit. The program counter (PC) of the processing core stores the address of the current instruction fetch. The current instruction count statistics circuit can, for example, monitor the output of the instruction fetch unit of the processing core and analyze the instructions contained in the current hardware interrupt handler one by one during the instruction fetch stage, identifying the instruction type based on the instruction opcode. During the execution of the current hardware interrupt handler, the instruction completion data statistics circuit monitors the output of the instruction retirement unit of the processing core in real time. Each time the instruction retirement unit retires an instruction, the instruction completion data statistics circuit determines whether it belongs to the first type of instruction or the second type of instruction based on the opcode of the instruction, and accumulates the number of completed instructions and the corresponding total time for each type of instruction. The time consumed is the number of clock cycles elapsed from the instruction being issued into the execution pipeline to retirement, provided by the instruction execution cycle counting unit inside the processing core. The instruction completion data statistics circuit outputs the statistical results to the remaining duration prediction circuit in real time. When the remaining execution time estimation circuit receives a trigger signal indicating a new hardware interrupt request, it reads the total number of instructions for each of the two types from the current instruction count statistics circuit, and the number of completed instructions and total execution time for each type from the instruction completion data statistics circuit. The execution time of a single instruction is obtained by dividing the total execution time by the number of completed instructions. The remaining instruction count is obtained by subtracting the number of completed instructions from the total number. The weight fluctuation factor is an adjustable parameter set according to the fluctuation characteristics of instruction execution time. There is one weight fluctuation factor for the first type of instruction and one for the second type of instruction, and the sum of the two is 1. The reason for setting the weight fluctuation factor is that different types of instructions are affected by factors such as cache hit rate and bus contention during actual execution, resulting in different degrees of fluctuation in execution time. Weighted adjustment can more accurately reflect the actual remaining execution time. The remaining execution time estimation circuit multiplies the remaining number of instructions for the first type by the single instruction execution time, then multiplies it by its weight, and adds the product with the corresponding product of the second type of instruction to obtain the remaining instruction completion time.

[0036] As can be seen from the above, this embodiment classifies and counts stored instructions, loaded instructions and other instructions through the current instruction quantity statistics circuit, records the number of completed instructions and the time consumed by the instruction completion data statistics circuit, and calculates the remaining time based on the average time consumed by a single instruction and the number of remaining instructions. This enables the first hardware interrupt handling prediction circuit to dynamically calculate the remaining completion time using the arithmetic operation circuit according to the actual instruction execution progress of the interrupt handler, thereby improving the matching degree between the remaining time prediction and the actual execution state of the current processing core.

[0037] Based on the above embodiments, this embodiment further defines the internal structure of the current instruction count circuit as including a program counter range comparator, a first instruction opcode extractor, a first instruction type discriminator, a first type of instruction count register, and a second type of instruction count register, which may include the following: A program counter range comparator has its first comparison input connected to the program counter, its second comparison input connected to an address register, its first comparison output connected to a first type of instruction quantity register, and its second comparison output connected to a second type of instruction quantity register. When the program counter value is between the start and end addresses, it outputs a counting enable signal; when it exceeds the end address, it outputs a latch enable signal. A first instruction type discriminator has its first discrimination input connected to a first instruction opcode extractor, its first discrimination output connected to a first type of instruction quantity register, and its second discrimination output connected to a second type of instruction quantity register. If the instruction type is specified... If the opcode is a store instruction or load instruction, output a first-type instruction count pulse; if the opcode is another instruction, output a second-type instruction count pulse. The first-type instruction count register increments by one for each first-type instruction count pulse received during the count enable signal period; and latches the current count value as the total number of first-type instructions upon receiving a latch enable signal. The second-type instruction count register increments by one for each second-type instruction count pulse received during the count enable signal period; and latches the current count value as the total number of second-type instructions upon receiving a latch enable signal.

[0038] In this embodiment, the program counter is connected to the instruction fetch unit of the processing core, and outputs the current program counter value in real time. The address register in this embodiment includes a start address register and an end address register, storing the start and end addresses of the current hardware interrupt handler, respectively. The program counter range comparator can be a set of logic comparison circuits with three input terminals: the first comparison input terminal is connected to the program counter and receives the current program counter value; the second comparison input terminal is connected to the start address register and receives the start address; the third comparison input terminal is connected to the end address register and receives the end address. The internal logic of the program counter range comparator is to determine whether the program counter value is within the closed interval between the start and end addresses. When the program counter value is greater than or equal to the start address and less than or equal to the end address, both the first and second comparison output terminals of the program counter range comparator output a count enable signal, which is a high-level active signal, indicating that the currently fetched instruction belongs to the range of the current hardware interrupt handler. When the program counter value is greater than the end address, the output terminal of the program counter range comparator outputs a latch enable signal, which is a low-to-high level transition signal, indicating the end of the instruction analysis phase. The input of the first instruction opcode extractor is physically connected to the output of the instruction fetch unit of the processing core. It extracts the opcode field from the currently fetched instruction code. The opcode field is a fixed-position field in the instruction encoding, typically located in the lower 7 bits of the instruction. The first instruction opcode extractor outputs this opcode field to the first instruction type discriminator. The first instruction type discriminator internally contains two sets of comparators, which compare the input opcode field with the opcode of the stored instruction and the opcode of the loaded instruction, respectively. If the opcode equals the stored instruction opcode or the loaded instruction opcode, the first discriminator outputs a first-type instruction count pulse; otherwise, the second discriminator outputs a second-type instruction count pulse. The first discriminator output is connected to the count input of the first-type instruction count register, and the second discriminator output is connected to the count input of the second-type instruction count register. Both the first-type and second-type instruction count registers are counters with enable and latch functions. During the active period of the count enable signal, the Type I instruction count register increments its internal count by one for each Type I instruction count pulse received; the Type II instruction count register increments its internal count by one for each Type II instruction count pulse received. When the program counter range comparator outputs the latch enable signal, both registers simultaneously latch the current internal count value. The latched values ​​are the total number of Type I instructions and the total number of Type II instructions, respectively, and are then output to the subsequent circuitry.

[0039] As can be seen from the above, this embodiment compares the program counter value with the start address and end address using a program counter range comparator and outputs a counting enable signal and a latch enable signal. The first instruction type discriminator distinguishes between stored instructions, loaded instructions and other instructions based on the instruction opcode and outputs different counting pulses. The first type of instruction quantity register and the second type of instruction quantity register accumulate the count and latch the total quantity when the latch signal arrives. This allows the current instruction quantity statistics circuit to use the instruction type discriminator and register circuit to complete the classification and counting of interrupt handling program instruction types in real time, providing accurate instruction total data for subsequent remaining time estimation.

[0040] Based on the above embodiments, this embodiment further defines the internal structure of the instruction completion data statistics circuit as a second instruction opcode extractor, a second instruction type discriminator, an instruction completion counter, and an instruction time accumulator, which may include the following: The second instruction type discriminator has a second discrimination input connected to the second instruction opcode extractor, a third discrimination output connected to the counting enable of the instruction completion counter, and a fourth discrimination output connected to the accumulation enable of the instruction time accumulator. Upon receiving an instruction opcode for an executed instruction, if the opcode is a store instruction or load instruction opcode, it outputs a first-type instruction completion counting pulse; if the opcode is an opcode for another instruction (meaning instructions that are not store or load instructions), it outputs a second-type instruction completion counting pulse. The instruction completion counter increments the count of completed first-type instructions by one for each received first-type instruction completion counting pulse. When a second type of instruction completion count pulse is received, the count value of the number of second type of instructions completed is incremented by one, and the number of first type of instructions completed or the number of second type of instructions completed is output through the count output terminal; the instruction time accumulator, whose data accumulation input terminal is connected to the instruction execution cycle counting unit, accumulates the actual execution cycle number of the corresponding first type of instruction into the first type of instruction time accumulation value for each first type of instruction completion count pulse received; and accumulates the actual execution cycle number of the corresponding second type of instruction into the second type of instruction time accumulation value for each second type of instruction completion count pulse received, and outputs the first total time consumed by the completed first type of instructions or the second total time consumed by the completed second type of instructions through the time consumption output terminal.

[0041] In this embodiment, the input of the second instruction opcode extractor is connected to the output of the instruction retirement unit of the processing core. The instruction retirement unit is the last stage of the processing core execution pipeline, responsible for removing completed instructions from the pipeline and submitting their execution results. The second instruction opcode extractor extracts the opcode field from the retired instructions and outputs it to the second instruction type discriminator. The judgment logic of the second instruction type discriminator is the same as that of the first instruction type discriminator, comparing the opcode with the opcodes of stored instructions and loaded instructions. The third discrimination output is connected to the counting enable terminal of the instruction completion counter. When the opcode is the opcode of a stored instruction or a loaded instruction, a first-type instruction completion counting pulse is output. The fourth discrimination output is connected to the accumulation enable terminal of the instruction latency accumulator. When the opcode is the opcode of other instructions, a second-type instruction completion counting pulse is output. The instruction completion counter internally contains two independent counting fields: a first-type instruction completion counter and a second-type instruction completion counter. Upon receiving a Type 1 instruction completion count pulse, the count of completed Type 1 instructions is incremented by one; upon receiving a Type 2 instruction completion count pulse, the count of completed Type 2 instructions is incremented by one. The count output is a multiplexed interface, allowing selection signals to output either the number of completed Type 1 instructions or the number of completed Type 2 instructions. The instruction execution time accumulator is an accumulator register whose data accumulation input is connected to the instruction execution cycle counting unit of the processing core. The instruction execution cycle counting unit is a hardware counter within the processing core that records the number of clock cycles consumed by each instruction from issuance to retirement. Upon receiving a Type 1 instruction completion count pulse, the instruction execution time accumulator adds the actual number of execution cycles of the corresponding Type 1 instruction to the accumulated time value for Type 1 instructions; upon receiving a Type 2 instruction completion count pulse, the instruction execution time accumulator adds the actual number of execution cycles of the corresponding Type 2 instruction to the accumulated time value for Type 2 instructions. The time consumption output, through multiplexing, outputs either the first total consumption time or the second total consumption time. The first total consumption time is the sum of the number of clock cycles consumed by all completed Type 1 instructions from issuance to retirement. The second total execution time is the sum of the clock cycles consumed by all completed Type II instructions. These two values ​​are used by the subsequent remaining time estimation circuit to calculate the average execution time of a single instruction.

[0042] As can be seen from the above, this embodiment uses a second instruction type discriminator to identify the opcode of the completed instruction and outputs a first or second type instruction completion counting pulse. The instruction completion counter accumulates the number of completed instructions for the two types respectively, and the instruction time accumulator accumulates the actual number of execution cycles to obtain the total time consumed. This allows the instruction completion data statistics circuit to use the counter and accumulator circuits to track the actual execution progress and time consumed of different types of instructions in the interrupt handler in real time, providing dynamically updated data on the number of completed instructions and the total time consumed for the remaining time estimation circuit.

[0043] Based on the above embodiments, this embodiment further defines the internal structure of the remaining duration estimation circuit as a first divider, a second divider, a first type of instruction average time register, a second type of instruction average time register, a first subtractor, a second subtractor, a first multiplier, a second multiplier, a first weight register, a second weight register, and an adder, which may include the following: The first divider performs a division operation on the first total time consumed and the number of first type instructions completed to obtain the first single instruction time corresponding to the first type of instructions, and inputs the first single instruction time into the first type of instruction average time register; the second divider performs a division operation on the second total time consumed and the number of first type of instructions completed to obtain the second single instruction time corresponding to the second type of instructions, and inputs the second single instruction time into the second type of instruction average time register; the first subtractor performs a subtraction operation on the total number of first type of instructions and the number of first type of instructions completed to obtain the first remaining instruction quantity, and sends the first remaining instruction quantity to the first multiplier; the second subtractor performs a subtraction operation on the total number of second type of instructions and the number of second type of instructions completed to obtain the second remaining instruction quantity, and sends the second remaining instruction quantity to the second multiplier; the first multiplier... The first multiplier, connected to the first instruction average time register, the first weight register, and the adder, reads the duration of the first single instruction and the first weight fluctuation factor, multiplies the first remaining instruction count, the duration of the first single instruction, and the first weight fluctuation factor to obtain the estimated completion time of the first instruction, and sends it to the adder; the second multiplier, connected to the second instruction average time register, the second weight register, and the adder, reads the duration of the second single instruction and the second weight fluctuation factor, multiplies the second remaining instruction count, the duration of the second single instruction, and the second weight fluctuation factor to obtain the estimated completion time of the second instruction, and sends it to the adder; the sum of the second weight fluctuation factor and the first weight fluctuation factor is 1; the adder adds the estimated completion time of the first instruction and the estimated completion time of the second instruction to obtain the remaining instruction completion time.

[0044] The first divider is an integer divider. Its dividend input is connected to the first type of time-consuming output of the instruction time-consuming accumulator, receiving the first total time consumed. Its divisor input is connected to the first type of count output of the instruction completion counter, receiving the number of first type instructions completed. The first divider performs a division operation on the two, and the quotient is the first single instruction time consumption time corresponding to the first type of instructions. This value is written into the first type of instruction average time register and stored. The second divider divides the second total time consumed by the number of second type of instructions completed in the same way to obtain the second single instruction time consumption time and writes it into the second type of instruction average time register. The minuend input of the first subtractor is connected to the output of the first type of instruction quantity register, receiving the total number of first type of instructions. Its subtrahend input is connected to the first type of count output of the instruction completion counter, receiving the number of first type of instructions completed. The first subtractor calculates the difference between the two to obtain the first remaining instruction quantity and outputs it to the first multiplier. The second subtractor calculates the difference between the total number of second-type instructions and the number of completed second-type instructions in the same way, obtaining the second remaining instruction count, which is then output to the second multiplier. The first multiplier can be a three-input multiplier. Its first input is connected to the output of the first subtractor, receiving the first remaining instruction count; its second input is connected to the output of the first-type instruction average time register, receiving the first single instruction duration; and its third input is connected to the output of the first weight register, receiving the first weight fluctuation factor. The first multiplier multiplies these three values ​​to obtain the first instruction's estimated completion time, which is then output to the adder. The second multiplier is also a three-input multiplier, with its three inputs receiving the second remaining instruction count, the second single instruction duration, and the second weight fluctuation factor, respectively. The sum of the second weight fluctuation factor and the first weight fluctuation factor is 1; for example, the first weight fluctuation factor is 0.6, and the second weight fluctuation factor is 0.4. The second multiplier multiplies these three values ​​to obtain the second instruction's estimated completion time, which is then output to the adder. The weighting fluctuation factor is pre-stored in a first weighting register and a second weighting register. These two registers can be written with specific values ​​by software during system initialization via the configuration bus. Since the execution time of memory access instructions fluctuates significantly due to cache status, the second weighting fluctuation factor is usually set to a value lower than the first weighting fluctuation factor to reduce its influence on the final prediction result.

[0045] For example, the total number of instruction classes of the second type is represented by `Instruction_normal_all`, and the total number of instruction classes of the first type is represented by `Instruction_LS_all`. The number of instruction classes of the second type completed at the current moment and the time taken are represented by `Instruction_normal_now` and `T_normal_now`, respectively. The number of instruction classes of the first type completed at the current moment and the time taken are represented by `Instruction_LS_now` and `T_LS_now`, respectively. This can be achieved by first calling the relational expression `T_normal_need = (Instruction_normal_all - Instruction_normal_now)`. (T_normal_now / Instruction_normal_now) calculates the time required for the completion of the unexecuted Type II instructions, T_normal_need, and then calculates it by calling the relation T_LS_need = (Instruction_LS_all - Instruction_LS_now). (T_LS_now / Instruction_LS_now) calculates the time required for the completion of the first type of instruction that has not yet been executed, T_LS_need, and finally calculates it using the relation T_Cur_need=T_normal_need. PARAM0+T_LS_need PARAM1 calculates the time T_Cur_need required for the current interrupt handler to complete, where PARAM0 and PARAM1 are two adjustable weight fluctuation factors, and PARAM0 + PARAM1 = 1.

[0046] As can be seen from the above, in this embodiment, the first divider and the second divider calculate the average time of a single instruction for the two types of instructions respectively, the first subtractor and the second subtractor calculate the remaining quantity of the two types of instructions respectively, the first multiplier and the second multiplier multiply the remaining quantity, the average time, and the weight fluctuation factor to obtain the estimated completion time of each type of instruction, and the adder adds the estimated times of the two types of instructions to obtain the remaining instruction completion time. This allows the remaining time estimation circuit to use the divider, subtractor, multiplier, and adder circuits to perform weighted time estimation for storage instructions, loading instructions, and other instructions respectively, reducing the deviation in remaining time calculation caused by the difference in execution time of instruction types.

[0047] Based on the above embodiments, this embodiment further defines the internal structure of the second hardware interrupt handling prediction circuit as a new instruction quantity statistics circuit and a task duration prediction circuit, which may include the following: The new instruction quantity statistics circuit, upon receiving a new hardware interrupt request, determines the total number of new first-type instructions and the total number of new second-type instructions included in the new hardware interrupt handler. The task duration estimation circuit determines the total estimated duration of first-type instructions based on the duration of a single first instruction and the total number of new first-type instructions; it determines the total estimated duration of second-type instructions based on the duration of a single second instruction and the total number of new second-type instructions; it determines the estimated duration of the first task corresponding to the first execution scenario based on the total estimated duration of the first and second-type instructions, and determines the estimated duration of the second task corresponding to the second execution scenario based on the remaining instruction completion time and the estimated duration of the first task.

[0048] In this embodiment, the new instruction count circuit starts working when the hardware interrupt controller determines that a new hardware interrupt request needs to be dispatched. The new instruction count circuit is connected to the instruction fetch path of the new hardware interrupt handler, and its analysis process is the same as that of the current instruction count circuit. Based on the start and end addresses of the new hardware interrupt handler, it analyzes the instruction opcodes one by one during the instruction fetch phase of the handler, and counts the total number of new instructions of the first type and the total number of new instructions of the second type. The classification criteria for these two types of instructions are completely consistent with those in the first hardware interrupt handling prediction circuit. The first type of instructions includes store instructions and load instructions, and the second type of instructions includes other instructions. The inputs to the task duration prediction circuit include the total number of new instructions of the first type and the total number of new instructions of the second type output by the new instruction count circuit, as well as the duration of the first single instruction and the duration of the second single instruction read from the first hardware interrupt handling prediction circuit. The reason for reusing the single instruction execution time in the first hardware interrupt handling estimation circuit is that the current hardware interrupt handler is executing on the same processing core. The average execution time of the two types of instructions can represent the current working state of the processing core. Using this reference value can reduce the additional analysis overhead for new interrupt handlers. The task duration estimation circuit first multiplies the first single instruction execution time by the total number of new first-type instructions to obtain the total estimated execution time of the first type of instructions, and multiplies the second single instruction execution time by the total number of new second-type instructions to obtain the total estimated execution time of the second type of instructions. Then, the two are added together to obtain the first task estimated execution time corresponding to the first execution scenario, that is, the total estimated time from start to finish if the new interrupt is executed immediately. Next, the first task estimated execution time is added to the remaining instruction completion time read from the first duration register to obtain the second task estimated execution time corresponding to the second execution scenario, that is, the total estimated time to wait for the current interrupt to complete before executing the new interrupt. The task duration estimation circuit outputs the first task estimated execution time and the second task estimated execution time to the signal trigger generation circuit respectively. The internal structure of the new instruction quantity statistics circuit and the task duration prediction circuit can be found in the components that implement the corresponding functions in the first hardware interrupt handling prediction circuit, and will not be described again here.

[0049] For example, the second hardware interrupt handling prediction circuit obtains new hardware interrupt requests containing instructions divided into two categories: second-class instructions and first-class instructions. It then calculates the number of instructions for each category. The total number of instructions in the second-class category is High_Instruction_normal_all, and the total number of instructions in the first-class category is High_Instruction_LS_all. This is first done by calling the relation High_T_normal_need = High_Instruction_normal_all. (T_normal_now / Instruction_normal_now) calculates the total estimated time High_T_normal_need for the second type of instruction in the first execution scenario, and then calculates it by calling the relation High_T_LS_need=High_Instruction_LS_all. (T_LS_now / Instruction_LS_now) calculates the total estimated time High_T_LS_need for the first type of instruction in the first execution scenario. Then, it calculates the first task duration High_T_need_mode1 for the first execution scenario by calling the relation High_T_need_mode1=High_T_normal_need+High_T_LS_need. Finally, it calculates the second task duration High_T_need_mode2 for the second execution scenario by calling the relation High_T_need_mode2=T_Cur_need+High_T_need_mode1.

[0050] As can be seen from the above, this embodiment determines the number of store instructions, load instructions and other instructions included in the new hardware interrupt handler through the new instruction quantity statistics circuit. The task duration estimation circuit calculates the total duration of various instructions consumed by the new interrupt based on the average time of a single instruction completed by the current processing core and determines the estimated task duration of the first execution scenario and the second execution scenario. This allows the second hardware interrupt handling estimation circuit to estimate the completion time of the new interrupt handler under different execution orders based on the actual instruction execution speed of the current processing core and using the arithmetic operation circuit, thereby improving the correlation between the new interrupt time estimation and the execution state of the current processing core.

[0051] Based on the above embodiments, this embodiment further defines the internal structure of the signal trigger generation circuit, which may include the following: A time limit register, connected to the operating system data bus, receives the maximum completion time of the corresponding hardware interrupt request dynamically written by the operating system when a hardware interrupt is triggered. A first comparator, connected to the second hardware interrupt handling estimation circuit and the time limit register, reads the estimated duration of the first task and the maximum completion time of the new hardware interrupt request, compares the numerical relationship between the estimated duration of the first task and the maximum completion time, and outputs a high level when the estimated duration of the first task is greater than the maximum completion time. A second comparator, connected to the second hardware interrupt handling estimation circuit and the time limit register, reads the estimated duration of the second task and the maximum completion time of the new hardware interrupt request, compares the numerical relationship between the estimated duration of the second task and the maximum completion time, and outputs a high level when the estimated duration of the second task is greater than the maximum completion time. A first NOT gate, connected to the first comparator, logically inverts the comparison output of the first comparator. A second NOT gate, connected to the second comparator, logically inverts the comparison output of the second comparator. The first AND gate, connected to the first comparator, outputs a first type of program execution control signal when the first comparator outputs a high level; the second AND gate, connected to the first NOT gate and the second comparator, outputs a second type of program execution control signal when both the first NOT gate and the second comparator output a high level; the third AND gate, connected to the first NOT gate and the second NOT gate, outputs a third type of program execution control signal when both the first NOT gate and the second NOT gate output a high level; the OR gate, connected to the first AND gate and the second AND gate, performs a logical OR operation on the first type of program execution control signal and the second type of program execution control signal to generate a resource adjustment enable bit; the mode encoder, connected to the first AND gate, the second AND gate, the third AND gate, and the OR gate, encodes various program execution control signals and resource adjustment enable bits into program execution encoded signals; the control signal register, connected to the mode encoder, latches the program execution encoded signals and outputs them to the processing core cluster. The resource adjustment enable bit in the program execution control signal is used to control whether the processing core cluster enables the resource adjustment circuit 33.

[0052] In this embodiment, the timing register is a set of readable and writable hardware registers connected to the operating system kernel interface via the operating system data bus. The operating system data bus connects the on-chip buses of various hardware and software interfaces of the processor. During system initialization or interrupt registration, the operating system writes the maximum completion time corresponding to each hardware interrupt request into the timing register via this data bus. In this embodiment, the timing register stores at least the maximum completion time of a new hardware interrupt request. The maximum completion time is an integer value in processor clock cycles, representing the upper limit of the number of clock cycles allowed for the interrupt handler to complete execution. The first comparator is a digital comparator. Its first input is connected to the first task estimation duration output of the second hardware interrupt handling estimation circuit to receive the first task estimation duration; its second input is connected to the new interrupt timing output of the timing register to receive the maximum completion time of the new hardware interrupt request. The first comparator compares the numerical relationship between the first task estimation duration and the maximum completion time. When the first task estimation duration is greater than the maximum completion time, its output is high; otherwise, it is low. The second comparator has the same structure as the first comparator. Its first input receives the estimated duration of the second task, and its second input receives the same maximum completion time through a time limit register. The second comparator compares the estimated duration of the second task with the maximum completion time. It outputs a high level when the estimated duration is greater than the maximum completion time, and a low level otherwise. The first NOT gate is a logic NOT gate circuit connected to the output of the first comparator. It logically inverts the comparison output of the first comparator. If the first comparator outputs a high level, the first NOT gate outputs a low level; if the first comparator outputs a low level, the first NOT gate outputs a high level. The second NOT gate is connected to the output of the second comparator and logically inverts the comparison output of the second comparator. Its circuit structure and logic function are the same as the first NOT gate.

[0053] The first AND gate is a two-input AND gate. Its first input is connected to the output of the first comparator, and its second input is either floating or connected to a fixed high level. The logic is that when the first comparator outputs a high level, the first AND gate outputs a high level, which is the first type of program execution control signal. The second AND gate is also a two-input AND gate. Its first input is connected to the output of the first NOT gate, receiving the inverted signal of the first comparison result; its second input is connected to the output of the second comparator, receiving the second comparison result. When both the first NOT gate and the second comparator output high levels, it means that the first comparator outputs a low level (i.e., the estimated duration of the first task does not exceed the maximum completion time), and the second comparator outputs a high level (i.e., the estimated duration of the second task exceeds the maximum completion time). In this case, the second AND gate outputs a high level, which is the second type of program execution control signal. The third AND gate is a two-input AND gate. Its first input is connected to the output of the first NOT gate, and its second input is connected to the output of the second NOT gate. When both the first and second NOT gates output high levels, it means that both the first and second comparators output low levels, indicating that the estimated duration in both scenarios does not exceed the maximum completion time. At this time, the third AND gate outputs a high level, which is the third type of program execution control signal. The OR gate is a two-input logic OR gate, with its first input connected to the output of the first AND gate and its second input connected to the output of the second AND gate. When either the first or second type of program execution control signal is high, the OR gate outputs a high level, generating a resource adjustment enable bit. This resource adjustment enable bit can be, for example, a 1-bit binary signal. A high level indicates that the resource adjustment circuit 33 needs to be enabled, while a low level indicates that it does not need to be enabled.

[0054] In this embodiment, the pattern encoder is an encoder whose input terminals are connected to the output terminals of the first AND gate, the second AND gate, the third AND gate, and the OR gate, respectively. Various program execution control signals include first-type, second-type, and third-type program execution control signals. The pattern encoder encodes these mutually exclusive one-hot code signals and the resource adjustment enable bit into a multi-bit binary program execution encoded signal. The encoded signal occupies fewer physical connections, facilitating forwarding and transmission within the processing core cluster. The control signal register can be a register group triggered by a clock signal, connected to the output terminal of the pattern encoder. It latches the program execution encoded signal on the rising edge of the clock and outputs it to the receiving interface of the processing core cluster. The resource adjustment enable bit in the program execution control signal is latched and sent along with the entire encoded signal. After decoding the received encoded signal, the distribution logic in the processing core cluster controls the execution order of new interrupts and the current interrupt accordingly, and determines whether to send an enable signal to the resource adjustment circuit 33 based on the value of the resource adjustment enable bit.

[0055] For example, when the operating system triggers a new hardware interrupt request, it issues a maximum requirement for the completion time of the interrupt program, which is T_MAX_HIGH, that is, the maximum completion time of the new interrupt handler. If High_T_need_mode1 > T_MAX_HIGH, it means that even if the current interrupt handler is paused and the RISC-V CPU fully processes the new hardware interrupt program, the requirement for the maximum completion time still cannot be met. At this time, the subsequent resource adjustment circuit 33 is enabled. At this time, the current interrupt program will continue to execute, and at the same time, the hardware interrupt program will be transferred to other processing cores for execution, relying on the resource adjustment circuit 33 to ensure the real-time performance of the current interrupt program. If High_T_need_mode1 < T_MAX_HIGH and High_T_need_mode2 > T_MAX_HIGH, it means that if the current interrupt handler is paused and the RISC-V CPU fully processes the new hardware interrupt program, the maximum completion time requirement of the new interrupt program can be met, but the maximum completion time requirement of the currently processed current hardware interrupt program cannot be met. At this time, the subsequent resource adjustment circuit 33 is enabled. At this time, the current interrupt program will be paused, and the higher-priority interrupt program will be executed first, relying on the resource adjustment circuit 33 to ensure the real-time performance of the current interrupt program and the higher-priority interrupt program. If High_T_need_mode1 < T_MAX_HIGH and High_T_need_mode2 < T_MAX_HIGH, it means that even if the current hardware interrupt program is not paused and the RISC-V CPU processes the new hardware interrupt program after completing the processing of the current hardware interrupt program, the maximum completion time requirement of the new hardware interrupt program can be met, and the maximum completion time requirement of the currently processed current interrupt program can also be met. At this time, the current interrupt program will be processed first, and then the high-priority interrupt program will be processed, and the subsequent resource adjustment circuit 33 will not be enabled.

[0056] As described above, this embodiment dynamically receives the maximum completion time of a hardware interrupt request from the operating system data bus via a time limit register. The first and second comparators compare the estimated durations of the first and second tasks with the maximum completion time and output high or low levels, respectively. The first and second NOT gates logically invert the comparison results, enabling the signal trigger generation circuit to perform time limit comparison and logical condition conversion through the comparator and NOT gate circuits, providing digital logic level signals for subsequent mode selection. The first, second, and third AND gates output first, second, and third type program execution control signals respectively based on the combination of the comparator and NOT gate output levels. An OR gate performs a logical OR operation on the first and second type signals to generate a resource adjustment enable bit. The mode encoder encodes the mode signal and the enable bit into a program execution encoded signal, which is latched and output by the control signal register. This allows the signal trigger generation circuit to automatically select the interrupt execution mode and latch the signal through digital logic gate circuits and the encoding register, ensuring stable output of the program execution control signal.

[0057] Based on the above embodiments, this embodiment further defines the process by which the software and hardware interrupt association processing circuit 32 implements software interrupt services and hardware interrupt services for the same processing core to execute the same processing task, which may include the following: The hardware / software interrupt association processing circuit 32 is configured to: predict at least one target external device that will initiate a hardware interrupt request within a future preset time period based on the hardware interrupt request statistics within the target historical time period, and determine the target processing core corresponding to the hardware interrupt request of the target external device; determine the target software interrupt request corresponding to the same processing task as the target external device among the generated software interrupt requests, and send at least one target software interrupt request to the corresponding target processing core, so that the same processing core executes the software interrupt service and hardware interrupt service for the same processing task.

[0058] The target historical time period is a pre-defined window of past time in the circuit configuration. Its duration can be configured by the user or use a default value, such as 10 milliseconds. The future preset time period is a pre-defined future prediction time window, and its duration is also configurable, such as 4 milliseconds. The target external device is an external device connected to the processor through a hardware interrupt controller. It has a unique device identifier, such as interface 3 corresponding to identifier 3, and interface 12 corresponding to identifier 12.

[0059] In this embodiment, the hardware / software interrupt association processing circuit 32 continuously tracks the hardware interrupt requests initiated by each external device within a target historical time period, counts the number of hardware interrupt requests initiated by each external device, and obtains hardware interrupt request statistics. The hardware interrupt request statistics record the cumulative number of hardware interrupt requests initiated by each external device within the target historical time period. Based on the historical statistics, the hardware / software interrupt association processing circuit 32 predicts at least one target external device that will initiate a hardware interrupt request within a future preset time period and determines the target processing core corresponding to these target external devices. The target processing core is a processor core pre-allocated by hardware to handle the hardware interrupt requests of the target external device. In the generated software interrupt requests, each software interrupt request carries a task identifier for its associated processing task. The hardware / software interrupt association processing circuit 32 filters out target software interrupt requests that correspond to the same processing task as the target external device based on the task identifier and sends them to the corresponding target processing core.

[0060] As can be seen from the above, since the software and hardware interrupt association processing circuit 32 makes predictions based on historical statistical patterns, it selects target software interrupt requests that correspond to the same processing task as the target external device from the generated software interrupt requests according to the prediction results and sends them to the corresponding target processing core. This makes the distribution of software interrupt requests no longer unconditionally send all generated requests, but correspond to the predicted hardware interrupt requests from the perspectives of processing tasks and processing cores respectively. This enables the software interrupt service and hardware interrupt service corresponding to the same processing task to be executed sequentially on the same processing core, reducing the idle waiting caused by waiting for the hardware interrupt result after the software interrupt processing is completed.

[0061] Based on the above embodiments, this embodiment further defines the internal structure of the hardware / software interrupt association processing circuit 32 as a hardware interrupt prediction circuit and a software interrupt core distribution circuit, such as... Figure 6 As shown, it may include the following: The hardware interrupt prediction circuit predicts at least one target external device that will initiate a hardware interrupt request within a preset future time period based on the hardware interrupt request statistics within the target historical time period. The software interrupt core distribution circuit is connected to the hardware interrupt prediction circuit and the processing core cluster. It determines the target processing core corresponding to the hardware interrupt request of the target external device, identifies the target software interrupt request with the same processing task as the target external device among the generated software interrupt requests, and sends at least one target software interrupt request to the corresponding target processing core so that the same processing core can execute the software interrupt service and hardware interrupt service for the same processing task.

[0062] In this embodiment, the hardware interrupt prediction circuit is used to statistically analyze the occurrence patterns of historical interrupt requests and output prediction results. Internally, it maintains a counter table indexed by external device identifiers, continuously accumulating the count of hardware interrupt requests initiated by each external device within a target historical time period. When the statistical window ends, the hardware interrupt prediction circuit calculates the number of target external devices expected to initiate hardware interrupt requests within a preset future time period based on the counting results and a preset duration ratio, and selects the external devices with the highest count values ​​as the prediction results. The software interrupt core distribution circuit is connected to both the hardware interrupt prediction circuit and the processing core cluster. The input of the software interrupt core distribution circuit receives the target external device identifiers output by the hardware interrupt prediction circuit and determines which processing core is responsible for handling the hardware interrupt requests of these target external devices by querying the internally stored mapping information. Then, the software interrupt core distribution circuit searches the queue of software interrupt requests currently generated but not yet sent by the software interrupt controller for software interrupt requests belonging to the same processing task and processed by the same processing core as each target external device. These software interrupt requests are marked as target software interrupt requests and sent to the corresponding target processing cores in a certain order.

[0063] As can be seen from the above, the hardware and software interrupt association processing circuit 32 in this embodiment is divided into two independent functional circuits: a hardware interrupt prediction circuit and a software interrupt core distribution circuit. The prediction operation and the distribution operation can be performed independently. While the hardware interrupt prediction circuit performs prediction calculations based on historical statistical information, the software interrupt core distribution circuit can mark the task ownership of the generated software interrupt requests. The outputs of the two circuits are matched through the connection signal between the circuits, which shortens the total delay from the end of the statistical window to the completion of the software interrupt distribution and realizes the physical circuit association between the software interrupt sending target and the hardware interrupt prediction result.

[0064] Based on the above embodiments, this embodiment further defines the internal structure of the hardware interrupt prediction circuit as including a peripheral request counter, a peripheral quantity calculation circuit, a peripheral sorting and selection circuit, and a prediction result output register, which may include the following: The peripheral request counter counts the hardware interrupt requests initiated by each external device within the target historical time period and outputs the historical hardware interrupt request count for each external device within the target historical time period. The peripheral quantity calculation circuit, connected to the peripheral request counter, calculates the predicted number of peripherals that will initiate hardware interrupt requests in the future preset time period based on the duration of the target historical time period, the duration of the future preset time period, and the historical hardware interrupt request count. The peripheral sorting and selection circuit, connected to the peripheral request counter and the peripheral quantity calculation circuit, sorts the historical hardware interrupt request counts of each external device and selects each target external device in descending order of hardware interrupt request count until the target external device count matches the predicted peripheral count. The prediction result output register, connected to the peripheral sorting and selection circuit, latches the device identifier of each target external device and outputs the device identifier of each target external device as the hardware interrupt prediction information for the future preset time period.

[0065] In this embodiment, the peripheral request counter is a counter group composed of multiple counting units, each corresponding to one external device. During the target historical time period, whenever the hardware interrupt controller distributes a hardware interrupt request, the peripheral request counter increments the value of the corresponding counting unit by one based on the identifier of the external device from which the request originates. When the target historical time period ends, the count value in each counting unit represents the number of historical hardware interrupt requests made by each external device during the target historical time period. The duration of the target historical time period is a configuration parameter of the peripheral request counter, determining the length of the statistical window. The peripheral quantity calculation circuit is connected to the output of the peripheral request counter and receives three parameters: the duration of the target historical time period, the duration of a future preset time period, and the total number of external devices that have initiated at least one hardware interrupt request during the target historical time period. When calculating the predicted number N of peripherals that will initiate hardware interrupt requests during the future preset time period, the peripheral quantity calculation circuit uses the formula: the predicted number of peripherals equals the total number of peripherals that have initiated hardware interrupt requests during the target historical time period multiplied by the duration of the future preset time period, divided by the duration of the target historical time period, and finally rounded down. The peripheral sorting and selection circuit is connected to the output of the peripheral request counter and the peripheral quantity calculation circuit. It sorts the historical hardware interrupt request counts of each external device from largest to smallest, forming an ordered list. Then, starting from the external device with the highest number in this list, it selects one external device at a time as the target external device, and increments the selected count by one, until the selected count equals the predicted peripheral quantity N, at which point the selection stops.

[0066] For example, the hardware interrupt prediction circuit performs statistical analysis on peripheral interrupt requests within the past time period T1, creating a peripheral request analysis table, as shown in Table 1. Analyzing Table 1 reveals the top N peripheral IDs with the highest probability of initiating a peripheral hardware interrupt request within the future time period T0, where N = [the number of peripherals initiating hardware interrupt requests within time period T1, M]. [(T0 / T1)], where [] indicates rounding. For example, if the number of peripherals initiating hardware interrupt requests during time period T1 is 6, T1=10ms, T0=4, then N=2. The IDs of the two peripheral interfaces with the highest probability of occurrence in the above table (e.g., interface 3 and interface 12, then ID=3, 12) are used as the output of this submodule, which gives the peripheral IDs that will initiate hardware interrupt requests during the future time period T0.

[0067] Table 1 Peripheral Request Analysis Table

[0068] The prediction result output register is connected to the output of the external device selection circuit. It can be a multi-bit register, with each bit corresponding to an external device identifier or directly storing the identifier code of the selected external device. The peripheral device sorting and selection circuit writes the device identifiers of each selected target external device into the prediction result output register. This register latches these identifiers and outputs them to the subsequent circuits as hardware interrupt prediction information for a preset time period in the future.

[0069] As shown above, this embodiment uses a peripheral request counter to count the number of hardware interrupt requests initiated by each external device within a historical time period. The peripheral quantity calculation circuit calculates the predicted number of peripherals based on the ratio of the duration of the historical time period to the future time period. The peripheral sorting and selection circuit sorts the peripheral interrupt requests from high to low and selects the top predicted number of target external devices. The prediction result output register latches the device identifier of the target external device. This allows the hardware interrupt prediction circuit to automatically complete the peripheral interrupt probability statistics and predicted peripheral selection through the counter, proportional calculation circuit, and sorting and selection circuit, improving the hardware calculation efficiency of the prediction results. The entire prediction process is completed by a hardware pipeline consisting of a counter, calculation circuit, and sorting and selection circuit, without requiring the processing core to participate in the statistical and sorting operations, and without occupying the execution cycle of the processing core.

[0070] Based on the above embodiments, this embodiment further defines the internal structure of the software interrupt core distribution circuit as a mapping relationship memory, a first mapping conversion circuit, a second mapping conversion circuit, and an interrupt request selection circuit, which may include the following: A mapping relationship memory, connected to the memory of the software interrupt controller, stores the pre-built peripheral-interrupt mapping relationship and interrupt-processing core mapping relationship read from the memory of the software interrupt controller. A first mapping conversion circuit, connected to the mapping relationship memory, reads the corresponding target interrupt identifier from the mapping relationship memory according to the target external device identifier in the hardware interrupt prediction information. A second mapping conversion circuit, connected to the mapping relationship memory and the first mapping conversion circuit, reads the corresponding target core identifier from the mapping relationship memory according to the target interrupt identifier. An interrupt request selection circuit, connected to the software interrupt controller and the second mapping conversion circuit, selects the target software interrupt request to be executed by the processing core corresponding to each target core identifier from the generated software interrupt requests, and sends each target software interrupt request to the processing core corresponding to the corresponding target core identifier.

[0071] In this embodiment, the memory of the software interrupt controller can be a read-only memory area within the software interrupt controller, where the pre-built peripheral interrupt mapping relationship and interrupt handling core mapping relationship are embedded during the processor design phase. The peripheral-interrupt mapping relationship records the correspondence between each external device identifier and all interrupt identifiers it can generate. For example, the peripheral-interrupt mapping relationship can be a peripheral ID-interrupt ID mapping table, as shown in Table 2. In Table 2, Q-1 indicates that the RISC-V CPU has Q external devices, and 500-S indicates that the RISC-V CPU has S hardware interrupts. The interrupt-handling core mapping relationship records the correspondence between each interrupt identifier and the designated handling core responsible for handling it. For example, the interrupt-handling core mapping relationship can be an interrupt ID-handling core ID mapping table, as shown in Table 3. In Table 3, RISC-V Core P-1 indicates a 64-core CPU, where P=64. Based on the peripheral ID-interrupt ID mapping table, the interrupt IDs of peripheral hardware interrupt requests that will occur within the future T0 time period are obtained. Then, based on the interrupt ID-processor core ID mapping table, the corresponding RISC-V CoreID is determined for each interrupt ID.

[0072] Table 2 Peripheral ID-Interrupt ID Mapping Table

[0073] Table 3 Interrupt ID-Handler Core ID Mapping Table

[0074] In this embodiment, the mapping relationship memory and the memory of the software interrupt controller are connected via an internal bus. When the processor powers on, the entire contents of the two mapping tables are automatically loaded from the memory of the software interrupt controller and cached in its own static random access memory. This eliminates the need to access external memory for subsequent table lookup operations, allowing completion in a single cycle. The first mapping conversion circuit is connected to the output of the peripheral interrupt mapping table in the mapping relationship memory. It receives the target external device identifier from the hardware interrupt prediction information, uses the target external device identifier as an index address, and reads the corresponding target interrupt identifier in parallel from the peripheral interrupt mapping relationship. One target external device may correspond to multiple target interrupt identifiers; the first mapping conversion circuit packages all these target interrupt identifiers and outputs them together. The second mapping conversion circuit is connected to the output of the interrupt handling core mapping table in the mapping relationship memory and the output of the first mapping conversion circuit. It receives the target interrupt identifiers output by the first mapping conversion circuit, uses each target interrupt identifier as an index address, and reads the corresponding target core identifier from the interrupt handling core mapping relationship. The interrupt request selection circuit is connected to the software interrupt request queue in the software interrupt controller and the output of the second mapping conversion circuit. The software interrupt request queue temporarily stores all generated but undistributed software interrupt requests, each carrying an interrupt identifier field. The interrupt request selection circuit matches the interrupt identifiers of each request in the software interrupt request queue with the target interrupt identifier set output by the second mapping and conversion circuit. Software interrupt requests that successfully match are the target software interrupt requests. The interrupt request selection circuit then retrieves these target software interrupt requests from the queue and sends them to the processing core corresponding to the appropriate target core identifier. The sending order can be either first-in-first-out (FIFO) or sorted by task priority.

[0075] For example, the hardware interrupt prediction circuit predicts that the peripheral IDs that will initiate hardware interrupt requests during the T0 time period are peripheral ID3 and peripheral ID6. By looking up Table 2, it determines that the peripheral interrupt IDs included in these requests are 40-49 and 100-109. By looking up Table 3, it determines that the RISC-V Core IDs corresponding to interrupt IDs 40-49 and 100-109 are 8, 12, and 19. For software interrupt requests generated within the RISC-V CPU during the T2 time period, only the software interrupt requests with RISC-V Core IDs 8, 12, and 19 are sent to the corresponding RISC-V Cores, instead of sending all software interrupt requests to the corresponding RISC-V Cores. This greatly ensures that, during the future T0 time period, hardware interrupt requests and software interrupts of the same process will be processed collaboratively by the RISC-V Cores, significantly improving the processing speed and real-time performance of the process.

[0076] As can be seen from the above, this embodiment stores the mapping relationship between peripheral identifiers and interrupt identifiers, as well as between interrupt identifiers and processing core identifiers, through a mapping relationship memory. The first mapping conversion circuit and the second mapping conversion circuit sequentially perform mapping conversion based on the peripheral identifier and the target interrupt identifier to obtain the target processing core identifier. The interrupt request selection circuit selects the target software interrupt request to be executed by the processing core corresponding to the target processing core identifier from the generated software interrupt requests and sends it. This allows the software interrupt core distribution circuit to automatically complete the physical routing of the software interrupt request to the target processing core through the mapping relationship memory and the identifier conversion circuit, ensuring that the software interrupt transmission and the hardware interrupt prediction result point to the same processing core. The entire process is completed by the hardware conversion circuit, without the need for software to traverse the queue or perform table lookup operations, which can shorten the delay from the output of the hardware interrupt prediction result to the selection and transmission of the target software interrupt request.

[0077] Based on the above embodiments, this embodiment further defines the internal structure of the resource adjustment circuit 33 as a signal parsing circuit, an overclocking mode startup circuit, an interface adaptation circuit, and an interrupt process inter-core movement circuit, such as... Figure 7 As shown, it may include the following: The signal parsing circuit has its signal input connected to the processing core cluster and its signal output connected to the overclocking mode startup circuit, interface adaptation circuit, and interrupt process inter-core movement circuit, respectively. It parses the control signal type from the program execution control signals forwarded by the processing core cluster. If the program execution control signal is a first-type program execution control signal, it outputs an enable signal to the overclocking mode startup circuit, interface adaptation circuit, and interrupt process inter-core movement circuit; if the program execution control signal is a second-type program execution control signal, it outputs an enable signal to the overclocking mode startup circuit and interface adaptation circuit. The overclocking mode startup circuit, upon receiving an enable signal, increases the power consumption parameters of the target processing cores corresponding to each target software interrupt request. The interface adaptation circuit, upon receiving an enable signal, increases the bandwidth allocation ratio for memory access between the target processing cores corresponding to each target software interrupt request and the current processing core corresponding to the current hardware interrupt request. The interrupt process inter-core movement circuit, upon receiving an enable signal, transfers the interrupt handler corresponding to a new hardware interrupt request from the source processing core to the migrating processing core for processing.

[0078] In this embodiment, the signal input terminal of the signal parsing circuit is connected to the program execution control signal distribution interface of the processing core cluster, and the signal output terminal is connected to the enable input terminals of the overclocking mode startup circuit, the interface adaptation circuit, and the interrupt process inter-core migration circuit, respectively. The program execution control signal forwarded by the processing core cluster can be a multi-bit encoded signal. The signal parsing circuit contains a decoder to decode the encoded signal and extract the control signal type field. If the encoded signal indicates that the original control signal is a first-type program execution control signal, the signal parsing circuit simultaneously outputs an enable signal to the overclocking mode startup circuit, the interface adaptation circuit, and the interrupt process inter-core migration circuit. The enable signal is a high-level active signal. If the encoded signal indicates that the original control signal is a second-type program execution control signal, the signal parsing circuit outputs an enable signal to the overclocking mode startup circuit and the interface adaptation circuit, but does not output an enable signal to the interrupt process inter-core migration circuit, because the second-type execution order is to pause the current interrupt and then prioritize the execution of the new interrupt on the current processing core, without requiring inter-core migration. If the encoded signal indicates that the original control signal is a third-class program execution control signal, the signal parsing circuit does not output an enable signal to any sub-circuit, because no additional hardware operating parameters need to be adjusted in these cases.

[0079] The overclocking mode activation circuit, upon receiving an enable signal, performs corresponding power consumption parameter adjustments. These parameters may include, for example, the processing core's operating frequency and voltage. Increasing power consumption parameters increases the processing core's ability to execute instructions per unit time, thereby accelerating the execution speed of interrupt handlers. Upon receiving an enable signal, the interface adaptation circuit, by sending a bandwidth reallocation command to the memory controller, increases the bandwidth allocation ratio for the specified processing core accessing memory. Memory access bandwidth is a shared resource in multi-core systems, and by default, it is evenly allocated among the processing cores. The interface adaptation circuit can break this even allocation in a short time, prioritizing the processing core executing the interrupt handler to obtain greater data throughput. Upon receiving an enable signal, the interrupt process inter-core migration circuit transfers the interrupt handler corresponding to a new hardware interrupt request from the source processing core to the migration processing core for processing. The source processing core is the processing core currently executing the hardware interrupt handler, carrying the current hardware interrupt request. The migration processing core is a less loaded processing core selected from the processing core cluster. The migration process may include: pausing the current execution task of the migration processing core, temporarily storing the context data of the current task in memory, modifying the instruction fetch address of the migration processing core to the entry address of the new interrupt handler, and restoring the context of the original task after the new interrupt handler has finished executing.

[0080] As can be seen from the above, the resource adjustment circuit 33 enables different combinations of sub-circuits based on the type of control signal contained in the program execution control signal. The first type of program execution control signal simultaneously enables the overclocking mode startup circuit, the interface adaptation circuit, and the interrupt process inter-core migration circuit—three adjustment methods working together. Therefore, in the first scenario, when a new hardware interrupt request cannot be completed on time on the current processing core, the resource adjustment circuit 33 can simultaneously overclock and adjust the bandwidth of the current processing core, and perform inter-core migration for the new hardware interrupt request, applying adjustments in parallel from multiple aspects, increasing the probability that both interrupts can be completed on time. When the control signal type is the second type of program execution control signal, the signal parsing circuit only enables the overclocking mode startup circuit and the interface adaptation circuit, but not the interrupt process inter-core migration circuit. In this case, the frequency and bandwidth of the current processing core are adjusted to support the priority execution of the new interrupt on the current processing core, while avoiding the context saving and recovery overhead caused by unnecessary inter-core migration operations.

[0081] Based on the above embodiments, this embodiment further defines the internal structure of the overclocking mode startup circuit as a frequency adjustment register, a voltage adjustment register, a frequency control circuit, and a voltage control circuit, which may include the following: The frequency adjustment register stores the frequency adjustment amplitude value; the voltage adjustment register stores the voltage adjustment amplitude value; the frequency control circuit, connected to the signal parsing circuit and the frequency adjustment register, receives the target core identifier of the target processing core corresponding to the target software interrupt request from the program execution control signal, and adjusts the operating frequency of the corresponding target processing core according to the target core identifier and the frequency adjustment amplitude value; the voltage control circuit, connected to the signal parsing circuit and the voltage adjustment register, receives the target core identifier of the target processing core corresponding to the target software interrupt request from the program execution control signal, and adjusts the operating voltage of the corresponding target processing core according to the target core identifier and the voltage adjustment amplitude value.

[0082] The frequency adjustment register, which can be a programmable configuration register, stores the frequency adjustment amplitude value. This amplitude value can be a percentage or an absolute value, representing the upper limit of the increase from the current operating frequency, for example, a maximum increase of 20%. It can be written by software during the initialization phase through the register configuration interface, or it can use the default value embedded in the fuse during processor manufacturing. The voltage adjustment register has a similar structure to the frequency adjustment register, storing the voltage adjustment amplitude value. Since increasing the frequency usually requires a simultaneous increase in the processing core's operating voltage to ensure transistor switching stability, the voltage adjustment amplitude value is determined by the processor's internal voltage-frequency mapping relationship based on the frequency increase. The input terminal of the frequency control circuit is connected to the enable output terminal of the signal parsing circuit and the data output terminal of the frequency adjustment register. When an enable signal is received, the frequency control circuit reads the target core identifier of each target software interrupt request obtained by the signal parsing circuit from the program execution control signal, as well as the frequency adjustment amplitude value stored in the frequency adjustment register. The frequency control circuit internally includes a clock management unit interface, through which a frequency adjustment command is sent to the processing core's phase-locked loop circuit to increase the clock frequency of the processing core corresponding to the target core identifier by a specified amount. The voltage control circuit and the frequency control circuit can operate in parallel, and their inputs are also connected to the signal analysis circuit and the voltage regulation register. The voltage control circuit sends a voltage adjustment command to the power supply circuit of the processing core corresponding to the target core identifier through the power management unit interface inside the processor, adjusting the operating voltage to a value that matches the target frequency.

[0083] As can be seen from the above, in the overclocking mode startup circuit of this embodiment, the frequency control circuit and the voltage control circuit receive the same enable signal from the signal parsing circuit in parallel, and send adjustment commands to the clock management unit and power management unit of the processing core through independent physical paths. The frequency and voltage adjustments can start simultaneously, eliminating the time window where the frequency is increased first but the voltage has not followed, causing the processing core to be unable to operate stably at the target frequency. In addition, the frequency control circuit and the voltage control circuit increase the operating frequency and operating voltage of the corresponding target processing core according to the target processing core identifier, so that the overclocking mode startup circuit can achieve independent frequency and voltage adjustment for specific processing cores through register configuration and core identifier addressing, avoiding unnecessary power consumption increases for unrelated processing cores.

[0084] Based on the above embodiments, this embodiment further defines the internal structure of the interface adapter circuit as a bandwidth ratio register, a bandwidth allocation adjustment circuit, and a bandwidth upper limit constraint circuit, which may include the following: The bandwidth ratio register stores the bandwidth adjustment ratio value and the upper limit of the bandwidth allocation ratio. The bandwidth allocation adjustment circuit is connected to the signal parsing circuit, the bandwidth ratio register, and the memory controller. It receives the target core identifier of the target processing core corresponding to the target software interrupt request and the current core identifier of the current processing core corresponding to the current hardware interrupt request from the program execution control signal. Based on the target core identifier, the current core identifier, and the bandwidth adjustment ratio value, it increases the bandwidth allocation ratio of the memory controller for the target processing core and the current processing core accessing memory. The bandwidth upper limit constraint circuit is connected to the bandwidth allocation adjustment circuit and limits the bandwidth allocation ratio of a single processing core to not exceeding the upper limit of the bandwidth allocation ratio.

[0085] In this embodiment, the bandwidth ratio register may contain two fields. One field stores the bandwidth adjustment ratio value, representing the step size by which the bandwidth allocation ratio of a single processing core increases with each adjustment. The other field stores the upper limit of the bandwidth allocation ratio, which is the maximum bandwidth ratio that a single processing core can occupy, for example, no more than 30% of the total bandwidth, to prevent a single processing core from monopolizing memory bandwidth and preventing other processing cores from accessing memory normally. The bandwidth allocation adjustment circuit is connected to the signal parsing circuit, the bandwidth ratio register, and the memory controller, respectively. It receives the core identifiers that need increased bandwidth from the program execution control signals parsed by the signal parsing circuit, including the target core identifiers of the target processing cores corresponding to each target software interrupt request, and the current core identifier of the current processing core corresponding to the current hardware interrupt request. The bandwidth allocation adjustment circuit sends a bandwidth reallocation instruction containing these core identifiers and the bandwidth adjustment ratio value to the memory controller. After receiving the instruction, the memory controller temporarily increases the access priority and bandwidth quota of the processing cores corresponding to these core identifiers in its internal bandwidth allocation scheduling table. The bandwidth upper limit constraint circuit is connected to the bandwidth allocation adjustment circuit and the bandwidth allocation ratio upper limit field of the bandwidth ratio register. After the bandwidth allocation adjustment circuit calculates the new bandwidth allocation ratio for each processing core, the bandwidth upper limit constraint circuit checks whether the new bandwidth allocation ratio exceeds the upper limit stored in the bandwidth ratio register for each core. If the bandwidth allocation ratio of a processing core exceeds the upper limit, the bandwidth upper limit constraint circuit truncates it to the upper limit value and writes the truncated result back to the bandwidth allocation adjustment circuit, which then uses this result to generate the final bandwidth reallocation instruction.

[0086] As can be seen from the above, the bandwidth allocation adjustment circuit in this embodiment increases the bandwidth allocation ratio of the memory controller for the corresponding processing core to access memory based on the target processing core identifier and the current processing core identifier. This allows the interface adaptation circuit to improve the memory access speed of interrupt-related processing cores through register configuration and memory controller interface adjustment. While the bandwidth allocation adjustment circuit adjusts the memory bandwidth allocation ratio of each processing core, the bandwidth upper limit constraint circuit performs core-by-core upper limit verification and truncation on the adjustment result. This ensures that the bandwidth allocation adjustment can be performed within the preset upper limit, preventing other processing cores from being unable to complete basic memory access operations due to the bandwidth allocation ratio of a single processing core exceeding the upper limit.

[0087] Based on the above embodiments, this embodiment further defines the internal structure of the interrupt process inter-core movement circuit as a load detection circuit, a core instruction pause circuit, a context storage circuit, an address modification circuit, and a context recovery circuit, which may include the following: The load detection circuit, connected to the running status register, acquires the running status information of each processing core in the processing core cluster and determines the migration processing core with the least load. The core instruction pause circuit, connected to the load detection circuit, pauses the instruction execution of the migration processing core. The context storage circuit, connected to the core instruction pause circuit and the memory, temporarily stores the context data of the program currently running on the migration processing core, such as the internal register status and related data, into the memory. The address modification circuit, connected to the load detection circuit, modifies the instruction fetch address of the migration processing core to the entry address of the new hardware interrupt request. The context recovery circuit, connected to the memory and the migration processing core, reads the context data of the migration processing core from the memory and restores it to the migration processing core after the new hardware interrupt handler finishes running.

[0088] The runtime status register is a set of status monitoring registers within each processing core in the processing core cluster. It records the current runtime status information of each processing core in real time, including whether the core is idle, the type of program currently being executed, and the current instruction throughput. The load detection circuit is connected to the runtime status registers of each processing core via a status monitoring bus. It periodically samples the runtime status information of each processing core and calculates the current load level of each processing core based on the runtime status information. The load level can be measured by the number of currently active tasks or the number of instruction issue pause cycles per unit time. The load detection circuit compares the load levels of each processing core and selects the processing core with the lowest load as the migration processing core, outputting its core identifier to subsequent circuits. The core instruction pause circuit is connected to the load detection circuit. After receiving the core identifier of the migration processing core, it sends an instruction pause signal to the instruction issue control terminal of the migration processing core via the control bus within the processing core cluster. Upon receiving this signal, the migration processing core stops instruction fetching after completing all instructions currently in the pipeline and enters a paused state. The context storage circuit is connected to the core instruction pause circuit and external or internal memory. After the core instruction pause circuit confirms that the migration processing core has paused instruction execution, the context storage circuit reads the context data of the currently running program from the internal status output of the migration processing core through a dedicated data channel. The context data includes system-level status information such as the values ​​of general-purpose registers, control status registers, program counters, and page table base address registers. The context storage circuit packages this context data and writes it to a designated temporary storage area of ​​memory through the memory controller. The address modification circuit is connected to the load detection circuit and the program counter input interface of the migration processing core. The address modification circuit uses the preset entry address of the new hardware interrupt request as the new value and writes it directly into the program counter of the migration processing core through the internal write path of the processing core. The entry address of the new hardware interrupt request is the entry address of the corresponding interrupt identifier in the interrupt vector table, which is provided by the hardware interrupt controller when distributing the interrupt request. The context recovery circuit is connected to the memory and the internal status recovery input of the migration processing core. The context recovery circuit listens for the completion signal line of a new hardware interrupt handler. When a level transition indicating completion occurs on this signal line, the context recovery circuit triggers the recovery process. It reads the previously temporarily stored context data of the migration processing core from memory and writes it back to the corresponding registers of the migration processing core item by item according to a preset recovery order. After all context data has been written back, the context recovery circuit releases the paused state of the migration processing core, and the migration processing core resumes execution from the next instruction before it was paused.

[0089] As can be seen from the above, when the inter-core migration circuit operates on the migration processing core, it sequentially executes a hardware operation sequence of load detection, instruction pause, context storage, address modification, and context restoration, so that high-priority interrupt handlers can be executed independently on idle processing cores, reducing resource contention with the current interrupt handler and satisfying the real-time requirements of more processes.

[0090] Based on the above embodiments, please refer to Figure 8 According to an interrupt control method provided by the present invention, applied to the interrupt control device described in any of the above embodiments, in some embodiments of the method, the method includes the following steps: S801: When a new hardware interrupt request is received from the hardware interrupt controller, the estimated completion time of the currently executing hardware interrupt handler and the new hardware interrupt handler corresponding to the new hardware interrupt request are determined, and a program execution control signal is generated according to the task time limit requirements.

[0091] S802: Predicts hardware interrupt requests within a preset time period in the future, selects the target software interrupt request from the generated software interrupt requests that corresponds to the hardware interrupt prediction information and is executed by the same processing core, and sends the target software interrupt request to the processing core.

[0092] S803: Receives program execution control signals forwarded by the processing core cluster and adjusts the processor's hardware operating parameters according to the program execution control signals.

[0093] Among them, the new hardware interrupt request has a higher priority than the current hardware interrupt request. The program execution control signal is used to control the execution order of the new hardware interrupt request and the current hardware interrupt request, and to enable the resource adjustment circuit 33.

[0094] First, the hardware interrupt control circuit 31 continuously monitors the interrupt request output interface of the hardware interrupt controller. When the hardware interrupt controller sends a new hardware interrupt request with a higher priority than the currently executing hardware interrupt request, the hardware interrupt control circuit 31 triggers an estimation process. It reads the instruction information and execution statistics of completed instructions from both the current and new hardware interrupt handlers to determine the estimated completion time for each program segment. Then, the hardware interrupt control circuit 31 compares the two estimated completion times with their corresponding task time limits and generates a program execution control signal based on the comparison result. This signal is then sent to the processing core cluster via its output.

[0095] Meanwhile, the hardware / software interrupt association processing circuit 32 continuously counts the frequency of hardware interrupt requests initiated by each external device within the target historical time period in the background. Based on the statistical results, it predicts which processing cores will execute hardware interrupt handlers within a preset future time period. The hardware / software interrupt association processing circuit 32 continuously checks the queue of software interrupt requests generated but not yet sent in the software interrupt controller. When it finds that a software interrupt request belongs to the same processing task as the hardware interrupt prediction information and is the same as the target processing core, it selects the software interrupt request as the target software interrupt request and sends it to the corresponding processing core.

[0096] After receiving the program execution control signal from the hardware interrupt control circuit 31, the processing core cluster schedules the task execution of each processing core according to the execution order information indicated in the signal, and forwards the program execution control signal to the resource adjustment circuit 33. Upon receiving the program execution control signal forwarded by the processing core cluster, the resource adjustment circuit 33, if the signal contains a resource adjustment enable bit, adjusts the operating frequency, operating voltage, or memory access bandwidth of the corresponding processing core according to the adjustment object and parameters specified in the signal.

[0097] As can be seen from the above, this embodiment dynamically determines the time of each new interrupt based on the current actual execution progress and the estimated completion time of the new interrupt. It also distributes and schedules software interrupts by combining the correlation information between software interrupts and hardware interrupts, and supplements this with automatic hardware adjustment of hardware operating parameters. Therefore, it can maximize the satisfaction of the completion time limits of multiple real-time tasks without the need for software intervention in scheduling decisions and resource adjustment operations.

[0098] It should be noted that there is no strict order of execution between the steps in this invention. As long as they conform to the logical order, these steps can be executed simultaneously or in a certain preset order. Figure 8 This is just an illustrative example and does not mean that this is the only possible execution order.

[0099] Finally, the present invention also provides a processor, see below. Figure 9The processor can be an embedded processor, a microcontroller, or a main processor core cluster. It employs a reduced instruction set computer architecture, such as RISC-V, and includes the interrupt control device described in any of the above embodiments. The fixed instruction code length and simplified addressing mode of the RISC-V architecture allow for the extraction of the instruction opcode and the determination of the instruction type within a single cycle during the instruction fetch phase. When the processor is running a real-time operating system, if multiple external devices generate hardware interrupt requests simultaneously or sequentially, the internal interrupt control device uses a parallel hardware interrupt control circuit 31 and a hardware / software interrupt association processing circuit 32 to perform hardware-level optimization scheduling of the execution order of interrupt requests and the distribution of software interrupts. This achieves coordinated control of software and hardware interrupts, enabling the processor to improve the response speed of multiple interrupt tasks with minimal software intervention, and enhancing the real-time performance of both software and hardware interrupts on the same core and for the same processing task. The hardware / software interrupt association processing circuit 32 determines different processing modes for newly arriving high-priority interrupts and currently being processed interrupts to ensure that the real-time performance of multiple processes is met to the greatest extent possible, further guaranteeing the real-time performance of the RISC-V CPU interrupt control system. Interrupt acceleration is achieved through resource regulation circuit 33, which sacrifices some power consumption in exchange for satisfying the real-time performance of both the current process and higher priority processes, thereby further improving the real-time processing capability and security of the RISC-V CPU.

[0100] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The systems, computing devices, or apparatuses described herein encompass a wide range of means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0101] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0102] The foregoing has provided a detailed description of a processor and its interrupt control method and apparatus provided by the present invention. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Several improvements and modifications can be made to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. An interrupt control device, characterized in that, include: The hardware interrupt control circuit is connected to the hardware interrupt controller and the processing core cluster. When it receives a new hardware interrupt request sent by the hardware interrupt controller, it determines the estimated completion time of the current hardware interrupt handler and the new hardware interrupt handler corresponding to the new hardware interrupt request, and generates a program execution control signal according to the task time limit requirements. The hardware and software interrupt association processing circuit is connected to the processing core cluster. It predicts hardware interrupt requests within a preset time period in the future. Among the generated software interrupt requests, it selects the target software interrupt request that corresponds to the hardware interrupt prediction information, belongs to the same processing task, and is executed by the same processing core. It then sends at least one target software interrupt request to the corresponding processing core. A resource adjustment circuit, connected to the processing core cluster, receives program execution control signals sent by the processing core cluster and adjusts the processor's hardware operating parameters according to the program execution control signals. The new hardware interrupt request has a higher priority than the current hardware interrupt request. The program execution control signal is used to control the execution order of the new hardware interrupt request and the current hardware interrupt request, and to enable the resource adjustment circuit.

2. The interrupt control device according to claim 1, characterized in that, When the hardware interrupt control circuit receives a new hardware interrupt request from the hardware interrupt controller with a priority higher than the currently executing hardware interrupt request, it estimates the remaining instruction completion time based on the total number of instructions in the current hardware interrupt handler and the information on completed instructions; it estimates the corresponding task completion time based on the different execution order of the new hardware interrupt request; and it generates a program execution control signal based on the remaining instruction completion time, the completion time of each task, and the time limit requirements of the current hardware interrupt request and the new hardware interrupt request.

3. The interrupt control device according to claim 2, characterized in that, The hardware interrupt control circuit: Based on the completion time of the first task in the first execution scenario of the new hardware interrupt request, the estimated duration of the first task corresponding to the first execution scenario is determined; the first execution scenario is to end the task execution process of the current hardware interrupt request and directly execute the new hardware interrupt request. Based on the remaining instruction completion time and the second task completion time under the second execution scenario, the estimated duration of the second task corresponding to the second execution scenario is determined; the second execution scenario is that after the current hardware interrupt request task is completed, a new hardware interrupt request is executed. If the estimated duration of the first task exceeds the maximum completion time of the new hardware interrupt request, a first type of program execution control signal is generated and sent to the processing core cluster. The first type of program execution control signal is a control signal that continues to execute the current hardware interrupt handler, transfers the new hardware interrupt handler to other processing cores for execution, and enables the resource adjustment circuit. The task time limit requirement of the new hardware interrupt request is the maximum completion time. If the estimated duration of the first task is less than the maximum completion time of the new hardware interrupt request, and the estimated duration of the second task is greater than the maximum completion time of the new hardware interrupt request, then a second type of program execution control signal is generated and sent to the processing core cluster; the second type of program execution control signal is a control signal that suspends the execution of the current hardware interrupt handler, executes the new hardware interrupt request, and enables the resource adjustment circuit. If the estimated duration of the first task is less than the maximum completion time of the new hardware interrupt request, and the estimated duration of the second task is less than the maximum completion time of the new hardware interrupt request, then a third type of program execution control signal is generated; the third type of program execution control signal is a control signal to continue executing the current hardware interrupt handler and to execute the new hardware interrupt request after the current hardware interrupt handler has been completed.

4. The interrupt control device according to claim 1, characterized in that, The hardware interrupt control circuit includes: The first hardware interrupt handling prediction circuit, when receiving a new hardware interrupt request from the hardware interrupt controller with a priority higher than the currently executing hardware interrupt request, estimates the remaining instruction completion time based on the total number of instructions in the current hardware interrupt handler and the information on completed instructions. The second hardware interrupt handling prediction circuit estimates the corresponding task completion time based on the different execution order of the new hardware interrupt request. The signal trigger generation circuit is connected to the output terminals of the first hardware interrupt handling prediction circuit and the second hardware interrupt handling prediction circuit, respectively. Based on the remaining instruction completion time, the completion time of each task, and the task time limit requirements of the current hardware interrupt request and the new hardware interrupt request, it generates program execution control signals.

5. The interrupt control device according to claim 4, characterized in that, The first hardware interrupt handling prediction circuit includes: The current instruction count counting circuit, when starting to execute the current hardware interrupt request, determines the total number of first-type instructions and the total number of second-type instructions contained in the current hardware interrupt handler based on the start address and end address of the current hardware interrupt handler. The first-type instructions include store instructions and load instructions, and the second-type instructions include other instructions that are not store instructions or load instructions. The instruction completion data statistics circuit counts the number of instructions of the first type and the second type that have been completed at the current moment and the corresponding time consumed. The remaining time estimation circuit is connected to the outputs of the current instruction quantity statistics circuit and the instruction completion data statistics circuit, respectively. It calculates the time consumption of a single instruction corresponding to the first type of instruction and the second type of instruction, and counts the remaining instruction quantity of the first type of instruction and the second type of instruction. Based on the time consumption of a single instruction corresponding to the first type of instruction and the second type of instruction, the remaining instruction quantity, and the weight fluctuation factor, the remaining instruction completion time is calculated. The first duration register is connected to the output of the remaining duration estimation circuit and stores the remaining instruction completion time.

6. The interrupt control device according to claim 5, characterized in that, The current instruction count counting circuit includes: A program counter range comparator has a first comparison input connected to the program counter, a second comparison input connected to an address register, a first comparison output connected to a first type of instruction quantity register, and a second comparison output connected to a second type of instruction quantity register. When the program counter value is between the start address and the end address, it outputs a counting enable signal, and when it exceeds the end address, it outputs a latch enable signal. The first instruction type discriminator has a first discrimination input connected to a first instruction opcode extractor, a first discrimination output connected to a first type of instruction quantity register, and a second discrimination output connected to a second type of instruction quantity register. If the instruction opcode is the opcode of a store instruction or a load instruction, it outputs a first type of instruction counting pulse; if the instruction opcode is the opcode of another instruction, it outputs a second type of instruction counting pulse. The first type of instruction quantity register increments the count value by one for each first type of instruction count pulse received during the count enable signal period; and latches the current count value as the total number of first type of instructions upon receiving the latch enable signal. The second type of instruction quantity register increments the count value by one for each second type of instruction count pulse received during the count enable signal period; and latches the current count value as the total number of second type of instructions upon receiving the latch enable signal.

7. The interrupt control device according to claim 5, characterized in that, The instruction completes the data statistics circuit, including: The second instruction type discriminator has a second discrimination input connected to the second instruction opcode extractor, a third discrimination output connected to the counting enable of the instruction completion counter, and a fourth discrimination output connected to the accumulation enable of the instruction time accumulator. Upon receiving the opcode of a completed instruction, if the opcode is a store instruction or a load instruction, it outputs a first-type instruction completion counting pulse; if the opcode is another instruction, it outputs a second-type instruction completion counting pulse. The instruction completion counter increments the count of completed first-type instructions by one for each first-type instruction completion count pulse received; it also increments the count of completed second-type instructions by one for each second-type instruction completion count pulse received, and outputs the count of completed first-type instructions or the count of completed second-type instructions through the count output terminal. The instruction time accumulator has its data accumulation input connected to the instruction execution cycle counting unit. Each time a first type of instruction completion counting pulse is received, the actual number of execution cycles of the corresponding first type of instruction is accumulated into the cumulative time value of the first type of instruction. Each time a second type of instruction completion counting pulse is received, the actual number of execution cycles of the corresponding second type of instruction is accumulated into the cumulative time value of the second type of instruction. The first total time consumed by the completed first type of instruction or the second total time consumed by the completed second type of instruction is output through the time consumption output terminal.

8. The interrupt control device according to claim 5, characterized in that, The remaining duration estimation circuit includes: The first divider performs a division operation on the first total consumption time and the number of first type instructions completed to obtain the consumption time of the first single instruction corresponding to the first type of instructions, and inputs the consumption time of the first single instruction into the average time register of the first type of instructions; The second divider performs a division operation on the second total consumption time and the number of instructions completed in the second type of instruction to obtain the consumption time of the second single instruction corresponding to the second type of instruction, and inputs the consumption time of the second single instruction into the average time register of the second type of instruction. The first subtractor performs a subtraction operation on the total number of first type instructions and the number of first type instructions completed to obtain the first remaining number of instructions, and sends the first remaining number of instructions to the first multiplier; The second subtractor performs a subtraction operation on the total number of second type instructions and the number of completed second type instructions to obtain the second remaining instruction number, and sends the second remaining instruction number to the second multiplier; The first multiplier is connected to the first type of instruction average time register, the first weight register, and the adder. It reads the duration of the first single instruction and the first weight fluctuation factor, performs multiplication on the first remaining number of instructions, the duration of the first single instruction, and the first weight fluctuation factor to obtain the estimated completion time of the first instruction, and sends it to the adder. The second multiplier is connected to the second type of instruction average time register, the second weight register, and the adder. It reads the duration of the second single instruction and the second weight fluctuation factor, performs a multiplication operation on the second remaining instruction quantity, the duration of the second single instruction, and the second weight fluctuation factor to obtain the estimated completion time of the second instruction, and sends it to the adder; the sum of the second weight fluctuation factor and the first weight fluctuation factor is 1. The adder performs an addition operation on the estimated completion time of the first instruction and the estimated completion time of the second instruction to obtain the remaining instruction completion time.

9. The interrupt control device according to claim 4, characterized in that, The second hardware interrupt handling prediction circuit includes: The new instruction count counting circuit, when receiving a new hardware interrupt request, determines the total number of the first type of instructions and the total number of the second type of instructions contained in the new hardware interrupt handler; The task duration estimation circuit determines the total estimated duration of the first type of instructions based on the duration of the first single instruction and the total number of the first type of instructions; it determines the total estimated duration of the second type of instructions based on the duration of the second single instruction and the total number of the second type of instructions; it determines the estimated duration of the first task corresponding to the first execution scenario based on the total estimated duration of the first type of instructions and the total estimated duration of the second type of instructions; and it determines the estimated duration of the second task corresponding to the second execution scenario based on the remaining instruction completion time and the estimated duration of the first task.

10. The interrupt control device according to claim 4, characterized in that, The signal triggering generation circuit includes: The time limit register is connected to the operating system data bus. When a hardware interrupt is triggered, it receives the maximum completion time of the corresponding hardware interrupt request dynamically written by the operating system. The first comparator is connected to the second hardware interrupt handling estimation circuit and the time limit register, and reads the estimated duration of the first task and the maximum completion time of the new hardware interrupt request, compares the numerical relationship between the estimated duration of the first task and the maximum completion time, and outputs a high level when the estimated duration of the first task is greater than the maximum completion time. The second comparator is connected to the second hardware interrupt handling estimation circuit and the time limit register, and reads the estimated duration of the second task and the maximum completion time of the new hardware interrupt request, compares the numerical relationship between the estimated duration of the second task and the maximum completion time, and outputs a high level when the estimated duration of the second task is greater than the maximum completion time. The first NOT gate is connected to the first comparator and performs a logical inversion on the comparison output of the first comparator. The second NOT gate, connected to the second comparator, performs a logical inversion on the comparison output of the second comparator.

11. The interrupt control device according to claim 10, characterized in that, The signal triggering generation circuit further includes: The first AND gate is connected to the first comparator. When the first comparator outputs a high level, it outputs a first type of program execution control signal. The second AND gate is connected to the first NOT gate and the second comparator. When both the first NOT gate and the second comparator output a high level, it outputs a second type of program execution control signal. The third AND gate is connected to the first NOT gate and the second NOT gate. When both the first NOT gate and the second NOT gate output a high level, a third type of program execution control signal is output. An OR gate, connected to the first AND gate and the second AND gate, performs a logical OR operation on the first type of program execution control signal and the second type of program execution control signal to generate a resource adjustment enable bit; the resource adjustment enable bit in the program execution control signal is used to control whether the processing core cluster enables the resource adjustment circuit. The pattern encoder is connected to the first AND gate, the second AND gate, the third AND gate and the OR gate, and encodes various program execution control signals and the resource adjustment enable bit into program execution code signals; The control signal register is connected to the mode encoder, latches the program execution encoding signal, and outputs it to the processing core cluster.

12. The interruption control device according to any one of claims 1 to 11, characterized in that, The hardware / software interrupt association processing circuit predicts at least one target external device that will initiate a hardware interrupt request within a future preset time period based on the hardware interrupt request statistics within the target historical time period, and determines the target processing core corresponding to the hardware interrupt request of the target external device; it also identifies the target software interrupt request that corresponds to the same processing task as the target external device among the generated software interrupt requests, and sends at least one target software interrupt request to the corresponding target processing core so that the same processing core can execute the software interrupt service and hardware interrupt service for the same processing task.

13. The interrupt control device according to claim 12, characterized in that, The hardware / software interrupt association processing circuit includes: The hardware interrupt prediction circuit predicts at least one target external device that will initiate a hardware interrupt request within a preset future time period based on the hardware interrupt request statistics within the target historical time period. The software interrupt core distribution circuit is connected to the hardware interrupt prediction circuit and the processing core cluster; it determines the target processing core corresponding to the hardware interrupt request of the target external device, identifies the target software interrupt request with the same processing task as the target external device among the generated software interrupt requests, and sends at least one target software interrupt request to the corresponding target processing core so that the same processing core can execute the software interrupt service and hardware interrupt service for the same processing task.

14. The interrupt control device according to claim 13, characterized in that, The hardware interrupt prediction circuit includes: Peripheral request counter: Counts the hardware interrupt requests initiated by each external device within the target historical time period, and outputs the number of historical hardware interrupt requests for each external device within the target historical time period. A peripheral quantity calculation circuit, connected to the peripheral request counter, calculates the predicted number of peripherals that will initiate hardware interrupt requests in the future preset time period based on the duration of the target historical time period, the duration of the future preset time period, and the number of historical hardware interrupt requests. The peripheral device sorting and selection circuit is connected to the peripheral device request counter and the peripheral device quantity calculation circuit. It sorts the historical hardware interrupt request counts of each external device and selects each target external device in descending order of hardware interrupt request counts until the number of target external devices is the same as the predicted number of peripheral devices. The prediction result output register is connected to the peripheral sorting and selection circuit, latches the device identifier of each target external device, and outputs the device identifier of each target external device as hardware interruption prediction information for a future preset time period.

15. The interrupt control device according to claim 13, characterized in that, The software interrupt core distribution circuit includes: The mapping memory, connected to the memory of the software interrupt controller, stores the pre-built peripheral-interrupt mapping and interrupt-processor core mapping read from the memory of the software interrupt controller. The first mapping conversion circuit is connected to the mapping relationship memory and reads the corresponding target interrupt identifier from the mapping relationship memory according to the target external device identifier in the hardware interrupt prediction information. The second mapping conversion circuit is connected to the mapping relationship memory and the first mapping conversion circuit, and reads the corresponding target core identifier from the mapping relationship memory according to the target interrupt identifier; The interrupt request selection circuit, connected to the software interrupt controller and the second mapping conversion circuit, selects the target software interrupt request to be executed by the processing core corresponding to each target core identifier from the generated software interrupt requests, and sends each target software interrupt request to the processing core corresponding to the corresponding target core identifier.

16. The interruption control device according to any one of claims 1 to 11, characterized in that, The resource regulation circuit includes: The signal parsing circuit has its signal input terminal connected to the processing core cluster, and its signal output terminal connected to the overclocking mode startup circuit, the interface adaptation circuit, and the interrupt process inter-core movement circuit, respectively. It parses the control signal type from the program execution control signals sent by the processing core cluster. If the program execution control signal is a first-type program execution control signal, it outputs an enable signal to the overclocking mode startup circuit, the interface adaptation circuit, and the interrupt process inter-core movement circuit; if the program execution control signal is a second-type program execution control signal, it outputs an enable signal to the overclocking mode startup circuit and the interface adaptation circuit. The overclocking mode startup circuit, upon receiving an enable signal, increases the power consumption parameters of the target processing core corresponding to each target software interrupt request; When the interface adapter circuit receives an enable signal, it increases the bandwidth allocation ratio for memory access of the target processing core corresponding to each target software interrupt request and the current processing core corresponding to the current hardware interrupt request. The interrupt process inter-core migration circuit, upon receiving an enable signal, transfers the interrupt handler corresponding to a new hardware interrupt request from the source processing core to the migration processing core for processing.

17. The interrupt control device according to claim 16, characterized in that, The overclocking mode startup circuit includes: Frequency adjustment register stores the frequency adjustment amplitude value; Voltage regulation register, which stores the voltage regulation amplitude value; A frequency control circuit, connected to the signal parsing circuit and the frequency adjustment register, receives the target core identifier of the target processing core corresponding to the target software interrupt request obtained by the signal parsing circuit from the program execution control signal, and adjusts the operating frequency of the corresponding target processing core according to the target core identifier and the frequency adjustment amplitude value. A voltage control circuit, connected to the signal parsing circuit and the voltage adjustment register, receives the target core identifier of the target processing core corresponding to the target software interrupt request obtained by the signal parsing circuit from the program execution control signal, and adjusts the operating voltage of the corresponding target processing core according to the target core identifier and the voltage adjustment amplitude value.

18. The interrupt control device according to claim 16, characterized in that, The interface adapter circuit includes: The bandwidth ratio register stores the bandwidth adjustment ratio value and the upper limit of the bandwidth allocation ratio. A bandwidth allocation adjustment circuit, connected to the signal parsing circuit, the bandwidth ratio register, and the memory controller, receives the target core identifier of the target processing core corresponding to the target software interrupt request and the current core identifier of the current processing core corresponding to the current hardware interrupt request from the program execution control signal obtained by the signal parsing circuit. Based on the target core identifier, the current core identifier, and the bandwidth adjustment ratio value, the circuit increases the bandwidth allocation ratio of the memory controller for the target processing core and the current processing core accessing the memory. A bandwidth limit constraint circuit, connected to the bandwidth allocation adjustment circuit, limits the bandwidth allocation ratio of a single processing core to no more than the upper limit of the bandwidth allocation ratio.

19. The interrupt control device according to claim 16, characterized in that, The interrupt process inter-core movement circuit includes: The load detection circuit is connected to the running status register to obtain the running status information of each processing core in the processing core cluster and determine the migration processing core with the least load. A core instruction pause circuit, connected to the load detection circuit, pauses the instruction execution of the migration processing core; The context storage circuit, connected to the core instruction pause circuit and the memory, temporarily stores the context data of the program running on the migration processing core into the memory. The address modification circuit is connected to the load detection circuit and modifies the instruction fetch address of the migration processing core to the entry address of the new hardware interrupt request. The context recovery circuit is connected to both the memory and the migration processing core. After the new hardware interrupt handler finishes running, it reads the context data of the migration processing core from the memory and restores it to the migration processing core.

20. An interrupt control method, characterized in that, An interrupt control device as described in any one of claims 1 to 19, comprising: When a new hardware interrupt request is received from the hardware interrupt controller, the estimated completion time of the currently executing hardware interrupt handler and the new hardware interrupt handler corresponding to the new hardware interrupt request are determined, and program execution control signals are generated according to the task time limit requirements. Predict hardware interrupt requests within a preset time period in the future; among the generated software interrupt requests, select the target software interrupt request that corresponds to the hardware interrupt prediction information, is executed by the same processing core, and send the target software interrupt request to the corresponding processing core. Receive program execution control signals sent by the processing core cluster, and adjust the processor's hardware operating parameters according to the program execution control signals; The new hardware interrupt request has a higher priority than the current hardware interrupt request. The program execution control signal is used to control the execution order of the new hardware interrupt request and the current hardware interrupt request, and to enable the resource adjustment circuit.

21. A processor, characterized in that, It employs a reduced instruction set computer architecture, including the interrupt control device as described in any one of claims 1 to 19.

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