A server management system and method

Abstract

The application provides a server management system and method, relates to the technical field of servers, and comprises a BMC management board, a node expansion board, a first CPU mainboard node and a second CPU mainboard node. A first management interface of the BMC management board is connected with management interfaces of the two mainboard nodes through the node expansion board. The node expansion board is integrated with a link switching unit, which is connected with a first data interface and the first management interface of the BMC management board, a second data interface of the first CPU mainboard node and a third data interface of the second CPU mainboard node. The BMC management board obtains state information of the two CPU mainboard nodes through the first management interface, and controls the link switching unit to connect the first data interface of the BMC management board to the data interface of the first CPU mainboard node or the second CPU mainboard node based on the state information and a server management instruction, so that the management of the two mainboard nodes by a single BMC is realized.

Description

Technical Field

[0001] This application relates to the field of server technology, and more specifically, to a server management system and method. Background Technology

[0002] The mainstream standard width for rack-mount servers is 19 inches or 21 inches. In traditional designs, a single chassis contains only one BMC (Baseboard Management Controller) board and one motherboard, which onboards two cascaded CPU (Central Processing Unit) chips (i.e., a single motherboard with dual CPUs). As CPU computing power continues to increase, the communication latency between the two CPUs has gradually become a bottleneck for system performance. Therefore, some solutions have been adjusted to a single motherboard, single CPU architecture. However, the single CPU solution still lags behind the dual CPU in terms of computing power. To address this, the industry has adopted a dual-node design: integrating two independent single-CPU motherboard nodes within a standard chassis size to maximize system performance.

[0003] The remote management function of the server is carried out by the BMC. However, due to the limitations of the existing BMC hardware resources and design architecture, one BMC can only support the management of one CPU motherboard node, which cannot meet the management requirements of a dual-node chassis. If two BMCs are used to manage two motherboard nodes respectively, it will lead to an increase in size and cost.

[0004] In summary, how to effectively manage dual-CPU nodes while balancing system computing power and cost is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a server management system and method for effectively managing dual-CPU nodes while balancing system computing power and cost.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows: On the one hand, this application provides a server management system, including a node expansion board, and a BMC management board, a first CPU motherboard node, and a second CPU motherboard node, all connected to the node expansion board. The first management interface of the BMC management board is connected to the second management interface of the first CPU motherboard node and the third management interface of the second CPU motherboard node through the node expansion board. The node expansion board integrates a link switching unit, which is connected to the first data interface and the first management interface of the BMC management board, the second data interface of the first CPU motherboard node, and the third data interface of the second CPU motherboard node. The BMC management board is used to obtain the status information of two CPU motherboard nodes through the first management interface, and based on the status information and the received server management instructions, control the link switching unit to connect the first data interface of the BMC management board to the second data interface of the first CPU motherboard node or the third data interface of the second CPU motherboard node.

[0007] Furthermore, the BMC management board includes a BMC chip, which is connected to the first management interface and the first data interface respectively; the first management interface includes a first IO interface, a second IO interface and a third IO interface, the second management interface includes a first presence detection interface, and the third management interface includes a second presence detection interface; The first IO interface is connected to the first presence detection interface through the node expansion board, and is used to provide the BMC chip with the presence status information of the first CPU motherboard node; The second IO interface is connected to the second presence detection interface through the node expansion board, and is used to provide the BMC chip with the presence status information of the second CPU motherboard node; The third I / O interface is connected to the control terminal of the link switching unit and is used to control the link switching unit to connect the first data interface to the second data interface or the third data interface according to the instructions sent by the BMC chip.

[0008] Furthermore, when the BMC chip determines, based on the presence status information, that only one CPU motherboard node is currently in the presence state, the BMC chip sends a link locking command to the link switching unit through the third IO interface to connect the first data interface to the data interface corresponding to the CPU motherboard node in the presence state.

[0009] Furthermore, the BMC management board also includes a first CPLD chip, and the first management interface further includes a first LTPI interface and a fourth LTPI interface; the first CPLD chip is connected to the BMC chip, the first LTPI interface, and the fourth LTPI interface respectively; The first CPU motherboard node includes a first CPU chip and a second CPLD chip; the first CPU chip is connected to the second management interface and the second data interface respectively; the second management interface further includes a second LTPI interface, and the second CPLD chip is connected to the first CPU chip and the second LTPI interface respectively; The second CPU motherboard node includes a second CPU chip and a third CPLD chip; the second CPU chip is connected to the third management interface and the third data interface respectively; the third management interface further includes a third LTPI interface, and the third CPLD chip is connected to the second CPU chip and the third LTPI interface respectively; The first LTPI interface is connected to the second LTPI interface through the node expansion board, and the fourth LTPI interface is connected to the third LTPI interface through the node expansion board.

[0010] Furthermore, when the BMC chip determines that both CPU motherboard nodes are in the in-situ state based on the in-situ status information, and the server management instruction indicates that the node to be managed is the first CPU motherboard node, the BMC chip is used to send a first switching instruction to the link switching unit to connect the first data interface to the second data interface, and send a first management notification to the first CPLD chip. Upon receiving the first management notification, the first CPLD chip sends a first access preparation signal to the second CPLD chip via the first LTPI interface, the node expansion board, and the second LTPI interface. The second CPLD chip is used to send a valid interrupt signal to the first CPU chip after receiving the first access preparation signal, so as to trigger the first CPU chip to perform hot insertion with the BMC chip.

[0011] Furthermore, when the BMC chip is managing the first CPU motherboard node, if the BMC chip receives a server management instruction instructing the node to be managed to switch from the first CPU motherboard node to the second CPU motherboard node, the BMC chip is used to send a switching notification to the first CPLD chip. Upon receiving the switching notification, the first CPLD chip sends a first removal preparation signal to the second CPLD chip via the first LTPI interface, the node expansion board, and the second LTPI interface. The second CPLD chip is used to send a valid interrupt signal to the first CPU chip after receiving the first removal preparation signal, so as to trigger the first CPU chip to perform hot removal with the BMC chip; After confirming that the first CPU chip has completed hot removal, the BMC chip sends a second switching command to the link switching unit to disconnect the first data interface from the second data interface and connect it to the third data interface, and sends a second management notification to the first CPLD chip. Upon receiving the second management notification, the first CPLD chip sends a second access preparation signal to the third CPLD chip via the fourth LTPI interface, the node expansion board, and the third LTPI interface. The third CPLD chip is used to send a valid interrupt signal to the second CPU chip after receiving the second access preparation signal, so as to trigger the second CPU chip to perform hot insertion with the BMC chip.

[0012] Furthermore, the link switching unit includes a USB multiplexer and a PCIe multiplexer, the first data interface includes a first USB interface and a first PCIe interface, the second data interface includes a second USB interface and a second PCIe interface, and the third data interface includes a third USB interface and a third PCIe interface. The control terminals of the USB multiplexer and the PCIe multiplexer are both connected to the first management interface of the BMC management board. The first, second, and third terminals of the PCIe multiplexer are respectively connected to the first PCIe interface of the BMC management board, the second PCIe interface of the first CPU motherboard node, and the third PCIe interface of the second CPU motherboard node. The first, second, and third ends of the USB multiplexer are respectively connected to the first USB interface of the BMC management board, the second USB interface of the first CPU motherboard node, and the third USB interface of the second CPU motherboard node.

[0013] Furthermore, the first management interface includes a first I3C interface and a first I2C interface, the second management interface includes a second I3C interface and a second I2C interface, and the third management interface includes a third I3C interface and a third I2C interface; The first I3C interface of the BMC management board is connected to the second I3C interface of the first CPU motherboard node and the third I3C interface of the second CPU motherboard node through the node expansion board, respectively, for communication and interaction with the first CPU motherboard node and the second CPU motherboard node. The first I2C interface of the BMC management board is connected to the second I2C interface of the first CPU motherboard node and the third I2C interface of the second CPU motherboard node through the node expansion board, respectively, for collecting temperature and voltage information of the first CPU motherboard node and the second CPU motherboard node.

[0014] Furthermore, the BMC management board integrates a network interface, through which the BMC management board communicates with the host computer; The BMC management board is used to provide a Web management interface to the host computer to receive server management commands sent by the host computer and to display the status information of the two CPU motherboard nodes and the video screen data of the currently managed node to the host computer.

[0015] On the other hand, this application also provides a server management method, applied to a server management system as described in any of the foregoing embodiments, the method comprising: The BMC management board obtains the status information of the two CPU motherboard nodes through the first management interface; Based on the status information and the received server management instructions, the BMC management board controls the link switching unit to connect the first data interface of the BMC management board to the second data interface of the first CPU motherboard node or the third data interface of the second CPU motherboard node.

[0016] Compared with the prior art, this application has the following advantages: The server management system provided in this application includes: a node expansion board, and a BMC management board, a first CPU motherboard node, and a second CPU motherboard node, all connected to the node expansion board. The first management interface of the BMC management board is connected to the second management interface of the first CPU motherboard node and the third management interface of the second CPU motherboard node via the node expansion board. The node expansion board integrates a link switching unit, which is connected to the first data interface and the first management interface of the BMC management board, the second data interface of the first CPU motherboard node, and the third data interface of the second CPU motherboard node. The BMC management board obtains the status information of the two CPU motherboard nodes through the first management interface, and based on the status information and received server management commands, controls the link switching unit to connect the first data interface of the BMC management board to the second data interface of the first CPU motherboard node or the third data interface of the second CPU motherboard node, thereby achieving effective management of two independent CPU motherboard nodes by a single BMC. This system retains the high computing power advantage of a dual-node architecture, overcomes the hardware limitation of traditional BMCs that only support single-motherboard management, and avoids the increased size and cost associated with a dual-BMC solution. Attached Figure Description

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0018] Figure 1 This is a schematic diagram of the existing server architecture; Figure 2 One of the schematic diagrams of a server management system provided in this application embodiment; Figure 3 A second schematic diagram of the architecture of a server management system provided in this application embodiment; Figure 4 This is a flowchart illustrating a server management method provided in an embodiment of this application.

[0019] Icons: 10-Server Management System; 20-Host Computer; 100-BMC Management Board; 110-First Management Interface; 111-First IO Interface; 112-Second IO Interface; 113-Third IO Interface; 114-First LTPI Interface; 115-First I3C Interface; 116-First I2C Interface; 117-Fourth LTPI Interface; 120-First Data Interface; 121-First USB Interface; 122-First PCIe Interface; 130-BMC Chip; 140-First CPLD Chip; 150-Network Interface; 200-Node Expansion Board; 210-Link Switching Unit; 211-USB Multiplexer; 212-PCIe Multiplexer; 300-First CPU Motherboard Node; 3 10 - Second management interface; 311 - First presence detection interface; 312 - Second LTPI interface; 313 - Second I3C interface; 314 - Second I2C interface; 320 - Second data interface; 321 - Second USB interface; 322 - Second PCIe interface; 330 - First CPU chip; 340 - Second CPLD chip; 400 - Second CPU motherboard node; 410 - Third management interface; 411 - Second presence detection interface; 412 - Third LTPI interface; 413 - Third I3C interface; 414 - Third I2C interface; 420 - Third data interface; 421 - Third USB interface; 422 - Third PCIe interface; 430 - Second CPU chip; 440 - Third CPLD chip. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0022] like Figure 1 As shown, in traditional server architecture design, a single server chassis contains only one BMC management board and one motherboard, with two cascaded CPU chips (CPU0 and CPU1) on the motherboard. However, as CPU computing power continues to increase, the communication latency between the two CPUs has gradually become a bottleneck for system performance. Therefore, some solutions have been adjusted to a single-motherboard, single-CPU architecture. But the single-CPU solution still lags behind the dual-CPU solution in terms of computing power. To address this, the industry has adopted a dual-node design: integrating two independent single-CPU motherboard nodes within a standard chassis size to maximize system performance.

[0023] The remote management function of the server is carried out by the BMC. However, due to the limitations of existing BMC hardware resources and design architecture, one BMC can only support the management of one CPU motherboard node, which cannot meet the management requirements of a dual-node chassis. If two BMCs are used to manage two motherboard nodes respectively, it will lead to an increase in size and cost. Therefore, how to effectively manage dual CPU nodes to balance system computing power and cost is a technical problem that urgently needs to be solved by those skilled in the art.

[0024] To resolve the above technical issues, please refer to Figure 2 This application provides a server management system 10, which includes a BMC management board 100, a node expansion board 200, and independent first CPU motherboard nodes 300 and second CPU motherboard nodes 400. The node expansion board 200 is connected to the BMC management board 100, the first CPU motherboard node 300, and the second CPU motherboard node 400.

[0025] The first management interface 110 of the BMC management board 100 is connected to the second management interface 310 of the first CPU motherboard node 300 and the third management interface 410 of the second CPU motherboard node 400 via the bus in the node expansion board 200.

[0026] The node expansion board 200 integrates a link switching unit 210, which is connected to the first management interface 110 of the BMC management board 100, the first data interface 120 of the BMC management board 100, the second data interface 320 of the first CPU motherboard node 300, and the third data interface 420 of the second CPU motherboard node 400.

[0027] The BMC management board 100 is used to obtain the status information of the two CPU motherboard nodes through the first management interface 110, and based on the status information and the received server management instructions, control the link switching unit 210 to connect the first data interface 120 of the BMC management board 100 to the second data interface 320 of the first CPU motherboard node 300 or the third data interface 420 of the second CPU motherboard node 400, thereby realizing effective management of the two CPU motherboard nodes.

[0028] It should be noted that the management interface and data interface in the embodiments of this application may each include one or more sub-interfaces to implement different signal transmission and control functions respectively.

[0029] Therefore, this embodiment of the application constructs a "one-to-two" server management architecture by setting up a node expansion board 200 and integrating a link switching unit 210 within the node expansion board 200. In this architecture, the BMC management board 100 maintains a constant connection with the two CPU motherboard nodes through a management bus to achieve real-time status monitoring of the two nodes. Furthermore, the BMC management board 100 also controls the link switching unit 210 to dynamically select the data bus based on the status signals of the two nodes and server management commands, thereby achieving unified management of two independent CPU motherboard nodes by a single BMC.

[0030] The server management system 10 provided in this application embodiment retains the high computing power advantage of the dual-node architecture, overcomes the hardware limitation of traditional BMCs that only support single motherboard management, and avoids the problems of increased size and cost caused by adopting a dual-BMC solution.

[0031] In one optional implementation, the link switching unit 210 includes a USB (Universal Serial Bus) multiplexer 211 and a PCIe (Peripheral Component Interconnect Express) multiplexer 212. Correspondingly, the first data interface 120 includes a first USB interface 121 and a first PCIe interface 122, the second data interface 320 includes a second USB interface 321 and a second PCIe interface 322, and the third data interface 420 includes a third USB interface 421 and a third PCIe interface 422.

[0032] The control terminals of the USB multiplexer 211 and the PCIe multiplexer 212 are both connected to the first management interface 110 of the BMC management board 100.

[0033] The first, second, and third ends of the PCIe multiplexer 212 are respectively connected to the first PCIe interface 122 of the BMC management board 100, the second PCIe interface 322 of the first CPU motherboard node 300, and the third PCIe interface 422 of the second CPU motherboard node 400.

[0034] The first, second, and third ends of the USB multiplexer 211 are respectively connected to the first USB interface 121 of the BMC management board 100, the second USB interface 321 of the first CPU motherboard node 300, and the third USB interface 421 of the second CPU motherboard node 400.

[0035] Understandably, the PCIe multiplexer 212 can selectively connect the first PCIe interface 122 of the BMC management board 100 to the second PCIe interface 322 of the first CPU motherboard node 300 or the third PCIe interface 422 of the second CPU motherboard node 400, based on the control signals sent by the BMC management board 100, thereby realizing dynamic selection of the PCIe bus. The PCIe bus is used to carry video signals to realize the BMC remote KVM (keyboard, video, mouse) management function, and the PCIe bus supports MCTPOver PCIe communication.

[0036] Similarly, the USB multiplexer 211 can selectively connect the first USB interface 121 of the BMC management board 100 to the second USB interface 321 of the first CPU motherboard node 300 or the third USB interface 421 of the second CPU motherboard node 400, based on the control signals sent by the BMC management board 100, thereby realizing dynamic selection of the USB bus. The USB bus is used in conjunction with KVM functionality to enable remote operation of peripherals such as keyboards, video outputs, and mice.

[0037] Both the PCIe bus and the USB bus only support "point-to-point communication", meaning that a connection can only be established with one target device at a time. By setting up a multiplexer for dynamic selection, a single BMC can access the PCIe and USB resources of two CPU motherboard nodes in a time-sharing manner, thereby solving the bus conflict problem of a single BMC managing two nodes.

[0038] In one alternative implementation, the first management interface 110 includes a first I3C (Improved InterIntegrated Circuit) interface 115 and a first I2C (Inter-Integrated Circuit) interface 116, the second management interface 310 includes a second I3C interface 313 and a second I2C interface 314, and the third management interface 410 includes a third I3C interface 413 and a third I2C interface 414.

[0039] The first I3C interface 115 of the BMC management board 100 is connected to the second I3C interface 313 of the first CPU motherboard node 300 and the third I3C interface 413 of the second CPU motherboard node 400 through the node expansion board 200, respectively, for communication and interaction with the first CPU motherboard node 300 and the second CPU motherboard node 400.

[0040] The first I2C interface 116 of the BMC management board 100 is connected to the second I2C interface 314 of the first CPU motherboard node 300 and the third I2C interface 414 of the second CPU motherboard node 400 via the node expansion board 200, respectively, for collecting sensor information such as temperature and voltage of the first CPU motherboard node 300 and the second CPU motherboard node 400.

[0041] Understandably, both the I3C and I2C buses support a "one master, multiple slaves" communication mode, meaning that a single BMC management board 100, acting as the master device, can simultaneously communicate with the first CPU motherboard node 300 and the second CPU motherboard node 400 without requiring selection via the link switching unit 210. Therefore, the BMC management board 100 can acquire real-time status monitoring data from both CPU motherboard nodes via the I3C and I2C buses, achieving synchronous monitoring of the two nodes.

[0042] In another alternative implementation, the BMC management board 100 integrates a network interface 150, through which the BMC management board 100 communicates with the host computer 20.

[0043] The BMC management board 100 is used to provide a Web management interface to the host computer 20, so as to receive server management commands sent by the host computer 20, and display the status information of the two CPU motherboard nodes and the video screen data of the currently managed node to the host computer 20.

[0044] For example, network interface 150 may be an RJ45 interface. Host computer 20 may be a user computer, used to run a browser to access the Web management interface provided by BMC management board 100, thereby sending server management commands to BMC management board 100 and receiving status information (such as temperature, voltage, etc.) of the two CPU motherboard nodes and video screen data of the managed nodes.

[0045] Therefore, the BMC management board 100, through the integrated network interface 150, constructs a unified remote management portal. Users can access the management interface simply through the browser on the host computer 20, enabling remote status monitoring, node switching, and remote KVM control of the two independent CPU motherboard nodes, thus improving the convenience of management operations and user experience.

[0046] Furthermore, in an optional embodiment, the BMC management board 100 includes a BMC chip 130, which is connected to a first management interface 110 and a first data interface 120, respectively. The first management interface 110 includes a first I / O interface 111, a second I / O interface 112, and a third I / O interface 113; the second management interface 310 includes a first presence detection interface 311; and the third management interface 410 includes a second presence detection interface 411.

[0047] The first IO interface 111 is connected to the first presence detection interface 311 through the node expansion board 200, and is used to provide the BMC chip 130 with the presence status information of the first CPU motherboard node 300.

[0048] The second IO interface 112 is connected to the second presence detection interface 411 via the node expansion board 200, and is used to provide the BMC chip 130 with the presence status information of the second CPU motherboard node 400.

[0049] The third IO interface 113 is connected to the control terminal of the link switching unit 210 and is used to control the link switching unit 210 to connect the first data interface 120 to the second data interface 320 or the third data interface 420 according to the instructions sent by the BMC chip 130.

[0050] Understandably, the BMC chip 130 obtains the on-site status information of the two CPU motherboard nodes in real time through the first IO interface 111 and the second IO interface 112, thereby determining the node configuration mode of the current system (single-node mode or dual-node mode); and according to the node configuration mode and the received server management instructions, sends the corresponding control signal to the link switching unit 210 through the third IO interface 113 to realize the dynamic selection of the target node.

[0051] To better understand this, we will first explain the working principle of the single-node mode.

[0052] After the server host is powered on, the BMC chip 130 reads the level signal of the first presence detection interface 311 through the first IO interface 111 and reads the level signal of the second presence detection interface 411 through the second IO interface 112, thereby identifying the presence status of the first CPU motherboard node 300 and the second CPU motherboard node 400, and finally determining the number of nodes deployed in the current server (single node or dual nodes).

[0053] When the BMC chip 130 determines, based on the presence status information, that only one CPU motherboard node is currently in the presence state (i.e., single-node mode), the BMC chip 130 sends a link locking command to the link switching unit 210 through the third IO interface 113 to connect the first data interface 120 to the data interface corresponding to the CPU motherboard node in the presence state.

[0054] For example, assuming only the first CPU motherboard node 300 is currently present, the BMC chip 130 sends level signals (such as high or low levels) to the control terminals of the USB multiplexer 211 and PCIe multiplexer 212 via the third I / O interface 113, respectively, to select the USB and PCIe links on the BMC side to the second USB interface 321 and the second PCIe interface 322 corresponding to the first CPU motherboard node 300, thereby establishing a data path between the BMC management board 100 and the first CPU motherboard node 300. At this time, all data signals of the first CPU motherboard node 300 are switched to the BMC, and the user can remotely manage the first CPU motherboard node 300 through a web interface.

[0055] In another optional implementation, the BMC management board 100 further includes a first CPLD (Complex Programmable Logic Device) chip 140, and the first management interface 110 further includes a first LTPI (Low-Voltage Differential Signaling Transport Protocol Interface) interface 114 and a fourth LTPI interface 117. The first CPLD chip 140 is connected to the BMC chip 130, the first LTPI interface 114, and the fourth LTPI interface 117, respectively.

[0056] The first CPU motherboard node 300 includes a first CPU chip 330 and a second CPLD chip 340. The first CPU chip 330 is connected to a second management interface 310 and a second data interface 320, respectively. The second management interface 310 also includes a second LTPI interface 312. The second CPLD chip 340 is connected to the first CPU chip 330 and the second LTPI interface 312, respectively.

[0057] The second CPU motherboard node 400 includes a second CPU chip 430 and a third CPLD chip 440. The second CPU chip 430 is connected to a third management interface 410 and a third data interface 420, respectively. The third management interface 410 also includes a third LTPI interface 412. The third CPLD chip 440 is connected to the second CPU chip 430 and the third LTPI interface 412, respectively.

[0058] The first LTPI interface 114 is connected to the second LTPI interface 312 via the node expansion board 200, and the fourth LTPI interface 117 is connected to the third LTPI interface 412 via the node expansion board 200. The LTPI bus is used to implement functions such as motherboard node power management, remote power-on / off, and serial communication.

[0059] Based on the above design, the working principle of the dual-node mode will be explained below.

[0060] When the BMC chip 130 determines that both CPU motherboard nodes are in the in-place state based on the in-place status information, and the server management instruction indicates that the node to be managed is the first CPU motherboard node 300, the BMC chip 130 sends a first switching instruction to the link switching unit 210 to connect the first data interface 120 to the second data interface 320, and sends a first management notification to the first CPLD chip 140.

[0061] The first CPLD chip 140 is used to send a first access preparation signal to the second CPLD chip 340 through the first LTPI interface 114, the node expansion board 200, and the second LTPI interface 312 after receiving the first management notification.

[0062] The second CPLD chip 340 is used to send a valid interrupt signal to the first CPU chip 330 after receiving the first access preparation signal, so as to trigger the first CPU chip 330 to perform hot insertion with the BMC chip 130.

[0063] Furthermore, when the BMC chip 130 is managing the first CPU motherboard node 300, if the BMC chip 130 receives a server management instruction instructing the node to be managed to switch from the first CPU motherboard node 300 to the second CPU motherboard node 400, the BMC chip 130 is used to send a switching notification to the first CPLD chip 140.

[0064] Upon receiving a handover notification, the first CPLD chip 140 sends a first removal preparation signal to the second CPLD chip 340 via the first LTPI interface 114, the node expansion board 200, and the second LTPI interface 312.

[0065] The second CPLD chip 340 is used to send a valid interrupt signal to the first CPU chip 330 after receiving the first removal preparation signal, so as to trigger the first CPU chip 330 to perform hot removal with the BMC chip 130.

[0066] After confirming that the first CPU chip 330 has completed hot removal, the BMC chip 130 sends a second switching command to the link switching unit 210 to disconnect the first data interface 120 from the second data interface 320 and connect it to the third data interface 420, and sends a second management notification to the first CPLD chip 140.

[0067] Upon receiving the second management notification, the first CPLD chip 140 sends a second access preparation signal to the third CPLD chip 440 via the fourth LTPI interface 117, the node expansion board 200, and the third LTPI interface 412.

[0068] The third CPLD chip 440 is used to send a valid interrupt signal to the second CPU chip 430 after receiving the second access preparation signal, so as to trigger the second CPU chip 430 to perform hot insertion with the BMC chip 130.

[0069] For example, BMC adds a "Node 1 / Node 2 switch button" to the web management interface so that users can select the target node to be managed.

[0070] Assuming both CPU motherboard nodes are currently in place, and the user clicks the "Node 1" button via the web interface of the host computer 20 (i.e., the server management command indicates that the node to be managed is the first CPU motherboard node 300), then the BMC chip 130 sends a first switching command through the third IO interface 113 to the control terminals of the USB multiplexer 211 and the PCIe multiplexer 212 respectively, to select the USB link and PCIe link on the BMC side to the second USB interface 321 and the second PCIe interface 322 corresponding to the first CPU motherboard node 300. Furthermore, the BMC chip 130 sends a first management notification to the first CPLD chip 140 to synchronize the current management node information with the first CPLD chip 140.

[0071] After receiving the first management notification, the first CPLD chip 140 sends a first access preparation signal (i.e., notifying the second CPLD chip 340 that "Node 1 is managed") to the second CPLD chip 340 in the first CPU motherboard node 300 via the LTPI bus. After receiving the first access preparation signal, the second CPLD chip 340 pulls the I2C Alert_N signal low and sends a valid interrupt signal to the first CPU chip 330 to trigger the first CPU chip 330 to perform PCIe hot-plugging with the BMC chip 130.

[0072] After hot-plugging is completed, the OS (Operating System) of the first CPU motherboard node 300 recognizes the BMC device, and the video signal is transmitted to the BMC chip 130 through the PCIe bus; at the same time, after the USB link is switched, the OS automatically recognizes the USB device, and finally realizes the remote KVM management function of the first CPU motherboard node 300.

[0073] When the BMC chip 130 is managing the first CPU motherboard node 300, if the user clicks the "Switch to Node 2" button through the Web interface (i.e., the server management command instructs the node to be managed to switch from the first CPU motherboard node 300 to the second CPU motherboard node 400), the BMC chip 130 sends a switching notification to the first CPLD chip 140.

[0074] After receiving the switching notification, the first CPLD chip 140 sends a first removal preparation signal to the second CPLD chip 340 via the LTPI bus (i.e., notifying the second CPLD chip 340 that "Node 1 management is canceled"). After receiving the first removal preparation signal, the second CPLD chip 340 pulls down the I2C Alert_N signal and sends a valid interrupt signal to the first CPU chip 330 to trigger the first CPU chip 330 to perform PCIe hot removal with the BMC chip 130.

[0075] After the first CPU chip 330 releases the PCIe resources of the BMC, it feeds back to the BMC chip 130 via the I2C bus. After confirming the completion of hot-removal of the first CPU chip 330 through the first I2C interface 116, the BMC chip 130 sends a second switching command to the control terminals of the USB multiplexer 211 and the PCIe multiplexer 212 respectively through the third I / O interface 113, to select the USB and PCIe links on the BMC side to the third USB interface 421 and the fourth PCIe interface corresponding to the second CPU motherboard node 400. Furthermore, the BMC chip 130 sends a second management notification to the first CPLD chip 140 to synchronize the current management node information with the first CPLD chip 140.

[0076] After receiving the second management notification, the first CPLD chip 140 sends a second access preparation signal to the third CPLD chip 440 via the LTPI bus (i.e., notifying the third CPLD chip 440 that "Node 2 is being managed"). Upon receiving the second access preparation signal, the third CPLD chip 440 pulls the I2C Alert_N signal low and sends a valid interrupt signal to the second CPU chip 430 to trigger the second CPU chip 430 to perform a PCIe hot-plug with the BMC chip 130. After the hot-plug is complete, the user can remotely manage the second CPU motherboard node 400 via the web.

[0077] In addition, please see Figure 3 In one optional implementation, the node expansion board 200 can be connected to the BMC management board 100, the node expansion board 200 to the first CPU motherboard node 300, and the node expansion board 200 to the second CPU motherboard node 400 via board-to-board connectors (such as GEN-Z 4C connectors + gold fingers), thereby realizing the modular combination of CPU motherboard nodes, BMC management cards, and node expansion cards, and improving the flexibility and scalability of hardware configuration.

[0078] In summary, the server management system provided in this application adopts a multi-node dynamic link switching architecture of "BMC+CPLD+MUX" to achieve dynamic selection of the PCIe / USB point-to-point bus between two nodes, thereby supporting remote switching management of two nodes. Through the CPLD's LTPI and I2C Alert_N hardware triggers, combined with the CPU's PCIe hot-plugging process, a hardware signal-based hot-plug linkage mechanism is constructed, realizing the automatic release and reconstruction of link resources during node switching and ensuring the stability of link switching. This application solves the bus conflict problem of a single BMC managing two nodes. After power-on, the BMC can automatically identify the number of nodes in place and can perform status monitoring, remote KVM control, power management, and other operations on two independent nodes. While balancing system computing power and cost, it significantly improves the manageability and reliability of the server.

[0079] Based on the above system concept, please refer to Figure 4 In another optional implementation, this application embodiment also provides a server management method, which is applied to a server management system as described in any of the foregoing embodiments, and the method includes the following steps: In step S10, the BMC management board obtains the status information of the two CPU motherboard nodes through the first management interface.

[0080] In step S20, based on the status information and the received server management instructions, the BMC management board controls the link switching unit to connect the first data interface of the BMC management board to the second data interface of the first CPU motherboard node or the third data interface of the second CPU motherboard node.

[0081] For specific limitations on server management methods, please refer to the limitations on server management systems mentioned above, which will not be repeated here.

[0082] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0083] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A server management system, characterized in that, It includes a node expansion board, and a BMC management board, a first CPU motherboard node, and a second CPU motherboard node, all of which are connected to the node expansion board. The first management interface of the BMC management board is connected to the second management interface of the first CPU motherboard node and the third management interface of the second CPU motherboard node through the node expansion board. The node expansion board integrates a link switching unit, which is connected to the first data interface and the first management interface of the BMC management board, the second data interface of the first CPU motherboard node, and the third data interface of the second CPU motherboard node. The BMC management board is used to obtain the status information of two CPU motherboard nodes through the first management interface, and based on the status information and the received server management instructions, control the link switching unit to connect the first data interface of the BMC management board to the second data interface of the first CPU motherboard node or the third data interface of the second CPU motherboard node. The BMC management board includes a BMC chip, which is connected to the first management interface and the first data interface respectively; the first management interface includes a first IO interface, a second IO interface and a third IO interface, the second management interface includes a first presence detection interface, and the third management interface includes a second presence detection interface. The first IO interface is connected to the first presence detection interface through the node expansion board, and is used to provide the BMC chip with the presence status information of the first CPU motherboard node; The second IO interface is connected to the second presence detection interface through the node expansion board, and is used to provide the BMC chip with the presence status information of the second CPU motherboard node; The third IO interface is connected to the control terminal of the link switching unit and is used to control the link switching unit to connect the first data interface to the second data interface or the third data interface according to the instructions sent by the BMC chip. The BMC management board further includes a first CPLD chip, and the first management interface further includes a first LTPI interface and a fourth LTPI interface; the first CPLD chip is connected to the BMC chip, the first LTPI interface and the fourth LTPI interface respectively; The first CPU motherboard node includes a first CPU chip and a second CPLD chip; the first CPU chip is connected to the second management interface and the second data interface respectively; the second management interface further includes a second LTPI interface, and the second CPLD chip is connected to the first CPU chip and the second LTPI interface respectively; The second CPU motherboard node includes a second CPU chip and a third CPLD chip; the second CPU chip is connected to the third management interface and the third data interface respectively; the third management interface further includes a third LTPI interface, and the third CPLD chip is connected to the second CPU chip and the third LTPI interface respectively; The first LTPI interface is connected to the second LTPI interface through the node expansion board, and the fourth LTPI interface is connected to the third LTPI interface through the node expansion board; When the BMC chip determines that both CPU motherboard nodes are in the in-place state based on the in-place status information, and the server management instruction indicates that the node to be managed is the first CPU motherboard node, the BMC chip is used to send a first switching instruction to the link switching unit to connect the first data interface to the second data interface, and send a first management notification to the first CPLD chip. Upon receiving the first management notification, the first CPLD chip sends a first access preparation signal to the second CPLD chip via the first LTPI interface, the node expansion board, and the second LTPI interface. The second CPLD chip is used to send a valid interrupt signal to the first CPU chip after receiving the first access preparation signal, so as to trigger the first CPU chip to perform hot insertion with the BMC chip; When the BMC chip is managing the first CPU motherboard node, if the BMC chip receives a server management instruction instructing the node to be managed to switch from the first CPU motherboard node to the second CPU motherboard node, the BMC chip is used to send a switching notification to the first CPLD chip. Upon receiving the switching notification, the first CPLD chip sends a first removal preparation signal to the second CPLD chip via the first LTPI interface, the node expansion board, and the second LTPI interface. The second CPLD chip is used to send a valid interrupt signal to the first CPU chip after receiving the first removal preparation signal, so as to trigger the first CPU chip to perform hot removal with the BMC chip; After confirming that the first CPU chip has completed hot removal, the BMC chip sends a second switching command to the link switching unit to disconnect the first data interface from the second data interface and connect it to the third data interface, and sends a second management notification to the first CPLD chip. Upon receiving the second management notification, the first CPLD chip sends a second access preparation signal to the third CPLD chip via the fourth LTPI interface, the node expansion board, and the third LTPI interface. The third CPLD chip is used to send a valid interrupt signal to the second CPU chip after receiving the second access preparation signal, so as to trigger the second CPU chip to perform hot insertion with the BMC chip.

2. The server management system according to claim 1, characterized in that, When the BMC chip determines that only one CPU motherboard node is in the in-situ state based on the in-situ status information, the BMC chip sends a link locking command to the link switching unit through the third IO interface to connect the first data interface to the data interface corresponding to the CPU motherboard node in the in-situ state.

3. The server management system according to claim 1, characterized in that, The link switching unit includes a USB multiplexer and a PCIe multiplexer. The first data interface includes a first USB interface and a first PCIe interface. The second data interface includes a second USB interface and a second PCIe interface. The third data interface includes a third USB interface and a third PCIe interface. The control terminals of the USB multiplexer and the PCIe multiplexer are both connected to the first management interface of the BMC management board. The first, second, and third terminals of the PCIe multiplexer are respectively connected to the first PCIe interface of the BMC management board, the second PCIe interface of the first CPU motherboard node, and the third PCIe interface of the second CPU motherboard node. The first, second, and third ends of the USB multiplexer are respectively connected to the first USB interface of the BMC management board, the second USB interface of the first CPU motherboard node, and the third USB interface of the second CPU motherboard node.

4. The server management system according to claim 1, characterized in that, The first management interface includes a first I3C interface and a first I2C interface; the second management interface includes a second I3C interface and a second I2C interface; and the third management interface includes a third I3C interface and a third I2C interface. The first I3C interface of the BMC management board is connected to the second I3C interface of the first CPU motherboard node and the third I3C interface of the second CPU motherboard node through the node expansion board, respectively, for communication and interaction with the first CPU motherboard node and the second CPU motherboard node. The first I2C interface of the BMC management board is connected to the second I2C interface of the first CPU motherboard node and the third I2C interface of the second CPU motherboard node through the node expansion board, respectively, for collecting temperature and voltage information of the first CPU motherboard node and the second CPU motherboard node.

5. The server management system according to claim 1, characterized in that, The BMC management board integrates a network interface, and the BMC management board communicates with the host computer through the network interface. The BMC management board is used to provide a Web management interface to the host computer to receive server management commands sent by the host computer and to display the status information of the two CPU motherboard nodes and the video screen data of the currently managed node to the host computer.

6. A server management method, characterized in that, Applied to the server management system as described in any one of claims 1-5, the method comprises: The BMC management board obtains the status information of the two CPU motherboard nodes through the first management interface; Based on the status information and the received server management instructions, the BMC management board controls the link switching unit to connect the first data interface of the BMC management board to the second data interface of the first CPU motherboard node or the third data interface of the second CPU motherboard node.

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