High-bandwidth memory fpga sparse lu decomposition acceleration method based on asynchronous task triggering

Abstract

This invention discloses a high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering, belonging to the field of LU decomposition hardware acceleration technology, to solve the performance bottlenecks and efficiency challenges faced by sparse LU decomposition acceleration on FPGAs. The method includes: data and dependency preprocessing to generate a dependency list and dependency triggering mapping list for FPGA runtime scheduling; customizing the FPGA hardware acceleration architecture; updating fine-grained dependencies based on runtime columns; employing a dual-queue task distribution strategy, prioritizing high data affinity tasks to corresponding processing unit groups based on pre-determined data affinity mapping relationships; when the local task queue is unavailable, tasks are allocated through a global task queue in a round-robin fashion; each PEG receives the triggered sparse segmentation task, asynchronously loads the original matrix data and dependency L / U factors, and completes the sparse LU numerical decomposition through parallel multiplication, accumulation, and division calculations.

Description

Technical Field

[0001] This invention belongs to the field of hardware acceleration technology for LU decomposition, specifically relating to a method for accelerating sparse LU decomposition in FPGA based on asynchronous task triggering with high bandwidth memory (HBM). Background Technology

[0002] Solving large sparse linear equation systems Ax = b is a core computational task in scientific computing and engineering applications, widely used in key areas such as circuit simulation, finite element analysis, and power system modeling. As the problem size in application scenarios continues to increase, sparse LU decomposition often accounts for the dominant computational cost of the entire solution process, making it a key bottleneck hindering high-performance computing efficiency. Therefore, developing efficient hardware acceleration techniques specifically for sparse LU decomposition is of paramount practical significance.

[0003] For decades, researchers have primarily focused on accelerating sparse LU decomposition on traditional central processing unit (CPU) and graphics processing unit (GPU) platforms. However, compared to the fixed hardware architectures of CPU and GPU platforms, field-programmable gate arrays (FPGAs) can implement customized parallel dataflow architectures, exhibiting lower computational latency, better power consumption control, and higher utilization of underlying hardware resources when handling sparse workloads. Furthermore, sparse LU decomposition is inherently a highly memory-intensive computational task, characterized by extremely frequent and complex random memory access patterns, which places stringent demands on the memory bandwidth of the hardware system. Compared to traditional double data rate (DDR) memory, HBM technology offers significantly higher memory access bandwidth and more independent parallel memory channels, making HBM-enabled FPGA architectures an ideal platform for addressing the severe memory access challenges in sparse LU decomposition.

[0004] Despite the immense hardware potential of the HBM FPGA platform, its efficient acceleration on HBM FPGAs still faces significant technical obstacles due to the inherently complex computational patterns and highly irregular data dependencies of sparse LU decomposition. Existing hardware acceleration schemes and scheduling mechanisms exhibit the following significant technical shortcomings and performance bottlenecks in practical applications: (1) Coarse-grained hierarchical dependencies lead to severe redundant synchronization overhead. Traditional sparse LU decomposition acceleration schemes typically rely on hierarchical synchronization scheduling strategies based on elimination trees. This strategy uses columns as the smallest scheduling unit and sets fixed synchronization barriers between different computational levels: the system forces a task in a certain column to wait for all tasks in its level to finish executing completely before starting tasks in the next level. This mechanism means that even if the prerequisites of a certain column have been satisfied, it must still wait due to the execution of other unrelated tasks in the same level. This coarse-grained scheduling method introduces redundant synchronization constraints far exceeding the inherent data dependencies of sparse LU decomposition, causing frequent pipeline stalls and resulting in a large amount of computing resources being idle.

[0005] (2) Centralized fine-grained scheduling architecture suffers from severe serial computing bottlenecks. Most existing accelerator architectures employ centralized scheduling units, requiring a central node to uniformly perform complex execution status tracking and fine-grained dependency resolution for each task. However, with the continuous expansion of the scale of on-chip parallel processing elements (PEs), this serial processing mechanism of centrally resolving dependent tasks and distributing instructions is difficult to fully match the ultra-high processing throughput of the underlying massively parallel PEs. The heavy burden of dependency resolution makes the centralized scheduler the performance bottleneck of the entire system, severely limiting the upper limit of parallel computing of the overall architecture.

[0006] (3) Dynamic task flow leads to an irreconcilable conflict between load balancing and data locality. The highly irregular dependencies in a sparse matrix generate a dynamic and non-uniform task distribution flow, which inevitably leads to severe load imbalance between different PEs. Blindly applying a global allocation scheme will disrupt the affinity mapping between computational tasks and specific PEs, thereby severely sacrificing the locality and reuse rate of cached L / U factor data in local memory. Under the current technology system, it is difficult to maintain high PE hardware utilization while dynamically taking into account and maximizing the locality of critical computational data.

[0007] In summary, there is an urgent need in this field for a novel approach to eliminate hardware synchronization overhead caused by coarse-grained dependencies, break the serial bottleneck caused by centralized scheduling, and resolve the technical contradiction between hardware load balancing and data locality. Summary of the Invention

[0008] To overcome the shortcomings of existing technologies, the present invention aims to provide a high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering, so as to solve the problems of large hierarchical synchronization overhead, severe centralized scheduling bottleneck, unbalanced dynamic task flow load, and difficulty in maintaining data locality when accelerating sparse LU decomposition on FPGA.

[0009] The technical problem to be solved by this invention can be achieved through the following specific technical solutions: The high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering includes the following steps: Data and dependency preprocessing: Based on the symbolic decomposition results of the sparse matrix, the column-level dependencies in the sparse LU decomposition process are decomposed in a fine-grained manner to generate a dependency list and a dependency trigger mapping list for FPGA runtime scheduling. Customized FPGA hardware acceleration architecture: Construct a hardware architecture that includes a global control unit, a dedicated computing core array, and a hierarchical storage module to decouple task triggering, dependency resolution, data loading, and numerical computation. Asynchronous task triggering: Fine-grained dependencies are updated based on runtime column completion signals. When the dependency count of a certain computation segment reaches zero, it is immediately triggered as an executable task without waiting for the computation of other irrelevant columns in the same level to complete. Locality-aware load balancing: A dual-queue task distribution strategy is adopted. Based on the pre-determined data affinity mapping relationship, tasks with high data affinity are preferentially allocated to the corresponding processing element group (PEG) to improve the reuse rate of the L / U factor in local storage. When the corresponding local task queue is full, the task affinity is not obvious, or the local task queue of the PEG is empty, tasks are then allocated to the idle PEG through the global task queue in a round-robin manner to ensure the utilization rate of processing units. Parallel execution of sparse LU decomposition: Each PEG receives the triggered sparse segmentation task, asynchronously loads the original matrix data and dependent L / U factors, and completes the sparse LU numerical decomposition through parallel multiplication, accumulation and division calculations.

[0010] Furthermore, the data and dependency preprocessing includes: constructing column dependencies based on the non-zero L / U structure obtained after preprocessing and symbolic decomposition of the sparse matrix; further decomposing the traditional coarse-grained dependencies based on columns into fine-grained dependencies based on continuous sparse segments, thereby forming a segmented task dependency graph.

[0011] Furthermore, the fine-grained dependencies are represented by a dependency degree list and a dependency triggering mapping list. The dependency degree list records the number of unmet predecessor dependencies for each sparse segment task; the dependency triggering mapping list records which subsequent segment tasks' dependencies should be updated after a column is decomposed. Through these lists, complex runtime dependency resolution is transformed into table entry lookups and counter update operations, thereby reducing the hardware complexity of dynamic scheduling on the FPGA.

[0012] Furthermore, the global control unit is used to maintain dependency count status, process column completion signals, trigger executable segmented tasks, and generate a ready task flow. The global control unit mainly includes a column completion signal merging module and a dependency scheduling module. The column completion signal merging module is used to collect column completion signals generated by multiple PEGs and merge them into a unified completion event flow. The dependency count scheduling module is used to query the dependency trigger mapping list according to the completion event flow, update the dependency count of the corresponding segmented task, and output the segmented task with the dependency count reaching zero as a ready task.

[0013] Furthermore, the dedicated computing core array is used to receive ready task streams and complete task allocation, dependency metadata parsing, matrix data loading, L / U factor acquisition, and multiplication-accumulation and division calculations. It includes a task allocation unit, a dependency entry unit, a segmentation processing unit, and multiple PEGs. Specifically, the task allocation unit allocates tasks to corresponding PEGs based on the locality attributes and queue status of ready tasks; the dependency entry unit reads dependency information from the metadata pointer carried by the task and generates dependency instructions; the segmentation processing unit asynchronously requests the original matrix data according to the task instructions and caches it in an on-chip buffer; the PEG obtains the required L / U factors from the hierarchical storage module according to the dependency instructions and performs sparse LU decomposition calculations.

[0014] Furthermore, the hierarchical storage module includes local storage and shared storage. Local storage is located within each PEG and is used to store L / U factors recently calculated or frequently accessed by that PEG. Shared storage is accessed by multiple PEGs and is used to store L / U factors reused across PEGs. When neither local storage nor shared storage is hit, external HBM is then accessed. The storage access order is: local storage, shared storage, external HBM.

[0015] Furthermore, the asynchronous task triggering process includes: the global control unit receiving a column completion signal from the computing core array; searching for the successor segmented task that depends on the column corresponding to the column completion signal according to the dependency triggering mapping list; performing a decrement operation on the dependency count of the corresponding segmented task; and when the dependency count of a segmented task becomes zero, immediately marking it as a ready task and sending it into the task flow. Thus, a task only needs to wait for its actual predecessor dependency to complete, without needing to wait for all column tasks in the entire hierarchy to complete.

[0016] Furthermore, the locality-aware dual-queue load balancing strategy includes a local task queue and a global task queue. For tasks with high data affinity, they are written into the local task queue corresponding to the PEG (Data Context), and tasks are preferentially retrieved from the local task queue for execution to improve the reuse rate of the L / U factor in local storage. For tasks with low affinity, or when the local task queue can no longer receive tasks, they are written into the global task queue and distributed to idle PEGs using a global round-robin method to avoid some processing units being idle for a long time.

[0017] Data affinity can be determined by the column to which the task belongs, the L / U factor accessed by the task, the HBM bank corresponding to the task, and the data reuse relationship between the task and a recently executed task in a PEG. A high data affinity task refers to a task whose required L / U factor has a high probability of reuse with data recently calculated or cached by a PEG. Such tasks are preferentially assigned to the corresponding PEG through static mapping, thereby reducing the overhead of off-chip HBM access and cross-PEG data transfer.

[0018] Furthermore, the sparse LU decomposition calculation adopts a left-look decomposition method. For the current segment to be processed, PEG first reads the L / U factor corresponding to the predecessor column according to the dependency instruction, and performs multiply-accumulate update on the original matrix data; after completing the elimination of all dependency contributions, it first generates the diagonal element U(j,j) of the current column, and then performs normalized division operation on the elements below the diagonal in the current column based on the diagonal element to generate the final L / U factor result.

[0019] Furthermore, the multiply-accumulate operation includes: multiple PEs reading the sparse data of the current segment and the dependent column L / U factor in parallel, performing multiplication and addition / subtraction updates on the corresponding elements to eliminate the contribution of the predecessor column to the current column; the division operation includes: after the multiply-accumulate update is completed, using a pipelined floating-point division unit to normalize the elements below the diagonal in the current column to obtain the final L factor, while retaining the corresponding U factor.

[0020] Furthermore, in the high-bandwidth memory FPGA sparse LU decomposition acceleration method, preprocessing and symbolic decomposition are performed once on the host side to generate reusable sparse structure information, fine-grained dependency metadata, segmented task information, and matrix layout information; during multiple numerical decomposition processes, the FPGA side reuses the above metadata, only updates the matrix values ​​and performs numerical LU decomposition.

[0021] Compared with the prior art, the present invention has the following advantages: (1) This invention improves the hierarchical synchronization method in traditional sparse LU decomposition to a fine-grained asynchronous task triggering method, so that the task only needs to wait for its real predecessor dependency to complete, without waiting for all tasks in the entire hierarchy to complete, thereby reducing redundant synchronization overhead and improving computational parallelism.

[0022] (2) The present invention adopts a hardware structure that decouples the global control unit from the dedicated computing core array, and separates the execution of dependency state maintenance, task triggering, task allocation, data loading and numerical calculation, thereby avoiding the centralized scheduler bearing all the pressure of dependency parsing and task distribution, thus alleviating the bottleneck of serial scheduling.

[0023] (3) This invention proposes a locality-aware dual-queue load balancing strategy, which prioritizes high affinity tasks to be executed within a fixed PEG while maintaining high utilization of the processing unit, thereby improving the reuse rate of the L / U factor in local storage and reducing high-latency off-chip HBM access.

[0024] (4) The present invention improves the on-chip data reuse rate by using a hierarchical storage access mechanism consisting of local storage, shared storage and HBM, while avoiding the complex full interconnection data forwarding structure between PEG, reducing hardware implementation complexity and improving overall energy efficiency. Attached Figure Description

[0025] Figure 1 This invention describes a fine-grained dependency resolution process used to generate dependency lists and dependency trigger lists. Figure 2 This is a hardware architecture diagram of the HBM FPGA hardware accelerator proposed in this invention; Figure 3 Here is the asynchronous task activation algorithm proposed in this invention; where (a) is an example of the asynchronous task activation mechanism, and (b) is a flowchart of the asynchronous task activation algorithm; Figure 4 This invention proposes a locality-aware dual-queue load balancing strategy. Figure 5 This is a comparison of the performance of the present invention and cuDSS on NVIDIA RTX A6000 and Tesla V100 GPUs; where (a) is a comparison of the throughput of the present invention and the GPU baseline, and (b) is a comparison of the energy efficiency of the present invention and the GPU baseline. Figure 6 This is a comparison of the relative performance of the present invention and CKTSO. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0027] This invention provides a high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering. This method generates fine-grained dependency metadata through host-side preprocessing and constructs a hardware acceleration architecture for asynchronous task triggering on the FPGA side. This allows the sparse LU decomposition task to start immediately after the actual predecessor dependency is satisfied, thereby reducing redundant waiting caused by traditional hierarchical synchronization and improving processing unit utilization and on-chip data reuse rate.

[0028] A high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering includes the following: (a) Host-side preprocessing The host-side preprocessing process mainly includes five steps: matrix reading, symbol analysis, sparse segmentation task generation, dependency metadata generation, and matrix data packaging.

[0029] First, the host reads the input sparse matrix and reorders the matrix data.

[0030] Subsequently, the host performs symbolic analysis based on the non-zero structure of the sparse matrix to obtain the non-zero patterns of the L and U factors, as well as the predecessor dependencies between each column.

[0031] Building upon this, the host no longer treats the entire column as the sole scheduling unit, but instead further divides each column into multiple sparse segmentation tasks. For a given column to be processed, the host first collects the non-zero row indices from the original matrix of that column; then, combining this with the set of predecessor dependent columns, it adds the L-factor row indices that may participate in the current column update to the active row set; finally, according to a preset row window height, the active row set is divided into multiple consecutive row ranges, each row range corresponding to a sparse segmentation task. Each sparse segmentation task includes information such as the column number, segment row range, matrix A data start address, number of data words, L-factor write-back base address, U-factor write-back address, and column end marker. The FPGA maintains a segment completion count for each column, and generates a column completion signal when all segments of that column have been written back.

[0032] Furthermore, the host generates dependency metadata based on the symbolic analysis results. The dependency metadata includes a dependency degree list and a dependency triggering mapping list. The dependency degree list records the number of unmet predecessor dependencies for each segment task; the dependency triggering mapping list records which subsequent segment tasks' dependency counts should be updated upon completion of a certain column. Specifically, such as... Figure 1As shown, the dependency metadata generation process includes steps 1 to 3. Step 1: The host determines the inter-column dependencies based on the non-zero structure of the U factor. If the current column j has a non-zero element U(k,j) at the corresponding position of the predecessor column k, then the predecessor column k is recorded as a dependent column of the current column j. Step 2: The host, combining the non-zero structure of the L factor and the segmentation results of the current column, determines whether each segment task is actually affected by the corresponding dependent column. If the row range corresponding to a certain segment intersects with the set of non-zero L factor rows of the predecessor column k, then the segment task is considered to depend on the predecessor column k. Step 3: The host generates a dependency degree list and a dependency trigger mapping list based on the segment-level dependency relationships. The dependency degree list records the set of predecessor dependencies or the number of predecessor dependencies that each segment task has not yet satisfied, and the dependency trigger mapping list records the set of subsequent segment tasks that need to be updated after a certain predecessor column is completed.

[0033] Furthermore, to accommodate the wide bit-width access characteristics of off-chip high-bandwidth storage, the host also packages the matrix A data. For each sparse segment, the host collects the non-zero elements of the original matrix that fall within the row range of that segment and packages them into wide data words. Each wide data word includes multiple element slots, and each slot stores the row offset and value of a sparse element. If a slot is not occupied by a valid element, an invalid element marker is filled in so that it can be skipped when read by the FPGA.

[0034] This invention moves the complex symbol structure analysis and dependency relationship construction to the host side, so that the FPGA side mainly performs metadata loading, task triggering and numerical calculation, thereby reducing the complexity of the FPGA side control logic.

[0035] (II) FPGA Hardware Acceleration Architecture Design like Figure 2 As shown, this invention constructs a hardware acceleration architecture for sparse LU decomposition on an FPGA for asynchronous task triggering. This architecture uses high-bandwidth memory as the off-chip data storage foundation and streaming data paths as the on-chip communication method. By decoupling task activation, dependency resolution, task allocation, matrix data loading, and numerical computation, it achieves parallel acceleration of sparse LU decomposition.

[0036] Overall, this FPGA hardware acceleration architecture mainly includes a global control unit, a dedicated computing core array, and a hierarchical storage module. The global control unit is responsible for collecting column completion events, updating dependency counts, and generating ready tasks. The dedicated computing core array is responsible for task allocation, dependency parsing, segmented reading of matrix A, and multiplication / accumulation / division calculations. The hierarchical storage module provides local access, shared access, and off-chip high-bandwidth storage access for L / U factors. Through this structure, this invention separates complex runtime dependency management from the numerical computation process, enabling the computing cores to receive tasks and data in a streaming manner, thereby reducing centralized scheduling bottlenecks.

[0037] (1) Global control unit The global control unit is used to implement asynchronous activation of sparse segmented tasks. This unit mainly includes a column completion signal merging module and a dependency counting scheduling module.

[0038] The column completion signal merging module receives column completion signals from multiple PEGs. Once all segments of a column have been calculated and the L / U factor has been written back, the corresponding PEG or column completion signal merging module generates a column completion signal. Since multiple PEGs may perform calculations on different columns in parallel, the column completion signal merging module aggregates column completion signals from different PEGs into a unified column completion event stream and sends it to the dependency counting scheduling module.

[0039] The dependency counting scheduling module updates the dependency status of subsequent segment tasks based on column completion events. Specifically, this module preloads a dependency list and a dependency trigger mapping list generated on the host side. When a completion event for a column is received, the dependency counting scheduling module searches for all subsequent segment tasks that depend on that column according to the dependency trigger mapping list and decrements the current dependency of these subsequent segment tasks. When the dependency of a subsequent segment task reaches zero, it means that all the preceding columns required by that segment task have been completed. At this point, the dependency counting scheduling module immediately packages the segment task into a ready segment task and outputs it to the dedicated computing core array.

[0040] This global control unit activates tasks using table lookups and counter updates, rather than performing complex dependency graph searches in real-time on the FPGA. This transforms the irregular runtime scheduling problem in sparse LU decomposition into a regular table access and counter update problem, making it more suitable for FPGA hardware implementation. Furthermore, since tasks are triggered only immediately after the actual dependencies are satisfied, this design breaks down traditional hierarchical synchronization barriers, reducing waiting time caused by irrelevant columns.

[0041] (2) Dedicated computing core array A dedicated computing core array is used to perform the main numerical computations for sparse LU decomposition. This array receives a stream of ready segmented tasks from the global control unit and performs task allocation, dependency resolution, segmented loading of matrix A, L / U factor reading, and multiply-accumulate and divide calculations.

[0042] The dedicated computing core array includes a task allocation unit, a dependency entry unit, a segmented processing unit, and multiple PEGs.

[0043] The task allocation unit is used to assign ready segmented tasks to available PEGs. To avoid overloading a single PEG and improve hardware utilization, the task allocation unit distributes ready tasks to the appropriate PEG based on the current availability of the PEG and the data affinity of the task. For tasks with strong locality, they can be preferentially allocated to the corresponding PEG to improve the reuse rate of the L / U factor in local storage; for tasks with weak locality or insufficient local queues, they can be allocated to other idle PEGs to maintain load balancing.

[0044] The dependency entry unit parses the dependency pointers carried by the ready segment task and reads the dependency information required by the segment task from the on-chip dependency metadata. Each dependency information includes at least the predecessor column number, L-factor read address, U-factor read address, and the number of valid L-factors in the current segment. The dependency entry unit organizes this dependency information into a dependency instruction stream and sends it to the corresponding PEG. By setting the dependency entry unit, this invention separates the dependency table parsing process from the numerical computation path of the PEG, enabling the PEG to perform computation according to a sequential dependency instruction stream.

[0045] The segmentation processing unit initiates an asynchronous read request to the matrix A data loading path based on the matrix A data address in the ready segmentation task. The read matrix A segment data is stored in the on-chip segment buffer and used by PEG for subsequent multiply-accumulate updates. Because the matrix A data uses a wide data word packing method, the segmentation processing unit can read the segment data with high bandwidth, avoiding the inefficiency caused by random access to memory based on individual non-zero elements.

[0046] PEG is a basic computational unit in a dedicated computing core array. Each PEG contains multiple processing units and adjacent local storage. PEG receives the dependency instruction stream output by the dependency entry unit and reads the corresponding L / U factor from the hierarchical storage module according to the dependency instruction for calculation.

[0047] By coordinating the task allocation unit, dependency entry unit, segmented processing unit, and PEG, this invention enables the ready task flow, dependency instruction flow, matrix A data flow, and L / U factor data flow to proceed in parallel. This design reduces the blocking of the computing core by the centralized scheduler, allowing multiple PEGs to process different segmented tasks simultaneously, thereby improving the parallelism of sparse LU decomposition.

[0048] (3) Hierarchical storage module The hierarchical storage module is used to improve the on-chip reuse rate of the L / U factor and reduce the number of off-chip high-bandwidth storage accesses. This module includes local storage private to each PEG, shared storage shared by multiple PEGs, and off-chip high-bandwidth storage access paths.

[0049] Local storage is located within each PEG (Power Grid) and is used to store L / U factors that have been recently calculated or frequently accessed for that PEG. Because local storage is closest to the PEG, access latency is low, making it suitable for storing L / U factors with short-term reuse characteristics. When subsequent tasks of the PEG require these factors again, they can be read directly from local storage without accessing off-chip high-bandwidth storage.

[0050] Shared memory is used to provide a wide range of data reuse across multiple PEGs. When a local memory for a PEG is not hit, the shared memory can be queried further. Shared memory stores the L / U factor that may be accessed by multiple PEGs, thus avoiding the need to establish a complex full interconnect forwarding network between PEGs. This design reduces the wiring complexity of cross-PEG data retrieval and improves the global data hit rate.

[0051] Off-chip high-bandwidth storage serves as the final data storage layer, used to store the complete matrix A data, L factors, and U factors. When both local and shared storage are not hit, PEG reads the required L / U factors through the off-chip high-bandwidth storage access path. To ensure data consistency, the L / U factors calculated by PEG are first written to its local storage, simultaneously updated to shared storage, and asynchronously written to the off-chip high-bandwidth storage via the write-back path. This write-back process can overlap with subsequent computation pipelines, thereby hiding some off-chip memory access latency.

[0052] Therefore, this invention employs a strict hierarchical access order: local memory is accessed first, followed by shared memory, and finally, off-chip high-bandwidth memory. Through this design combining local, shared, and off-chip memory, this invention can improve L / U factor reuse, reduce off-chip accesses, and enhance overall computational efficiency without introducing complex cross-PEG interconnect structures.

[0053] (iii) Asynchronous task triggering like Figure 3As shown, this invention proposes an asynchronous task triggering strategy to reduce redundant waiting caused by traditional hierarchical synchronization.

[0054] This strategy is implemented based on a dependency list and a dependency triggering mapping list. Each segment task corresponds to a current dependency, which represents the number of predecessor columns that the task has not yet completed. When a predecessor column is completed, the dependency count of all subsequent segment tasks that depend on that column is decremented by one; when the dependency count of a segment task reaches zero, that segment task is immediately triggered for execution.

[0055] For example, such as Figure 3 As shown, assume that segmented task segment 1 depends only on column 0, segmented task segment 2 depends on columns 0 and 2, and segmented task segment 3 depends only on column 2. Initially, the dependency counts for segments 1, 2, and 3 are 1, 2, and 1, respectively. When column 0 completes, the asynchronous task triggering unit finds segments 1 and 2 according to the dependency triggering mapping list, decrements the dependency count of segment 1 from 1 to 0, and decrements the dependency count of segment 2 from 2 to 1. Since the dependency count of segment 1 has reached zero, segment 1 immediately enters the ready state and is sent to the task dispatching unit without waiting for column 2 to complete. When column 2 subsequently completes, the dependency count of segment 2 is decremented from 1 to 0, and the dependency count of segment 3 is decremented from 1 to 0; both are then triggered for execution.

[0056] Therefore, in this invention, whether a segmented task can be executed depends on whether its actual predecessor dependency is completed, rather than on whether all columns within a certain level are completed. Thus, compared to traditional hierarchical synchronization methods, this invention can reduce the waiting time caused by irrelevant columns and increase the number of tasks that can be executed in parallel.

[0057] (iv) Locality perception task distribution The locality-aware task distribution strategy is used to improve L / U factor reuse while maintaining load balancing of processing units.

[0058] like Figure 4 As shown, this strategy combines local and global task queues. The local task queue can be implemented as a local FIFO queue, and the global task queue can be implemented as a global FIFO queue, where FIFO stands for First-In-First-Out (FIFO). After the asynchronous task triggering unit generates a ready task, the task distribution unit determines whether it enters the local or global task queue based on the task's data affinity. This data affinity can be determined by the column to which the task belongs, the L / U factor accessed by the task, the HBM bank corresponding to the task, and the data reuse relationship between the task and a recently executed task of a certain PEG.

[0059] For example, tasks T1 and T2 need to access L / U factors recently generated or cached by a certain PEG, so they are written to the local task queue of that PEG; task T3 does not have obvious locality, or its corresponding local task queue is full, so it is written to the global task queue. During task distribution, the PEG first retrieves tasks from its own local task queue to reuse L / U factors in local storage; only when the local task queue is empty does it retrieve tasks from the global task queue. For tasks in the global task queue, the task distribution unit allocates them to idle PEGs in a round-robin manner to avoid idle hardware resources.

[0060] Through such Figure 4 The task scheduling strategy shown in this invention enables segmented tasks to be executed immediately after the actual dependencies are met, while reusing existing on-chip data as much as possible, thereby improving task parallelism and overall system throughput.

[0061] (v) Sparse LU decomposition calculation The internal decomposition process of PEG employs a left-look decomposition approach for numerical computation. For the current segment to be processed, PEG reads the L / U factors corresponding to the predecessor columns according to the dependency instructions, and simultaneously reads the original matrix data of the current segment from the on-chip A buffer. Once the required data is prepared, PEG performs a multiply-accumulate update on the current segment to eliminate the contribution of each predecessor column to the current column.

[0062] Specifically, for the current column j and its predecessor column k, PEG reads U(k,j) and the corresponding L(i,k) within the current segment, and subtracts the product of L(i,k) and U(k,j) from A(i,j). If the current segment has multiple predecessor columns, the contribution elimination of each predecessor column is performed sequentially according to the dependency instruction flow. This multiply-accumulate process is executed in parallel by multiple processing units, with different processing units processing different sparse elements in the current segment to improve computational throughput.

[0063] After all predecessor dependency contributions are eliminated, PEG generates L / U factors based on element positions. For segments containing diagonal elements of the current column, PEG first generates and determines the diagonal element U(j,j) of the current column, and writes this diagonal element to local memory, shared memory, or sends it to other segments in the same column via the on-chip data path. For elements on and above the diagonal, the updated values ​​are retained as U factors; for elements below the diagonal in the same column, the relevant segment, after obtaining the diagonal element U(j,j) of the current column, performs normalization using a pipelined floating-point division unit to obtain the corresponding L factor. Subsequently, PEG writes the generated L / U factors to local memory and updates shared memory and off-chip HBM.

[0064] (vi) Experiment The sparse LU decomposition accelerator proposed in this invention is specifically implemented on a Xilinx Alveo U280 FPGA board. Its development utilizes Xilinx HLS C++ and is implemented in hardware using the Vitis 2022.2 toolchain. The HLS C++ code is built upon the streaming processing framework TAPA.

[0065] To evaluate the performance of the proposed sparse LU decomposition accelerator, this invention selected 15 sparse matrices from the SuiteSparse dataset for evaluation. These matrices cover multiple application areas, including circuit simulation, computational fluid dynamics, and two-dimensional / three-dimensional problems, ensuring the broad applicability of the evaluation results. Table 1 details the key information of these evaluation matrices, including but not limited to their dimensionality, number of non-zero elements, and matrix density. Table 2 reports in detail the resource utilization of this invention on the Xilinx Alveo U280 FPGA board.

[0066] Table 1 Information from the evaluation matrix

[0067] Table 2 Resource utilization of this invention on the Xilinx U280 FPGA board

[0068] To quantitatively evaluate the performance of the accelerator of this invention, an industry-standard GPU platform was used as a benchmark for comparison. Specifically, benchmark tests were performed on NVIDIA RTX A6000 and NVIDIA Tesla V100 GPUs, utilizing the CUDSS_PHASE_FACTORIZATION and CUDA 12.4 environments of the NVIDIA cuDSS library's secondary application programming interface (API) to perform sparse LU decomposition calculations. cuDSS is widely recognized as a state-of-the-art solution for sparse LU decomposition on current GPUs. On the GPU platform, the execution time of the LU decomposition phase was measured using cudaEventElapsedTime, and power consumption was obtained using the nvidia-smi tool.

[0069] Regarding the accelerator, kernel execution time was measured using Xilinx Runtime (XRT), and power consumption was obtained using the xbutil tool. To comprehensively evaluate the performance of the accelerator of this invention, the following three key metrics were used: throughput (measured in GFLOP / s, i.e., gigafloat operations per second), bandwidth efficiency (measured in MFLOP / s / (GB / s), i.e., throughput per unit of memory bandwidth), and energy efficiency (measured in MFLOP / s / W, i.e., throughput per watt).

[0070] (1) Performance comparison with GPU platform like Figure 5 As shown, this embodiment first compares the accelerator of the present invention with the cuDSS solver running on NVIDIA RTX A6000 and Tesla V100 GPUs.

[0071] Experimental results show that, in terms of throughput, the accelerator of this invention achieves a 4.0x geometric mean throughput improvement compared to the cuDSS implementation on RTX A6000 GPUs, and a 3.7x geometric mean throughput improvement compared to the cuDSS implementation on Tesla V100 GPUs. On large-scale matrices (largebasis), the accelerator of this invention achieves a throughput improvement of up to 6.7x compared to RTX A6000 GPUs.

[0072] Despite the significantly higher operating frequency of the GPU platform compared to the FPGA platform, the accelerator of this invention still achieves higher overall throughput. This is mainly because the invention employs a fine-grained asynchronous task triggering mechanism, transforming the redundant waiting in traditional hierarchical synchronization into task activation driven by real dependencies. This allows more segmented tasks to enter the computing core for execution earlier, thereby improving the utilization of processing units and the number of parallelizable tasks.

[0073] In terms of energy efficiency, the accelerator of this invention achieves a 6.5x geometric mean energy efficiency improvement compared to the RTX A6000 GPU and a 4.7x geometric mean energy efficiency improvement compared to the Tesla V100 GPU. These results demonstrate that the accelerator of this invention not only has advantages in throughput but also enables more efficient sparse LU numerical decomposition at lower power consumption.

[0074] The aforementioned energy efficiency improvement mainly stems from the following two aspects: Firstly, the asynchronous task triggering mechanism of this invention reduces idle waiting time of processing units and increases the effective computation ratio per unit time; secondly, the locality-aware task distribution and hierarchical memory access mechanism of this invention improves the on-chip reuse rate of the L / U factor and reduces high-latency, high-energy-consumption off-chip HBM access.

[0075] (2) Performance comparison with CPU platform like Figure 6 As shown, to further verify the acceleration effect of the method of the present invention outside of general processor platforms, this embodiment also compares the FPGA accelerator with a high-performance parallel sparse solver on a CPU platform.

[0076] Experimental results show that the accelerator of this invention achieves a geometric mean performance improvement of 2.3 times compared to the CPU sparse solver. The accelerator exhibits a more significant performance advantage on matrices with complex and irregular dependency structures, such as meg1, G62, and dtoc. This is because such matrices are prone to severe synchronization waits in traditional hierarchical synchronous scheduling, while this invention, through segmented dependency and asynchronous task triggering mechanisms, can more fully unleash fine-grained parallelism.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering, characterized by, Includes the following steps: Data and dependency preprocessing: Based on the symbolic decomposition results of the sparse matrix, the column-level dependencies in the sparse LU decomposition process are decomposed in a fine-grained manner to generate a dependency list and a dependency trigger mapping list for FPGA runtime scheduling. Based on the non-zero L / U structure obtained after preprocessing and symbolic decomposition of the sparse matrix, column dependencies are constructed. The traditional coarse-grained dependencies based on columns are further decomposed into fine-grained dependencies based on continuous sparse segments, thus forming a segmented task dependency graph. The fine-grained dependencies are represented by a dependency degree list and a dependency triggering mapping list. The dependency degree list records the number of predecessor dependencies that have not yet been satisfied for each sparse segment task. The dependency triggering mapping list records the dependencies of subsequent segment tasks that should be updated after a column is decomposed. Customized FPGA hardware acceleration architecture: Construct a hardware architecture that includes a global control unit, a dedicated computing core array, and a hierarchical storage module to decouple task triggering, dependency resolution, data loading, and numerical computation. Asynchronous task triggering: Update fine-grained dependencies based on runtime column completion signals, and immediately trigger an executable task when the dependency count of a computation segment reaches zero; Locality-aware load balancing: A dual-queue task distribution strategy is adopted. Based on the pre-determined data affinity mapping relationship, tasks with high data affinity are preferentially allocated to the corresponding processing unit groups. When the local task queue is unavailable, tasks are allocated in a round-robin manner through the global task queue to ensure the utilization rate of the processing units. Parallel execution of sparse LU decomposition: Each PEG receives the triggered sparse segmentation task, asynchronously loads the original matrix data and dependent L / U factors, and completes the sparse LU numerical decomposition through parallel multiplication, accumulation and division calculations.

2. The high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering according to claim 1, characterized in that, The global control unit is used to maintain the dependency count state, process column completion signals, trigger executable segmented tasks, and generate a ready task flow. The global control unit includes a column completion signal merging module and a dependency scheduling module. The column completion signal merging module is used to collect column completion signals generated by multiple PEGs and merge them into a unified completion event flow. The dependency counting scheduling module is used to query the dependency trigger mapping list based on the completion event stream, update the dependency count of the corresponding segment task, and output the segment task with the dependency count reaching zero as a ready task.

3. The high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering according to claim 1, wherein, The dedicated computing core array is used to receive ready task streams and complete task allocation, dependency metadata parsing, matrix data loading, L / U factor acquisition, and multiplication-accumulation and division calculations. The dedicated computing core array includes a task allocation unit, a dependency entry unit, a segmentation processing unit, and multiple PEGs. The task allocation unit allocates tasks to corresponding PEGs based on the locality attributes and queue status of ready tasks. The dependency entry unit reads dependency information and generates dependency instructions based on the metadata pointers carried by the tasks. The segmentation processing unit asynchronously requests the original matrix data according to the task instructions and caches it in an on-chip buffer. The PEG obtains the required L / U factors from the hierarchical storage module according to the dependency instructions and performs sparse LU decomposition calculations.

4. The high-bandwidth memory (HBM) FPGA sparse LU decomposition acceleration method based on asynchronous task triggering according to claim 1, wherein, The hierarchical storage module includes local storage and shared storage. Local storage is located within each PEG and is used to store L / U factors recently calculated or frequently accessed by that PEG. Shared storage is accessed by multiple PEGs and is used to store L / U factors reused across PEGs. When neither local storage nor shared storage is hit, external HBM is accessed. The storage access order is: local storage, shared storage, external HBM.

5. The high-bandwidth memory (HBM) FPGA sparse LU decomposition acceleration method based on asynchronous task triggering according to claim 1, wherein, The asynchronous task triggering process includes: the global control unit receiving a column completion signal from the computing core array; searching for the successor segmented task that depends on the column corresponding to the column completion signal according to the dependency triggering mapping list; performing a decrement operation on the dependency count of the corresponding segmented task; and immediately marking the segmented task as a ready task and sending it into the task flow when the dependency count becomes zero.

6. The high-bandwidth memory (HBM) FPGA sparse LU decomposition acceleration method based on asynchronous task triggering according to claim 1, wherein, The dual-queue task distribution strategy includes a local task queue and a global task queue. For tasks with high data affinity, they are written into the local task queue corresponding to the PEG, and tasks are preferentially retrieved from the local task queue for execution to improve the reuse rate of the L / U factor in local storage. For tasks with low affinity, or when the local task queue can no longer receive tasks, they are written into the global task queue and distributed to idle PEGs in a global round-robin manner to avoid some processing units being idle for a long time.

7. The high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering according to claim 1, characterized in that, The sparse LU decomposition calculation adopts a left-look decomposition method. For the current segment to be processed, PEG first reads the L / U factor corresponding to the predecessor column according to the dependency instruction and performs multiply-accumulate update on the original matrix data. After completing the elimination of all dependency contributions, the diagonal element U(j,j) of the current column j is generated first, and then the normalization division operation is performed on the elements below the diagonal in the current column based on the diagonal element to generate the final L / U factor result.

8. The high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering according to claim 7, characterized in that, The multiply-accumulate operation includes: multiple PEs read the sparse data and dependent column L / U factors of the current segment in parallel, and perform multiplication and addition / subtraction updates on the corresponding elements to eliminate the contribution of the predecessor column to the current column; the division operation includes: after the multiply-accumulate update is completed, the elements below the diagonal in the current column are normalized using a pipelined floating-point division unit to obtain the final L factor, while retaining the corresponding U factor.

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