A timing optimization post-processing method for RSFQ circuits

Abstract

This invention discloses a timing optimization post-processing method for RSFQ circuits, comprising the following steps: S1, performing topology analysis on the process-mapped RSFQ circuit netlist to determine the movable range of each node in the pipeline stage; S2-S3, fan-out-aware D flip-flop insertion strategy; S4, performing path balancing on unbalanced paths in the circuit netlist and updating the circuit netlist; S5-S6, a splitter structure optimization method based on node replication; S7, iteratively executing S2 to S3 and S5 to S6 until the worst-case stage delay converges or the set number of iterations is reached; S8, inserting splitters into the RSFQ circuit netlist, and finally outputting the optimized valid RSFQ circuit netlist. This method, without changing the circuit logic depth and functional correctness, restructures high fan-out nodes in the circuit, thereby reducing the splitter tree depth and lowering the worst-case stage delay.

Description

Technical Field

[0001] This invention relates to the field of automation technology for superconducting digital circuit design, specifically to a timing optimization post-processing method for RSFQ circuits. Background Technology

[0002] With the rapid development of information technology, traditional CMOS technology is gradually approaching its physical limits, and exploring new high-performance computing technologies has become an important research direction in the field of integrated circuits. Superconducting electronic technology based on Josephson junctions (JJ) has attracted widespread attention due to its ultra-high operating speed and extremely low energy consumption. Among them, Rapid Single Flux Quantum (RSFQ) logic is one of the most mature and widely used superconducting logic systems. RSFQ circuits use quantum flux pulses as information carriers and achieve high-speed logic operations through Josephson junctions. Their operating frequencies can reach tens to hundreds of GHz, with single-switch energy as low as 10 kilovolts per second. -19 With a joule scale, it has significant application prospects in the field of high-performance computing.

[0003] However, RSFQ circuits differ significantly from traditional CMOS circuits in their structure and design methodology. RSFQ circuits typically employ a strict gate-level pipelined structure, where each logic operation is driven by a clock signal. Therefore, all input signals must arrive within the same clock cycle; otherwise, the circuit will malfunction. To ensure that all input signals arrive in the same cycle, D flip-flops (DFFs) must be inserted into the circuit for path balancing to meet the timing constraints of its gate-level pipelined structure.

[0004] Furthermore, due to the limited driving capability of Josephson junctions, most RSFQ logic gates only support single fan-out. When a signal needs to drive multiple subsequent logic units, it must be replicated using a splitter structure, thus forming a splitter tree. As the number of fan-outs increases, the depth of the splitter tree grows rapidly, leading to significant delay overhead.

[0005] In practical RSFQ synthesis processes, traditional path balancing and splitter insertion methods typically prioritize ensuring the legality of circuit functionality and structural cost, such as reducing the number of D flip-flops or the use of Josephson junctions. However, these methods often overlook the impact of fan-out distribution on circuit timing performance. Especially when some nodes have large fan-outs, deep splitter trees can form, significantly increasing the stage delay of the RSFQ circuit and thus limiting its maximum operating frequency. Therefore, optimizing the fan-out structure and reducing stage delays while ensuring path balancing and fan-out constraints has become a key technical challenge in RSFQ circuit design. Summary of the Invention

[0006] To address the aforementioned problems in existing technologies, this invention proposes a timing optimization post-processing method for RSFQ circuits. This method, without altering the circuit's logic depth or functional correctness, restructures high fan-out nodes in the circuit using a fan-out-aware D flip-flop insertion strategy and a node replication-based splitter structure optimization method. This reduces the splitter tree depth and lowers the worst-case stage delay (WSD).

[0007] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a timing optimization post-processing method for RSFQ circuits, comprising the following steps: S1. Perform topology analysis on the RSFQ circuit netlist after process mapping to determine the movable range of each node in the pipeline stage. S2. Traverse the circuit netlist and identify nodes whose fan-out number exceeds a preset threshold as candidate optimization nodes. S3. Based on the allowable mobility range of each fan-out node of the candidate optimization node, the fan-out nodes that were originally concentrated in the same pipeline stage are redistributed to multiple different pipeline stages, and D flip-flops are inserted between the candidate optimization node and its fan-out nodes to perform path balancing. S4. Balance the unbalanced paths in the circuit netlist and update the circuit netlist. S5. Based on the logic gate delay information and the delay model of the splitter tree, calculate the delay of each pipeline stage and determine the worst-case stage delay and its corresponding critical node. S6. If the difference between the worst stage delay caused by the critical node and the stage delay of its fan-in node is greater than the delay of a splitter, then the critical node is replicated into multiple equivalent nodes, and the fan-out nodes of the critical node are assigned to each replicated node, and the circuit netlist is updated. S7. Iterate through S2 to S3 (i.e., the fan-out sensing D-flip-flop insertion strategy) and S5 to S6 (i.e., the splitter structure optimization method based on node replication) until the worst-case phase delay converges or the set number of iterations is reached. S8. Insert a splitter into the RSFQ circuit netlist and finally output the optimized valid RSFQ circuit netlist.

[0008] Preferably, the difference between the latest and earliest levels of a node is defined as the topology margin to characterize the movable range of a node in the pipeline stage. The specific process of step S1 is as follows: First, the RSFQ circuit netlist after process mapping is topologically sorted to obtain the predecessor and successor relationships between nodes in the netlist. Then, a forward traversal is performed starting from the circuit input node, calculating the earliest level ASAP (As Soon As Possible) of each node based on the predecessor node level, which is the earliest pipeline stage that each node can reach under the condition of satisfying logical dependencies. Subsequently, a reverse traversal is performed starting from the circuit output node, calculating the latest level ALAP (As Late As Possible) of each node based on the successor node level, which is the latest pipeline stage that each node can be arranged in without changing the overall pipeline depth. Finally, the topology margin Slack of each node is calculated based on the difference between the latest level ALAP and the earliest level ASAP, and its calculation formula is: ; The above calculations yield the movable range of each node in the pipeline stage.

[0009] As a preferred embodiment, the specific process of step S3 is as follows: First, obtain the set of all fan-out nodes of the candidate optimization node; then, calculate the allowed mobility range of each fan-out node based on its topology margin; subsequently, without violating the logical dependencies between nodes, evenly redistribute the fan-out nodes that were originally concentrated in the same pipeline stage to multiple different pipeline stages within the allowed mobility range; finally, insert D triggers between the candidate optimization node and its fan-out nodes according to the hierarchical distribution of the fan-out nodes.

[0010] Preferably, step S4 involves inserting D flip-flops into paths in the circuit netlist that have not yet been inserted to balance the paths. The insertion principle is as follows: when the hierarchical difference n between a node and its parent node is greater than or equal to 1, n-1 D flip-flops are inserted between that node and its parent node. Simultaneously, the circuit netlist is updated, including re-recording the connection relationships between nodes and the pipeline stage information for each node. Through these operations, the gate-level pipeline constraints of the RSFQ circuit can be satisfied while maintaining the original logic functionality.

[0011] Preferably, step S5 involves the following process: based on the logic gate delay information and the delay model of the splitter tree, adjusting the delay of each pipeline stage. StageDelay The calculation is performed using the following formula: ; in, Delay Gate Indicates door delay. Delay Splitter Indicates the delay of the branch tree connected to the gate. Delay JTL This represents the interconnect delay; in actual calculations, the interconnect delay is ignored, and the delay of each pipeline stage is considered. StageDelay The calculation formula is optimized as follows: ; Based on the delay calculation results of each pipeline stage, the maximum delay is selected as the worst stage delay, and the node corresponding to the worst stage delay is determined as the critical node.

[0012] Preferably, step S6 is as follows: if the difference between the worst-case stage delay caused by the critical node and the stage delay of its fan-in node is greater than the delay of a splitter, then the critical node is replicated into N equivalent nodes through node replication, where the value of N satisfies the following formula: ; ; ; in, Delay last This indicates the delay of the previous stage of the production line. Delay current This indicates the delay of the current pipeline stage. d Spl Indicates the delay of a single splitter. i It is a natural number; Subsequently, obtain the set of all fan-out nodes of the critical node, divide the set into N subsets, and connect each subset to a different replicated node, so that each replicated node drives only a portion of the fan-out nodes, and then update the circuit netlist.

[0013] As a preferred option, the specific process of step S8 is as follows: when the number of fan-outs M of a certain node is greater than 1, a splitter binary tree structure with output M is inserted at the output end of this node, and the splitter binary tree structure is connected to the fan-out nodes of this node, and finally the optimized legal RSFQ circuit netlist is output.

[0014] Compared with existing technologies, this invention has the following advantages: This invention provides a timing optimization post-processing method for RSFQ circuits. Addressing the strict gate-level pipeline structure and finite fan-out constraints of RSFQ circuits, the method utilizes a fan-out-aware D flip-flop insertion strategy to distribute high fan-out loads across multiple pipeline stages, effectively reducing single-stage fan-out pressure. Furthermore, it employs a node-replication-based splitter structure optimization method to significantly reduce the splitter tree depth, thereby lowering the worst-case stage delay of the RSFQ circuit. This invention significantly improves the timing performance of RSFQ circuits while maintaining logic depth and path balance constraints. It is applicable to the post-optimization stage in RSFQ logic synthesis and can serve as a general post-processing optimization method after process mapping. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall process of the method of the present invention; Figure 2 A comparison diagram of the traditional D flip-flop insertion method and the D flip-flop insertion method of the present invention; Figure 3 A comparison diagram of the binary tree structure of the splitter with high fan-out nodes in the RSFQ circuit. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0017] Example: A timing optimization post-processing method for RSFQ circuits. This method optimizes the RSFQ logic netlist that has already undergone process mapping to reduce worst-case stage delay and improve the overall timing performance of the circuit. Figure 1 As shown, the method includes the following steps: S1. Perform topology analysis on the RSFQ circuit netlist after process mapping to determine the movable range of each node in the pipeline stage. Define the difference between the latest level and the earliest level of the node as the topology margin to characterize the movable range of the node in the pipeline stage.

[0018] The specific process of step S1 is as follows: First, perform topological sorting on the RSFQ circuit netlist after process mapping to obtain the predecessor and successor relationships between nodes in the circuit netlist; then, perform a forward traversal starting from the circuit input node, and calculate the earliest level ASAP of each node based on the predecessor node level, that is, the earliest pipeline stage that each node can reach under the condition of satisfying logical dependencies; subsequently, perform a reverse traversal starting from the circuit output node, and calculate the latest level ALAP of each node based on the successor node level, that is, the latest pipeline stage that each node can be arranged without changing the overall pipeline depth; finally, calculate the topological margin Slack of each node based on the difference between the latest level ALAP and the earliest level ASAP, the calculation formula is: ; The above calculations provide the movable range of each node in the pipeline stage, which serves as a basis for subsequent fan-out redistribution.

[0019] S2. Traverse the circuit netlist, count the fan-out of each node, and select nodes with a fan-out exceeding a preset threshold as candidate optimization nodes. This step can quickly locate nodes that may lead to deep splitter trees and large stage delays, thus providing candidate optimization nodes for subsequent optimization.

[0020] S3. Based on the allowable mobility of each fan-out node of the candidate optimization node, the fan-out nodes originally concentrated in the same pipeline stage are redistributed to multiple different pipeline stages. D flip-flops are inserted between the candidate optimization node and its fan-out nodes to perform path balancing. By redistributing the fan-out nodes as described above, the fan-out load of the candidate optimization node is distributed across multiple pipeline stages, thereby reducing the fan-out scale within a single pipeline stage.

[0021] The specific process of step S3 is as follows: First, obtain the set of all fan-out nodes of the candidate optimization node; then, calculate the allowed mobility range of each fan-out node based on its topology margin; subsequently, without violating the logical dependencies of the nodes, within the allowed mobility range, evenly redistribute the fan-out nodes that were originally concentrated in the same pipeline stage to multiple different pipeline stages, thereby reducing the fan-out pressure of a single pipeline stage; finally, based on the hierarchical distribution of the fan-out nodes at this time, insert D flip-flops between the candidate optimization node and its fan-out nodes.

[0022] S4. Perform path balancing on unbalanced paths in the circuit netlist and update the circuit netlist.

[0023] Step S4 involves inserting D flip-flops into paths in the circuit netlist that haven't yet been inserted to balance the paths and satisfy the gate-level pipeline constraints of the RSFQ circuit. The insertion principle is: when the hierarchical gap n ≥ 1 between a node and its parent node, n-1 D flip-flops are inserted between that node and its parent node. Simultaneously, the circuit netlist is updated, including re-recording the connection relationships between nodes and the pipeline stage information for each node. Through these operations, the gate-level pipeline constraints of the RSFQ circuit can be satisfied while maintaining the original logic functionality.

[0024] S5. Based on the logic gate delay information and the delay model of the splitter tree, calculate the delay of each pipeline stage and determine the worst-case stage delay and its corresponding critical node.

[0025] The specific process of step S5 is as follows: Based on the logic gate delay information and the delay model of the splitter tree, the delay of each pipeline stage is calculated. StageDelay The calculation is performed using the following formula: ; in, Delay Gate Indicates door delay. Delay Splitter Indicates the delay of the branch tree connected to the gate. Delay JTL This represents the interconnect delay. In actual calculations, since it is difficult to accurately characterize the interconnect delay before placement and routing, the interconnect delay is ignored, and the delay of each pipeline stage is considered instead. StageDelay The calculation formula is optimized as follows: ; Based on the delay calculation results of each pipeline stage, the largest delay is selected as the worst stage delay, and the node corresponding to the worst stage delay is determined as the critical node for further optimization.

[0026] S6. If the difference between the worst-case stage delay caused by the critical node and the stage delay of its fan-in node is greater than the delay of a splitter, meaning there is still room for optimization of the worst-case stage delay, the critical node is replicated into N equivalent nodes by node replication, where the value of N satisfies the following formula: ; ; ; in, Delay last This indicates the delay of the previous stage of the production line. Delay current This indicates the delay of the current pipeline stage.d Spl Indicates the delay of a single splitter. i It is a natural number.

[0027] Subsequently, the set of all fan-out nodes of the critical node is obtained, the set is divided into N subsets, and each subset is connected to a different replicated node, so that each replicated node drives only a portion of the fan-out nodes. In this way, the number of fan-out nodes that a single node needs to drive can be significantly reduced, thereby reducing the depth of the splitter tree and reducing stage delay; then the circuit netlist is updated.

[0028] S7. Iterate through S2 to S3 and S5 to S6 until the worst-case phase converges or the set number of iterations is reached.

[0029] S8. When the number of fan-outs M of a certain node is greater than 1, insert a splitter binary tree structure with output M at the output end of this node, and connect the splitter binary tree structure to the fan-out nodes of this node, and finally output the optimized legal RSFQ circuit netlist.

[0030] Figure 2 This diagram compares the traditional D flip-flop insertion method with the D flip-flop insertion method of this invention. Figure 2 (a) in the diagram is a schematic diagram of the connection between the candidate optimization node and its fan-out node in the RSFQ circuit before the D flip-flop is inserted. Figure 2 (b) is a schematic diagram of the RSFQ circuit after inserting a D flip-flop using the traditional D flip-flop insertion method. Figure 2 (c) is a schematic diagram of the RSFQ circuit after inserting a D flip-flop using the D flip-flop insertion method of the present invention. Figure 2 In the diagram, circles represent nodes in the RSFQ circuit; squares marked DFF represent D flip-flops; squares marked Spl2 represent two-output splitters; lev and slack represent the current ASAP level and slack information of the node, respectively.

[0031] Figure 3 A comparative diagram of the binary tree structure of the splitter at a high fan-out node in an RSFQ circuit is provided, illustrating the structural differences before and after node replication using the method of this invention. Figure 3 (a) is an example diagram of a high fan-out node in the RSFQ circuit before node replication. Figure 3 (b) in the text is a pair Figure 3 (a) is a schematic diagram illustrating the effect of replicating high fan-out nodes using the method of this invention. Figure 3 (c) in the text is a pair Figure 3 The schematic diagram of the effect of inserting the circuit shown in (a) into the binary tree structure of the splitter is shown in the figure. Figure 3 (d) in the text is a pair Figure 3The diagram shows the effect of inserting the circuit shown in (b) into the binary tree structure of the splitter. Figure 3 In the diagram, circles represent nodes in the RSFQ circuit, and squares marked Spl2 represent two-output splitters.

[0032] like Figure 2 and Figure 3 As shown, the method of the present invention can effectively reduce the shunt tree depth caused by high fan-out nodes in the RSFQ circuit, thereby reducing the worst-case stage delay and increasing the circuit operating frequency.

[0033] To verify the effectiveness and practicality of the method of this invention, multiple typical RSFQ circuit test cases were selected for experimental evaluation. These cases covered different scales and fan-out distribution characteristics, including small-scale verification circuits and medium-to-large-scale complex circuits, to comprehensively evaluate the performance of the method of this invention in different application scenarios. The experimental results of the method of this invention, method 1, and method 2 on different RSFQ circuit test cases are shown in Table 1. The data for method 1 are the data described in the literature "PBMap: A PathBalancing Technology Mapping Algorithm for Single Flux Quantum LogicCircuits". The data for method 2 are the results obtained by adding the xmgrw logic synthesis optimization operator from the open-source tool ALSO to the call to the open-source logic synthesis tool ABC process and then performing RSFQ legalization.

[0034] Table 1

[0035] The experimental results in Table 1 fully demonstrate that, after optimization using the method of the present invention, the depth of the splitter tree can be effectively reduced by lowering the maximum fan-out and optimizing the pipeline stage division without significantly increasing hardware resource overhead. This significantly reduces the worst-case stage delay of the RSFQ circuit, verifying the effectiveness and superiority of the method of the present invention in timing optimization of RSFQ circuits.

Claims

1. A timing optimization post-processing method for RSFQ circuits, characterized in that, Includes the following steps: S1. Perform topology analysis on the RSFQ circuit netlist after process mapping to determine the movable range of each node in the pipeline stage. Define the difference between the latest level and the earliest level of the node as the topology margin to characterize the movable range of the node in the pipeline stage. S2. Traverse the circuit netlist and identify nodes whose fan-out number exceeds a preset threshold as candidate optimization nodes. S3. Based on the allowable mobility range of each fan-out node of the candidate optimization node, the fan-out nodes that were originally concentrated in the same pipeline stage are redistributed to multiple different pipeline stages, and D flip-flops are inserted between the candidate optimization node and its fan-out nodes to perform path balancing. S4. Balance the unbalanced paths in the circuit netlist and update the circuit netlist. S5. Calculate the delay of each pipeline stage based on the logic gate delay information and the delay model of the splitter tree; based on the delay calculation results of each pipeline stage, select the largest delay as the worst stage delay, and determine the worst stage delay and its corresponding key nodes. S6. If the difference between the worst stage delay caused by the critical node and the stage delay of its fan-in node is greater than the delay of a splitter, then the critical node is replicated into multiple equivalent nodes, and the fan-out nodes of the critical node are assigned to each replicated node, and the circuit netlist is updated. S7. Iterate through S2 to S3 and S5 to S6 until the worst-case phase convergence is achieved or the set number of iterations is reached. S8. Insert a splitter into the RSFQ circuit netlist and finally output the optimized valid RSFQ circuit netlist.

2. The timing optimization post-processing method for RSFQ circuits according to claim 1, characterized in that, The specific process of step S1 is as follows: First, perform topological sorting on the RSFQ circuit netlist after process mapping to obtain the predecessor and successor relationships between nodes in the circuit netlist; then, perform a forward traversal starting from the circuit input node, and calculate the earliest level ASAP of each node based on the predecessor node level, that is, the earliest pipeline stage that each node can reach under the condition of satisfying logical dependencies; subsequently, perform a reverse traversal starting from the circuit output node, and calculate the latest level ALAP of each node based on the successor node level, that is, the latest pipeline stage that each node can be arranged without changing the overall pipeline depth; finally, calculate the topological margin Slack of each node based on the difference between the latest level ALAP and the earliest level ASAP, the calculation formula is: ； The above calculations yield the movable range of each node in the pipeline stage.

3. The timing optimization post-processing method for RSFQ circuits according to claim 2, characterized in that, The specific process of step S3 is as follows: First, obtain the set of all fan-out nodes of the candidate optimization node; then, calculate the allowed mobility range of each fan-out node based on its topology margin; subsequently, without violating the logical dependencies of the nodes, evenly redistribute the fan-out nodes that were originally concentrated in the same pipeline stage to multiple different pipeline stages within the allowed mobility range; finally, insert D flip-flops between the candidate optimization node and its fan-out nodes according to the hierarchical distribution of the fan-out nodes.

4. The timing optimization post-processing method for RSFQ circuits according to claim 1, characterized in that, The specific process of step S4 is as follows: For paths in the circuit netlist that have not yet had D flip-flops inserted, D flip-flops are inserted to balance the paths. The insertion principle is: when the hierarchical difference n between a certain node and the previous level node is greater than or equal to 1, n-1 D flip-flops are inserted between the certain node and the previous level node. At the same time, the circuit netlist is updated. The update content includes re-recording the connection relationship between nodes and the pipeline stage information of each node.

5. The timing optimization post-processing method for RSFQ circuits according to claim 1, characterized in that, The specific process of step S5 is as follows: Based on the logic gate delay information and the delay model of the splitter tree, the delay of each pipeline stage is calculated. StageDelay The calculation is performed using the following formula: ； in, Delay Gate Indicates door delay. Delay Splitter Indicates the delay of the branch tree connected to the gate. Delay JTL This represents the interconnect delay; in actual calculations, the interconnect delay is ignored, and the delay of each pipeline stage is considered. StageDelay The calculation formula is optimized as follows: ； Based on the delay calculation results of each pipeline stage, the maximum delay is selected as the worst stage delay, and the node corresponding to the worst stage delay is determined as the critical node.

6. The timing optimization post-processing method for RSFQ circuits according to claim 1, characterized in that, The specific process of step S6 is as follows: If the difference between the worst-case stage delay caused by the critical node and the stage delay of its fan-in node is greater than the delay of a splitter, then the critical node is replicated into N equivalent nodes by node replication, where the value of N satisfies the following formula: ； ； ； in, Delay last This indicates the delay of the previous stage of the production line. Delay current This indicates the delay of the current pipeline stage. d Spl Indicates the delay of a single splitter. i It is a natural number; Subsequently, obtain the set of all fan-out nodes of the critical node, divide the set into N subsets, and connect each subset to a different replicated node, so that each replicated node drives only a portion of the fan-out nodes, and then update the circuit netlist.

7. The timing optimization post-processing method for RSFQ circuits according to claim 1, characterized in that, The specific process of step S8 is as follows: when the number of fan-outs M of a certain node is greater than 1, a splitter binary tree structure with output M is inserted at the output end of this node, and the splitter binary tree structure is connected to the fan-out nodes of this node, and finally the optimized legal RSFQ circuit netlist is output.

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